Blame - drivers/irqchip/Kconfig - kernel/msm-4.19

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Thomas Petazzoni	f6e916b	2012-11-20 23:00:52 +0100	[diff] [blame]	1	config IRQCHIP
				2	def_bool y
				3	depends on OF_IRQ
				4
Rob Herring	81243e4	2012-11-20 21:21:40 -0600	[diff] [blame]	5	config ARM_GIC
				6	bool
				7	select IRQ_DOMAIN
				8	select MULTI_IRQ_HANDLER
				9
				10	config GIC_NON_BANKED
				11	bool
				12
Marc Zyngier	021f653	2014-06-30 16:01:31 +0100	[diff] [blame]	13	config ARM_GIC_V3
				14	bool
				15	select IRQ_DOMAIN
				16	select MULTI_IRQ_HANDLER
Marc Zyngier	443acc4	2014-11-24 14:35:09 +0000	[diff] [blame]	17	select IRQ_DOMAIN_HIERARCHY
Marc Zyngier	021f653	2014-06-30 16:01:31 +0100	[diff] [blame]	18
Marc Zyngier	1981272	2014-11-24 14:35:19 +0000	[diff] [blame^]	19	config ARM_GIC_V3_ITS
				20	bool
				21	select PCI_MSI_IRQ_DOMAIN
				22
Uwe Kleine-König	292ec08	2013-06-26 09:18:48 +0200	[diff] [blame]	23	config ARM_NVIC
				24	bool
				25	select IRQ_DOMAIN
				26	select GENERIC_IRQ_CHIP
				27
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	28	config ARM_VIC
				29	bool
				30	select IRQ_DOMAIN
				31	select MULTI_IRQ_HANDLER
				32
				33	config ARM_VIC_NR
				34	int
				35	default 4 if ARCH_S5PV210
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	36	default 2
				37	depends on ARM_VIC
				38	help
				39	The maximum number of VICs available in the system, for
				40	power management.
				41
Boris BREZILLON	b1479eb	2014-07-10 19:14:18 +0200	[diff] [blame]	42	config ATMEL_AIC_IRQ
				43	bool
				44	select GENERIC_IRQ_CHIP
				45	select IRQ_DOMAIN
				46	select MULTI_IRQ_HANDLER
				47	select SPARSE_IRQ
				48
				49	config ATMEL_AIC5_IRQ
				50	bool
				51	select GENERIC_IRQ_CHIP
				52	select IRQ_DOMAIN
				53	select MULTI_IRQ_HANDLER
				54	select SPARSE_IRQ
				55
Florian Fainelli	7f646e9	2014-05-23 17:40:53 -0700	[diff] [blame]	56	config BRCMSTB_L2_IRQ
				57	bool
				58	depends on ARM
				59	select GENERIC_IRQ_CHIP
				60	select IRQ_DOMAIN
				61
Sebastian Hesselbarth	350d71b9	2013-09-09 14:01:20 +0200	[diff] [blame]	62	config DW_APB_ICTL
				63	bool
				64	select IRQ_DOMAIN
				65
James Hogan	b6ef916	2013-04-22 15:43:50 +0100	[diff] [blame]	66	config IMGPDC_IRQ
				67	bool
				68	select GENERIC_IRQ_CHIP
				69	select IRQ_DOMAIN
				70
Alexander Shiyan	afc98d9	2014-02-02 12:07:46 +0400	[diff] [blame]	71	config CLPS711X_IRQCHIP
				72	bool
				73	depends on ARCH_CLPS711X
				74	select IRQ_DOMAIN
				75	select MULTI_IRQ_HANDLER
				76	select SPARSE_IRQ
				77	default y
				78
Stefan Kristiansson	4db8e6d	2014-05-26 23:31:42 +0300	[diff] [blame]	79	config OR1K_PIC
				80	bool
				81	select IRQ_DOMAIN
				82
Felipe Balbi	8598066	2014-09-15 16:15:02 -0500	[diff] [blame]	83	config OMAP_IRQCHIP
				84	bool
				85	select GENERIC_IRQ_CHIP
				86	select IRQ_DOMAIN
				87
Sebastian Hesselbarth	9dbd90f	2013-06-06 18:27:09 +0200	[diff] [blame]	88	config ORION_IRQCHIP
				89	bool
				90	select IRQ_DOMAIN
				91	select MULTI_IRQ_HANDLER
				92
Magnus Damm	4435804	2013-02-18 23:28:34 +0900	[diff] [blame]	93	config RENESAS_INTC_IRQPIN
				94	bool
				95	select IRQ_DOMAIN
				96
Magnus Damm	fbc83b7	2013-02-27 17:15:01 +0900	[diff] [blame]	97	config RENESAS_IRQC
				98	bool
				99	select IRQ_DOMAIN
				100
Christian Ruppert	b06eb01	2013-06-25 18:29:57 +0200	[diff] [blame]	101	config TB10X_IRQC
				102	bool
				103	select IRQ_DOMAIN
				104	select GENERIC_IRQ_CHIP
				105
Linus Walleij	2389d50	2012-10-31 22:04:31 +0100	[diff] [blame]	106	config VERSATILE_FPGA_IRQ
				107	bool
				108	select IRQ_DOMAIN
				109
				110	config VERSATILE_FPGA_IRQ_NR
				111	int
				112	default 4
				113	depends on VERSATILE_FPGA_IRQ
Max Filippov	26a8e96	2013-12-01 12:04:57 +0400	[diff] [blame]	114
				115	config XTENSA_MX
				116	bool
				117	select IRQ_DOMAIN
Sricharan R	96ca848	2013-12-03 15:57:23 +0530	[diff] [blame]	118
				119	config IRQ_CROSSBAR
				120	bool
				121	help
Masanari Iida	f54619f	2014-09-18 12:09:42 +0900	[diff] [blame]	122	Support for a CROSSBAR ip that precedes the main interrupt controller.
Sricharan R	96ca848	2013-12-03 15:57:23 +0530	[diff] [blame]	123	The primary irqchip invokes the crossbar's callback which inturn allocates
				124	a free irq and configures the IP. Thus the peripheral interrupts are
				125	routed to one of the free irqchip interrupt lines.
Grygorii Strashko	89323f8	2014-07-23 17:40:30 +0300	[diff] [blame]	126
				127	config KEYSTONE_IRQ
				128	tristate "Keystone 2 IRQ controller IP"
				129	depends on ARCH_KEYSTONE
				130	help
				131	Support for Texas Instruments Keystone 2 IRQ controller IP which
				132	is part of the Keystone 2 IPC mechanism