blob: ccacc40e64ee38d7b32250b88e24e78a85750461 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* linux/drivers/mtd/nand/s3c2410.c
2 *
Ben Dooksa4f957f2005-06-20 12:48:25 +01003 * Copyright (c) 2004,2005 Simtec Electronics
Ben Dooksfdf2fd52005-02-18 14:46:15 +00004 * http://www.simtec.co.uk/products/SWLINUX/
5 * Ben Dooks <ben@simtec.co.uk>
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 *
Ben Dooksa4f957f2005-06-20 12:48:25 +01007 * Samsung S3C2410/S3C240 NAND driver
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 *
9 * Changelog:
10 * 21-Sep-2004 BJD Initial version
Joe Perches8e87d782008-02-03 17:22:34 +020011 * 23-Sep-2004 BJD Multiple device support
Linus Torvalds1da177e2005-04-16 15:20:36 -070012 * 28-Sep-2004 BJD Fixed ECC placement for Hardware mode
13 * 12-Oct-2004 BJD Fixed errors in use of platform data
Ben Dooks3e4ef3b2005-03-17 11:31:30 +000014 * 18-Feb-2005 BJD Fix sparse errors
15 * 14-Mar-2005 BJD Applied tglx's code reduction patch
Ben Dooksa4f957f2005-06-20 12:48:25 +010016 * 02-May-2005 BJD Fixed s3c2440 support
17 * 02-May-2005 BJD Reduced hwcontrol decode
18 * 20-Jun-2005 BJD Updated s3c2440 support, fixed timing bug
Ben Dooksfb8d82a2005-07-06 21:05:10 +010019 * 08-Jul-2005 BJD Fix OOPS when no platform data supplied
Ben Dookscfd320f2005-10-20 22:22:58 +010020 * 20-Oct-2005 BJD Fix timing calculation bug
Ben Dooksd1fef3c2006-06-19 09:29:38 +010021 * 14-Jan-2006 BJD Allow clock to be stopped when idle
Linus Torvalds1da177e2005-04-16 15:20:36 -070022 *
Ben Dooksd1fef3c2006-06-19 09:29:38 +010023 * $Id: s3c2410.c,v 1.23 2006/04/01 18:06:29 bjd Exp $
Linus Torvalds1da177e2005-04-16 15:20:36 -070024 *
25 * This program is free software; you can redistribute it and/or modify
26 * it under the terms of the GNU General Public License as published by
27 * the Free Software Foundation; either version 2 of the License, or
28 * (at your option) any later version.
29 *
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
34 *
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software
37 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
38*/
39
Linus Torvalds1da177e2005-04-16 15:20:36 -070040#ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
41#define DEBUG
42#endif
43
44#include <linux/module.h>
45#include <linux/types.h>
46#include <linux/init.h>
47#include <linux/kernel.h>
48#include <linux/string.h>
49#include <linux/ioport.h>
Russell Kingd052d1b2005-10-29 19:07:23 +010050#include <linux/platform_device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070051#include <linux/delay.h>
52#include <linux/err.h>
Tim Schmielau4e57b682005-10-30 15:03:48 -080053#include <linux/slab.h>
Russell Kingf8ce2542006-01-07 16:15:52 +000054#include <linux/clk.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070055
56#include <linux/mtd/mtd.h>
57#include <linux/mtd/nand.h>
58#include <linux/mtd/nand_ecc.h>
59#include <linux/mtd/partitions.h>
60
61#include <asm/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070062
Ben Dooksb7a70182007-07-24 13:37:27 +010063#include <asm/plat-s3c/regs-nand.h>
64#include <asm/plat-s3c/nand.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070065
Linus Torvalds1da177e2005-04-16 15:20:36 -070066#ifdef CONFIG_MTD_NAND_S3C2410_HWECC
67static int hardware_ecc = 1;
68#else
69static int hardware_ecc = 0;
70#endif
71
Ben Dooksd1fef3c2006-06-19 09:29:38 +010072#ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
73static int clock_stop = 1;
74#else
75static const int clock_stop = 0;
76#endif
77
78
Linus Torvalds1da177e2005-04-16 15:20:36 -070079/* new oob placement block for use with hardware ecc generation
80 */
81
Thomas Gleixner5bd34c02006-05-27 22:16:10 +020082static struct nand_ecclayout nand_hw_eccoob = {
David Woodhousee0c7d762006-05-13 18:07:53 +010083 .eccbytes = 3,
84 .eccpos = {0, 1, 2},
85 .oobfree = {{8, 8}}
Linus Torvalds1da177e2005-04-16 15:20:36 -070086};
87
88/* controller and mtd information */
89
90struct s3c2410_nand_info;
91
92struct s3c2410_nand_mtd {
93 struct mtd_info mtd;
94 struct nand_chip chip;
95 struct s3c2410_nand_set *set;
96 struct s3c2410_nand_info *info;
97 int scan_res;
98};
99
Ben Dooks2c06a082006-06-27 14:35:46 +0100100enum s3c_cpu_type {
101 TYPE_S3C2410,
102 TYPE_S3C2412,
103 TYPE_S3C2440,
104};
105
Linus Torvalds1da177e2005-04-16 15:20:36 -0700106/* overview of the s3c2410 nand state */
107
108struct s3c2410_nand_info {
109 /* mtd info */
110 struct nand_hw_control controller;
111 struct s3c2410_nand_mtd *mtds;
112 struct s3c2410_platform_nand *platform;
113
114 /* device info */
115 struct device *device;
116 struct resource *area;
117 struct clk *clk;
Ben Dooksfdf2fd52005-02-18 14:46:15 +0000118 void __iomem *regs;
Ben Dooks2c06a082006-06-27 14:35:46 +0100119 void __iomem *sel_reg;
120 int sel_bit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121 int mtd_count;
Ben Dooks09160832008-04-15 11:36:18 +0100122 unsigned long save_sel;
Ben Dooks03680b12007-11-19 23:28:07 +0000123
Ben Dooks2c06a082006-06-27 14:35:46 +0100124 enum s3c_cpu_type cpu_type;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125};
126
127/* conversion functions */
128
129static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
130{
131 return container_of(mtd, struct s3c2410_nand_mtd, mtd);
132}
133
134static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
135{
136 return s3c2410_nand_mtd_toours(mtd)->info;
137}
138
Russell King3ae5eae2005-11-09 22:32:44 +0000139static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140{
Russell King3ae5eae2005-11-09 22:32:44 +0000141 return platform_get_drvdata(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700142}
143
Russell King3ae5eae2005-11-09 22:32:44 +0000144static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700145{
Russell King3ae5eae2005-11-09 22:32:44 +0000146 return dev->dev.platform_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147}
148
Ben Dooksd1fef3c2006-06-19 09:29:38 +0100149static inline int allow_clk_stop(struct s3c2410_nand_info *info)
150{
151 return clock_stop;
152}
153
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154/* timing calculations */
155
Ben Dookscfd320f2005-10-20 22:22:58 +0100156#define NS_IN_KHZ 1000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700157
Ben Dooks2c06a082006-06-27 14:35:46 +0100158static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700159{
160 int result;
161
Ben Dookscfd320f2005-10-20 22:22:58 +0100162 result = (wanted * clk) / NS_IN_KHZ;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163 result++;
164
165 pr_debug("result %d from %ld, %d\n", result, clk, wanted);
166
167 if (result > max) {
David Woodhousee0c7d762006-05-13 18:07:53 +0100168 printk("%d ns is too big for current clock rate %ld\n", wanted, clk);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700169 return -1;
170 }
171
172 if (result < 1)
173 result = 1;
174
175 return result;
176}
177
Ben Dookscfd320f2005-10-20 22:22:58 +0100178#define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700179
180/* controller setup */
181
Ben Dooks2c06a082006-06-27 14:35:46 +0100182static int s3c2410_nand_inithw(struct s3c2410_nand_info *info,
183 struct platform_device *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700184{
Russell King3ae5eae2005-11-09 22:32:44 +0000185 struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186 unsigned long clkrate = clk_get_rate(info->clk);
Ben Dooks2c06a082006-06-27 14:35:46 +0100187 int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
Ben Dookscfd320f2005-10-20 22:22:58 +0100188 int tacls, twrph0, twrph1;
Ben Dooks2c06a082006-06-27 14:35:46 +0100189 unsigned long cfg = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700190
191 /* calculate the timing information for the controller */
192
Ben Dookscfd320f2005-10-20 22:22:58 +0100193 clkrate /= 1000; /* turn clock into kHz for ease of use */
194
Linus Torvalds1da177e2005-04-16 15:20:36 -0700195 if (plat != NULL) {
Ben Dooks2c06a082006-06-27 14:35:46 +0100196 tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max);
197 twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8);
198 twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700199 } else {
200 /* default timings */
Ben Dooks2c06a082006-06-27 14:35:46 +0100201 tacls = tacls_max;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202 twrph0 = 8;
203 twrph1 = 8;
204 }
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000205
Linus Torvalds1da177e2005-04-16 15:20:36 -0700206 if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
Ben Dooks99974c62006-06-21 15:43:05 +0100207 dev_err(info->device, "cannot get suitable timings\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700208 return -EINVAL;
209 }
210
Ben Dooks99974c62006-06-21 15:43:05 +0100211 dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
David Woodhousee0c7d762006-05-13 18:07:53 +0100212 tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700213
Ben Dooks2c06a082006-06-27 14:35:46 +0100214 switch (info->cpu_type) {
215 case TYPE_S3C2410:
David Woodhousee0c7d762006-05-13 18:07:53 +0100216 cfg = S3C2410_NFCONF_EN;
217 cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
218 cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
219 cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
Ben Dooks2c06a082006-06-27 14:35:46 +0100220 break;
221
222 case TYPE_S3C2440:
223 case TYPE_S3C2412:
David Woodhousee0c7d762006-05-13 18:07:53 +0100224 cfg = S3C2440_NFCONF_TACLS(tacls - 1);
225 cfg |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
226 cfg |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
Ben Dooksd1fef3c2006-06-19 09:29:38 +0100227
228 /* enable the controller and de-assert nFCE */
229
Ben Dooks2c06a082006-06-27 14:35:46 +0100230 writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
Ben Dooksa4f957f2005-06-20 12:48:25 +0100231 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232
Ben Dooks99974c62006-06-21 15:43:05 +0100233 dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700234
235 writel(cfg, info->regs + S3C2410_NFCONF);
236 return 0;
237}
238
239/* select chip */
240
241static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
242{
243 struct s3c2410_nand_info *info;
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000244 struct s3c2410_nand_mtd *nmtd;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245 struct nand_chip *this = mtd->priv;
246 unsigned long cur;
247
248 nmtd = this->priv;
249 info = nmtd->info;
250
Ben Dooksd1fef3c2006-06-19 09:29:38 +0100251 if (chip != -1 && allow_clk_stop(info))
252 clk_enable(info->clk);
253
Ben Dooks2c06a082006-06-27 14:35:46 +0100254 cur = readl(info->sel_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700255
256 if (chip == -1) {
Ben Dooks2c06a082006-06-27 14:35:46 +0100257 cur |= info->sel_bit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258 } else {
Ben Dooksfb8d82a2005-07-06 21:05:10 +0100259 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
Ben Dooks99974c62006-06-21 15:43:05 +0100260 dev_err(info->device, "invalid chip %d\n", chip);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700261 return;
262 }
263
264 if (info->platform != NULL) {
265 if (info->platform->select_chip != NULL)
David Woodhousee0c7d762006-05-13 18:07:53 +0100266 (info->platform->select_chip) (nmtd->set, chip);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267 }
268
Ben Dooks2c06a082006-06-27 14:35:46 +0100269 cur &= ~info->sel_bit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700270 }
271
Ben Dooks2c06a082006-06-27 14:35:46 +0100272 writel(cur, info->sel_reg);
Ben Dooksd1fef3c2006-06-19 09:29:38 +0100273
274 if (chip == -1 && allow_clk_stop(info))
275 clk_disable(info->clk);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700276}
277
Ben Dooksad3b5fb2006-06-19 09:43:23 +0100278/* s3c2410_nand_hwcontrol
Ben Dooksa4f957f2005-06-20 12:48:25 +0100279 *
Ben Dooksad3b5fb2006-06-19 09:43:23 +0100280 * Issue command and address cycles to the chip
Ben Dooksa4f957f2005-06-20 12:48:25 +0100281*/
Linus Torvalds1da177e2005-04-16 15:20:36 -0700282
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200283static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd,
David Woodhousef9068872006-06-10 00:53:16 +0100284 unsigned int ctrl)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285{
286 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
David Woodhousec9ac5972006-11-30 08:17:38 +0000287
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200288 if (cmd == NAND_CMD_NONE)
289 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700290
David Woodhousef9068872006-06-10 00:53:16 +0100291 if (ctrl & NAND_CLE)
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200292 writeb(cmd, info->regs + S3C2410_NFCMD);
293 else
294 writeb(cmd, info->regs + S3C2410_NFADDR);
Ben Dooksa4f957f2005-06-20 12:48:25 +0100295}
296
297/* command and control functions */
298
David Woodhousef9068872006-06-10 00:53:16 +0100299static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd,
300 unsigned int ctrl)
Ben Dooksa4f957f2005-06-20 12:48:25 +0100301{
302 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
Ben Dooksa4f957f2005-06-20 12:48:25 +0100303
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200304 if (cmd == NAND_CMD_NONE)
305 return;
Ben Dooksa4f957f2005-06-20 12:48:25 +0100306
David Woodhousef9068872006-06-10 00:53:16 +0100307 if (ctrl & NAND_CLE)
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200308 writeb(cmd, info->regs + S3C2440_NFCMD);
309 else
310 writeb(cmd, info->regs + S3C2440_NFADDR);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700311}
312
Linus Torvalds1da177e2005-04-16 15:20:36 -0700313/* s3c2410_nand_devready()
314 *
315 * returns 0 if the nand is busy, 1 if it is ready
316*/
317
318static int s3c2410_nand_devready(struct mtd_info *mtd)
319{
320 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321 return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
322}
323
Ben Dooks2c06a082006-06-27 14:35:46 +0100324static int s3c2440_nand_devready(struct mtd_info *mtd)
325{
326 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
327 return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
328}
329
330static int s3c2412_nand_devready(struct mtd_info *mtd)
331{
332 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
333 return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY;
334}
335
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336/* ECC handling functions */
337
Ben Dooks2c06a082006-06-27 14:35:46 +0100338static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
339 u_char *read_ecc, u_char *calc_ecc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340{
Ben Dooksa2593242007-02-02 16:59:33 +0000341 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
342 unsigned int diff0, diff1, diff2;
343 unsigned int bit, byte;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700344
Ben Dooksa2593242007-02-02 16:59:33 +0000345 pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700346
Ben Dooksa2593242007-02-02 16:59:33 +0000347 diff0 = read_ecc[0] ^ calc_ecc[0];
348 diff1 = read_ecc[1] ^ calc_ecc[1];
349 diff2 = read_ecc[2] ^ calc_ecc[2];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700350
Ben Dooksa2593242007-02-02 16:59:33 +0000351 pr_debug("%s: rd %02x%02x%02x calc %02x%02x%02x diff %02x%02x%02x\n",
352 __func__,
353 read_ecc[0], read_ecc[1], read_ecc[2],
354 calc_ecc[0], calc_ecc[1], calc_ecc[2],
355 diff0, diff1, diff2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356
Ben Dooksa2593242007-02-02 16:59:33 +0000357 if (diff0 == 0 && diff1 == 0 && diff2 == 0)
358 return 0; /* ECC is ok */
359
Ben Dooksc45c6c62008-04-15 11:36:20 +0100360 /* sometimes people do not think about using the ECC, so check
361 * to see if we have an 0xff,0xff,0xff read ECC and then ignore
362 * the error, on the assumption that this is an un-eccd page.
363 */
364 if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff
365 && info->platform->ignore_unset_ecc)
366 return 0;
367
Ben Dooksa2593242007-02-02 16:59:33 +0000368 /* Can we correct this ECC (ie, one row and column change).
369 * Note, this is similar to the 256 error code on smartmedia */
370
371 if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 &&
372 ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 &&
373 ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) {
374 /* calculate the bit position of the error */
375
Matt Reimerd0bf3792007-10-18 18:02:43 -0700376 bit = ((diff2 >> 3) & 1) |
377 ((diff2 >> 4) & 2) |
378 ((diff2 >> 5) & 4);
Ben Dooksa2593242007-02-02 16:59:33 +0000379
380 /* calculate the byte position of the error */
381
Matt Reimerd0bf3792007-10-18 18:02:43 -0700382 byte = ((diff2 << 7) & 0x100) |
383 ((diff1 << 0) & 0x80) |
384 ((diff1 << 1) & 0x40) |
385 ((diff1 << 2) & 0x20) |
386 ((diff1 << 3) & 0x10) |
387 ((diff0 >> 4) & 0x08) |
388 ((diff0 >> 3) & 0x04) |
389 ((diff0 >> 2) & 0x02) |
390 ((diff0 >> 1) & 0x01);
Ben Dooksa2593242007-02-02 16:59:33 +0000391
392 dev_dbg(info->device, "correcting error bit %d, byte %d\n",
393 bit, byte);
394
395 dat[byte] ^= (1 << bit);
396 return 1;
397 }
398
399 /* if there is only one bit difference in the ECC, then
400 * one of only a row or column parity has changed, which
401 * means the error is most probably in the ECC itself */
402
403 diff0 |= (diff1 << 8);
404 diff0 |= (diff2 << 16);
405
406 if ((diff0 & ~(1<<fls(diff0))) == 0)
407 return 1;
408
Matt Reimer4fac9f62007-10-18 18:02:44 -0700409 return -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700410}
411
Ben Dooksa4f957f2005-06-20 12:48:25 +0100412/* ECC functions
413 *
414 * These allow the s3c2410 and s3c2440 to use the controller's ECC
415 * generator block to ECC the data as it passes through]
416*/
417
Linus Torvalds1da177e2005-04-16 15:20:36 -0700418static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
419{
420 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
421 unsigned long ctrl;
422
423 ctrl = readl(info->regs + S3C2410_NFCONF);
424 ctrl |= S3C2410_NFCONF_INITECC;
425 writel(ctrl, info->regs + S3C2410_NFCONF);
426}
427
Matthieu CASTET4f659922007-02-13 12:30:38 +0100428static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode)
429{
430 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
431 unsigned long ctrl;
432
433 ctrl = readl(info->regs + S3C2440_NFCONT);
434 writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC, info->regs + S3C2440_NFCONT);
435}
436
Ben Dooksa4f957f2005-06-20 12:48:25 +0100437static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode)
438{
439 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
440 unsigned long ctrl;
441
442 ctrl = readl(info->regs + S3C2440_NFCONT);
443 writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
444}
445
David Woodhousee0c7d762006-05-13 18:07:53 +0100446static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447{
448 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
449
450 ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
451 ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
452 ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
453
Ben Dooksa2593242007-02-02 16:59:33 +0000454 pr_debug("%s: returning ecc %02x%02x%02x\n", __func__,
455 ecc_code[0], ecc_code[1], ecc_code[2]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700456
457 return 0;
458}
459
Matthieu CASTET4f659922007-02-13 12:30:38 +0100460static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
461{
462 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
463 unsigned long ecc = readl(info->regs + S3C2412_NFMECC0);
464
465 ecc_code[0] = ecc;
466 ecc_code[1] = ecc >> 8;
467 ecc_code[2] = ecc >> 16;
468
469 pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]);
470
471 return 0;
472}
473
David Woodhousee0c7d762006-05-13 18:07:53 +0100474static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
Ben Dooksa4f957f2005-06-20 12:48:25 +0100475{
476 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
477 unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
478
479 ecc_code[0] = ecc;
480 ecc_code[1] = ecc >> 8;
481 ecc_code[2] = ecc >> 16;
482
Ben Dooks71d54f32008-04-15 11:36:19 +0100483 pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff);
Ben Dooksa4f957f2005-06-20 12:48:25 +0100484
485 return 0;
486}
487
Ben Dooksa4f957f2005-06-20 12:48:25 +0100488/* over-ride the standard functions for a little more speed. We can
489 * use read/write block to move the data buffers to/from the controller
490*/
Linus Torvalds1da177e2005-04-16 15:20:36 -0700491
492static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
493{
494 struct nand_chip *this = mtd->priv;
495 readsb(this->IO_ADDR_R, buf, len);
496}
497
Matt Reimerb773bb22007-10-18 17:43:07 -0700498static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
499{
500 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
501 readsl(info->regs + S3C2440_NFDATA, buf, len / 4);
502}
503
David Woodhousee0c7d762006-05-13 18:07:53 +0100504static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700505{
506 struct nand_chip *this = mtd->priv;
507 writesb(this->IO_ADDR_W, buf, len);
508}
509
Matt Reimerb773bb22007-10-18 17:43:07 -0700510static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
511{
512 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
513 writesl(info->regs + S3C2440_NFDATA, buf, len / 4);
514}
515
Linus Torvalds1da177e2005-04-16 15:20:36 -0700516/* device management functions */
517
Russell King3ae5eae2005-11-09 22:32:44 +0000518static int s3c2410_nand_remove(struct platform_device *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700519{
Russell King3ae5eae2005-11-09 22:32:44 +0000520 struct s3c2410_nand_info *info = to_nand_info(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700521
Russell King3ae5eae2005-11-09 22:32:44 +0000522 platform_set_drvdata(pdev, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700523
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000524 if (info == NULL)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700525 return 0;
526
527 /* first thing we need to do is release all our mtds
528 * and their partitions, then go through freeing the
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000529 * resources used
Linus Torvalds1da177e2005-04-16 15:20:36 -0700530 */
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000531
Linus Torvalds1da177e2005-04-16 15:20:36 -0700532 if (info->mtds != NULL) {
533 struct s3c2410_nand_mtd *ptr = info->mtds;
534 int mtdno;
535
536 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
537 pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
538 nand_release(&ptr->mtd);
539 }
540
541 kfree(info->mtds);
542 }
543
544 /* free the common resources */
545
546 if (info->clk != NULL && !IS_ERR(info->clk)) {
Ben Dooksd1fef3c2006-06-19 09:29:38 +0100547 if (!allow_clk_stop(info))
548 clk_disable(info->clk);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700549 clk_put(info->clk);
550 }
551
552 if (info->regs != NULL) {
553 iounmap(info->regs);
554 info->regs = NULL;
555 }
556
557 if (info->area != NULL) {
558 release_resource(info->area);
559 kfree(info->area);
560 info->area = NULL;
561 }
562
563 kfree(info);
564
565 return 0;
566}
567
568#ifdef CONFIG_MTD_PARTITIONS
569static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
570 struct s3c2410_nand_mtd *mtd,
571 struct s3c2410_nand_set *set)
572{
573 if (set == NULL)
574 return add_mtd_device(&mtd->mtd);
575
576 if (set->nr_partitions > 0 && set->partitions != NULL) {
David Woodhousee0c7d762006-05-13 18:07:53 +0100577 return add_mtd_partitions(&mtd->mtd, set->partitions, set->nr_partitions);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700578 }
579
580 return add_mtd_device(&mtd->mtd);
581}
582#else
583static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
584 struct s3c2410_nand_mtd *mtd,
585 struct s3c2410_nand_set *set)
586{
587 return add_mtd_device(&mtd->mtd);
588}
589#endif
590
591/* s3c2410_nand_init_chip
592 *
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000593 * init a single instance of an chip
Linus Torvalds1da177e2005-04-16 15:20:36 -0700594*/
595
596static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
597 struct s3c2410_nand_mtd *nmtd,
598 struct s3c2410_nand_set *set)
599{
600 struct nand_chip *chip = &nmtd->chip;
Ben Dooks2c06a082006-06-27 14:35:46 +0100601 void __iomem *regs = info->regs;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700602
Linus Torvalds1da177e2005-04-16 15:20:36 -0700603 chip->write_buf = s3c2410_nand_write_buf;
604 chip->read_buf = s3c2410_nand_read_buf;
605 chip->select_chip = s3c2410_nand_select_chip;
606 chip->chip_delay = 50;
607 chip->priv = nmtd;
608 chip->options = 0;
609 chip->controller = &info->controller;
610
Ben Dooks2c06a082006-06-27 14:35:46 +0100611 switch (info->cpu_type) {
612 case TYPE_S3C2410:
613 chip->IO_ADDR_W = regs + S3C2410_NFDATA;
614 info->sel_reg = regs + S3C2410_NFCONF;
615 info->sel_bit = S3C2410_NFCONF_nFCE;
616 chip->cmd_ctrl = s3c2410_nand_hwcontrol;
617 chip->dev_ready = s3c2410_nand_devready;
618 break;
619
620 case TYPE_S3C2440:
621 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
622 info->sel_reg = regs + S3C2440_NFCONT;
623 info->sel_bit = S3C2440_NFCONT_nFCE;
624 chip->cmd_ctrl = s3c2440_nand_hwcontrol;
625 chip->dev_ready = s3c2440_nand_devready;
Matt Reimerb773bb22007-10-18 17:43:07 -0700626 chip->read_buf = s3c2440_nand_read_buf;
627 chip->write_buf = s3c2440_nand_write_buf;
Ben Dooks2c06a082006-06-27 14:35:46 +0100628 break;
629
630 case TYPE_S3C2412:
631 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
632 info->sel_reg = regs + S3C2440_NFCONT;
633 info->sel_bit = S3C2412_NFCONT_nFCE0;
634 chip->cmd_ctrl = s3c2440_nand_hwcontrol;
635 chip->dev_ready = s3c2412_nand_devready;
636
637 if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT)
638 dev_info(info->device, "System booted from NAND\n");
639
640 break;
641 }
642
643 chip->IO_ADDR_R = chip->IO_ADDR_W;
Ben Dooksa4f957f2005-06-20 12:48:25 +0100644
Linus Torvalds1da177e2005-04-16 15:20:36 -0700645 nmtd->info = info;
646 nmtd->mtd.priv = chip;
David Woodhouse552d9202006-05-14 01:20:46 +0100647 nmtd->mtd.owner = THIS_MODULE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700648 nmtd->set = set;
649
650 if (hardware_ecc) {
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200651 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
Ben Dooks2c06a082006-06-27 14:35:46 +0100652 chip->ecc.correct = s3c2410_nand_correct_data;
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200653 chip->ecc.mode = NAND_ECC_HW;
Ben Dooksa4f957f2005-06-20 12:48:25 +0100654
Ben Dooks2c06a082006-06-27 14:35:46 +0100655 switch (info->cpu_type) {
656 case TYPE_S3C2410:
657 chip->ecc.hwctl = s3c2410_nand_enable_hwecc;
658 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
659 break;
660
661 case TYPE_S3C2412:
Matthieu CASTET4f659922007-02-13 12:30:38 +0100662 chip->ecc.hwctl = s3c2412_nand_enable_hwecc;
663 chip->ecc.calculate = s3c2412_nand_calculate_ecc;
664 break;
665
Ben Dooks2c06a082006-06-27 14:35:46 +0100666 case TYPE_S3C2440:
667 chip->ecc.hwctl = s3c2440_nand_enable_hwecc;
668 chip->ecc.calculate = s3c2440_nand_calculate_ecc;
669 break;
670
Ben Dooksa4f957f2005-06-20 12:48:25 +0100671 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700672 } else {
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200673 chip->ecc.mode = NAND_ECC_SOFT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700674 }
Ben Dooks1c21ab62008-04-15 11:36:21 +0100675
676 if (set->ecc_layout != NULL)
677 chip->ecc.layout = set->ecc_layout;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700678}
679
Ben Dooks71d54f32008-04-15 11:36:19 +0100680/* s3c2410_nand_update_chip
681 *
682 * post-probe chip update, to change any items, such as the
683 * layout for large page nand
684 */
685
686static void s3c2410_nand_update_chip(struct s3c2410_nand_info *info,
687 struct s3c2410_nand_mtd *nmtd)
688{
689 struct nand_chip *chip = &nmtd->chip;
690
691 printk("%s: chip %p: %d\n", __func__, chip, chip->page_shift);
692
693 if (hardware_ecc) {
694 /* change the behaviour depending on wether we are using
695 * the large or small page nand device */
696
697 if (chip->page_shift > 10) {
698 chip->ecc.size = 256;
699 chip->ecc.bytes = 3;
700 } else {
701 chip->ecc.size = 512;
702 chip->ecc.bytes = 3;
703 chip->ecc.layout = &nand_hw_eccoob;
704 }
705 }
706}
707
Linus Torvalds1da177e2005-04-16 15:20:36 -0700708/* s3c2410_nand_probe
709 *
710 * called by device layer when it finds a device matching
711 * one our driver can handled. This code checks to see if
712 * it can allocate all necessary resources then calls the
713 * nand layer to look for devices
714*/
715
Ben Dooks2c06a082006-06-27 14:35:46 +0100716static int s3c24xx_nand_probe(struct platform_device *pdev,
717 enum s3c_cpu_type cpu_type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700718{
Russell King3ae5eae2005-11-09 22:32:44 +0000719 struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700720 struct s3c2410_nand_info *info;
721 struct s3c2410_nand_mtd *nmtd;
722 struct s3c2410_nand_set *sets;
723 struct resource *res;
724 int err = 0;
725 int size;
726 int nr_sets;
727 int setno;
728
Russell King3ae5eae2005-11-09 22:32:44 +0000729 pr_debug("s3c2410_nand_probe(%p)\n", pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700730
731 info = kmalloc(sizeof(*info), GFP_KERNEL);
732 if (info == NULL) {
Russell King3ae5eae2005-11-09 22:32:44 +0000733 dev_err(&pdev->dev, "no memory for flash info\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700734 err = -ENOMEM;
735 goto exit_error;
736 }
737
738 memzero(info, sizeof(*info));
Russell King3ae5eae2005-11-09 22:32:44 +0000739 platform_set_drvdata(pdev, info);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700740
741 spin_lock_init(&info->controller.lock);
Ben Dooksa4f957f2005-06-20 12:48:25 +0100742 init_waitqueue_head(&info->controller.wq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700743
744 /* get the clock source and enable it */
745
Russell King3ae5eae2005-11-09 22:32:44 +0000746 info->clk = clk_get(&pdev->dev, "nand");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700747 if (IS_ERR(info->clk)) {
Joe Perches898eb712007-10-18 03:06:30 -0700748 dev_err(&pdev->dev, "failed to get clock\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700749 err = -ENOENT;
750 goto exit_error;
751 }
752
Linus Torvalds1da177e2005-04-16 15:20:36 -0700753 clk_enable(info->clk);
754
755 /* allocate and map the resource */
756
Ben Dooksa4f957f2005-06-20 12:48:25 +0100757 /* currently we assume we have the one resource */
758 res = pdev->resource;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700759 size = res->end - res->start + 1;
760
761 info->area = request_mem_region(res->start, size, pdev->name);
762
763 if (info->area == NULL) {
Russell King3ae5eae2005-11-09 22:32:44 +0000764 dev_err(&pdev->dev, "cannot reserve register region\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700765 err = -ENOENT;
766 goto exit_error;
767 }
768
Russell King3ae5eae2005-11-09 22:32:44 +0000769 info->device = &pdev->dev;
Ben Dooksa4f957f2005-06-20 12:48:25 +0100770 info->platform = plat;
771 info->regs = ioremap(res->start, size);
Ben Dooks2c06a082006-06-27 14:35:46 +0100772 info->cpu_type = cpu_type;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700773
774 if (info->regs == NULL) {
Russell King3ae5eae2005-11-09 22:32:44 +0000775 dev_err(&pdev->dev, "cannot reserve register region\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700776 err = -EIO;
777 goto exit_error;
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000778 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700779
Russell King3ae5eae2005-11-09 22:32:44 +0000780 dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700781
782 /* initialise the hardware */
783
Russell King3ae5eae2005-11-09 22:32:44 +0000784 err = s3c2410_nand_inithw(info, pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700785 if (err != 0)
786 goto exit_error;
787
788 sets = (plat != NULL) ? plat->sets : NULL;
789 nr_sets = (plat != NULL) ? plat->nr_sets : 1;
790
791 info->mtd_count = nr_sets;
792
793 /* allocate our information */
794
795 size = nr_sets * sizeof(*info->mtds);
796 info->mtds = kmalloc(size, GFP_KERNEL);
797 if (info->mtds == NULL) {
Russell King3ae5eae2005-11-09 22:32:44 +0000798 dev_err(&pdev->dev, "failed to allocate mtd storage\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700799 err = -ENOMEM;
800 goto exit_error;
801 }
802
803 memzero(info->mtds, size);
804
805 /* initialise all possible chips */
806
807 nmtd = info->mtds;
808
809 for (setno = 0; setno < nr_sets; setno++, nmtd++) {
David Woodhousee0c7d762006-05-13 18:07:53 +0100810 pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd, info);
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000811
Linus Torvalds1da177e2005-04-16 15:20:36 -0700812 s3c2410_nand_init_chip(info, nmtd, sets);
813
Ben Dooks71d54f32008-04-15 11:36:19 +0100814 nmtd->scan_res = nand_scan_ident(&nmtd->mtd,
815 (sets) ? sets->nr_chips : 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700816
817 if (nmtd->scan_res == 0) {
Ben Dooks71d54f32008-04-15 11:36:19 +0100818 s3c2410_nand_update_chip(info, nmtd);
819 nand_scan_tail(&nmtd->mtd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700820 s3c2410_nand_add_partition(info, nmtd, sets);
821 }
822
823 if (sets != NULL)
824 sets++;
825 }
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000826
Ben Dooksd1fef3c2006-06-19 09:29:38 +0100827 if (allow_clk_stop(info)) {
828 dev_info(&pdev->dev, "clock idle support enabled\n");
829 clk_disable(info->clk);
830 }
831
Linus Torvalds1da177e2005-04-16 15:20:36 -0700832 pr_debug("initialised ok\n");
833 return 0;
834
835 exit_error:
Russell King3ae5eae2005-11-09 22:32:44 +0000836 s3c2410_nand_remove(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700837
838 if (err == 0)
839 err = -EINVAL;
840 return err;
841}
842
Ben Dooksd1fef3c2006-06-19 09:29:38 +0100843/* PM Support */
844#ifdef CONFIG_PM
845
846static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
847{
848 struct s3c2410_nand_info *info = platform_get_drvdata(dev);
849
850 if (info) {
Ben Dooks09160832008-04-15 11:36:18 +0100851 info->save_sel = readl(info->sel_reg);
Ben Dooks03680b12007-11-19 23:28:07 +0000852
853 /* For the moment, we must ensure nFCE is high during
854 * the time we are suspended. This really should be
855 * handled by suspending the MTDs we are using, but
856 * that is currently not the case. */
857
Ben Dooks09160832008-04-15 11:36:18 +0100858 writel(info->save_sel | info->sel_bit, info->sel_reg);
Ben Dooks03680b12007-11-19 23:28:07 +0000859
Ben Dooksd1fef3c2006-06-19 09:29:38 +0100860 if (!allow_clk_stop(info))
861 clk_disable(info->clk);
862 }
863
864 return 0;
865}
866
867static int s3c24xx_nand_resume(struct platform_device *dev)
868{
869 struct s3c2410_nand_info *info = platform_get_drvdata(dev);
Ben Dooks09160832008-04-15 11:36:18 +0100870 unsigned long sel;
Ben Dooksd1fef3c2006-06-19 09:29:38 +0100871
872 if (info) {
873 clk_enable(info->clk);
874 s3c2410_nand_inithw(info, dev);
875
Ben Dooks03680b12007-11-19 23:28:07 +0000876 /* Restore the state of the nFCE line. */
877
Ben Dooks09160832008-04-15 11:36:18 +0100878 sel = readl(info->sel_reg);
879 sel &= ~info->sel_bit;
880 sel |= info->save_sel & info->sel_bit;
881 writel(sel, info->sel_reg);
Ben Dooks03680b12007-11-19 23:28:07 +0000882
Ben Dooksd1fef3c2006-06-19 09:29:38 +0100883 if (allow_clk_stop(info))
884 clk_disable(info->clk);
885 }
886
887 return 0;
888}
889
890#else
891#define s3c24xx_nand_suspend NULL
892#define s3c24xx_nand_resume NULL
893#endif
894
Ben Dooksa4f957f2005-06-20 12:48:25 +0100895/* driver device registration */
896
Russell King3ae5eae2005-11-09 22:32:44 +0000897static int s3c2410_nand_probe(struct platform_device *dev)
Ben Dooksa4f957f2005-06-20 12:48:25 +0100898{
Ben Dooks2c06a082006-06-27 14:35:46 +0100899 return s3c24xx_nand_probe(dev, TYPE_S3C2410);
Ben Dooksa4f957f2005-06-20 12:48:25 +0100900}
901
Russell King3ae5eae2005-11-09 22:32:44 +0000902static int s3c2440_nand_probe(struct platform_device *dev)
Ben Dooksa4f957f2005-06-20 12:48:25 +0100903{
Ben Dooks2c06a082006-06-27 14:35:46 +0100904 return s3c24xx_nand_probe(dev, TYPE_S3C2440);
905}
906
907static int s3c2412_nand_probe(struct platform_device *dev)
908{
909 return s3c24xx_nand_probe(dev, TYPE_S3C2412);
Ben Dooksa4f957f2005-06-20 12:48:25 +0100910}
911
Russell King3ae5eae2005-11-09 22:32:44 +0000912static struct platform_driver s3c2410_nand_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700913 .probe = s3c2410_nand_probe,
914 .remove = s3c2410_nand_remove,
Ben Dooksd1fef3c2006-06-19 09:29:38 +0100915 .suspend = s3c24xx_nand_suspend,
916 .resume = s3c24xx_nand_resume,
Russell King3ae5eae2005-11-09 22:32:44 +0000917 .driver = {
918 .name = "s3c2410-nand",
919 .owner = THIS_MODULE,
920 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700921};
922
Russell King3ae5eae2005-11-09 22:32:44 +0000923static struct platform_driver s3c2440_nand_driver = {
Ben Dooksa4f957f2005-06-20 12:48:25 +0100924 .probe = s3c2440_nand_probe,
925 .remove = s3c2410_nand_remove,
Ben Dooksd1fef3c2006-06-19 09:29:38 +0100926 .suspend = s3c24xx_nand_suspend,
927 .resume = s3c24xx_nand_resume,
Russell King3ae5eae2005-11-09 22:32:44 +0000928 .driver = {
929 .name = "s3c2440-nand",
930 .owner = THIS_MODULE,
931 },
Ben Dooksa4f957f2005-06-20 12:48:25 +0100932};
933
Ben Dooks2c06a082006-06-27 14:35:46 +0100934static struct platform_driver s3c2412_nand_driver = {
935 .probe = s3c2412_nand_probe,
936 .remove = s3c2410_nand_remove,
937 .suspend = s3c24xx_nand_suspend,
938 .resume = s3c24xx_nand_resume,
939 .driver = {
940 .name = "s3c2412-nand",
941 .owner = THIS_MODULE,
942 },
943};
944
Linus Torvalds1da177e2005-04-16 15:20:36 -0700945static int __init s3c2410_nand_init(void)
946{
Ben Dooksa4f957f2005-06-20 12:48:25 +0100947 printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n");
948
Ben Dooks2c06a082006-06-27 14:35:46 +0100949 platform_driver_register(&s3c2412_nand_driver);
Russell King3ae5eae2005-11-09 22:32:44 +0000950 platform_driver_register(&s3c2440_nand_driver);
951 return platform_driver_register(&s3c2410_nand_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700952}
953
954static void __exit s3c2410_nand_exit(void)
955{
Ben Dooks2c06a082006-06-27 14:35:46 +0100956 platform_driver_unregister(&s3c2412_nand_driver);
Russell King3ae5eae2005-11-09 22:32:44 +0000957 platform_driver_unregister(&s3c2440_nand_driver);
958 platform_driver_unregister(&s3c2410_nand_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700959}
960
961module_init(s3c2410_nand_init);
962module_exit(s3c2410_nand_exit);
963
964MODULE_LICENSE("GPL");
965MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
Ben Dooksa4f957f2005-06-20 12:48:25 +0100966MODULE_DESCRIPTION("S3C24XX MTD NAND driver");
Kay Sievers1ff18422008-04-18 13:44:27 -0700967MODULE_ALIAS("platform:s3c2410-nand");
968MODULE_ALIAS("platform:s3c2412-nand");
969MODULE_ALIAS("platform:s3c2440-nand");