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gerrit-public.fairphone.software / kernel / msm-4.19 / 2995a9e7094716bba08ca05f7a58e56d03ea4f9a / . / arch / arm / boot / dts / omap3.dtsi
blob: e31ea5efb1632bd6ac6e5defa5d2432e3c90e157 [file] [log] [blame]
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]1/*
2 * Device Tree Source for OMAP3 SoC
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussard6d624ea2013-05-31 14:32:56 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard71fdc6e2013-06-11 16:49:46 +0200[diff] [blame]12#include <dt-bindings/interrupt-controller/irq.h>
Florian Vaussardbcd3cca2013-05-31 14:32:59 +0200[diff] [blame]13#include <dt-bindings/pinctrl/omap.h>
Florian Vaussard6d624ea2013-05-31 14:32:56 +0200[diff] [blame]14
Florian Vaussard98ef79572013-05-31 14:32:55 +0200[diff] [blame]15#include "skeleton.dtsi"
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]16
17/ {
18 compatible = "ti,omap3430", "ti,omap3";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]19 interrupt-parent = <&intc>;
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]20
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]21 aliases {
Nishanth Menon20b80942013-10-16 15:21:03 -0500[diff] [blame]22 i2c0 = &i2c1;
23 i2c1 = &i2c2;
24 i2c2 = &i2c3;
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]25 serial0 = &uart1;
26 serial1 = &uart2;
27 serial2 = &uart3;
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]28 };
29
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]30 cpus {
Lorenzo Pieralisieeb25fd2013-04-18 18:35:59 +0100[diff] [blame]31 #address-cells = <1>;
32 #size-cells = <0>;
33
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]34 cpu@0 {
35 compatible = "arm,cortex-a8";
Lorenzo Pieralisieeb25fd2013-04-18 18:35:59 +0100[diff] [blame]36 device_type = "cpu";
37 reg = <0x0>;
Nishanth Menon8d766fa2014-01-29 12:19:17 -0600[diff] [blame]38
39 clocks = <&dpll1_ck>;
40 clock-names = "cpu";
41
42 clock-latency = <300000>; /* From omap-cpufreq driver */
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]43 };
44 };
45
Javier Martinez Canillas2995a9e2016-04-01 16:20:20 -0400[diff] [blame^]46 pmu@54000000 {
Jon Hunter9b07b472012-10-18 09:28:52 -0500[diff] [blame]47 compatible = "arm,cortex-a8-pmu";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]48 reg = <0x54000000 0x800000>;
Jon Hunter9b07b472012-10-18 09:28:52 -0500[diff] [blame]49 interrupts = <3>;
50 ti,hwmods = "debugss";
51 };
52
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]53 /*
Christoph Fritz161e89a2013-03-29 17:32:05 +0100[diff] [blame]54 * The soc node represents the soc top level view. It is used for IPs
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]55 * that are not memory mapped in the MPU view or for the MPU itself.
56 */
57 soc {
58 compatible = "ti,omap-infra";
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]59 mpu {
60 compatible = "ti,omap3-mpu";
61 ti,hwmods = "mpu";
62 };
63
Suman Anna4c051602014-04-22 17:23:37 -0500[diff] [blame]64 iva: iva {
Benoit Cousson476b6792011-08-16 11:49:08 +0200[diff] [blame]65 compatible = "ti,iva2.2";
66 ti,hwmods = "iva";
67
68 dsp {
69 compatible = "ti,omap3-c64";
70 };
71 };
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]72 };
73
74 /*
75 * XXX: Use a flat representation of the OMAP3 interconnect.
76 * The real OMAP interconnect network is quite complex.
Geert Uytterhoevenb7ab5242014-03-28 11:11:39 +0100[diff] [blame]77 * Since it will not bring real advantage to represent that in DT for
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]78 * the moment, just use a fake OCP bus entry to represent the whole bus
79 * hierarchy.
80 */
81 ocp {
Tony Lindgrenaa25729c2014-11-05 09:21:23 -0800[diff] [blame]82 compatible = "ti,omap3-l3-smx", "simple-bus";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]83 reg = <0x68000000 0x10000>;
84 interrupts = <9 10>;
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]85 #address-cells = <1>;
86 #size-cells = <1>;
87 ranges;
88 ti,hwmods = "l3_main";
89
Tero Kristob8845072015-02-24 16:22:45 +0200[diff] [blame]90 l4_core: l4@48000000 {
91 compatible = "ti,omap3-l4-core", "simple-bus";
92 #address-cells = <1>;
93 #size-cells = <1>;
94 ranges = <0 0x48000000 0x1000000>;
95
96 scm: scm@2000 {
97 compatible = "ti,omap3-scm", "simple-bus";
98 reg = <0x2000 0x2000>;
99 #address-cells = <1>;
100 #size-cells = <1>;
101 ranges = <0 0x2000 0x2000>;
102
103 omap3_pmx_core: pinmux@30 {
104 compatible = "ti,omap3-padconf",
105 "pinctrl-single";
106 reg = <0x30 0x238>;
107 #address-cells = <1>;
108 #size-cells = <0>;
109 #interrupt-cells = <1>;
110 interrupt-controller;
111 pinctrl-single,register-width = <16>;
112 pinctrl-single,function-mask = <0xff1f>;
113 };
114
115 scm_conf: scm_conf@270 {
Kishon Vijay Abraham I9a5e3f22015-09-04 17:38:24 +0530[diff] [blame]116 compatible = "syscon", "simple-bus";
Tero Kristob8845072015-02-24 16:22:45 +0200[diff] [blame]117 reg = <0x270 0x330>;
118 #address-cells = <1>;
119 #size-cells = <1>;
Kishon Vijay Abraham I9a5e3f22015-09-04 17:38:24 +0530[diff] [blame]120 ranges = <0 0x270 0x330>;
121
Javier Martinez Canillas308cfda2016-04-01 16:20:18 -0400[diff] [blame]122 pbias_regulator: pbias_regulator@2b0 {
Kishon Vijay Abraham I9a5e3f22015-09-04 17:38:24 +0530[diff] [blame]123 compatible = "ti,pbias-omap3", "ti,pbias-omap";
124 reg = <0x2b0 0x4>;
125 syscon = <&scm_conf>;
126 pbias_mmc_reg: pbias_mmc_omap2430 {
127 regulator-name = "pbias_mmc_omap2430";
128 regulator-min-microvolt = <1800000>;
129 regulator-max-microvolt = <3000000>;
130 };
131 };
Tero Kristob8845072015-02-24 16:22:45 +0200[diff] [blame]132
133 scm_clocks: clocks {
134 #address-cells = <1>;
135 #size-cells = <0>;
136 };
137 };
138
139 scm_clockdomains: clockdomains {
140 };
141
142 omap3_pmx_wkup: pinmux@a00 {
143 compatible = "ti,omap3-padconf",
144 "pinctrl-single";
145 reg = <0xa00 0x5c>;
146 #address-cells = <1>;
147 #size-cells = <0>;
148 #interrupt-cells = <1>;
149 interrupt-controller;
150 pinctrl-single,register-width = <16>;
151 pinctrl-single,function-mask = <0xff1f>;
152 };
153 };
154 };
155
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]156 aes: aes@480c5000 {
157 compatible = "ti,omap3-aes";
158 ti,hwmods = "aes";
159 reg = <0x480c5000 0x50>;
160 interrupts = <0>;
Pali Rohárd6e5b7c2015-02-26 14:49:56 +0100[diff] [blame]161 dmas = <&sdma 65 &sdma 66>;
162 dma-names = "tx", "rx";
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]163 };
164
Tero Kristo657fc112013-07-22 12:29:29 +0300[diff] [blame]165 prm: prm@48306000 {
166 compatible = "ti,omap3-prm";
167 reg = <0x48306000 0x4000>;
Nishanth Menon5081ce62014-08-22 09:03:50 -0500[diff] [blame]168 interrupts = <11>;
Tero Kristo657fc112013-07-22 12:29:29 +0300[diff] [blame]169
170 prm_clocks: clocks {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 };
174
175 prm_clockdomains: clockdomains {
176 };
177 };
178
179 cm: cm@48004000 {
180 compatible = "ti,omap3-cm";
181 reg = <0x48004000 0x4000>;
182
183 cm_clocks: clocks {
184 #address-cells = <1>;
185 #size-cells = <0>;
186 };
187
188 cm_clockdomains: clockdomains {
189 };
190 };
191
Jon Hunter510c0ff2012-10-25 14:24:14 -0500[diff] [blame]192 counter32k: counter@48320000 {
193 compatible = "ti,omap-counter32k";
194 reg = <0x48320000 0x20>;
195 ti,hwmods = "counter_32k";
196 };
197
Benoit Coussond65c5422011-11-30 19:26:42 +0100[diff] [blame]198 intc: interrupt-controller@48200000 {
Felipe Balbicab82b72014-09-08 17:54:48 -0700[diff] [blame]199 compatible = "ti,omap3-intc";
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]200 interrupt-controller;
201 #interrupt-cells = <1>;
Benoit Coussond65c5422011-11-30 19:26:42 +0100[diff] [blame]202 reg = <0x48200000 0x1000>;
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]203 };
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]204
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]205 sdma: dma-controller@48056000 {
206 compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
207 reg = <0x48056000 0x1000>;
208 interrupts = <12>,
209 <13>,
210 <14>,
211 <15>;
212 #dma-cells = <1>;
Peter Ujfalusi7e8d25d2015-02-20 15:42:03 +0200[diff] [blame]213 dma-channels = <32>;
214 dma-requests = <96>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]215 };
216
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]217 gpio1: gpio@48310000 {
218 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]219 reg = <0x48310000 0x200>;
220 interrupts = <29>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]221 ti,hwmods = "gpio1";
Jon Huntere4b9b9f2013-04-04 15:16:16 -0500[diff] [blame]222 ti,gpio-always-on;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]223 gpio-controller;
224 #gpio-cells = <2>;
225 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]226 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]227 };
228
229 gpio2: gpio@49050000 {
230 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]231 reg = <0x49050000 0x200>;
232 interrupts = <30>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]233 ti,hwmods = "gpio2";
234 gpio-controller;
235 #gpio-cells = <2>;
236 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]237 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]238 };
239
240 gpio3: gpio@49052000 {
241 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]242 reg = <0x49052000 0x200>;
243 interrupts = <31>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]244 ti,hwmods = "gpio3";
245 gpio-controller;
246 #gpio-cells = <2>;
247 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]248 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]249 };
250
251 gpio4: gpio@49054000 {
252 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]253 reg = <0x49054000 0x200>;
254 interrupts = <32>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]255 ti,hwmods = "gpio4";
256 gpio-controller;
257 #gpio-cells = <2>;
258 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]259 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]260 };
261
262 gpio5: gpio@49056000 {
263 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]264 reg = <0x49056000 0x200>;
265 interrupts = <33>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]266 ti,hwmods = "gpio5";
267 gpio-controller;
268 #gpio-cells = <2>;
269 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]270 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]271 };
272
273 gpio6: gpio@49058000 {
274 compatible = "ti,omap3-gpio";
Jon Huntere2991852013-03-07 16:02:31 -0600[diff] [blame]275 reg = <0x49058000 0x200>;
276 interrupts = <34>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]277 ti,hwmods = "gpio6";
278 gpio-controller;
279 #gpio-cells = <2>;
280 interrupt-controller;
Jon Hunterff5c9052013-03-07 15:44:39 -0600[diff] [blame]281 #interrupt-cells = <2>;
Benoit Cousson385a64b2011-08-16 11:51:54 +0200[diff] [blame]282 };
283
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]284 uart1: serial@4806a000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]285 compatible = "ti,omap3-uart";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]286 reg = <0x4806a000 0x2000>;
Tony Lindgren31f08202014-05-05 17:27:39 -0700[diff] [blame]287 interrupts-extended = <&intc 72>;
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]288 dmas = <&sdma 49 &sdma 50>;
289 dma-names = "tx", "rx";
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]290 ti,hwmods = "uart1";
291 clock-frequency = <48000000>;
292 };
293
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]294 uart2: serial@4806c000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]295 compatible = "ti,omap3-uart";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]296 reg = <0x4806c000 0x400>;
Tony Lindgren31f08202014-05-05 17:27:39 -0700[diff] [blame]297 interrupts-extended = <&intc 73>;
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]298 dmas = <&sdma 51 &sdma 52>;
299 dma-names = "tx", "rx";
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]300 ti,hwmods = "uart2";
301 clock-frequency = <48000000>;
302 };
303
Benoit Cousson19bfb762012-02-16 11:55:27 +0100[diff] [blame]304 uart3: serial@49020000 {
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]305 compatible = "ti,omap3-uart";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]306 reg = <0x49020000 0x400>;
Tony Lindgren31f08202014-05-05 17:27:39 -0700[diff] [blame]307 interrupts-extended = <&intc 74>;
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]308 dmas = <&sdma 53 &sdma 54>;
309 dma-names = "tx", "rx";
Rajendra Nayakcf3c79d2011-12-14 17:25:46 +0530[diff] [blame]310 ti,hwmods = "uart3";
311 clock-frequency = <48000000>;
312 };
313
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]314 i2c1: i2c@48070000 {
315 compatible = "ti,omap3-i2c";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]316 reg = <0x48070000 0x80>;
317 interrupts = <56>;
318 dmas = <&sdma 27 &sdma 28>;
319 dma-names = "tx", "rx";
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]320 #address-cells = <1>;
321 #size-cells = <0>;
322 ti,hwmods = "i2c1";
323 };
324
325 i2c2: i2c@48072000 {
326 compatible = "ti,omap3-i2c";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]327 reg = <0x48072000 0x80>;
328 interrupts = <57>;
329 dmas = <&sdma 29 &sdma 30>;
330 dma-names = "tx", "rx";
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]331 #address-cells = <1>;
332 #size-cells = <0>;
333 ti,hwmods = "i2c2";
334 };
335
336 i2c3: i2c@48060000 {
337 compatible = "ti,omap3-i2c";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]338 reg = <0x48060000 0x80>;
339 interrupts = <61>;
340 dmas = <&sdma 25 &sdma 26>;
341 dma-names = "tx", "rx";
Benoit Coussonca59a5c2011-08-30 16:50:24 +0200[diff] [blame]342 #address-cells = <1>;
343 #size-cells = <0>;
344 ti,hwmods = "i2c3";
345 };
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]346
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]347 mailbox: mailbox@48094000 {
348 compatible = "ti,omap3-mailbox";
349 ti,hwmods = "mailbox";
350 reg = <0x48094000 0x200>;
351 interrupts = <26>;
Suman Anna24df0452014-11-03 17:07:35 -0600[diff] [blame]352 #mbox-cells = <1>;
Suman Anna41ffada2014-07-11 16:44:34 -0500[diff] [blame]353 ti,mbox-num-users = <2>;
354 ti,mbox-num-fifos = <2>;
Suman Annad27704d2014-09-10 14:27:23 -0500[diff] [blame]355 mbox_dsp: dsp {
356 ti,mbox-tx = <0 0 0>;
357 ti,mbox-rx = <1 0 0>;
358 };
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]359 };
360
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]361 mcspi1: spi@48098000 {
362 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]363 reg = <0x48098000 0x100>;
364 interrupts = <65>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]365 #address-cells = <1>;
366 #size-cells = <0>;
367 ti,hwmods = "mcspi1";
368 ti,spi-num-cs = <4>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]369 dmas = <&sdma 35>,
370 <&sdma 36>,
371 <&sdma 37>,
372 <&sdma 38>,
373 <&sdma 39>,
374 <&sdma 40>,
375 <&sdma 41>,
376 <&sdma 42>;
377 dma-names = "tx0", "rx0", "tx1", "rx1",
378 "tx2", "rx2", "tx3", "rx3";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]379 };
380
381 mcspi2: spi@4809a000 {
382 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]383 reg = <0x4809a000 0x100>;
384 interrupts = <66>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]385 #address-cells = <1>;
386 #size-cells = <0>;
387 ti,hwmods = "mcspi2";
388 ti,spi-num-cs = <2>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]389 dmas = <&sdma 43>,
390 <&sdma 44>,
391 <&sdma 45>,
392 <&sdma 46>;
393 dma-names = "tx0", "rx0", "tx1", "rx1";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]394 };
395
396 mcspi3: spi@480b8000 {
397 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]398 reg = <0x480b8000 0x100>;
399 interrupts = <91>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]400 #address-cells = <1>;
401 #size-cells = <0>;
402 ti,hwmods = "mcspi3";
403 ti,spi-num-cs = <2>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]404 dmas = <&sdma 15>,
405 <&sdma 16>,
406 <&sdma 23>,
407 <&sdma 24>;
408 dma-names = "tx0", "rx0", "tx1", "rx1";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]409 };
410
411 mcspi4: spi@480ba000 {
412 compatible = "ti,omap2-mcspi";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]413 reg = <0x480ba000 0x100>;
414 interrupts = <48>;
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]415 #address-cells = <1>;
416 #size-cells = <0>;
417 ti,hwmods = "mcspi4";
418 ti,spi-num-cs = <1>;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]419 dmas = <&sdma 70>, <&sdma 71>;
420 dma-names = "tx0", "rx0";
Benoit Coussonfc72d242012-01-20 14:15:58 +0100[diff] [blame]421 };
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]422
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]423 hdqw1w: 1w@480b2000 {
424 compatible = "ti,omap3-1w";
425 reg = <0x480b2000 0x1000>;
426 interrupts = <58>;
427 ti,hwmods = "hdq1w";
428 };
429
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]430 mmc1: mmc@4809c000 {
431 compatible = "ti,omap3-hsmmc";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]432 reg = <0x4809c000 0x200>;
433 interrupts = <83>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]434 ti,hwmods = "mmc1";
435 ti,dual-volt;
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]436 dmas = <&sdma 61>, <&sdma 62>;
437 dma-names = "tx", "rx";
Balaji T Kcd042fe2014-02-19 20:26:40 +0530[diff] [blame]438 pbias-supply = <&pbias_mmc_reg>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]439 };
440
441 mmc2: mmc@480b4000 {
442 compatible = "ti,omap3-hsmmc";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]443 reg = <0x480b4000 0x200>;
444 interrupts = <86>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]445 ti,hwmods = "mmc2";
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]446 dmas = <&sdma 47>, <&sdma 48>;
447 dma-names = "tx", "rx";
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]448 };
449
450 mmc3: mmc@480ad000 {
451 compatible = "ti,omap3-hsmmc";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]452 reg = <0x480ad000 0x200>;
453 interrupts = <94>;
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]454 ti,hwmods = "mmc3";
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]455 dmas = <&sdma 77>, <&sdma 78>;
456 dma-names = "tx", "rx";
Rajendra Nayakb3431f52012-02-22 17:42:27 +0530[diff] [blame]457 };
Xiao Jiang94c30732012-06-01 12:44:14 +0800[diff] [blame]458
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]459 mmu_isp: mmu@480bd400 {
Sebastian Reichel20550882015-03-31 03:28:10 +0200[diff] [blame]460 #iommu-cells = <0>;
Florian Vaussardb7cd9592014-03-05 18:24:16 -0600[diff] [blame]461 compatible = "ti,omap2-iommu";
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]462 reg = <0x480bd400 0x80>;
Florian Vaussardb7cd9592014-03-05 18:24:16 -0600[diff] [blame]463 interrupts = <24>;
464 ti,hwmods = "mmu_isp";
465 ti,#tlb-entries = <8>;
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]466 };
467
Florian Vaussard40ac0512014-03-05 18:24:17 -0600[diff] [blame]468 mmu_iva: mmu@5d000000 {
Sebastian Reichel20550882015-03-31 03:28:10 +0200[diff] [blame]469 #iommu-cells = <0>;
Florian Vaussard40ac0512014-03-05 18:24:17 -0600[diff] [blame]470 compatible = "ti,omap2-iommu";
471 reg = <0x5d000000 0x80>;
472 interrupts = <28>;
473 ti,hwmods = "mmu_iva";
474 status = "disabled";
475 };
476
Xiao Jiang94c30732012-06-01 12:44:14 +0800[diff] [blame]477 wdt2: wdt@48314000 {
478 compatible = "ti,omap3-wdt";
Tony Lindgrend7c8f252013-10-17 15:15:22 -0700[diff] [blame]479 reg = <0x48314000 0x80>;
Xiao Jiang94c30732012-06-01 12:44:14 +0800[diff] [blame]480 ti,hwmods = "wd_timer2";
481 };
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]482
483 mcbsp1: mcbsp@48074000 {
484 compatible = "ti,omap3-mcbsp";
485 reg = <0x48074000 0xff>;
486 reg-names = "mpu";
487 interrupts = <16>, /* OCP compliant interrupt */
488 <59>, /* TX interrupt */
489 <60>; /* RX interrupt */
490 interrupt-names = "common", "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]491 ti,buffer-size = <128>;
492 ti,hwmods = "mcbsp1";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]493 dmas = <&sdma 31>,
494 <&sdma 32>;
495 dma-names = "tx", "rx";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200[diff] [blame]496 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]497 };
498
499 mcbsp2: mcbsp@49022000 {
500 compatible = "ti,omap3-mcbsp";
501 reg = <0x49022000 0xff>,
502 <0x49028000 0xff>;
503 reg-names = "mpu", "sidetone";
504 interrupts = <17>, /* OCP compliant interrupt */
505 <62>, /* TX interrupt */
506 <63>, /* RX interrupt */
507 <4>; /* Sidetone */
508 interrupt-names = "common", "tx", "rx", "sidetone";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]509 ti,buffer-size = <1280>;
Peter Ujfalusieef6fca2012-10-18 11:25:07 +0200[diff] [blame]510 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]511 dmas = <&sdma 33>,
512 <&sdma 34>;
513 dma-names = "tx", "rx";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200[diff] [blame]514 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]515 };
516
517 mcbsp3: mcbsp@49024000 {
518 compatible = "ti,omap3-mcbsp";
519 reg = <0x49024000 0xff>,
520 <0x4902a000 0xff>;
521 reg-names = "mpu", "sidetone";
522 interrupts = <22>, /* OCP compliant interrupt */
523 <89>, /* TX interrupt */
524 <90>, /* RX interrupt */
525 <5>; /* Sidetone */
526 interrupt-names = "common", "tx", "rx", "sidetone";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]527 ti,buffer-size = <128>;
Peter Ujfalusieef6fca2012-10-18 11:25:07 +0200[diff] [blame]528 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]529 dmas = <&sdma 17>,
530 <&sdma 18>;
531 dma-names = "tx", "rx";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200[diff] [blame]532 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]533 };
534
535 mcbsp4: mcbsp@49026000 {
536 compatible = "ti,omap3-mcbsp";
537 reg = <0x49026000 0xff>;
538 reg-names = "mpu";
539 interrupts = <23>, /* OCP compliant interrupt */
540 <54>, /* TX interrupt */
541 <55>; /* RX interrupt */
542 interrupt-names = "common", "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]543 ti,buffer-size = <128>;
544 ti,hwmods = "mcbsp4";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]545 dmas = <&sdma 19>,
546 <&sdma 20>;
547 dma-names = "tx", "rx";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200[diff] [blame]548 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]549 };
550
551 mcbsp5: mcbsp@48096000 {
552 compatible = "ti,omap3-mcbsp";
553 reg = <0x48096000 0xff>;
554 reg-names = "mpu";
555 interrupts = <27>, /* OCP compliant interrupt */
556 <81>, /* TX interrupt */
557 <82>; /* RX interrupt */
558 interrupt-names = "common", "tx", "rx";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]559 ti,buffer-size = <128>;
560 ti,hwmods = "mcbsp5";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]561 dmas = <&sdma 21>,
562 <&sdma 22>;
563 dma-names = "tx", "rx";
Peter Ujfalusi726322c2014-01-24 10:19:05 +0200[diff] [blame]564 status = "disabled";
Peter Ujfalusi0be484b2012-09-05 14:21:22 +0300[diff] [blame]565 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]566
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]567 sham: sham@480c3000 {
568 compatible = "ti,omap3-sham";
569 ti,hwmods = "sham";
570 reg = <0x480c3000 0x64>;
571 interrupts = <49>;
Pali Rohárd6e5b7c2015-02-26 14:49:56 +0100[diff] [blame]572 dmas = <&sdma 69>;
573 dma-names = "rx";
Tony Lindgren7ce93f32013-11-25 14:23:45 -0800[diff] [blame]574 };
575
576 smartreflex_core: smartreflex@480cb000 {
577 compatible = "ti,omap3-smartreflex-core";
578 ti,hwmods = "smartreflex_core";
579 reg = <0x480cb000 0x400>;
580 interrupts = <19>;
581 };
582
583 smartreflex_mpu_iva: smartreflex@480c9000 {
584 compatible = "ti,omap3-smartreflex-iva";
585 ti,hwmods = "smartreflex_mpu_iva";
586 reg = <0x480c9000 0x400>;
587 interrupts = <18>;
588 };
589
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]590 timer1: timer@48318000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]591 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]592 reg = <0x48318000 0x400>;
593 interrupts = <37>;
594 ti,hwmods = "timer1";
595 ti,timer-alwon;
596 };
597
598 timer2: timer@49032000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]599 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]600 reg = <0x49032000 0x400>;
601 interrupts = <38>;
602 ti,hwmods = "timer2";
603 };
604
605 timer3: timer@49034000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]606 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]607 reg = <0x49034000 0x400>;
608 interrupts = <39>;
609 ti,hwmods = "timer3";
610 };
611
612 timer4: timer@49036000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]613 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]614 reg = <0x49036000 0x400>;
615 interrupts = <40>;
616 ti,hwmods = "timer4";
617 };
618
619 timer5: timer@49038000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]620 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]621 reg = <0x49038000 0x400>;
622 interrupts = <41>;
623 ti,hwmods = "timer5";
624 ti,timer-dsp;
625 };
626
627 timer6: timer@4903a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]628 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]629 reg = <0x4903a000 0x400>;
630 interrupts = <42>;
631 ti,hwmods = "timer6";
632 ti,timer-dsp;
633 };
634
635 timer7: timer@4903c000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]636 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]637 reg = <0x4903c000 0x400>;
638 interrupts = <43>;
639 ti,hwmods = "timer7";
640 ti,timer-dsp;
641 };
642
643 timer8: timer@4903e000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]644 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]645 reg = <0x4903e000 0x400>;
646 interrupts = <44>;
647 ti,hwmods = "timer8";
648 ti,timer-pwm;
649 ti,timer-dsp;
650 };
651
652 timer9: timer@49040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]653 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]654 reg = <0x49040000 0x400>;
655 interrupts = <45>;
656 ti,hwmods = "timer9";
657 ti,timer-pwm;
658 };
659
660 timer10: timer@48086000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]661 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]662 reg = <0x48086000 0x400>;
663 interrupts = <46>;
664 ti,hwmods = "timer10";
665 ti,timer-pwm;
666 };
667
668 timer11: timer@48088000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]669 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]670 reg = <0x48088000 0x400>;
671 interrupts = <47>;
672 ti,hwmods = "timer11";
673 ti,timer-pwm;
674 };
675
676 timer12: timer@48304000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]677 compatible = "ti,omap3430-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]678 reg = <0x48304000 0x400>;
679 interrupts = <95>;
680 ti,hwmods = "timer12";
681 ti,timer-alwon;
682 ti,timer-secure;
683 };
Roger Quadrosaf3eb362013-03-20 17:44:59 +0200[diff] [blame]684
685 usbhstll: usbhstll@48062000 {
686 compatible = "ti,usbhs-tll";
687 reg = <0x48062000 0x1000>;
688 interrupts = <78>;
689 ti,hwmods = "usb_tll_hs";
690 };
691
692 usbhshost: usbhshost@48064000 {
693 compatible = "ti,usbhs-host";
694 reg = <0x48064000 0x400>;
695 ti,hwmods = "usb_host_hs";
696 #address-cells = <1>;
697 #size-cells = <1>;
698 ranges;
699
700 usbhsohci: ohci@48064400 {
Roger Quadrosa2525e52014-02-27 16:18:30 +0200[diff] [blame]701 compatible = "ti,ohci-omap3";
Roger Quadrosaf3eb362013-03-20 17:44:59 +0200[diff] [blame]702 reg = <0x48064400 0x400>;
703 interrupt-parent = <&intc>;
704 interrupts = <76>;
705 };
706
707 usbhsehci: ehci@48064800 {
Roger Quadrosa2525e52014-02-27 16:18:30 +0200[diff] [blame]708 compatible = "ti,ehci-omap";
Roger Quadrosaf3eb362013-03-20 17:44:59 +0200[diff] [blame]709 reg = <0x48064800 0x400>;
710 interrupt-parent = <&intc>;
711 interrupts = <77>;
712 };
713 };
714
Florian Vaussard6e8489d2013-01-28 18:54:07 +0100[diff] [blame]715 gpmc: gpmc@6e000000 {
716 compatible = "ti,omap3430-gpmc";
717 ti,hwmods = "gpmc";
Javier Martinez Canillas41644e72013-02-27 02:30:51 +0100[diff] [blame]718 reg = <0x6e000000 0x02d0>;
Florian Vaussard6e8489d2013-01-28 18:54:07 +0100[diff] [blame]719 interrupts = <20>;
Franklin S Cooper Jr201c7e32015-10-15 12:37:27 -0500[diff] [blame]720 dmas = <&sdma 4>;
721 dma-names = "rxtx";
Florian Vaussard6e8489d2013-01-28 18:54:07 +0100[diff] [blame]722 gpmc,num-cs = <8>;
723 gpmc,num-waitpins = <4>;
724 #address-cells = <2>;
725 #size-cells = <1>;
Roger Quadros44e47162016-02-23 18:37:25 +0200[diff] [blame]726 interrupt-controller;
727 #interrupt-cells = <2>;
Florian Vaussard6e8489d2013-01-28 18:54:07 +0100[diff] [blame]728 };
Kishon Vijay Abraham Iad871c12013-03-07 19:05:16 +0530[diff] [blame]729
730 usb_otg_hs: usb_otg_hs@480ab000 {
731 compatible = "ti,omap3-musb";
732 reg = <0x480ab000 0x1000>;
Tony Lindgren304e71e2013-05-14 20:28:15 -0700[diff] [blame]733 interrupts = <92>, <93>;
Kishon Vijay Abraham Iad871c12013-03-07 19:05:16 +0530[diff] [blame]734 interrupt-names = "mc", "dma";
735 ti,hwmods = "usb_otg_hs";
Kishon Vijay Abraham Iad871c12013-03-07 19:05:16 +0530[diff] [blame]736 multipoint = <1>;
737 num-eps = <16>;
738 ram-bits = <12>;
739 };
Tomi Valkeinenb8a7e422013-03-19 11:38:13 +0200[diff] [blame]740
741 dss: dss@48050000 {
742 compatible = "ti,omap3-dss";
743 reg = <0x48050000 0x200>;
744 status = "disabled";
745 ti,hwmods = "dss_core";
746 clocks = <&dss1_alwon_fck>;
747 clock-names = "fck";
748 #address-cells = <1>;
749 #size-cells = <1>;
750 ranges;
751
752 dispc@48050400 {
753 compatible = "ti,omap3-dispc";
754 reg = <0x48050400 0x400>;
755 interrupts = <25>;
756 ti,hwmods = "dss_dispc";
757 clocks = <&dss1_alwon_fck>;
758 clock-names = "fck";
759 };
760
761 dsi: encoder@4804fc00 {
762 compatible = "ti,omap3-dsi";
763 reg = <0x4804fc00 0x200>,
764 <0x4804fe00 0x40>,
765 <0x4804ff00 0x20>;
766 reg-names = "proto", "phy", "pll";
767 interrupts = <25>;
768 status = "disabled";
769 ti,hwmods = "dss_dsi1";
770 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
771 clock-names = "fck", "sys_clk";
772 };
773
774 rfbi: encoder@48050800 {
775 compatible = "ti,omap3-rfbi";
776 reg = <0x48050800 0x100>;
777 status = "disabled";
778 ti,hwmods = "dss_rfbi";
779 clocks = <&dss1_alwon_fck>, <&dss_ick>;
780 clock-names = "fck", "ick";
781 };
782
783 venc: encoder@48050c00 {
784 compatible = "ti,omap3-venc";
785 reg = <0x48050c00 0x100>;
786 status = "disabled";
787 ti,hwmods = "dss_venc";
788 clocks = <&dss_tv_fck>;
789 clock-names = "fck";
790 };
791 };
Sebastian Reichel782e25a2014-05-10 18:37:49 +0200[diff] [blame]792
793 ssi: ssi-controller@48058000 {
794 compatible = "ti,omap3-ssi";
795 ti,hwmods = "ssi";
796
797 status = "disabled";
798
799 reg = <0x48058000 0x1000>,
800 <0x48059000 0x1000>;
801 reg-names = "sys",
802 "gdd";
803
804 interrupts = <71>;
805 interrupt-names = "gdd_mpu";
806
807 #address-cells = <1>;
808 #size-cells = <1>;
809 ranges;
810
811 ssi_port1: ssi-port@4805a000 {
812 compatible = "ti,omap3-ssi-port";
813
814 reg = <0x4805a000 0x800>,
815 <0x4805a800 0x800>;
816 reg-names = "tx",
817 "rx";
818
819 interrupt-parent = <&intc>;
820 interrupts = <67>,
821 <68>;
822 };
823
824 ssi_port2: ssi-port@4805b000 {
825 compatible = "ti,omap3-ssi-port";
826
827 reg = <0x4805b000 0x800>,
828 <0x4805b800 0x800>;
829 reg-names = "tx",
830 "rx";
831
832 interrupt-parent = <&intc>;
833 interrupts = <69>,
834 <70>;
835 };
836 };
Benoit Cousson189892f2011-08-16 21:02:01 +0530[diff] [blame]837 };
838};
Tero Kristo657fc112013-07-22 12:29:29 +0300[diff] [blame]839
840/include/ "omap3xxx-clocks.dtsi"