Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Freescale eSDHC i.MX controller driver for the platform bus. |
| 3 | * |
| 4 | * derived from the OF-version. |
| 5 | * |
| 6 | * Copyright (c) 2010 Pengutronix e.K. |
Wolfram Sang | 035ff83 | 2015-04-20 15:51:42 +0200 | [diff] [blame] | 7 | * Author: Wolfram Sang <kernel@pengutronix.de> |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/io.h> |
| 15 | #include <linux/delay.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/clk.h> |
Wolfram Sang | 0c6d49c | 2011-02-26 14:44:39 +0100 | [diff] [blame] | 18 | #include <linux/gpio.h> |
Shawn Guo | 66506f7 | 2011-08-15 10:28:18 +0800 | [diff] [blame] | 19 | #include <linux/module.h> |
Richard Zhu | e149860 | 2011-03-25 09:18:27 -0400 | [diff] [blame] | 20 | #include <linux/slab.h> |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 21 | #include <linux/mmc/host.h> |
Richard Zhu | 58ac817 | 2011-03-21 13:22:16 +0800 | [diff] [blame] | 22 | #include <linux/mmc/mmc.h> |
| 23 | #include <linux/mmc/sdio.h> |
Shawn Guo | fbe5fdd | 2012-12-11 22:32:20 +0800 | [diff] [blame] | 24 | #include <linux/mmc/slot-gpio.h> |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 25 | #include <linux/of.h> |
| 26 | #include <linux/of_device.h> |
| 27 | #include <linux/of_gpio.h> |
Dong Aisheng | e62d8b8 | 2012-05-11 14:56:01 +0800 | [diff] [blame] | 28 | #include <linux/pinctrl/consumer.h> |
Arnd Bergmann | 82906b1 | 2012-08-24 15:14:29 +0200 | [diff] [blame] | 29 | #include <linux/platform_data/mmc-esdhc-imx.h> |
Dong Aisheng | 89d7e5c | 2013-11-04 16:38:29 +0800 | [diff] [blame] | 30 | #include <linux/pm_runtime.h> |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 31 | #include "sdhci-pltfm.h" |
| 32 | #include "sdhci-esdhc.h" |
| 33 | |
Shawn Guo | 60bf639 | 2013-01-15 23:36:53 +0800 | [diff] [blame] | 34 | #define ESDHC_CTRL_D3CD 0x08 |
Richard Zhu | 58ac817 | 2011-03-21 13:22:16 +0800 | [diff] [blame] | 35 | /* VENDOR SPEC register */ |
Shawn Guo | 60bf639 | 2013-01-15 23:36:53 +0800 | [diff] [blame] | 36 | #define ESDHC_VENDOR_SPEC 0xc0 |
| 37 | #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 38 | #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) |
Dong Aisheng | fed2f6e | 2013-09-13 19:11:33 +0800 | [diff] [blame] | 39 | #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) |
Shawn Guo | 60bf639 | 2013-01-15 23:36:53 +0800 | [diff] [blame] | 40 | #define ESDHC_WTMK_LVL 0x44 |
| 41 | #define ESDHC_MIX_CTRL 0x48 |
Dong Aisheng | de5bdbf | 2013-10-18 19:48:46 +0800 | [diff] [blame] | 42 | #define ESDHC_MIX_CTRL_DDREN (1 << 3) |
Shawn Guo | 2a15f98 | 2013-01-21 19:02:26 +0800 | [diff] [blame] | 43 | #define ESDHC_MIX_CTRL_AC23EN (1 << 7) |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 44 | #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) |
| 45 | #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) |
| 46 | #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) |
Shawn Guo | 2a15f98 | 2013-01-21 19:02:26 +0800 | [diff] [blame] | 47 | /* Bits 3 and 6 are not SDHCI standard definitions */ |
| 48 | #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 |
Dong Aisheng | d131a71 | 2013-11-04 16:38:26 +0800 | [diff] [blame] | 49 | /* Tuning bits */ |
| 50 | #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 |
Richard Zhu | 58ac817 | 2011-03-21 13:22:16 +0800 | [diff] [blame] | 51 | |
Dong Aisheng | 602519b | 2013-10-18 19:48:47 +0800 | [diff] [blame] | 52 | /* dll control register */ |
| 53 | #define ESDHC_DLL_CTRL 0x60 |
| 54 | #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 |
| 55 | #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 |
| 56 | |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 57 | /* tune control register */ |
| 58 | #define ESDHC_TUNE_CTRL_STATUS 0x68 |
| 59 | #define ESDHC_TUNE_CTRL_STEP 1 |
| 60 | #define ESDHC_TUNE_CTRL_MIN 0 |
| 61 | #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) |
| 62 | |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 63 | #define ESDHC_TUNING_CTRL 0xcc |
| 64 | #define ESDHC_STD_TUNING_EN (1 << 24) |
| 65 | /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ |
| 66 | #define ESDHC_TUNING_START_TAP 0x1 |
| 67 | |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 68 | /* pinctrl state */ |
| 69 | #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" |
| 70 | #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" |
| 71 | |
Richard Zhu | 58ac817 | 2011-03-21 13:22:16 +0800 | [diff] [blame] | 72 | /* |
Sascha Hauer | af51079 | 2013-01-21 19:02:28 +0800 | [diff] [blame] | 73 | * Our interpretation of the SDHCI_HOST_CONTROL register |
| 74 | */ |
| 75 | #define ESDHC_CTRL_4BITBUS (0x1 << 1) |
| 76 | #define ESDHC_CTRL_8BITBUS (0x2 << 1) |
| 77 | #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) |
| 78 | |
| 79 | /* |
Richard Zhu | 97e4ba6 | 2011-08-11 16:51:46 -0400 | [diff] [blame] | 80 | * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: |
| 81 | * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, |
| 82 | * but bit28 is used as the INT DMA ERR in fsl eSDHC design. |
| 83 | * Define this macro DMA error INT for fsl eSDHC |
| 84 | */ |
Shawn Guo | 60bf639 | 2013-01-15 23:36:53 +0800 | [diff] [blame] | 85 | #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) |
Richard Zhu | 97e4ba6 | 2011-08-11 16:51:46 -0400 | [diff] [blame] | 86 | |
| 87 | /* |
Richard Zhu | 58ac817 | 2011-03-21 13:22:16 +0800 | [diff] [blame] | 88 | * The CMDTYPE of the CMD register (offset 0xE) should be set to |
| 89 | * "11" when the STOP CMD12 is issued on imx53 to abort one |
| 90 | * open ended multi-blk IO. Otherwise the TC INT wouldn't |
| 91 | * be generated. |
| 92 | * In exact block transfer, the controller doesn't complete the |
| 93 | * operations automatically as required at the end of the |
| 94 | * transfer and remains on hold if the abort command is not sent. |
| 95 | * As a result, the TC flag is not asserted and SW received timeout |
| 96 | * exeception. Bit1 of Vendor Spec registor is used to fix it. |
| 97 | */ |
Shawn Guo | 31fbb30 | 2013-10-17 15:19:44 +0800 | [diff] [blame] | 98 | #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) |
| 99 | /* |
| 100 | * The flag enables the workaround for ESDHC errata ENGcm07207 which |
| 101 | * affects i.MX25 and i.MX35. |
| 102 | */ |
| 103 | #define ESDHC_FLAG_ENGCM07207 BIT(2) |
Shawn Guo | 9d61c00 | 2013-10-17 15:19:45 +0800 | [diff] [blame] | 104 | /* |
| 105 | * The flag tells that the ESDHC controller is an USDHC block that is |
| 106 | * integrated on the i.MX6 series. |
| 107 | */ |
| 108 | #define ESDHC_FLAG_USDHC BIT(3) |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 109 | /* The IP supports manual tuning process */ |
| 110 | #define ESDHC_FLAG_MAN_TUNING BIT(4) |
| 111 | /* The IP supports standard tuning process */ |
| 112 | #define ESDHC_FLAG_STD_TUNING BIT(5) |
| 113 | /* The IP has SDHCI_CAPABILITIES_1 register */ |
| 114 | #define ESDHC_FLAG_HAVE_CAP1 BIT(6) |
Dong Aisheng | 1809443 | 2015-05-27 18:13:28 +0800 | [diff] [blame] | 115 | /* |
| 116 | * The IP has errata ERR004536 |
| 117 | * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, |
| 118 | * when reading data from the card |
| 119 | */ |
| 120 | #define ESDHC_FLAG_ERR004536 BIT(7) |
Dong Aisheng | 4245aff | 2015-05-27 18:13:31 +0800 | [diff] [blame] | 121 | /* The IP supports HS200 mode */ |
| 122 | #define ESDHC_FLAG_HS200 BIT(8) |
Richard Zhu | e149860 | 2011-03-25 09:18:27 -0400 | [diff] [blame] | 123 | |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 124 | struct esdhc_soc_data { |
| 125 | u32 flags; |
| 126 | }; |
| 127 | |
| 128 | static struct esdhc_soc_data esdhc_imx25_data = { |
| 129 | .flags = ESDHC_FLAG_ENGCM07207, |
| 130 | }; |
| 131 | |
| 132 | static struct esdhc_soc_data esdhc_imx35_data = { |
| 133 | .flags = ESDHC_FLAG_ENGCM07207, |
| 134 | }; |
| 135 | |
| 136 | static struct esdhc_soc_data esdhc_imx51_data = { |
| 137 | .flags = 0, |
| 138 | }; |
| 139 | |
| 140 | static struct esdhc_soc_data esdhc_imx53_data = { |
| 141 | .flags = ESDHC_FLAG_MULTIBLK_NO_INT, |
| 142 | }; |
| 143 | |
| 144 | static struct esdhc_soc_data usdhc_imx6q_data = { |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 145 | .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, |
| 146 | }; |
| 147 | |
| 148 | static struct esdhc_soc_data usdhc_imx6sl_data = { |
| 149 | .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
Dong Aisheng | 4245aff | 2015-05-27 18:13:31 +0800 | [diff] [blame] | 150 | | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536 |
| 151 | | ESDHC_FLAG_HS200, |
Shawn Guo | 57ed331 | 2011-06-30 09:24:26 +0800 | [diff] [blame] | 152 | }; |
| 153 | |
Dong Aisheng | 913d495 | 2015-05-27 18:13:30 +0800 | [diff] [blame] | 154 | static struct esdhc_soc_data usdhc_imx6sx_data = { |
| 155 | .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
Dong Aisheng | 4245aff | 2015-05-27 18:13:31 +0800 | [diff] [blame] | 156 | | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, |
Dong Aisheng | 913d495 | 2015-05-27 18:13:30 +0800 | [diff] [blame] | 157 | }; |
| 158 | |
Richard Zhu | e149860 | 2011-03-25 09:18:27 -0400 | [diff] [blame] | 159 | struct pltfm_imx_data { |
Richard Zhu | e149860 | 2011-03-25 09:18:27 -0400 | [diff] [blame] | 160 | u32 scratchpad; |
Dong Aisheng | e62d8b8 | 2012-05-11 14:56:01 +0800 | [diff] [blame] | 161 | struct pinctrl *pinctrl; |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 162 | struct pinctrl_state *pins_default; |
| 163 | struct pinctrl_state *pins_100mhz; |
| 164 | struct pinctrl_state *pins_200mhz; |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 165 | const struct esdhc_soc_data *socdata; |
Shawn Guo | 842afc0 | 2011-07-06 22:57:48 +0800 | [diff] [blame] | 166 | struct esdhc_platform_data boarddata; |
Sascha Hauer | 52dac61 | 2012-03-07 09:31:34 +0100 | [diff] [blame] | 167 | struct clk *clk_ipg; |
| 168 | struct clk *clk_ahb; |
| 169 | struct clk *clk_per; |
Lucas Stach | 361b848 | 2013-03-15 09:49:26 +0100 | [diff] [blame] | 170 | enum { |
| 171 | NO_CMD_PENDING, /* no multiblock command pending*/ |
| 172 | MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ |
| 173 | WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ |
| 174 | } multiblock_status; |
Dong Aisheng | de5bdbf | 2013-10-18 19:48:46 +0800 | [diff] [blame] | 175 | u32 is_ddr; |
Richard Zhu | e149860 | 2011-03-25 09:18:27 -0400 | [diff] [blame] | 176 | }; |
| 177 | |
Krzysztof Kozlowski | f8cbf46 | 2015-05-02 00:49:21 +0900 | [diff] [blame] | 178 | static const struct platform_device_id imx_esdhc_devtype[] = { |
Shawn Guo | 57ed331 | 2011-06-30 09:24:26 +0800 | [diff] [blame] | 179 | { |
| 180 | .name = "sdhci-esdhc-imx25", |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 181 | .driver_data = (kernel_ulong_t) &esdhc_imx25_data, |
Shawn Guo | 57ed331 | 2011-06-30 09:24:26 +0800 | [diff] [blame] | 182 | }, { |
| 183 | .name = "sdhci-esdhc-imx35", |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 184 | .driver_data = (kernel_ulong_t) &esdhc_imx35_data, |
Shawn Guo | 57ed331 | 2011-06-30 09:24:26 +0800 | [diff] [blame] | 185 | }, { |
| 186 | .name = "sdhci-esdhc-imx51", |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 187 | .driver_data = (kernel_ulong_t) &esdhc_imx51_data, |
Shawn Guo | 57ed331 | 2011-06-30 09:24:26 +0800 | [diff] [blame] | 188 | }, { |
Shawn Guo | 57ed331 | 2011-06-30 09:24:26 +0800 | [diff] [blame] | 189 | /* sentinel */ |
| 190 | } |
| 191 | }; |
| 192 | MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); |
| 193 | |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 194 | static const struct of_device_id imx_esdhc_dt_ids[] = { |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 195 | { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, |
| 196 | { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, |
| 197 | { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, |
| 198 | { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, |
Dong Aisheng | 913d495 | 2015-05-27 18:13:30 +0800 | [diff] [blame] | 199 | { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 200 | { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 201 | { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 202 | { /* sentinel */ } |
| 203 | }; |
| 204 | MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); |
| 205 | |
Shawn Guo | 57ed331 | 2011-06-30 09:24:26 +0800 | [diff] [blame] | 206 | static inline int is_imx25_esdhc(struct pltfm_imx_data *data) |
| 207 | { |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 208 | return data->socdata == &esdhc_imx25_data; |
Shawn Guo | 57ed331 | 2011-06-30 09:24:26 +0800 | [diff] [blame] | 209 | } |
| 210 | |
| 211 | static inline int is_imx53_esdhc(struct pltfm_imx_data *data) |
| 212 | { |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 213 | return data->socdata == &esdhc_imx53_data; |
Shawn Guo | 57ed331 | 2011-06-30 09:24:26 +0800 | [diff] [blame] | 214 | } |
| 215 | |
Shawn Guo | 95a2482 | 2011-09-19 17:32:21 +0800 | [diff] [blame] | 216 | static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) |
| 217 | { |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 218 | return data->socdata == &usdhc_imx6q_data; |
Shawn Guo | 95a2482 | 2011-09-19 17:32:21 +0800 | [diff] [blame] | 219 | } |
| 220 | |
Shawn Guo | 9d61c00 | 2013-10-17 15:19:45 +0800 | [diff] [blame] | 221 | static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) |
| 222 | { |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 223 | return !!(data->socdata->flags & ESDHC_FLAG_USDHC); |
Shawn Guo | 9d61c00 | 2013-10-17 15:19:45 +0800 | [diff] [blame] | 224 | } |
| 225 | |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 226 | static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) |
| 227 | { |
| 228 | void __iomem *base = host->ioaddr + (reg & ~0x3); |
| 229 | u32 shift = (reg & 0x3) * 8; |
| 230 | |
| 231 | writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); |
| 232 | } |
| 233 | |
Wolfram Sang | 7e29c30 | 2011-02-26 14:44:41 +0100 | [diff] [blame] | 234 | static u32 esdhc_readl_le(struct sdhci_host *host, int reg) |
| 235 | { |
Lucas Stach | 361b848 | 2013-03-15 09:49:26 +0100 | [diff] [blame] | 236 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 237 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
Wolfram Sang | 7e29c30 | 2011-02-26 14:44:41 +0100 | [diff] [blame] | 238 | u32 val = readl(host->ioaddr + reg); |
| 239 | |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 240 | if (unlikely(reg == SDHCI_PRESENT_STATE)) { |
| 241 | u32 fsl_prss = val; |
| 242 | /* save the least 20 bits */ |
| 243 | val = fsl_prss & 0x000FFFFF; |
| 244 | /* move dat[0-3] bits */ |
| 245 | val |= (fsl_prss & 0x0F000000) >> 4; |
| 246 | /* move cmd line bit */ |
| 247 | val |= (fsl_prss & 0x00800000) << 1; |
| 248 | } |
| 249 | |
Richard Zhu | 97e4ba6 | 2011-08-11 16:51:46 -0400 | [diff] [blame] | 250 | if (unlikely(reg == SDHCI_CAPABILITIES)) { |
Dong Aisheng | 6b4fb67 | 2013-10-18 19:48:44 +0800 | [diff] [blame] | 251 | /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ |
| 252 | if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) |
| 253 | val &= 0xffff0000; |
| 254 | |
Richard Zhu | 97e4ba6 | 2011-08-11 16:51:46 -0400 | [diff] [blame] | 255 | /* In FSL esdhc IC module, only bit20 is used to indicate the |
| 256 | * ADMA2 capability of esdhc, but this bit is messed up on |
| 257 | * some SOCs (e.g. on MX25, MX35 this bit is set, but they |
| 258 | * don't actually support ADMA2). So set the BROKEN_ADMA |
| 259 | * uirk on MX25/35 platforms. |
| 260 | */ |
| 261 | |
| 262 | if (val & SDHCI_CAN_DO_ADMA1) { |
| 263 | val &= ~SDHCI_CAN_DO_ADMA1; |
| 264 | val |= SDHCI_CAN_DO_ADMA2; |
| 265 | } |
| 266 | } |
| 267 | |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 268 | if (unlikely(reg == SDHCI_CAPABILITIES_1)) { |
| 269 | if (esdhc_is_usdhc(imx_data)) { |
| 270 | if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) |
| 271 | val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; |
| 272 | else |
| 273 | /* imx6q/dl does not have cap_1 register, fake one */ |
| 274 | val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 |
Dong Aisheng | 888824b | 2013-10-18 19:48:48 +0800 | [diff] [blame] | 275 | | SDHCI_SUPPORT_SDR50 |
| 276 | | SDHCI_USE_SDR50_TUNING; |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 277 | } |
| 278 | } |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 279 | |
Shawn Guo | 9d61c00 | 2013-10-17 15:19:45 +0800 | [diff] [blame] | 280 | if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 281 | val = 0; |
| 282 | val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; |
| 283 | val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; |
| 284 | val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; |
| 285 | } |
| 286 | |
Richard Zhu | 97e4ba6 | 2011-08-11 16:51:46 -0400 | [diff] [blame] | 287 | if (unlikely(reg == SDHCI_INT_STATUS)) { |
Shawn Guo | 60bf639 | 2013-01-15 23:36:53 +0800 | [diff] [blame] | 288 | if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { |
| 289 | val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; |
Richard Zhu | 97e4ba6 | 2011-08-11 16:51:46 -0400 | [diff] [blame] | 290 | val |= SDHCI_INT_ADMA_ERROR; |
| 291 | } |
Lucas Stach | 361b848 | 2013-03-15 09:49:26 +0100 | [diff] [blame] | 292 | |
| 293 | /* |
| 294 | * mask off the interrupt we get in response to the manually |
| 295 | * sent CMD12 |
| 296 | */ |
| 297 | if ((imx_data->multiblock_status == WAIT_FOR_INT) && |
| 298 | ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { |
| 299 | val &= ~SDHCI_INT_RESPONSE; |
| 300 | writel(SDHCI_INT_RESPONSE, host->ioaddr + |
| 301 | SDHCI_INT_STATUS); |
| 302 | imx_data->multiblock_status = NO_CMD_PENDING; |
| 303 | } |
Richard Zhu | 97e4ba6 | 2011-08-11 16:51:46 -0400 | [diff] [blame] | 304 | } |
| 305 | |
Wolfram Sang | 7e29c30 | 2011-02-26 14:44:41 +0100 | [diff] [blame] | 306 | return val; |
| 307 | } |
| 308 | |
| 309 | static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) |
| 310 | { |
Richard Zhu | e149860 | 2011-03-25 09:18:27 -0400 | [diff] [blame] | 311 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 312 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
Tony Lin | 0d58864 | 2011-08-11 16:45:59 -0400 | [diff] [blame] | 313 | u32 data; |
Richard Zhu | e149860 | 2011-03-25 09:18:27 -0400 | [diff] [blame] | 314 | |
Tony Lin | 0d58864 | 2011-08-11 16:45:59 -0400 | [diff] [blame] | 315 | if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { |
Dong Aisheng | b732104 | 2015-05-27 18:13:27 +0800 | [diff] [blame] | 316 | if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { |
Tony Lin | 0d58864 | 2011-08-11 16:45:59 -0400 | [diff] [blame] | 317 | /* |
| 318 | * Clear and then set D3CD bit to avoid missing the |
| 319 | * card interrupt. This is a eSDHC controller problem |
| 320 | * so we need to apply the following workaround: clear |
| 321 | * and set D3CD bit will make eSDHC re-sample the card |
| 322 | * interrupt. In case a card interrupt was lost, |
| 323 | * re-sample it by the following steps. |
| 324 | */ |
| 325 | data = readl(host->ioaddr + SDHCI_HOST_CONTROL); |
Shawn Guo | 60bf639 | 2013-01-15 23:36:53 +0800 | [diff] [blame] | 326 | data &= ~ESDHC_CTRL_D3CD; |
Tony Lin | 0d58864 | 2011-08-11 16:45:59 -0400 | [diff] [blame] | 327 | writel(data, host->ioaddr + SDHCI_HOST_CONTROL); |
Shawn Guo | 60bf639 | 2013-01-15 23:36:53 +0800 | [diff] [blame] | 328 | data |= ESDHC_CTRL_D3CD; |
Tony Lin | 0d58864 | 2011-08-11 16:45:59 -0400 | [diff] [blame] | 329 | writel(data, host->ioaddr + SDHCI_HOST_CONTROL); |
| 330 | } |
Dong Aisheng | 915be485 | 2015-05-27 18:13:26 +0800 | [diff] [blame] | 331 | |
| 332 | if (val & SDHCI_INT_ADMA_ERROR) { |
| 333 | val &= ~SDHCI_INT_ADMA_ERROR; |
| 334 | val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; |
| 335 | } |
Tony Lin | 0d58864 | 2011-08-11 16:45:59 -0400 | [diff] [blame] | 336 | } |
Wolfram Sang | 7e29c30 | 2011-02-26 14:44:41 +0100 | [diff] [blame] | 337 | |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 338 | if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) |
Richard Zhu | 58ac817 | 2011-03-21 13:22:16 +0800 | [diff] [blame] | 339 | && (reg == SDHCI_INT_STATUS) |
| 340 | && (val & SDHCI_INT_DATA_END))) { |
| 341 | u32 v; |
Shawn Guo | 60bf639 | 2013-01-15 23:36:53 +0800 | [diff] [blame] | 342 | v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
| 343 | v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; |
| 344 | writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); |
Lucas Stach | 361b848 | 2013-03-15 09:49:26 +0100 | [diff] [blame] | 345 | |
| 346 | if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) |
| 347 | { |
| 348 | /* send a manual CMD12 with RESPTYP=none */ |
| 349 | data = MMC_STOP_TRANSMISSION << 24 | |
| 350 | SDHCI_CMD_ABORTCMD << 16; |
| 351 | writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); |
| 352 | imx_data->multiblock_status = WAIT_FOR_INT; |
| 353 | } |
Richard Zhu | 58ac817 | 2011-03-21 13:22:16 +0800 | [diff] [blame] | 354 | } |
| 355 | |
Wolfram Sang | 7e29c30 | 2011-02-26 14:44:41 +0100 | [diff] [blame] | 356 | writel(val, host->ioaddr + reg); |
| 357 | } |
| 358 | |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 359 | static u16 esdhc_readw_le(struct sdhci_host *host, int reg) |
| 360 | { |
Shawn Guo | ef4d088 | 2013-01-15 23:30:27 +0800 | [diff] [blame] | 361 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 362 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 363 | u16 ret = 0; |
| 364 | u32 val; |
Shawn Guo | ef4d088 | 2013-01-15 23:30:27 +0800 | [diff] [blame] | 365 | |
Shawn Guo | 95a2482 | 2011-09-19 17:32:21 +0800 | [diff] [blame] | 366 | if (unlikely(reg == SDHCI_HOST_VERSION)) { |
Shawn Guo | ef4d088 | 2013-01-15 23:30:27 +0800 | [diff] [blame] | 367 | reg ^= 2; |
Shawn Guo | 9d61c00 | 2013-10-17 15:19:45 +0800 | [diff] [blame] | 368 | if (esdhc_is_usdhc(imx_data)) { |
Shawn Guo | ef4d088 | 2013-01-15 23:30:27 +0800 | [diff] [blame] | 369 | /* |
| 370 | * The usdhc register returns a wrong host version. |
| 371 | * Correct it here. |
| 372 | */ |
| 373 | return SDHCI_SPEC_300; |
| 374 | } |
Shawn Guo | 95a2482 | 2011-09-19 17:32:21 +0800 | [diff] [blame] | 375 | } |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 376 | |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 377 | if (unlikely(reg == SDHCI_HOST_CONTROL2)) { |
| 378 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
| 379 | if (val & ESDHC_VENDOR_SPEC_VSELECT) |
| 380 | ret |= SDHCI_CTRL_VDD_180; |
| 381 | |
Shawn Guo | 9d61c00 | 2013-10-17 15:19:45 +0800 | [diff] [blame] | 382 | if (esdhc_is_usdhc(imx_data)) { |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 383 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) |
| 384 | val = readl(host->ioaddr + ESDHC_MIX_CTRL); |
| 385 | else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) |
| 386 | /* the std tuning bits is in ACMD12_ERR for imx6sl */ |
| 387 | val = readl(host->ioaddr + SDHCI_ACMD12_ERR); |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 388 | } |
| 389 | |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 390 | if (val & ESDHC_MIX_CTRL_EXE_TUNE) |
| 391 | ret |= SDHCI_CTRL_EXEC_TUNING; |
| 392 | if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) |
| 393 | ret |= SDHCI_CTRL_TUNED_CLK; |
| 394 | |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 395 | ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; |
| 396 | |
| 397 | return ret; |
| 398 | } |
| 399 | |
Dong Aisheng | 7dd109e | 2013-10-30 22:09:49 +0800 | [diff] [blame] | 400 | if (unlikely(reg == SDHCI_TRANSFER_MODE)) { |
| 401 | if (esdhc_is_usdhc(imx_data)) { |
| 402 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); |
| 403 | ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; |
| 404 | /* Swap AC23 bit */ |
| 405 | if (m & ESDHC_MIX_CTRL_AC23EN) { |
| 406 | ret &= ~ESDHC_MIX_CTRL_AC23EN; |
| 407 | ret |= SDHCI_TRNS_AUTO_CMD23; |
| 408 | } |
| 409 | } else { |
| 410 | ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); |
| 411 | } |
| 412 | |
| 413 | return ret; |
| 414 | } |
| 415 | |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 416 | return readw(host->ioaddr + reg); |
| 417 | } |
| 418 | |
| 419 | static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) |
| 420 | { |
| 421 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
Richard Zhu | e149860 | 2011-03-25 09:18:27 -0400 | [diff] [blame] | 422 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 423 | u32 new_val = 0; |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 424 | |
| 425 | switch (reg) { |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 426 | case SDHCI_CLOCK_CONTROL: |
| 427 | new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
| 428 | if (val & SDHCI_CLOCK_CARD_EN) |
| 429 | new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; |
| 430 | else |
| 431 | new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; |
Dan Carpenter | eeed702 | 2015-02-26 23:37:55 +0300 | [diff] [blame] | 432 | writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 433 | return; |
| 434 | case SDHCI_HOST_CONTROL2: |
| 435 | new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
| 436 | if (val & SDHCI_CTRL_VDD_180) |
| 437 | new_val |= ESDHC_VENDOR_SPEC_VSELECT; |
| 438 | else |
| 439 | new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; |
| 440 | writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 441 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { |
| 442 | new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); |
| 443 | if (val & SDHCI_CTRL_TUNED_CLK) |
| 444 | new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; |
| 445 | else |
| 446 | new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; |
| 447 | writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); |
| 448 | } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { |
| 449 | u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR); |
| 450 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); |
Dong Aisheng | 8b2bb0ad | 2013-11-04 16:38:27 +0800 | [diff] [blame] | 451 | if (val & SDHCI_CTRL_TUNED_CLK) { |
| 452 | v |= ESDHC_MIX_CTRL_SMPCLK_SEL; |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 453 | } else { |
Dong Aisheng | 8b2bb0ad | 2013-11-04 16:38:27 +0800 | [diff] [blame] | 454 | v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 455 | m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; |
| 456 | } |
| 457 | |
Dong Aisheng | 8b2bb0ad | 2013-11-04 16:38:27 +0800 | [diff] [blame] | 458 | if (val & SDHCI_CTRL_EXEC_TUNING) { |
| 459 | v |= ESDHC_MIX_CTRL_EXE_TUNE; |
| 460 | m |= ESDHC_MIX_CTRL_FBCLK_SEL; |
| 461 | } else { |
| 462 | v &= ~ESDHC_MIX_CTRL_EXE_TUNE; |
| 463 | } |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 464 | |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 465 | writel(v, host->ioaddr + SDHCI_ACMD12_ERR); |
| 466 | writel(m, host->ioaddr + ESDHC_MIX_CTRL); |
| 467 | } |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 468 | return; |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 469 | case SDHCI_TRANSFER_MODE: |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 470 | if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) |
Richard Zhu | 58ac817 | 2011-03-21 13:22:16 +0800 | [diff] [blame] | 471 | && (host->cmd->opcode == SD_IO_RW_EXTENDED) |
| 472 | && (host->cmd->data->blocks > 1) |
| 473 | && (host->cmd->data->flags & MMC_DATA_READ)) { |
| 474 | u32 v; |
Shawn Guo | 60bf639 | 2013-01-15 23:36:53 +0800 | [diff] [blame] | 475 | v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
| 476 | v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; |
| 477 | writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); |
Richard Zhu | 58ac817 | 2011-03-21 13:22:16 +0800 | [diff] [blame] | 478 | } |
Shawn Guo | 69f5469 | 2013-01-21 19:02:24 +0800 | [diff] [blame] | 479 | |
Shawn Guo | 9d61c00 | 2013-10-17 15:19:45 +0800 | [diff] [blame] | 480 | if (esdhc_is_usdhc(imx_data)) { |
Shawn Guo | 69f5469 | 2013-01-21 19:02:24 +0800 | [diff] [blame] | 481 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); |
Shawn Guo | 2a15f98 | 2013-01-21 19:02:26 +0800 | [diff] [blame] | 482 | /* Swap AC23 bit */ |
| 483 | if (val & SDHCI_TRNS_AUTO_CMD23) { |
| 484 | val &= ~SDHCI_TRNS_AUTO_CMD23; |
| 485 | val |= ESDHC_MIX_CTRL_AC23EN; |
| 486 | } |
| 487 | m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); |
Shawn Guo | 69f5469 | 2013-01-21 19:02:24 +0800 | [diff] [blame] | 488 | writel(m, host->ioaddr + ESDHC_MIX_CTRL); |
| 489 | } else { |
| 490 | /* |
| 491 | * Postpone this write, we must do it together with a |
| 492 | * command write that is down below. |
| 493 | */ |
| 494 | imx_data->scratchpad = val; |
| 495 | } |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 496 | return; |
| 497 | case SDHCI_COMMAND: |
Lucas Stach | 361b848 | 2013-03-15 09:49:26 +0100 | [diff] [blame] | 498 | if (host->cmd->opcode == MMC_STOP_TRANSMISSION) |
Richard Zhu | 58ac817 | 2011-03-21 13:22:16 +0800 | [diff] [blame] | 499 | val |= SDHCI_CMD_ABORTCMD; |
Shawn Guo | 95a2482 | 2011-09-19 17:32:21 +0800 | [diff] [blame] | 500 | |
Lucas Stach | 361b848 | 2013-03-15 09:49:26 +0100 | [diff] [blame] | 501 | if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 502 | (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) |
Lucas Stach | 361b848 | 2013-03-15 09:49:26 +0100 | [diff] [blame] | 503 | imx_data->multiblock_status = MULTIBLK_IN_PROCESS; |
| 504 | |
Shawn Guo | 9d61c00 | 2013-10-17 15:19:45 +0800 | [diff] [blame] | 505 | if (esdhc_is_usdhc(imx_data)) |
Shawn Guo | 95a2482 | 2011-09-19 17:32:21 +0800 | [diff] [blame] | 506 | writel(val << 16, |
| 507 | host->ioaddr + SDHCI_TRANSFER_MODE); |
Shawn Guo | 69f5469 | 2013-01-21 19:02:24 +0800 | [diff] [blame] | 508 | else |
Shawn Guo | 95a2482 | 2011-09-19 17:32:21 +0800 | [diff] [blame] | 509 | writel(val << 16 | imx_data->scratchpad, |
| 510 | host->ioaddr + SDHCI_TRANSFER_MODE); |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 511 | return; |
| 512 | case SDHCI_BLOCK_SIZE: |
| 513 | val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); |
| 514 | break; |
| 515 | } |
| 516 | esdhc_clrset_le(host, 0xffff, val, reg); |
| 517 | } |
| 518 | |
| 519 | static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) |
| 520 | { |
Wilson Callan | 9a0985b | 2012-07-19 02:49:16 -0400 | [diff] [blame] | 521 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 522 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 523 | u32 new_val; |
Sascha Hauer | af51079 | 2013-01-21 19:02:28 +0800 | [diff] [blame] | 524 | u32 mask; |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 525 | |
| 526 | switch (reg) { |
| 527 | case SDHCI_POWER_CONTROL: |
| 528 | /* |
| 529 | * FSL put some DMA bits here |
| 530 | * If your board has a regulator, code should be here |
| 531 | */ |
| 532 | return; |
| 533 | case SDHCI_HOST_CONTROL: |
Shawn Guo | 6b40d18 | 2013-01-15 23:36:52 +0800 | [diff] [blame] | 534 | /* FSL messed up here, so we need to manually compose it. */ |
Sascha Hauer | af51079 | 2013-01-21 19:02:28 +0800 | [diff] [blame] | 535 | new_val = val & SDHCI_CTRL_LED; |
Masanari Iida | 7122bbb | 2012-08-05 23:25:40 +0900 | [diff] [blame] | 536 | /* ensure the endianness */ |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 537 | new_val |= ESDHC_HOST_CONTROL_LE; |
Wilson Callan | 9a0985b | 2012-07-19 02:49:16 -0400 | [diff] [blame] | 538 | /* bits 8&9 are reserved on mx25 */ |
| 539 | if (!is_imx25_esdhc(imx_data)) { |
| 540 | /* DMA mode bits are shifted */ |
| 541 | new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; |
| 542 | } |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 543 | |
Sascha Hauer | af51079 | 2013-01-21 19:02:28 +0800 | [diff] [blame] | 544 | /* |
| 545 | * Do not touch buswidth bits here. This is done in |
| 546 | * esdhc_pltfm_bus_width. |
Martin Fuzzey | f682574 | 2013-04-15 17:08:35 +0200 | [diff] [blame] | 547 | * Do not touch the D3CD bit either which is used for the |
| 548 | * SDIO interrupt errata workaround. |
Sascha Hauer | af51079 | 2013-01-21 19:02:28 +0800 | [diff] [blame] | 549 | */ |
Martin Fuzzey | f682574 | 2013-04-15 17:08:35 +0200 | [diff] [blame] | 550 | mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); |
Sascha Hauer | af51079 | 2013-01-21 19:02:28 +0800 | [diff] [blame] | 551 | |
| 552 | esdhc_clrset_le(host, mask, new_val, reg); |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 553 | return; |
| 554 | } |
| 555 | esdhc_clrset_le(host, 0xff, val, reg); |
Shawn Guo | 913413c | 2011-06-21 22:41:51 +0800 | [diff] [blame] | 556 | |
| 557 | /* |
| 558 | * The esdhc has a design violation to SDHC spec which tells |
| 559 | * that software reset should not affect card detection circuit. |
| 560 | * But esdhc clears its SYSCTL register bits [0..2] during the |
| 561 | * software reset. This will stop those clocks that card detection |
| 562 | * circuit relies on. To work around it, we turn the clocks on back |
| 563 | * to keep card detection circuit functional. |
| 564 | */ |
Shawn Guo | 58c8c4f | 2013-01-21 19:02:25 +0800 | [diff] [blame] | 565 | if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) { |
Shawn Guo | 913413c | 2011-06-21 22:41:51 +0800 | [diff] [blame] | 566 | esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); |
Shawn Guo | 58c8c4f | 2013-01-21 19:02:25 +0800 | [diff] [blame] | 567 | /* |
| 568 | * The reset on usdhc fails to clear MIX_CTRL register. |
| 569 | * Do it manually here. |
| 570 | */ |
Dong Aisheng | de5bdbf | 2013-10-18 19:48:46 +0800 | [diff] [blame] | 571 | if (esdhc_is_usdhc(imx_data)) { |
Dong Aisheng | d131a71 | 2013-11-04 16:38:26 +0800 | [diff] [blame] | 572 | /* the tuning bits should be kept during reset */ |
| 573 | new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); |
| 574 | writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, |
| 575 | host->ioaddr + ESDHC_MIX_CTRL); |
Dong Aisheng | de5bdbf | 2013-10-18 19:48:46 +0800 | [diff] [blame] | 576 | imx_data->is_ddr = 0; |
| 577 | } |
Shawn Guo | 58c8c4f | 2013-01-21 19:02:25 +0800 | [diff] [blame] | 578 | } |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 579 | } |
| 580 | |
Lucas Stach | 0ddf03c | 2013-06-05 15:13:26 +0200 | [diff] [blame] | 581 | static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) |
| 582 | { |
| 583 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
Lucas Stach | 0ddf03c | 2013-06-05 15:13:26 +0200 | [diff] [blame] | 584 | |
Dong Aisheng | a3bd4f9 | 2015-07-22 20:53:09 +0800 | [diff] [blame] | 585 | return pltfm_host->clock; |
Lucas Stach | 0ddf03c | 2013-06-05 15:13:26 +0200 | [diff] [blame] | 586 | } |
| 587 | |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 588 | static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) |
| 589 | { |
| 590 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 591 | |
Dong Aisheng | a974862 | 2013-12-26 15:23:53 +0800 | [diff] [blame] | 592 | return pltfm_host->clock / 256 / 16; |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 593 | } |
| 594 | |
Lucas Stach | 8ba9580 | 2013-06-05 15:13:25 +0200 | [diff] [blame] | 595 | static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, |
| 596 | unsigned int clock) |
| 597 | { |
| 598 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
Dong Aisheng | fed2f6e | 2013-09-13 19:11:33 +0800 | [diff] [blame] | 599 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
Dong Aisheng | a974862 | 2013-12-26 15:23:53 +0800 | [diff] [blame] | 600 | unsigned int host_clock = pltfm_host->clock; |
Dong Aisheng | d31fc00 | 2013-09-13 19:11:32 +0800 | [diff] [blame] | 601 | int pre_div = 2; |
| 602 | int div = 1; |
Dong Aisheng | fed2f6e | 2013-09-13 19:11:33 +0800 | [diff] [blame] | 603 | u32 temp, val; |
Lucas Stach | 8ba9580 | 2013-06-05 15:13:25 +0200 | [diff] [blame] | 604 | |
Dong Aisheng | fed2f6e | 2013-09-13 19:11:33 +0800 | [diff] [blame] | 605 | if (clock == 0) { |
Russell King | 1650d0c | 2014-04-25 12:58:50 +0100 | [diff] [blame] | 606 | host->mmc->actual_clock = 0; |
| 607 | |
Shawn Guo | 9d61c00 | 2013-10-17 15:19:45 +0800 | [diff] [blame] | 608 | if (esdhc_is_usdhc(imx_data)) { |
Dong Aisheng | fed2f6e | 2013-09-13 19:11:33 +0800 | [diff] [blame] | 609 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
| 610 | writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, |
| 611 | host->ioaddr + ESDHC_VENDOR_SPEC); |
| 612 | } |
Russell King | 373073e | 2014-04-25 12:58:45 +0100 | [diff] [blame] | 613 | return; |
Dong Aisheng | fed2f6e | 2013-09-13 19:11:33 +0800 | [diff] [blame] | 614 | } |
Dong Aisheng | d31fc00 | 2013-09-13 19:11:32 +0800 | [diff] [blame] | 615 | |
Dong Aisheng | de5bdbf | 2013-10-18 19:48:46 +0800 | [diff] [blame] | 616 | if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr) |
Dong Aisheng | 5f7886c | 2013-09-13 19:11:36 +0800 | [diff] [blame] | 617 | pre_div = 1; |
| 618 | |
Dong Aisheng | d31fc00 | 2013-09-13 19:11:32 +0800 | [diff] [blame] | 619 | temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); |
| 620 | temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN |
| 621 | | ESDHC_CLOCK_MASK); |
| 622 | sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); |
| 623 | |
| 624 | while (host_clock / pre_div / 16 > clock && pre_div < 256) |
| 625 | pre_div *= 2; |
| 626 | |
| 627 | while (host_clock / pre_div / div > clock && div < 16) |
| 628 | div++; |
| 629 | |
Dong Aisheng | e76b855 | 2013-09-13 19:11:37 +0800 | [diff] [blame] | 630 | host->mmc->actual_clock = host_clock / pre_div / div; |
Dong Aisheng | d31fc00 | 2013-09-13 19:11:32 +0800 | [diff] [blame] | 631 | dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", |
Dong Aisheng | e76b855 | 2013-09-13 19:11:37 +0800 | [diff] [blame] | 632 | clock, host->mmc->actual_clock); |
Dong Aisheng | d31fc00 | 2013-09-13 19:11:32 +0800 | [diff] [blame] | 633 | |
Dong Aisheng | de5bdbf | 2013-10-18 19:48:46 +0800 | [diff] [blame] | 634 | if (imx_data->is_ddr) |
| 635 | pre_div >>= 2; |
| 636 | else |
| 637 | pre_div >>= 1; |
Dong Aisheng | d31fc00 | 2013-09-13 19:11:32 +0800 | [diff] [blame] | 638 | div--; |
| 639 | |
| 640 | temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); |
| 641 | temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN |
| 642 | | (div << ESDHC_DIVIDER_SHIFT) |
| 643 | | (pre_div << ESDHC_PREDIV_SHIFT)); |
| 644 | sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); |
Dong Aisheng | fed2f6e | 2013-09-13 19:11:33 +0800 | [diff] [blame] | 645 | |
Shawn Guo | 9d61c00 | 2013-10-17 15:19:45 +0800 | [diff] [blame] | 646 | if (esdhc_is_usdhc(imx_data)) { |
Dong Aisheng | fed2f6e | 2013-09-13 19:11:33 +0800 | [diff] [blame] | 647 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
| 648 | writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, |
| 649 | host->ioaddr + ESDHC_VENDOR_SPEC); |
| 650 | } |
| 651 | |
Dong Aisheng | d31fc00 | 2013-09-13 19:11:32 +0800 | [diff] [blame] | 652 | mdelay(1); |
Lucas Stach | 8ba9580 | 2013-06-05 15:13:25 +0200 | [diff] [blame] | 653 | } |
| 654 | |
Shawn Guo | 913413c | 2011-06-21 22:41:51 +0800 | [diff] [blame] | 655 | static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) |
| 656 | { |
Shawn Guo | 842afc0 | 2011-07-06 22:57:48 +0800 | [diff] [blame] | 657 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 658 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
| 659 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; |
Shawn Guo | 913413c | 2011-06-21 22:41:51 +0800 | [diff] [blame] | 660 | |
| 661 | switch (boarddata->wp_type) { |
| 662 | case ESDHC_WP_GPIO: |
Shawn Guo | fbe5fdd | 2012-12-11 22:32:20 +0800 | [diff] [blame] | 663 | return mmc_gpio_get_ro(host->mmc); |
Shawn Guo | 913413c | 2011-06-21 22:41:51 +0800 | [diff] [blame] | 664 | case ESDHC_WP_CONTROLLER: |
| 665 | return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & |
| 666 | SDHCI_WRITE_PROTECT); |
| 667 | case ESDHC_WP_NONE: |
| 668 | break; |
| 669 | } |
| 670 | |
| 671 | return -ENOSYS; |
| 672 | } |
| 673 | |
Russell King | 2317f56 | 2014-04-25 12:57:07 +0100 | [diff] [blame] | 674 | static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) |
Sascha Hauer | af51079 | 2013-01-21 19:02:28 +0800 | [diff] [blame] | 675 | { |
| 676 | u32 ctrl; |
| 677 | |
| 678 | switch (width) { |
| 679 | case MMC_BUS_WIDTH_8: |
| 680 | ctrl = ESDHC_CTRL_8BITBUS; |
| 681 | break; |
| 682 | case MMC_BUS_WIDTH_4: |
| 683 | ctrl = ESDHC_CTRL_4BITBUS; |
| 684 | break; |
| 685 | default: |
| 686 | ctrl = 0; |
| 687 | break; |
| 688 | } |
| 689 | |
| 690 | esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, |
| 691 | SDHCI_HOST_CONTROL); |
Sascha Hauer | af51079 | 2013-01-21 19:02:28 +0800 | [diff] [blame] | 692 | } |
| 693 | |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 694 | static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) |
| 695 | { |
| 696 | u32 reg; |
| 697 | |
| 698 | /* FIXME: delay a bit for card to be ready for next tuning due to errors */ |
| 699 | mdelay(1); |
| 700 | |
| 701 | reg = readl(host->ioaddr + ESDHC_MIX_CTRL); |
| 702 | reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | |
| 703 | ESDHC_MIX_CTRL_FBCLK_SEL; |
| 704 | writel(reg, host->ioaddr + ESDHC_MIX_CTRL); |
| 705 | writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); |
| 706 | dev_dbg(mmc_dev(host->mmc), |
| 707 | "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", |
| 708 | val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); |
| 709 | } |
| 710 | |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 711 | static void esdhc_post_tuning(struct sdhci_host *host) |
| 712 | { |
| 713 | u32 reg; |
| 714 | |
| 715 | reg = readl(host->ioaddr + ESDHC_MIX_CTRL); |
| 716 | reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; |
| 717 | writel(reg, host->ioaddr + ESDHC_MIX_CTRL); |
| 718 | } |
| 719 | |
| 720 | static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) |
| 721 | { |
| 722 | int min, max, avg, ret; |
| 723 | |
| 724 | /* find the mininum delay first which can pass tuning */ |
| 725 | min = ESDHC_TUNE_CTRL_MIN; |
| 726 | while (min < ESDHC_TUNE_CTRL_MAX) { |
| 727 | esdhc_prepare_tuning(host, min); |
Ulf Hansson | d178532 | 2014-12-05 12:59:40 +0100 | [diff] [blame] | 728 | if (!mmc_send_tuning(host->mmc)) |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 729 | break; |
| 730 | min += ESDHC_TUNE_CTRL_STEP; |
| 731 | } |
| 732 | |
| 733 | /* find the maxinum delay which can not pass tuning */ |
| 734 | max = min + ESDHC_TUNE_CTRL_STEP; |
| 735 | while (max < ESDHC_TUNE_CTRL_MAX) { |
| 736 | esdhc_prepare_tuning(host, max); |
Ulf Hansson | d178532 | 2014-12-05 12:59:40 +0100 | [diff] [blame] | 737 | if (mmc_send_tuning(host->mmc)) { |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 738 | max -= ESDHC_TUNE_CTRL_STEP; |
| 739 | break; |
| 740 | } |
| 741 | max += ESDHC_TUNE_CTRL_STEP; |
| 742 | } |
| 743 | |
| 744 | /* use average delay to get the best timing */ |
| 745 | avg = (min + max) / 2; |
| 746 | esdhc_prepare_tuning(host, avg); |
Ulf Hansson | d178532 | 2014-12-05 12:59:40 +0100 | [diff] [blame] | 747 | ret = mmc_send_tuning(host->mmc); |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 748 | esdhc_post_tuning(host); |
| 749 | |
| 750 | dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n", |
| 751 | ret ? "failed" : "passed", avg, ret); |
| 752 | |
| 753 | return ret; |
| 754 | } |
| 755 | |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 756 | static int esdhc_change_pinstate(struct sdhci_host *host, |
| 757 | unsigned int uhs) |
| 758 | { |
| 759 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 760 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
| 761 | struct pinctrl_state *pinctrl; |
| 762 | |
| 763 | dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); |
| 764 | |
| 765 | if (IS_ERR(imx_data->pinctrl) || |
| 766 | IS_ERR(imx_data->pins_default) || |
| 767 | IS_ERR(imx_data->pins_100mhz) || |
| 768 | IS_ERR(imx_data->pins_200mhz)) |
| 769 | return -EINVAL; |
| 770 | |
| 771 | switch (uhs) { |
| 772 | case MMC_TIMING_UHS_SDR50: |
| 773 | pinctrl = imx_data->pins_100mhz; |
| 774 | break; |
| 775 | case MMC_TIMING_UHS_SDR104: |
Dong Aisheng | 429a5b4 | 2013-10-30 22:10:42 +0800 | [diff] [blame] | 776 | case MMC_TIMING_MMC_HS200: |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 777 | pinctrl = imx_data->pins_200mhz; |
| 778 | break; |
| 779 | default: |
| 780 | /* back to default state for other legacy timing */ |
| 781 | pinctrl = imx_data->pins_default; |
| 782 | } |
| 783 | |
| 784 | return pinctrl_select_state(imx_data->pinctrl, pinctrl); |
| 785 | } |
| 786 | |
Russell King | 850a29b | 2014-04-25 12:59:41 +0100 | [diff] [blame] | 787 | static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 788 | { |
| 789 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 790 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
Dong Aisheng | 602519b | 2013-10-18 19:48:47 +0800 | [diff] [blame] | 791 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 792 | |
Russell King | 850a29b | 2014-04-25 12:59:41 +0100 | [diff] [blame] | 793 | switch (timing) { |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 794 | case MMC_TIMING_UHS_SDR12: |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 795 | case MMC_TIMING_UHS_SDR25: |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 796 | case MMC_TIMING_UHS_SDR50: |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 797 | case MMC_TIMING_UHS_SDR104: |
Dong Aisheng | 429a5b4 | 2013-10-30 22:10:42 +0800 | [diff] [blame] | 798 | case MMC_TIMING_MMC_HS200: |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 799 | break; |
| 800 | case MMC_TIMING_UHS_DDR50: |
Aisheng Dong | 69f5bf3 | 2014-05-09 14:53:15 +0800 | [diff] [blame] | 801 | case MMC_TIMING_MMC_DDR52: |
Dong Aisheng | de5bdbf | 2013-10-18 19:48:46 +0800 | [diff] [blame] | 802 | writel(readl(host->ioaddr + ESDHC_MIX_CTRL) | |
| 803 | ESDHC_MIX_CTRL_DDREN, |
| 804 | host->ioaddr + ESDHC_MIX_CTRL); |
| 805 | imx_data->is_ddr = 1; |
Dong Aisheng | 602519b | 2013-10-18 19:48:47 +0800 | [diff] [blame] | 806 | if (boarddata->delay_line) { |
| 807 | u32 v; |
| 808 | v = boarddata->delay_line << |
| 809 | ESDHC_DLL_OVERRIDE_VAL_SHIFT | |
| 810 | (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); |
| 811 | if (is_imx53_esdhc(imx_data)) |
| 812 | v <<= 1; |
| 813 | writel(v, host->ioaddr + ESDHC_DLL_CTRL); |
| 814 | } |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 815 | break; |
| 816 | } |
| 817 | |
Russell King | 850a29b | 2014-04-25 12:59:41 +0100 | [diff] [blame] | 818 | esdhc_change_pinstate(host, timing); |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 819 | } |
| 820 | |
Russell King | 0718e59 | 2014-04-25 12:57:18 +0100 | [diff] [blame] | 821 | static void esdhc_reset(struct sdhci_host *host, u8 mask) |
| 822 | { |
| 823 | sdhci_reset(host, mask); |
| 824 | |
| 825 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 826 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
| 827 | } |
| 828 | |
Aisheng Dong | 10fd0ad | 2014-08-27 15:26:28 +0800 | [diff] [blame] | 829 | static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) |
| 830 | { |
| 831 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 832 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
| 833 | |
| 834 | return esdhc_is_usdhc(imx_data) ? 1 << 28 : 1 << 27; |
| 835 | } |
| 836 | |
Aisheng Dong | e33eb8e2 | 2014-08-27 15:26:30 +0800 | [diff] [blame] | 837 | static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
| 838 | { |
| 839 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 840 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
| 841 | |
| 842 | /* use maximum timeout counter */ |
| 843 | sdhci_writeb(host, esdhc_is_usdhc(imx_data) ? 0xF : 0xE, |
| 844 | SDHCI_TIMEOUT_CONTROL); |
| 845 | } |
| 846 | |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 847 | static struct sdhci_ops sdhci_esdhc_ops = { |
Richard Zhu | e149860 | 2011-03-25 09:18:27 -0400 | [diff] [blame] | 848 | .read_l = esdhc_readl_le, |
Wolfram Sang | 0c6d49c | 2011-02-26 14:44:39 +0100 | [diff] [blame] | 849 | .read_w = esdhc_readw_le, |
Richard Zhu | e149860 | 2011-03-25 09:18:27 -0400 | [diff] [blame] | 850 | .write_l = esdhc_writel_le, |
Wolfram Sang | 0c6d49c | 2011-02-26 14:44:39 +0100 | [diff] [blame] | 851 | .write_w = esdhc_writew_le, |
| 852 | .write_b = esdhc_writeb_le, |
Lucas Stach | 8ba9580 | 2013-06-05 15:13:25 +0200 | [diff] [blame] | 853 | .set_clock = esdhc_pltfm_set_clock, |
Lucas Stach | 0ddf03c | 2013-06-05 15:13:26 +0200 | [diff] [blame] | 854 | .get_max_clock = esdhc_pltfm_get_max_clock, |
Wolfram Sang | 0c6d49c | 2011-02-26 14:44:39 +0100 | [diff] [blame] | 855 | .get_min_clock = esdhc_pltfm_get_min_clock, |
Aisheng Dong | 10fd0ad | 2014-08-27 15:26:28 +0800 | [diff] [blame] | 856 | .get_max_timeout_count = esdhc_get_max_timeout_count, |
Shawn Guo | 913413c | 2011-06-21 22:41:51 +0800 | [diff] [blame] | 857 | .get_ro = esdhc_pltfm_get_ro, |
Aisheng Dong | e33eb8e2 | 2014-08-27 15:26:30 +0800 | [diff] [blame] | 858 | .set_timeout = esdhc_set_timeout, |
Russell King | 2317f56 | 2014-04-25 12:57:07 +0100 | [diff] [blame] | 859 | .set_bus_width = esdhc_pltfm_set_bus_width, |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 860 | .set_uhs_signaling = esdhc_set_uhs_signaling, |
Russell King | 0718e59 | 2014-04-25 12:57:18 +0100 | [diff] [blame] | 861 | .reset = esdhc_reset, |
Wolfram Sang | 0c6d49c | 2011-02-26 14:44:39 +0100 | [diff] [blame] | 862 | }; |
| 863 | |
Lars-Peter Clausen | 1db5eeb | 2013-03-13 19:26:03 +0100 | [diff] [blame] | 864 | static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { |
Richard Zhu | 97e4ba6 | 2011-08-11 16:51:46 -0400 | [diff] [blame] | 865 | .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT |
| 866 | | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
| 867 | | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 868 | | SDHCI_QUIRK_BROKEN_CARD_DETECTION, |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 869 | .ops = &sdhci_esdhc_ops, |
| 870 | }; |
| 871 | |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 872 | #ifdef CONFIG_OF |
Bill Pemberton | c3be1ef | 2012-11-19 13:23:06 -0500 | [diff] [blame] | 873 | static int |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 874 | sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, |
Sascha Hauer | 07bf2b5 | 2015-03-24 14:45:04 +0100 | [diff] [blame] | 875 | struct sdhci_host *host, |
Dong Aisheng | 91fa425 | 2015-07-22 20:53:06 +0800 | [diff] [blame] | 876 | struct pltfm_imx_data *imx_data) |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 877 | { |
| 878 | struct device_node *np = pdev->dev.of_node; |
Dong Aisheng | 91fa425 | 2015-07-22 20:53:06 +0800 | [diff] [blame] | 879 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; |
Dong Aisheng | 4800e87 | 2015-07-22 20:53:05 +0800 | [diff] [blame] | 880 | int ret; |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 881 | |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 882 | if (of_get_property(np, "fsl,wp-controller", NULL)) |
| 883 | boarddata->wp_type = ESDHC_WP_CONTROLLER; |
| 884 | |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 885 | boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); |
| 886 | if (gpio_is_valid(boarddata->wp_gpio)) |
| 887 | boarddata->wp_type = ESDHC_WP_GPIO; |
| 888 | |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 889 | if (of_find_property(np, "no-1-8-v", NULL)) |
| 890 | boarddata->support_vsel = false; |
| 891 | else |
| 892 | boarddata->support_vsel = true; |
| 893 | |
Dong Aisheng | 602519b | 2013-10-18 19:48:47 +0800 | [diff] [blame] | 894 | if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) |
| 895 | boarddata->delay_line = 0; |
| 896 | |
Sascha Hauer | 07bf2b5 | 2015-03-24 14:45:04 +0100 | [diff] [blame] | 897 | mmc_of_parse_voltage(np, &host->ocr_mask); |
| 898 | |
Dong Aisheng | 91fa425 | 2015-07-22 20:53:06 +0800 | [diff] [blame] | 899 | /* sdr50 and sdr104 needs work on 1.8v signal voltage */ |
| 900 | if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) && |
| 901 | !IS_ERR(imx_data->pins_default)) { |
| 902 | imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, |
| 903 | ESDHC_PINCTRL_STATE_100MHZ); |
| 904 | imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, |
| 905 | ESDHC_PINCTRL_STATE_200MHZ); |
| 906 | if (IS_ERR(imx_data->pins_100mhz) || |
| 907 | IS_ERR(imx_data->pins_200mhz)) { |
| 908 | dev_warn(mmc_dev(host->mmc), |
| 909 | "could not get ultra high speed state, work on normal mode\n"); |
| 910 | /* |
| 911 | * fall back to not support uhs by specify no 1.8v quirk |
| 912 | */ |
| 913 | host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; |
| 914 | } |
| 915 | } else { |
| 916 | host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; |
| 917 | } |
| 918 | |
Fabio Estevam | 1506411 | 2015-05-09 09:57:08 -0300 | [diff] [blame] | 919 | /* call to generic mmc_of_parse to support additional capabilities */ |
Dong Aisheng | 4800e87 | 2015-07-22 20:53:05 +0800 | [diff] [blame] | 920 | ret = mmc_of_parse(host->mmc); |
| 921 | if (ret) |
| 922 | return ret; |
| 923 | |
| 924 | if (!IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc))) |
| 925 | host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; |
| 926 | |
| 927 | return 0; |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 928 | } |
| 929 | #else |
| 930 | static inline int |
| 931 | sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, |
Sascha Hauer | 07bf2b5 | 2015-03-24 14:45:04 +0100 | [diff] [blame] | 932 | struct sdhci_host *host, |
Dong Aisheng | 91fa425 | 2015-07-22 20:53:06 +0800 | [diff] [blame] | 933 | struct pltfm_imx_data *imx_data) |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 934 | { |
| 935 | return -ENODEV; |
| 936 | } |
| 937 | #endif |
| 938 | |
Dong Aisheng | 91fa425 | 2015-07-22 20:53:06 +0800 | [diff] [blame] | 939 | static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev, |
| 940 | struct sdhci_host *host, |
| 941 | struct pltfm_imx_data *imx_data) |
| 942 | { |
| 943 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; |
| 944 | int err; |
| 945 | |
| 946 | if (!host->mmc->parent->platform_data) { |
| 947 | dev_err(mmc_dev(host->mmc), "no board data!\n"); |
| 948 | return -EINVAL; |
| 949 | } |
| 950 | |
| 951 | imx_data->boarddata = *((struct esdhc_platform_data *) |
| 952 | host->mmc->parent->platform_data); |
| 953 | /* write_protect */ |
| 954 | if (boarddata->wp_type == ESDHC_WP_GPIO) { |
| 955 | err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); |
| 956 | if (err) { |
| 957 | dev_err(mmc_dev(host->mmc), |
| 958 | "failed to request write-protect gpio!\n"); |
| 959 | return err; |
| 960 | } |
| 961 | host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; |
| 962 | } |
| 963 | |
| 964 | /* card_detect */ |
| 965 | switch (boarddata->cd_type) { |
| 966 | case ESDHC_CD_GPIO: |
| 967 | err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0); |
| 968 | if (err) { |
| 969 | dev_err(mmc_dev(host->mmc), |
| 970 | "failed to request card-detect gpio!\n"); |
| 971 | return err; |
| 972 | } |
| 973 | /* fall through */ |
| 974 | |
| 975 | case ESDHC_CD_CONTROLLER: |
| 976 | /* we have a working card_detect back */ |
| 977 | host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; |
| 978 | break; |
| 979 | |
| 980 | case ESDHC_CD_PERMANENT: |
| 981 | host->mmc->caps |= MMC_CAP_NONREMOVABLE; |
| 982 | break; |
| 983 | |
| 984 | case ESDHC_CD_NONE: |
| 985 | break; |
| 986 | } |
| 987 | |
| 988 | switch (boarddata->max_bus_width) { |
| 989 | case 8: |
| 990 | host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; |
| 991 | break; |
| 992 | case 4: |
| 993 | host->mmc->caps |= MMC_CAP_4_BIT_DATA; |
| 994 | break; |
| 995 | case 1: |
| 996 | default: |
| 997 | host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; |
| 998 | break; |
| 999 | } |
| 1000 | |
| 1001 | return 0; |
| 1002 | } |
| 1003 | |
Bill Pemberton | c3be1ef | 2012-11-19 13:23:06 -0500 | [diff] [blame] | 1004 | static int sdhci_esdhc_imx_probe(struct platform_device *pdev) |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 1005 | { |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 1006 | const struct of_device_id *of_id = |
| 1007 | of_match_device(imx_esdhc_dt_ids, &pdev->dev); |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1008 | struct sdhci_pltfm_host *pltfm_host; |
| 1009 | struct sdhci_host *host; |
Wolfram Sang | 0c6d49c | 2011-02-26 14:44:39 +0100 | [diff] [blame] | 1010 | int err; |
Richard Zhu | e149860 | 2011-03-25 09:18:27 -0400 | [diff] [blame] | 1011 | struct pltfm_imx_data *imx_data; |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 1012 | |
Christian Daudt | 0e74823 | 2013-05-29 13:50:05 -0700 | [diff] [blame] | 1013 | host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0); |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1014 | if (IS_ERR(host)) |
| 1015 | return PTR_ERR(host); |
| 1016 | |
| 1017 | pltfm_host = sdhci_priv(host); |
| 1018 | |
Shawn Guo | e3af31c | 2012-11-26 14:39:43 +0800 | [diff] [blame] | 1019 | imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL); |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 1020 | if (!imx_data) { |
| 1021 | err = -ENOMEM; |
Shawn Guo | e3af31c | 2012-11-26 14:39:43 +0800 | [diff] [blame] | 1022 | goto free_sdhci; |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 1023 | } |
Shawn Guo | 57ed331 | 2011-06-30 09:24:26 +0800 | [diff] [blame] | 1024 | |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 1025 | imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) |
| 1026 | pdev->id_entry->driver_data; |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1027 | pltfm_host->priv = imx_data; |
| 1028 | |
Sascha Hauer | 52dac61 | 2012-03-07 09:31:34 +0100 | [diff] [blame] | 1029 | imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
| 1030 | if (IS_ERR(imx_data->clk_ipg)) { |
| 1031 | err = PTR_ERR(imx_data->clk_ipg); |
Shawn Guo | e3af31c | 2012-11-26 14:39:43 +0800 | [diff] [blame] | 1032 | goto free_sdhci; |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 1033 | } |
Sascha Hauer | 52dac61 | 2012-03-07 09:31:34 +0100 | [diff] [blame] | 1034 | |
| 1035 | imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); |
| 1036 | if (IS_ERR(imx_data->clk_ahb)) { |
| 1037 | err = PTR_ERR(imx_data->clk_ahb); |
Shawn Guo | e3af31c | 2012-11-26 14:39:43 +0800 | [diff] [blame] | 1038 | goto free_sdhci; |
Sascha Hauer | 52dac61 | 2012-03-07 09:31:34 +0100 | [diff] [blame] | 1039 | } |
| 1040 | |
| 1041 | imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); |
| 1042 | if (IS_ERR(imx_data->clk_per)) { |
| 1043 | err = PTR_ERR(imx_data->clk_per); |
Shawn Guo | e3af31c | 2012-11-26 14:39:43 +0800 | [diff] [blame] | 1044 | goto free_sdhci; |
Sascha Hauer | 52dac61 | 2012-03-07 09:31:34 +0100 | [diff] [blame] | 1045 | } |
| 1046 | |
| 1047 | pltfm_host->clk = imx_data->clk_per; |
Dong Aisheng | a974862 | 2013-12-26 15:23:53 +0800 | [diff] [blame] | 1048 | pltfm_host->clock = clk_get_rate(pltfm_host->clk); |
Sascha Hauer | 52dac61 | 2012-03-07 09:31:34 +0100 | [diff] [blame] | 1049 | clk_prepare_enable(imx_data->clk_per); |
| 1050 | clk_prepare_enable(imx_data->clk_ipg); |
| 1051 | clk_prepare_enable(imx_data->clk_ahb); |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 1052 | |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 1053 | imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); |
Dong Aisheng | e62d8b8 | 2012-05-11 14:56:01 +0800 | [diff] [blame] | 1054 | if (IS_ERR(imx_data->pinctrl)) { |
| 1055 | err = PTR_ERR(imx_data->pinctrl); |
Shawn Guo | e3af31c | 2012-11-26 14:39:43 +0800 | [diff] [blame] | 1056 | goto disable_clk; |
Dong Aisheng | e62d8b8 | 2012-05-11 14:56:01 +0800 | [diff] [blame] | 1057 | } |
| 1058 | |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 1059 | imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, |
| 1060 | PINCTRL_STATE_DEFAULT); |
Dirk Behme | cd529af | 2014-10-01 04:25:32 -0500 | [diff] [blame] | 1061 | if (IS_ERR(imx_data->pins_default)) |
| 1062 | dev_warn(mmc_dev(host->mmc), "could not get default state\n"); |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 1063 | |
Eric Bénard | b8915282 | 2012-04-18 02:30:20 +0200 | [diff] [blame] | 1064 | host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; |
Eric Bénard | 37865fe | 2010-10-23 01:57:21 +0200 | [diff] [blame] | 1065 | |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 1066 | if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207) |
Wolfram Sang | 0c6d49c | 2011-02-26 14:44:39 +0100 | [diff] [blame] | 1067 | /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ |
Richard Zhu | 97e4ba6 | 2011-08-11 16:51:46 -0400 | [diff] [blame] | 1068 | host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK |
| 1069 | | SDHCI_QUIRK_BROKEN_ADMA; |
Wolfram Sang | 0c6d49c | 2011-02-26 14:44:39 +0100 | [diff] [blame] | 1070 | |
Shawn Guo | f750ba9 | 2011-11-10 16:39:32 +0800 | [diff] [blame] | 1071 | /* |
| 1072 | * The imx6q ROM code will change the default watermark level setting |
| 1073 | * to something insane. Change it back here. |
| 1074 | */ |
Dong Aisheng | 69ed60e | 2013-10-18 19:48:49 +0800 | [diff] [blame] | 1075 | if (esdhc_is_usdhc(imx_data)) { |
Shawn Guo | 60bf639 | 2013-01-15 23:36:53 +0800 | [diff] [blame] | 1076 | writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL); |
Dong Aisheng | 69ed60e | 2013-10-18 19:48:49 +0800 | [diff] [blame] | 1077 | host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; |
Dong Aisheng | e2997c9 | 2013-10-30 22:09:52 +0800 | [diff] [blame] | 1078 | host->mmc->caps |= MMC_CAP_1_8V_DDR; |
Dong Aisheng | 1809443 | 2015-05-27 18:13:28 +0800 | [diff] [blame] | 1079 | |
Dong Aisheng | 4245aff | 2015-05-27 18:13:31 +0800 | [diff] [blame] | 1080 | if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) |
| 1081 | host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; |
| 1082 | |
Dong Aisheng | 1809443 | 2015-05-27 18:13:28 +0800 | [diff] [blame] | 1083 | /* |
| 1084 | * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL |
| 1085 | * TO1.1, it's harmless for MX6SL |
| 1086 | */ |
| 1087 | writel(readl(host->ioaddr + 0x6c) | BIT(7), |
| 1088 | host->ioaddr + 0x6c); |
Dong Aisheng | 69ed60e | 2013-10-18 19:48:49 +0800 | [diff] [blame] | 1089 | } |
Shawn Guo | f750ba9 | 2011-11-10 16:39:32 +0800 | [diff] [blame] | 1090 | |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 1091 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) |
| 1092 | sdhci_esdhc_ops.platform_execute_tuning = |
| 1093 | esdhc_executing_tuning; |
Dong Aisheng | 8b2bb0ad | 2013-11-04 16:38:27 +0800 | [diff] [blame] | 1094 | |
| 1095 | if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) |
| 1096 | writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) | |
| 1097 | ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP, |
| 1098 | host->ioaddr + ESDHC_TUNING_CTRL); |
| 1099 | |
Dong Aisheng | 1809443 | 2015-05-27 18:13:28 +0800 | [diff] [blame] | 1100 | if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) |
| 1101 | host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; |
| 1102 | |
Dong Aisheng | 91fa425 | 2015-07-22 20:53:06 +0800 | [diff] [blame] | 1103 | if (of_id) |
| 1104 | err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); |
| 1105 | else |
| 1106 | err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data); |
| 1107 | if (err) |
| 1108 | goto disable_clk; |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 1109 | |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1110 | err = sdhci_add_host(host); |
| 1111 | if (err) |
Shawn Guo | e3af31c | 2012-11-26 14:39:43 +0800 | [diff] [blame] | 1112 | goto disable_clk; |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1113 | |
Dong Aisheng | 89d7e5c | 2013-11-04 16:38:29 +0800 | [diff] [blame] | 1114 | pm_runtime_set_active(&pdev->dev); |
Dong Aisheng | 89d7e5c | 2013-11-04 16:38:29 +0800 | [diff] [blame] | 1115 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
| 1116 | pm_runtime_use_autosuspend(&pdev->dev); |
| 1117 | pm_suspend_ignore_children(&pdev->dev, 1); |
Ulf Hansson | 77903c0 | 2014-12-11 15:12:25 +0100 | [diff] [blame] | 1118 | pm_runtime_enable(&pdev->dev); |
Dong Aisheng | 89d7e5c | 2013-11-04 16:38:29 +0800 | [diff] [blame] | 1119 | |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 1120 | return 0; |
Wolfram Sang | 7e29c30 | 2011-02-26 14:44:41 +0100 | [diff] [blame] | 1121 | |
Shawn Guo | e3af31c | 2012-11-26 14:39:43 +0800 | [diff] [blame] | 1122 | disable_clk: |
Sascha Hauer | 52dac61 | 2012-03-07 09:31:34 +0100 | [diff] [blame] | 1123 | clk_disable_unprepare(imx_data->clk_per); |
| 1124 | clk_disable_unprepare(imx_data->clk_ipg); |
| 1125 | clk_disable_unprepare(imx_data->clk_ahb); |
Shawn Guo | e3af31c | 2012-11-26 14:39:43 +0800 | [diff] [blame] | 1126 | free_sdhci: |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1127 | sdhci_pltfm_free(pdev); |
| 1128 | return err; |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 1129 | } |
| 1130 | |
Bill Pemberton | 6e0ee71 | 2012-11-19 13:26:03 -0500 | [diff] [blame] | 1131 | static int sdhci_esdhc_imx_remove(struct platform_device *pdev) |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 1132 | { |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1133 | struct sdhci_host *host = platform_get_drvdata(pdev); |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 1134 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
Richard Zhu | e149860 | 2011-03-25 09:18:27 -0400 | [diff] [blame] | 1135 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1136 | int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); |
| 1137 | |
Ulf Hansson | 0b41436 | 2014-12-11 14:56:15 +0100 | [diff] [blame] | 1138 | pm_runtime_get_sync(&pdev->dev); |
| 1139 | pm_runtime_disable(&pdev->dev); |
| 1140 | pm_runtime_put_noidle(&pdev->dev); |
| 1141 | |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1142 | sdhci_remove_host(host, dead); |
Wolfram Sang | 0c6d49c | 2011-02-26 14:44:39 +0100 | [diff] [blame] | 1143 | |
Ulf Hansson | 0b41436 | 2014-12-11 14:56:15 +0100 | [diff] [blame] | 1144 | clk_disable_unprepare(imx_data->clk_per); |
| 1145 | clk_disable_unprepare(imx_data->clk_ipg); |
| 1146 | clk_disable_unprepare(imx_data->clk_ahb); |
Sascha Hauer | 52dac61 | 2012-03-07 09:31:34 +0100 | [diff] [blame] | 1147 | |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1148 | sdhci_pltfm_free(pdev); |
| 1149 | |
| 1150 | return 0; |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 1151 | } |
| 1152 | |
Rafael J. Wysocki | 162d6f9 | 2014-12-05 03:05:33 +0100 | [diff] [blame] | 1153 | #ifdef CONFIG_PM |
Dong Aisheng | 89d7e5c | 2013-11-04 16:38:29 +0800 | [diff] [blame] | 1154 | static int sdhci_esdhc_runtime_suspend(struct device *dev) |
| 1155 | { |
| 1156 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 1157 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 1158 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
| 1159 | int ret; |
| 1160 | |
| 1161 | ret = sdhci_runtime_suspend_host(host); |
| 1162 | |
Russell King | be13855 | 2014-04-25 12:55:56 +0100 | [diff] [blame] | 1163 | if (!sdhci_sdio_irq_enabled(host)) { |
| 1164 | clk_disable_unprepare(imx_data->clk_per); |
| 1165 | clk_disable_unprepare(imx_data->clk_ipg); |
| 1166 | } |
Dong Aisheng | 89d7e5c | 2013-11-04 16:38:29 +0800 | [diff] [blame] | 1167 | clk_disable_unprepare(imx_data->clk_ahb); |
| 1168 | |
| 1169 | return ret; |
| 1170 | } |
| 1171 | |
| 1172 | static int sdhci_esdhc_runtime_resume(struct device *dev) |
| 1173 | { |
| 1174 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 1175 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 1176 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
| 1177 | |
Russell King | be13855 | 2014-04-25 12:55:56 +0100 | [diff] [blame] | 1178 | if (!sdhci_sdio_irq_enabled(host)) { |
| 1179 | clk_prepare_enable(imx_data->clk_per); |
| 1180 | clk_prepare_enable(imx_data->clk_ipg); |
| 1181 | } |
Dong Aisheng | 89d7e5c | 2013-11-04 16:38:29 +0800 | [diff] [blame] | 1182 | clk_prepare_enable(imx_data->clk_ahb); |
| 1183 | |
| 1184 | return sdhci_runtime_resume_host(host); |
| 1185 | } |
| 1186 | #endif |
| 1187 | |
| 1188 | static const struct dev_pm_ops sdhci_esdhc_pmops = { |
| 1189 | SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume) |
| 1190 | SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, |
| 1191 | sdhci_esdhc_runtime_resume, NULL) |
| 1192 | }; |
| 1193 | |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1194 | static struct platform_driver sdhci_esdhc_imx_driver = { |
| 1195 | .driver = { |
| 1196 | .name = "sdhci-esdhc-imx", |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 1197 | .of_match_table = imx_esdhc_dt_ids, |
Dong Aisheng | 89d7e5c | 2013-11-04 16:38:29 +0800 | [diff] [blame] | 1198 | .pm = &sdhci_esdhc_pmops, |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1199 | }, |
Shawn Guo | 57ed331 | 2011-06-30 09:24:26 +0800 | [diff] [blame] | 1200 | .id_table = imx_esdhc_devtype, |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1201 | .probe = sdhci_esdhc_imx_probe, |
Bill Pemberton | 0433c14 | 2012-11-19 13:20:26 -0500 | [diff] [blame] | 1202 | .remove = sdhci_esdhc_imx_remove, |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 1203 | }; |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1204 | |
Axel Lin | d1f81a6 | 2011-11-26 12:55:43 +0800 | [diff] [blame] | 1205 | module_platform_driver(sdhci_esdhc_imx_driver); |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1206 | |
| 1207 | MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); |
Wolfram Sang | 035ff83 | 2015-04-20 15:51:42 +0200 | [diff] [blame] | 1208 | MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1209 | MODULE_LICENSE("GPL v2"); |