blob: a28c060a839bbb95b573cbac8f32be839a454966 [file] [log] [blame]
Peter De Schrijveradd29e62011-10-12 14:53:05 +03001/dts-v1/;
2
Laxman Dewangan6bccbd52013-12-02 18:39:57 +05303#include <dt-bindings/input/input.h>
Stephen Warren1bd0bd42012-10-17 16:38:21 -06004#include "tegra20.dtsi"
Peter De Schrijveradd29e62011-10-12 14:53:05 +03005
6/ {
Bryan Wu8fef5df2012-12-20 09:41:29 +00007 model = "NVIDIA Tegra20 Ventana evaluation board";
Peter De Schrijveradd29e62011-10-12 14:53:05 +03008 compatible = "nvidia,ventana", "nvidia,tegra20";
9
Stephen Warren553c0a22013-12-09 14:43:59 -070010 aliases {
11 rtc0 = "/i2c@7000d000/tps6586x@34";
12 rtc1 = "/rtc@7000e000";
Olof Johanssonc4574aa2014-11-11 12:49:30 -080013 serial0 = &uartd;
Stephen Warren553c0a22013-12-09 14:43:59 -070014 };
15
Jon Hunterf5bbb322016-02-09 13:51:59 +000016 chosen {
17 stdout-path = "serial0:115200n8";
18 };
19
Peter De Schrijveradd29e62011-10-12 14:53:05 +030020 memory {
Stephen Warren95decf82012-05-11 16:11:38 -060021 reg = <0x00000000 0x40000000>;
Peter De Schrijveradd29e62011-10-12 14:53:05 +030022 };
23
Stephen Warren58ecb232013-11-25 17:53:16 -070024 host1x@50000000 {
Stephen Warren1771a252014-01-07 16:33:31 -070025 dc@54200000 {
26 rgb {
27 status = "okay";
28
29 nvidia,panel = <&panel>;
30 };
31 };
32
Stephen Warren58ecb232013-11-25 17:53:16 -070033 hdmi@54280000 {
Stephen Warren97d55202013-01-02 14:53:21 -070034 status = "okay";
35
36 vdd-supply = <&hdmi_vdd_reg>;
37 pll-supply = <&hdmi_pll_reg>;
38
39 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -070040 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
41 GPIO_ACTIVE_HIGH>;
Stephen Warren97d55202013-01-02 14:53:21 -070042 };
43 };
44
Stephen Warren58ecb232013-11-25 17:53:16 -070045 pinmux@70000014 {
Stephen Warrenecc295b2012-03-15 16:27:36 -060046 pinctrl-names = "default";
47 pinctrl-0 = <&state_default>;
48
49 state_default: pinmux {
50 ata {
51 nvidia,pins = "ata";
52 nvidia,function = "ide";
53 };
54 atb {
55 nvidia,pins = "atb", "gma", "gme";
56 nvidia,function = "sdio4";
57 };
58 atc {
59 nvidia,pins = "atc";
60 nvidia,function = "nand";
61 };
62 atd {
63 nvidia,pins = "atd", "ate", "gmb", "spia",
64 "spib", "spic";
65 nvidia,function = "gmi";
66 };
67 cdev1 {
68 nvidia,pins = "cdev1";
69 nvidia,function = "plla_out";
70 };
71 cdev2 {
72 nvidia,pins = "cdev2";
73 nvidia,function = "pllp_out4";
74 };
75 crtp {
76 nvidia,pins = "crtp", "lm1";
77 nvidia,function = "crt";
78 };
79 csus {
80 nvidia,pins = "csus";
81 nvidia,function = "vi_sensor_clk";
82 };
83 dap1 {
84 nvidia,pins = "dap1";
85 nvidia,function = "dap1";
86 };
87 dap2 {
88 nvidia,pins = "dap2";
89 nvidia,function = "dap2";
90 };
91 dap3 {
92 nvidia,pins = "dap3";
93 nvidia,function = "dap3";
94 };
95 dap4 {
96 nvidia,pins = "dap4";
97 nvidia,function = "dap4";
98 };
Stephen Warrenecc295b2012-03-15 16:27:36 -060099 dta {
100 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
101 nvidia,function = "vi";
102 };
103 dtf {
104 nvidia,pins = "dtf";
105 nvidia,function = "i2c3";
106 };
107 gmc {
108 nvidia,pins = "gmc";
109 nvidia,function = "uartd";
110 };
111 gmd {
112 nvidia,pins = "gmd";
113 nvidia,function = "sflash";
114 };
115 gpu {
116 nvidia,pins = "gpu";
117 nvidia,function = "pwm";
118 };
119 gpu7 {
120 nvidia,pins = "gpu7";
121 nvidia,function = "rtck";
122 };
123 gpv {
124 nvidia,pins = "gpv", "slxa", "slxk";
125 nvidia,function = "pcie";
126 };
127 hdint {
Mark Zhangcf633462012-10-25 14:52:30 +0800128 nvidia,pins = "hdint";
Stephen Warrenecc295b2012-03-15 16:27:36 -0600129 nvidia,function = "hdmi";
130 };
131 i2cp {
132 nvidia,pins = "i2cp";
133 nvidia,function = "i2cp";
134 };
135 irrx {
136 nvidia,pins = "irrx", "irtx";
137 nvidia,function = "uartb";
138 };
139 kbca {
140 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
141 "kbce", "kbcf";
142 nvidia,function = "kbc";
143 };
144 lcsn {
145 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
146 "lsdi", "lvp0";
147 nvidia,function = "rsvd4";
148 };
149 ld0 {
150 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
151 "ld5", "ld6", "ld7", "ld8", "ld9",
152 "ld10", "ld11", "ld12", "ld13", "ld14",
153 "ld15", "ld16", "ld17", "ldi", "lhp0",
154 "lhp1", "lhp2", "lhs", "lpp", "lpw0",
155 "lpw2", "lsc0", "lsc1", "lsck", "lsda",
156 "lspi", "lvp1", "lvs";
157 nvidia,function = "displaya";
158 };
Mark Zhangcf633462012-10-25 14:52:30 +0800159 owc {
160 nvidia,pins = "owc", "spdi", "spdo", "uac";
161 nvidia,function = "rsvd2";
162 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600163 pmc {
164 nvidia,pins = "pmc";
165 nvidia,function = "pwr_on";
166 };
167 rm {
168 nvidia,pins = "rm";
169 nvidia,function = "i2c1";
170 };
171 sdb {
172 nvidia,pins = "sdb", "sdc", "sdd", "slxc";
173 nvidia,function = "sdio3";
174 };
175 sdio1 {
176 nvidia,pins = "sdio1";
177 nvidia,function = "sdio1";
178 };
179 slxd {
180 nvidia,pins = "slxd";
181 nvidia,function = "spdif";
182 };
183 spid {
184 nvidia,pins = "spid", "spie", "spif";
185 nvidia,function = "spi1";
186 };
187 spig {
188 nvidia,pins = "spig", "spih";
189 nvidia,function = "spi2_alt";
190 };
191 uaa {
192 nvidia,pins = "uaa", "uab", "uda";
193 nvidia,function = "ulpi";
194 };
195 uad {
196 nvidia,pins = "uad";
197 nvidia,function = "irda";
198 };
199 uca {
200 nvidia,pins = "uca", "ucb";
201 nvidia,function = "uartc";
202 };
203 conf_ata {
204 nvidia,pins = "ata", "atb", "atc", "atd",
205 "cdev1", "cdev2", "dap1", "dap2",
206 "dap4", "ddc", "dtf", "gma", "gmc",
207 "gme", "gpu", "gpu7", "i2cp", "irrx",
208 "irtx", "pta", "rm", "sdc", "sdd",
209 "slxc", "slxd", "slxk", "spdi", "spdo",
210 "uac", "uad", "uca", "ucb", "uda";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530211 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
212 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600213 };
214 conf_ate {
215 nvidia,pins = "ate", "csus", "dap3", "gmd",
216 "gpv", "owc", "spia", "spib", "spic",
217 "spid", "spie", "spig";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530218 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
219 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600220 };
221 conf_ck32 {
222 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
223 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530224 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600225 };
226 conf_crtp {
227 nvidia,pins = "crtp", "gmb", "slxa", "spih";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530228 nvidia,pull = <TEGRA_PIN_PULL_UP>;
229 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600230 };
231 conf_dta {
232 nvidia,pins = "dta", "dtb", "dtc", "dtd";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530233 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
234 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600235 };
236 conf_dte {
237 nvidia,pins = "dte", "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530238 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
239 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600240 };
241 conf_hdint {
242 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
243 "lpw1", "lsck", "lsda", "lsdi", "lvp0";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530244 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600245 };
246 conf_kbca {
247 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
248 "kbce", "kbcf", "sdio1", "uaa", "uab";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530249 nvidia,pull = <TEGRA_PIN_PULL_UP>;
250 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600251 };
252 conf_lc {
253 nvidia,pins = "lc", "ls";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530254 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600255 };
256 conf_ld0 {
257 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
258 "ld5", "ld6", "ld7", "ld8", "ld9",
259 "ld10", "ld11", "ld12", "ld13", "ld14",
260 "ld15", "ld16", "ld17", "ldi", "lhp0",
261 "lhp1", "lhp2", "lhs", "lm0", "lpp",
262 "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
263 "lvp1", "lvs", "pmc", "sdb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530264 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600265 };
266 conf_ld17_0 {
267 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
268 "ld23_22";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530269 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600270 };
Wei Nic7294292012-09-21 16:54:58 +0800271 drive_sdio1 {
272 nvidia,pins = "drive_sdio1";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530273 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
274 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
275 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
Wei Nic7294292012-09-21 16:54:58 +0800276 nvidia,pull-down-strength = <31>;
277 nvidia,pull-up-strength = <31>;
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530278 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
279 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
Wei Nic7294292012-09-21 16:54:58 +0800280 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600281 };
Mark Zhangcf633462012-10-25 14:52:30 +0800282
283 state_i2cmux_ddc: pinmux_i2cmux_ddc {
284 ddc {
285 nvidia,pins = "ddc";
286 nvidia,function = "i2c2";
287 };
288 pta {
289 nvidia,pins = "pta";
290 nvidia,function = "rsvd4";
291 };
292 };
293
294 state_i2cmux_pta: pinmux_i2cmux_pta {
295 ddc {
296 nvidia,pins = "ddc";
297 nvidia,function = "rsvd4";
298 };
299 pta {
300 nvidia,pins = "pta";
301 nvidia,function = "i2c2";
302 };
303 };
304
305 state_i2cmux_idle: pinmux_i2cmux_idle {
306 ddc {
307 nvidia,pins = "ddc";
308 nvidia,function = "rsvd4";
309 };
310 pta {
311 nvidia,pins = "pta";
312 nvidia,function = "rsvd4";
313 };
314 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600315 };
316
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600317 i2s@70002800 {
318 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600319 };
320
321 serial@70006300 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600322 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600323 };
324
Stephen Warren1771a252014-01-07 16:33:31 -0700325 pwm: pwm@7000a000 {
326 status = "okay";
327 };
328
Stephen Warren88950f3b2011-11-21 14:44:09 -0700329 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600330 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700331 clock-frequency = <400000>;
Stephen Warren797acf72012-01-11 16:09:57 -0700332
333 wm8903: wm8903@1a {
334 compatible = "wlf,wm8903";
335 reg = <0x1a>;
336 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700337 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren797acf72012-01-11 16:09:57 -0700338
339 gpio-controller;
340 #gpio-cells = <2>;
341
342 micdet-cfg = <0>;
343 micdet-delay = <100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600344 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
Stephen Warren797acf72012-01-11 16:09:57 -0700345 };
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530346
347 /* ALS and proximity sensor */
348 isl29018@44 {
349 compatible = "isil,isl29018";
350 reg = <0x44>;
351 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700352 interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530353 };
Stephen Warren88950f3b2011-11-21 14:44:09 -0700354 };
355
356 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600357 status = "okay";
Stephen Warren97d55202013-01-02 14:53:21 -0700358 clock-frequency = <100000>;
Stephen Warren88950f3b2011-11-21 14:44:09 -0700359 };
360
Mark Zhangcf633462012-10-25 14:52:30 +0800361 i2cmux {
362 compatible = "i2c-mux-pinctrl";
363 #address-cells = <1>;
364 #size-cells = <0>;
365
366 i2c-parent = <&{/i2c@7000c400}>;
367
368 pinctrl-names = "ddc", "pta", "idle";
369 pinctrl-0 = <&state_i2cmux_ddc>;
370 pinctrl-1 = <&state_i2cmux_pta>;
371 pinctrl-2 = <&state_i2cmux_idle>;
372
Stephen Warren97d55202013-01-02 14:53:21 -0700373 hdmi_ddc: i2c@0 {
Mark Zhangcf633462012-10-25 14:52:30 +0800374 reg = <0>;
375 #address-cells = <1>;
376 #size-cells = <0>;
377 };
378
Stephen Warren1771a252014-01-07 16:33:31 -0700379 lvds_ddc: i2c@1 {
Mark Zhangcf633462012-10-25 14:52:30 +0800380 reg = <1>;
381 #address-cells = <1>;
382 #size-cells = <0>;
383 };
384 };
385
Stephen Warren88950f3b2011-11-21 14:44:09 -0700386 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600387 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700388 clock-frequency = <400000>;
389 };
390
391 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600392 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700393 clock-frequency = <400000>;
Stephen Warren017a0102012-06-20 16:53:41 -0600394
395 pmic: tps6586x@34 {
396 compatible = "ti,tps6586x";
397 reg = <0x34>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700398 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren017a0102012-06-20 16:53:41 -0600399
Stephen Warren44b12ef2012-09-11 11:42:26 -0600400 ti,system-power-controller;
401
Stephen Warren017a0102012-06-20 16:53:41 -0600402 #gpio-cells = <2>;
403 gpio-controller;
404
405 sys-supply = <&vdd_5v0_reg>;
406 vin-sm0-supply = <&sys_reg>;
407 vin-sm1-supply = <&sys_reg>;
408 vin-sm2-supply = <&sys_reg>;
409 vinldo01-supply = <&sm2_reg>;
410 vinldo23-supply = <&sm2_reg>;
411 vinldo4-supply = <&sm2_reg>;
412 vinldo678-supply = <&sm2_reg>;
413 vinldo9-supply = <&sm2_reg>;
414
415 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600416 sys_reg: sys {
Stephen Warren017a0102012-06-20 16:53:41 -0600417 regulator-name = "vdd_sys";
418 regulator-always-on;
419 };
420
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600421 sm0 {
Stephen Warren017a0102012-06-20 16:53:41 -0600422 regulator-name = "vdd_sm0,vdd_core";
423 regulator-min-microvolt = <1200000>;
424 regulator-max-microvolt = <1200000>;
425 regulator-always-on;
426 };
427
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600428 sm1 {
Stephen Warren017a0102012-06-20 16:53:41 -0600429 regulator-name = "vdd_sm1,vdd_cpu";
430 regulator-min-microvolt = <1000000>;
431 regulator-max-microvolt = <1000000>;
432 regulator-always-on;
433 };
434
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600435 sm2_reg: sm2 {
Stephen Warren017a0102012-06-20 16:53:41 -0600436 regulator-name = "vdd_sm2,vin_ldo*";
437 regulator-min-microvolt = <3700000>;
438 regulator-max-microvolt = <3700000>;
439 regulator-always-on;
440 };
441
442 /* LDO0 is not connected to anything */
443
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600444 ldo1 {
Stephen Warren017a0102012-06-20 16:53:41 -0600445 regulator-name = "vdd_ldo1,avdd_pll*";
446 regulator-min-microvolt = <1100000>;
447 regulator-max-microvolt = <1100000>;
448 regulator-always-on;
449 };
450
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600451 ldo2 {
Stephen Warren017a0102012-06-20 16:53:41 -0600452 regulator-name = "vdd_ldo2,vdd_rtc";
453 regulator-min-microvolt = <1200000>;
454 regulator-max-microvolt = <1200000>;
455 };
456
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600457 ldo3 {
Stephen Warren017a0102012-06-20 16:53:41 -0600458 regulator-name = "vdd_ldo3,avdd_usb*";
459 regulator-min-microvolt = <3300000>;
460 regulator-max-microvolt = <3300000>;
461 regulator-always-on;
462 };
463
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600464 ldo4 {
Stephen Warren017a0102012-06-20 16:53:41 -0600465 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
466 regulator-min-microvolt = <1800000>;
467 regulator-max-microvolt = <1800000>;
468 regulator-always-on;
469 };
470
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600471 ldo5 {
Stephen Warren017a0102012-06-20 16:53:41 -0600472 regulator-name = "vdd_ldo5,vcore_mmc";
473 regulator-min-microvolt = <2850000>;
474 regulator-max-microvolt = <2850000>;
475 regulator-always-on;
476 };
477
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600478 ldo6 {
Stephen Warren017a0102012-06-20 16:53:41 -0600479 regulator-name = "vdd_ldo6,avdd_vdac";
480 regulator-min-microvolt = <1800000>;
481 regulator-max-microvolt = <1800000>;
482 };
483
Stephen Warren97d55202013-01-02 14:53:21 -0700484 hdmi_vdd_reg: ldo7 {
Stephen Warren017a0102012-06-20 16:53:41 -0600485 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
486 regulator-min-microvolt = <3300000>;
487 regulator-max-microvolt = <3300000>;
488 };
489
Stephen Warren97d55202013-01-02 14:53:21 -0700490 hdmi_pll_reg: ldo8 {
Stephen Warren017a0102012-06-20 16:53:41 -0600491 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
492 regulator-min-microvolt = <1800000>;
493 regulator-max-microvolt = <1800000>;
494 };
495
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600496 ldo9 {
Stephen Warren017a0102012-06-20 16:53:41 -0600497 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
498 regulator-min-microvolt = <2850000>;
499 regulator-max-microvolt = <2850000>;
500 regulator-always-on;
501 };
502
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600503 ldo_rtc {
Stephen Warren017a0102012-06-20 16:53:41 -0600504 regulator-name = "vdd_rtc_out,vdd_cell";
505 regulator-min-microvolt = <3300000>;
506 regulator-max-microvolt = <3300000>;
507 regulator-always-on;
508 };
509 };
510 };
Thierry Redingee9f7262012-11-09 23:01:21 +0100511
512 temperature-sensor@4c {
513 compatible = "onnn,nct1008";
514 reg = <0x4c>;
515 };
Stephen Warren017a0102012-06-20 16:53:41 -0600516 };
517
Stephen Warren58ecb232013-11-25 17:53:16 -0700518 pmc@7000e400 {
Stephen Warren017a0102012-06-20 16:53:41 -0600519 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800520 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800521 nvidia,cpu-pwr-good-time = <2000>;
522 nvidia,cpu-pwr-off-time = <100>;
523 nvidia,core-pwr-good-time = <3845 3845>;
524 nvidia,core-pwr-off-time = <458>;
525 nvidia,sys-clock-req-active-high;
Stephen Warren88950f3b2011-11-21 14:44:09 -0700526 };
527
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600528 usb@c5000000 {
529 status = "okay";
530 };
531
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530532 usb-phy@c5000000 {
533 status = "okay";
534 };
535
Stephen Warrenc04abb32012-05-11 17:03:26 -0600536 usb@c5004000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600537 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700538 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
539 GPIO_ACTIVE_LOW>;
Venu Byravarasu9dffe3b2013-05-16 19:42:56 +0530540 };
541
542 usb-phy@c5004000 {
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530543 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700544 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
545 GPIO_ACTIVE_LOW>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600546 };
547
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600548 usb@c5008000 {
549 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600550 };
551
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530552 usb-phy@c5008000 {
553 status = "okay";
554 };
555
Wei Nic7294292012-09-21 16:54:58 +0800556 sdhci@c8000000 {
557 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700558 power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
Wei Nic7294292012-09-21 16:54:58 +0800559 bus-width = <4>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600560 keep-power-in-suspend;
Wei Nic7294292012-09-21 16:54:58 +0800561 };
562
Stephen Warrenc04abb32012-05-11 17:03:26 -0600563 sdhci@c8000400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600564 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700565 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
566 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
567 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200568 bus-width = <4>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600569 };
570
571 sdhci@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600572 status = "okay";
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200573 bus-width = <8>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600574 non-removable;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600575 };
576
Stephen Warren1771a252014-01-07 16:33:31 -0700577 backlight: backlight {
578 compatible = "pwm-backlight";
579
580 enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
581 power-supply = <&vdd_bl_reg>;
582 pwms = <&pwm 2 5000000>;
583
584 brightness-levels = <0 4 8 16 32 64 128 255>;
585 default-brightness-level = <6>;
586 };
587
Joseph Lo7021d122013-04-03 19:31:27 +0800588 clocks {
589 compatible = "simple-bus";
590 #address-cells = <1>;
591 #size-cells = <0>;
592
Stephen Warren58ecb232013-11-25 17:53:16 -0700593 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800594 compatible = "fixed-clock";
595 reg=<0>;
596 #clock-cells = <0>;
597 clock-frequency = <32768>;
598 };
599 };
600
Joseph Lo5741a252013-04-03 19:31:48 +0800601 gpio-keys {
602 compatible = "gpio-keys";
603
604 power {
605 label = "Power";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700606 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530607 linux,code = <KEY_POWER>;
Sudeep Hollad1c04d32016-02-08 21:55:43 +0000608 wakeup-source;
Joseph Lo5741a252013-04-03 19:31:48 +0800609 };
610 };
611
Stephen Warren1771a252014-01-07 16:33:31 -0700612 panel: panel {
613 compatible = "chunghwa,claa101wa01a", "simple-panel";
614
615 power-supply = <&vdd_pnl_reg>;
616 enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
617
618 backlight = <&backlight>;
619 ddc-i2c-bus = <&lvds_ddc>;
620 };
621
Stephen Warren017a0102012-06-20 16:53:41 -0600622 regulators {
623 compatible = "simple-bus";
624 #address-cells = <1>;
625 #size-cells = <0>;
626
627 vdd_5v0_reg: regulator@0 {
628 compatible = "regulator-fixed";
629 reg = <0>;
630 regulator-name = "vdd_5v0";
631 regulator-min-microvolt = <5000000>;
632 regulator-max-microvolt = <5000000>;
633 regulator-always-on;
634 };
635
636 regulator@1 {
637 compatible = "regulator-fixed";
638 reg = <1>;
639 regulator-name = "vdd_1v5";
640 regulator-min-microvolt = <1500000>;
641 regulator-max-microvolt = <1500000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700642 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
Stephen Warren017a0102012-06-20 16:53:41 -0600643 };
644
645 regulator@2 {
646 compatible = "regulator-fixed";
647 reg = <2>;
648 regulator-name = "vdd_1v2";
649 regulator-min-microvolt = <1200000>;
650 regulator-max-microvolt = <1200000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700651 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
Stephen Warren017a0102012-06-20 16:53:41 -0600652 enable-active-high;
653 };
654
Stephen Warren1771a252014-01-07 16:33:31 -0700655 vdd_pnl_reg: regulator@3 {
Stephen Warren017a0102012-06-20 16:53:41 -0600656 compatible = "regulator-fixed";
657 reg = <3>;
658 regulator-name = "vdd_pnl";
659 regulator-min-microvolt = <2800000>;
660 regulator-max-microvolt = <2800000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700661 gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
Stephen Warren017a0102012-06-20 16:53:41 -0600662 enable-active-high;
663 };
664
Stephen Warren1771a252014-01-07 16:33:31 -0700665 vdd_bl_reg: regulator@4 {
Stephen Warren017a0102012-06-20 16:53:41 -0600666 compatible = "regulator-fixed";
667 reg = <4>;
668 regulator-name = "vdd_bl";
669 regulator-min-microvolt = <2800000>;
670 regulator-max-microvolt = <2800000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700671 gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
Stephen Warren017a0102012-06-20 16:53:41 -0600672 enable-active-high;
673 };
674 };
675
Stephen Warren797acf72012-01-11 16:09:57 -0700676 sound {
677 compatible = "nvidia,tegra-audio-wm8903-ventana",
678 "nvidia,tegra-audio-wm8903";
679 nvidia,model = "NVIDIA Tegra Ventana";
680
681 nvidia,audio-routing =
682 "Headphone Jack", "HPOUTR",
683 "Headphone Jack", "HPOUTL",
684 "Int Spk", "ROP",
685 "Int Spk", "RON",
686 "Int Spk", "LOP",
687 "Int Spk", "LON",
688 "Mic Jack", "MICBIAS",
689 "IN1L", "Mic Jack";
690
691 nvidia,i2s-controller = <&tegra_i2s1>;
692 nvidia,audio-codec = <&wm8903>;
693
Stephen Warren3325f1b2013-02-12 17:25:15 -0700694 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
695 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
696 nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
697 GPIO_ACTIVE_HIGH>;
698 nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
699 GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600700
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300701 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
702 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
703 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600704 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warren797acf72012-01-11 16:09:57 -0700705 };
Peter De Schrijveradd29e62011-10-12 14:53:05 +0300706};