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Shawn Guo082d33d2013-04-02 13:15:16 +08001/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Anson Huang22724cf12014-01-20 20:02:38 +080013#include <dt-bindings/gpio/gpio.h>
Anson Huang8e4422a2013-12-19 16:07:24 -050014#include <dt-bindings/input/input.h>
15
Shawn Guo082d33d2013-04-02 13:15:16 +080016/ {
Sascha Hauer48f51962014-05-07 15:19:00 +020017 chosen {
18 stdout-path = &uart1;
19 };
20
Shawn Guo082d33d2013-04-02 13:15:16 +080021 memory {
22 reg = <0x10000000 0x40000000>;
23 };
24
25 regulators {
26 compatible = "simple-bus";
Shawn Guo56160e32014-02-07 23:22:50 +080027 #address-cells = <1>;
28 #size-cells = <0>;
Shawn Guo082d33d2013-04-02 13:15:16 +080029
Shawn Guo56160e32014-02-07 23:22:50 +080030 reg_usb_otg_vbus: regulator@0 {
Shawn Guo082d33d2013-04-02 13:15:16 +080031 compatible = "regulator-fixed";
Shawn Guo56160e32014-02-07 23:22:50 +080032 reg = <0>;
Shawn Guo082d33d2013-04-02 13:15:16 +080033 regulator-name = "usb_otg_vbus";
34 regulator-min-microvolt = <5000000>;
35 regulator-max-microvolt = <5000000>;
36 gpio = <&gpio3 22 0>;
37 enable-active-high;
Peter Chen40f73772015-03-06 16:04:20 +080038 vin-supply = <&swbst_reg>;
Shawn Guo082d33d2013-04-02 13:15:16 +080039 };
Nicolin Chenfdbfb432013-06-13 19:51:00 +080040
Shawn Guo56160e32014-02-07 23:22:50 +080041 reg_usb_h1_vbus: regulator@1 {
Peter Chen015fa462013-08-12 16:46:24 +080042 compatible = "regulator-fixed";
Shawn Guo56160e32014-02-07 23:22:50 +080043 reg = <1>;
Peter Chen015fa462013-08-12 16:46:24 +080044 regulator-name = "usb_h1_vbus";
45 regulator-min-microvolt = <5000000>;
46 regulator-max-microvolt = <5000000>;
47 gpio = <&gpio1 29 0>;
48 enable-active-high;
Peter Chen40f73772015-03-06 16:04:20 +080049 vin-supply = <&swbst_reg>;
Peter Chen015fa462013-08-12 16:46:24 +080050 };
51
Shawn Guo56160e32014-02-07 23:22:50 +080052 reg_audio: regulator@2 {
Nicolin Chenfdbfb432013-06-13 19:51:00 +080053 compatible = "regulator-fixed";
Shawn Guo56160e32014-02-07 23:22:50 +080054 reg = <2>;
Nicolin Chenfdbfb432013-06-13 19:51:00 +080055 regulator-name = "wm8962-supply";
56 gpio = <&gpio4 10 0>;
57 enable-active-high;
58 };
Lucas Stach78827ec2014-07-23 19:29:11 +020059
60 reg_pcie: regulator@3 {
61 compatible = "regulator-fixed";
62 reg = <3>;
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_pcie_reg>;
65 regulator-name = "MPCIE_3V3";
66 regulator-min-microvolt = <3300000>;
67 regulator-max-microvolt = <3300000>;
68 gpio = <&gpio3 19 0>;
69 regulator-always-on;
70 enable-active-high;
71 };
Shawn Guo082d33d2013-04-02 13:15:16 +080072 };
73
74 gpio-keys {
75 compatible = "gpio-keys";
Anson Huang8e4422a2013-12-19 16:07:24 -050076 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_gpio_keys>;
78
79 power {
80 label = "Power Button";
Anson Huang22724cf12014-01-20 20:02:38 +080081 gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
Sudeep Holla26cefdd2015-10-21 11:10:08 +010082 wakeup-source;
Anson Huang8e4422a2013-12-19 16:07:24 -050083 linux,code = <KEY_POWER>;
84 };
Shawn Guo082d33d2013-04-02 13:15:16 +080085
86 volume-up {
87 label = "Volume Up";
Anson Huang22724cf12014-01-20 20:02:38 +080088 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
Sudeep Holla26cefdd2015-10-21 11:10:08 +010089 wakeup-source;
Anson Huang8e4422a2013-12-19 16:07:24 -050090 linux,code = <KEY_VOLUMEUP>;
Shawn Guo082d33d2013-04-02 13:15:16 +080091 };
92
93 volume-down {
94 label = "Volume Down";
Anson Huang22724cf12014-01-20 20:02:38 +080095 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
Sudeep Holla26cefdd2015-10-21 11:10:08 +010096 wakeup-source;
Anson Huang8e4422a2013-12-19 16:07:24 -050097 linux,code = <KEY_VOLUMEDOWN>;
Shawn Guo082d33d2013-04-02 13:15:16 +080098 };
99 };
Nicolin Chen77b38fc2013-06-14 13:22:46 +0800100
101 sound {
102 compatible = "fsl,imx6q-sabresd-wm8962",
103 "fsl,imx-audio-wm8962";
104 model = "wm8962-audio";
105 ssi-controller = <&ssi2>;
106 audio-codec = <&codec>;
107 audio-routing =
108 "Headphone Jack", "HPOUTL",
109 "Headphone Jack", "HPOUTR",
110 "Ext Spk", "SPKOUTL",
111 "Ext Spk", "SPKOUTR",
Fabio Estevam76e68682014-11-07 12:08:01 -0200112 "AMIC", "MICBIAS",
113 "IN3R", "AMIC";
Nicolin Chen77b38fc2013-06-14 13:22:46 +0800114 mux-int-port = <2>;
115 mux-ext-port = <3>;
116 };
Rogerio Pimentel2f35c0c2013-10-11 16:48:16 -0300117
Fabio Estevame0884942016-03-28 14:10:48 -0300118 backlight_lvds: backlight-lvds {
Rogerio Pimentel2f35c0c2013-10-11 16:48:16 -0300119 compatible = "pwm-backlight";
120 pwms = <&pwm1 0 5000000>;
121 brightness-levels = <0 4 8 16 32 64 128 255>;
122 default-brightness-level = <7>;
123 status = "okay";
124 };
Vincent Stehlé702bfbe2014-03-05 19:58:39 +0100125
126 leds {
127 compatible = "gpio-leds";
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_gpio_leds>;
130
131 red {
Jagan Tekibf5393c2016-10-14 15:09:29 +0530132 gpios = <&gpio1 2 0>;
133 default-state = "on";
Vincent Stehlé702bfbe2014-03-05 19:58:39 +0100134 };
135 };
Fabio Estevame0884942016-03-28 14:10:48 -0300136
137 panel {
138 compatible = "hannstar,hsd100pxn1";
139 backlight = <&backlight_lvds>;
140
141 port {
142 panel_in: endpoint {
143 remote-endpoint = <&lvds0_out>;
144 };
145 };
146 };
Shawn Guo082d33d2013-04-02 13:15:16 +0800147};
148
Nicolin Chen48828702013-06-14 13:19:57 +0800149&audmux {
150 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800151 pinctrl-0 = <&pinctrl_audmux>;
Nicolin Chen48828702013-06-14 13:19:57 +0800152 status = "okay";
153};
154
Fabio Estevamd28be492015-06-26 14:10:53 -0300155&clks {
156 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
157 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
158 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
159 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
160};
161
Huang Shijie9110ede2013-06-21 10:19:11 +0800162&ecspi1 {
Huang Shijie9110ede2013-06-21 10:19:11 +0800163 cs-gpios = <&gpio4 9 0>;
164 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800165 pinctrl-0 = <&pinctrl_ecspi1>;
Huang Shijie9110ede2013-06-21 10:19:11 +0800166 status = "okay";
167
168 flash: m25p80@0 {
169 #address-cells = <1>;
170 #size-cells = <1>;
Rafał Miłecki79826ac2015-08-16 08:39:17 +0200171 compatible = "st,m25p32", "jedec,spi-nor";
Huang Shijie9110ede2013-06-21 10:19:11 +0800172 spi-max-frequency = <20000000>;
173 reg = <0>;
174 };
175};
176
Shawn Guo082d33d2013-04-02 13:15:16 +0800177&fec {
178 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800179 pinctrl-0 = <&pinctrl_enet>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800180 phy-mode = "rgmii";
Fabio Estevamc5f592d2013-09-27 11:12:41 -0300181 phy-reset-gpios = <&gpio1 25 0>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800182 status = "okay";
183};
184
Fabio Estevamad704562014-04-22 10:04:59 -0300185&hdmi {
186 ddc-i2c-bus = <&i2c2>;
187 status = "okay";
188};
189
Nicolin Chen20426fe2013-06-13 19:51:01 +0800190&i2c1 {
191 clock-frequency = <100000>;
192 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800193 pinctrl-0 = <&pinctrl_i2c1>;
Nicolin Chen20426fe2013-06-13 19:51:01 +0800194 status = "okay";
195
196 codec: wm8962@1a {
197 compatible = "wlf,wm8962";
198 reg = <0x1a>;
Fabio Estevamf029ce32014-10-20 11:02:13 -0200199 clocks = <&clks IMX6QDL_CLK_CKO>;
Nicolin Chen20426fe2013-06-13 19:51:01 +0800200 DCVDD-supply = <&reg_audio>;
201 DBVDD-supply = <&reg_audio>;
202 AVDD-supply = <&reg_audio>;
203 CPVDD-supply = <&reg_audio>;
204 MICVDD-supply = <&reg_audio>;
205 PLLVDD-supply = <&reg_audio>;
206 SPKVDD1-supply = <&reg_audio>;
207 SPKVDD2-supply = <&reg_audio>;
208 gpio-cfg = <
209 0x0000 /* 0:Default */
210 0x0000 /* 1:Default */
211 0x0013 /* 2:FN_DMICCLK */
212 0x0000 /* 3:Default */
213 0x8014 /* 4:FN_DMICCDAT */
214 0x0000 /* 5:Default */
215 >;
216 };
217};
218
Fabio Estevam4b444bb2013-12-24 01:04:49 -0200219&i2c2 {
220 clock-frequency = <100000>;
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_i2c2>;
223 status = "okay";
224
225 pmic: pfuze100@08 {
226 compatible = "fsl,pfuze100";
227 reg = <0x08>;
228
229 regulators {
230 sw1a_reg: sw1ab {
231 regulator-min-microvolt = <300000>;
232 regulator-max-microvolt = <1875000>;
233 regulator-boot-on;
234 regulator-always-on;
235 regulator-ramp-delay = <6250>;
236 };
237
238 sw1c_reg: sw1c {
239 regulator-min-microvolt = <300000>;
240 regulator-max-microvolt = <1875000>;
241 regulator-boot-on;
242 regulator-always-on;
243 regulator-ramp-delay = <6250>;
244 };
245
246 sw2_reg: sw2 {
247 regulator-min-microvolt = <800000>;
248 regulator-max-microvolt = <3300000>;
249 regulator-boot-on;
250 regulator-always-on;
Bai Ping5d625372016-02-02 18:01:35 +0800251 regulator-ramp-delay = <6250>;
Fabio Estevam4b444bb2013-12-24 01:04:49 -0200252 };
253
254 sw3a_reg: sw3a {
255 regulator-min-microvolt = <400000>;
256 regulator-max-microvolt = <1975000>;
257 regulator-boot-on;
258 regulator-always-on;
259 };
260
261 sw3b_reg: sw3b {
262 regulator-min-microvolt = <400000>;
263 regulator-max-microvolt = <1975000>;
264 regulator-boot-on;
265 regulator-always-on;
266 };
267
268 sw4_reg: sw4 {
269 regulator-min-microvolt = <800000>;
270 regulator-max-microvolt = <3300000>;
271 };
272
273 swbst_reg: swbst {
274 regulator-min-microvolt = <5000000>;
275 regulator-max-microvolt = <5150000>;
276 };
277
278 snvs_reg: vsnvs {
279 regulator-min-microvolt = <1000000>;
280 regulator-max-microvolt = <3000000>;
281 regulator-boot-on;
282 regulator-always-on;
283 };
284
285 vref_reg: vrefddr {
286 regulator-boot-on;
287 regulator-always-on;
288 };
289
290 vgen1_reg: vgen1 {
291 regulator-min-microvolt = <800000>;
292 regulator-max-microvolt = <1550000>;
293 };
294
295 vgen2_reg: vgen2 {
296 regulator-min-microvolt = <800000>;
297 regulator-max-microvolt = <1550000>;
298 };
299
300 vgen3_reg: vgen3 {
301 regulator-min-microvolt = <1800000>;
302 regulator-max-microvolt = <3300000>;
303 };
304
305 vgen4_reg: vgen4 {
306 regulator-min-microvolt = <1800000>;
307 regulator-max-microvolt = <3300000>;
308 regulator-always-on;
309 };
310
311 vgen5_reg: vgen5 {
312 regulator-min-microvolt = <1800000>;
313 regulator-max-microvolt = <3300000>;
314 regulator-always-on;
315 };
316
317 vgen6_reg: vgen6 {
318 regulator-min-microvolt = <1800000>;
319 regulator-max-microvolt = <3300000>;
320 regulator-always-on;
321 };
322 };
323 };
324};
325
Fabio Estevam38501172013-07-24 17:20:03 -0300326&i2c3 {
327 clock-frequency = <100000>;
328 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800329 pinctrl-0 = <&pinctrl_i2c3>;
Fabio Estevam38501172013-07-24 17:20:03 -0300330 status = "okay";
331
332 egalax_ts@04 {
333 compatible = "eeti,egalax_ts";
334 reg = <0x04>;
335 interrupt-parent = <&gpio6>;
336 interrupts = <7 2>;
337 wakeup-gpios = <&gpio6 7 0>;
338 };
339};
340
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800341&iomuxc {
342 pinctrl-names = "default";
343 pinctrl-0 = <&pinctrl_hog>;
344
Shawn Guo817c27a2013-10-23 15:36:09 +0800345 imx6qdl-sabresd {
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800346 pinctrl_hog: hoggrp {
347 fsl,pins = <
Fabio Estevam9a060c12014-09-05 09:46:10 -0300348 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
349 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
350 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
351 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800352 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
Fabio Estevam9a060c12014-09-05 09:46:10 -0300353 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
354 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
355 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
356 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800357 >;
358 };
Shawn Guo817c27a2013-10-23 15:36:09 +0800359
360 pinctrl_audmux: audmuxgrp {
361 fsl,pins = <
Nicolin Chen77112dd2014-02-08 10:14:28 +0800362 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
363 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
364 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
365 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
Shawn Guo817c27a2013-10-23 15:36:09 +0800366 >;
367 };
368
369 pinctrl_ecspi1: ecspi1grp {
370 fsl,pins = <
371 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
372 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
373 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
Fabio Estevamf3c72382014-05-14 16:53:55 -0300374 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
Shawn Guo817c27a2013-10-23 15:36:09 +0800375 >;
376 };
377
378 pinctrl_enet: enetgrp {
379 fsl,pins = <
380 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
381 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
Uwe Kleine-Königc007b3a2016-07-08 23:22:54 +0200382 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
383 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
384 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
385 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
386 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
387 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
Shawn Guo817c27a2013-10-23 15:36:09 +0800388 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
Uwe Kleine-Königc007b3a2016-07-08 23:22:54 +0200389 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
390 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
391 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
392 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
393 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
394 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
Shawn Guo817c27a2013-10-23 15:36:09 +0800395 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
396 >;
397 };
398
Anson Huang8e4422a2013-12-19 16:07:24 -0500399 pinctrl_gpio_keys: gpio_keysgrp {
400 fsl,pins = <
Fabio Estevam9a060c12014-09-05 09:46:10 -0300401 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
402 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
403 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
Anson Huang8e4422a2013-12-19 16:07:24 -0500404 >;
405 };
406
Shawn Guo817c27a2013-10-23 15:36:09 +0800407 pinctrl_i2c1: i2c1grp {
408 fsl,pins = <
409 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
410 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
411 >;
412 };
413
Fabio Estevam4b444bb2013-12-24 01:04:49 -0200414 pinctrl_i2c2: i2c2grp {
415 fsl,pins = <
416 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
417 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
418 >;
419 };
420
Shawn Guo817c27a2013-10-23 15:36:09 +0800421 pinctrl_i2c3: i2c3grp {
422 fsl,pins = <
423 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
424 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
425 >;
426 };
427
Marek Vasut9d4ebb32014-04-21 22:56:49 +0200428 pinctrl_pcie: pciegrp {
429 fsl,pins = <
Fabio Estevam9a060c12014-09-05 09:46:10 -0300430 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
Marek Vasut9d4ebb32014-04-21 22:56:49 +0200431 >;
432 };
433
Lucas Stach78827ec2014-07-23 19:29:11 +0200434 pinctrl_pcie_reg: pciereggrp {
435 fsl,pins = <
436 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
437 >;
438 };
439
Shawn Guo817c27a2013-10-23 15:36:09 +0800440 pinctrl_pwm1: pwm1grp {
441 fsl,pins = <
442 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
443 >;
444 };
445
446 pinctrl_uart1: uart1grp {
447 fsl,pins = <
448 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
449 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
450 >;
451 };
452
453 pinctrl_usbotg: usbotggrp {
454 fsl,pins = <
455 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
456 >;
457 };
458
459 pinctrl_usdhc2: usdhc2grp {
460 fsl,pins = <
461 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
462 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
463 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
464 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
465 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
466 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
467 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
468 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
469 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
470 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
471 >;
472 };
473
474 pinctrl_usdhc3: usdhc3grp {
475 fsl,pins = <
476 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
477 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
478 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
479 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
480 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
481 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
482 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
483 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
484 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
485 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
486 >;
487 };
Fabio Estevame02ab39a2014-05-08 11:10:56 -0300488
489 pinctrl_usdhc4: usdhc4grp {
490 fsl,pins = <
491 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
492 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
493 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
494 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
495 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
496 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
497 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
498 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
499 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
500 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
501 >;
502 };
Fabio Estevam49607ff2016-06-13 22:07:56 -0300503
504 pinctrl_wdog: wdoggrp {
505 fsl,pins = <
506 MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0
507 >;
508 };
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800509 };
Vincent Stehlé702bfbe2014-03-05 19:58:39 +0100510
511 gpio_leds {
512 pinctrl_gpio_leds: gpioledsgrp {
513 fsl,pins = <
Fabio Estevam9a060c12014-09-05 09:46:10 -0300514 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
Vincent Stehlé702bfbe2014-03-05 19:58:39 +0100515 >;
516 };
517 };
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800518};
519
Shawn Guob7fb7102013-07-16 22:15:18 +0800520&ldb {
521 status = "okay";
522
523 lvds-channel@1 {
524 fsl,data-mapping = "spwg";
525 fsl,data-width = <18>;
526 status = "okay";
527
Fabio Estevame0884942016-03-28 14:10:48 -0300528 port@4 {
529 reg = <4>;
530
531 lvds0_out: endpoint {
532 remote-endpoint = <&panel_in>;
Shawn Guob7fb7102013-07-16 22:15:18 +0800533 };
534 };
535 };
536};
537
Marek Vasut9d4ebb32014-04-21 22:56:49 +0200538&pcie {
539 pinctrl-names = "default";
540 pinctrl-0 = <&pinctrl_pcie>;
Fabio Estevamf1472f82016-06-05 23:00:47 -0300541 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
Marek Vasut9d4ebb32014-04-21 22:56:49 +0200542 status = "okay";
543};
544
Rogerio Pimentel2f35c0c2013-10-11 16:48:16 -0300545&pwm1 {
546 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800547 pinctrl-0 = <&pinctrl_pwm1>;
Rogerio Pimentel2f35c0c2013-10-11 16:48:16 -0300548 status = "okay";
549};
550
Leonard Crestezc23568d2017-04-04 20:04:13 +0300551&reg_arm {
552 vin-supply = <&sw1a_reg>;
553};
554
555&reg_pu {
556 vin-supply = <&sw1c_reg>;
557};
558
559&reg_soc {
560 vin-supply = <&sw1c_reg>;
561};
562
Robin Gong422b0672014-11-12 16:20:37 +0800563&snvs_poweroff {
564 status = "okay";
565};
566
Nicolin Chen48828702013-06-14 13:19:57 +0800567&ssi2 {
Nicolin Chen48828702013-06-14 13:19:57 +0800568 status = "okay";
569};
570
Shawn Guo082d33d2013-04-02 13:15:16 +0800571&uart1 {
572 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800573 pinctrl-0 = <&pinctrl_uart1>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800574 status = "okay";
575};
576
577&usbh1 {
Peter Chen015fa462013-08-12 16:46:24 +0800578 vbus-supply = <&reg_usb_h1_vbus>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800579 status = "okay";
580};
581
582&usbotg {
583 vbus-supply = <&reg_usb_otg_vbus>;
584 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800585 pinctrl-0 = <&pinctrl_usbotg>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800586 disable-over-current;
587 status = "okay";
588};
589
590&usdhc2 {
591 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800592 pinctrl-0 = <&pinctrl_usdhc2>;
Fabio Estevame3678172013-09-17 13:46:23 -0300593 bus-width = <8>;
Dong Aisheng89c1a8cf2015-07-22 20:53:02 +0800594 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
595 wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800596 status = "okay";
597};
598
599&usdhc3 {
600 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800601 pinctrl-0 = <&pinctrl_usdhc3>;
Fabio Estevame3678172013-09-17 13:46:23 -0300602 bus-width = <8>;
Dong Aisheng89c1a8cf2015-07-22 20:53:02 +0800603 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
604 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800605 status = "okay";
606};
Fabio Estevame02ab39a2014-05-08 11:10:56 -0300607
608&usdhc4 {
609 pinctrl-names = "default";
610 pinctrl-0 = <&pinctrl_usdhc4>;
611 bus-width = <8>;
612 non-removable;
613 no-1-8-v;
614 status = "okay";
615};
Fabio Estevam49607ff2016-06-13 22:07:56 -0300616
617&wdog1 {
618 status = "disabled";
619};
620
621&wdog2 {
622 pinctrl-names = "default";
623 pinctrl-0 = <&pinctrl_wdog>;
624 fsl,ext-reset-output;
625 status = "okay";
626};