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gerrit-public.fairphone.software / kernel / msm-4.19 / 58ecb23f64ee3a2ef66bb55b2e1e841385b6d08b / . / arch / arm / boot / dts / tegra30-cardhu.dtsi
blob: b159a41c7338c94f5cb670a5d67e78bdb53a52ff [file] [log] [blame]
Stephen Warren1bd0bd42012-10-17 16:38:21 -0600[diff] [blame]1#include "tegra30.dtsi"
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]2
Laxman Dewangan640a7af2012-08-09 16:30:38 +0530[diff] [blame]3/**
4 * This file contains common DT entry for all fab version of Cardhu.
5 * There is multiple fab version of Cardhu starting from A01 to A07.
6 * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
7 * A02 will have different sets of GPIOs for fixed regulator compare to
8 * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
9 * compatible with fab version A04. Based on Cardhu fab version, the
10 * related dts file need to be chosen like for Cardhu fab version A02,
11 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
12 * tegra30-cardhu-a04.dts.
13 * The identification of board is done in two ways, by looking the sticker
14 * on PCB and by reading board id eeprom.
15 * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
16 * number is the fab version like here it is 002 and hence fab version A02.
17 * The (downstream internal) U-Boot of Cardhu display the board-id as
18 * follows:
19 * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
20 * In this Fab version is 02 i.e. A02.
21 * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
22 * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
23 * wide.
24 */
25
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]26/ {
27 model = "NVIDIA Tegra30 Cardhu evaluation board";
28 compatible = "nvidia,cardhu", "nvidia,tegra30";
29
30 memory {
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]31 reg = <0x80000000 0x40000000>;
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]32 };
33
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame^]34 pcie-controller@00003000 {
Jay Agarwal89e7ada2013-08-09 16:49:27 +0200[diff] [blame]35 status = "okay";
36 pex-clk-supply = <&pex_hvdd_3v3_reg>;
37 vdd-supply = <&ldo1_reg>;
38 avdd-supply = <&ldo2_reg>;
39
40 pci@1,0 {
41 nvidia,num-lanes = <4>;
42 };
43
44 pci@2,0 {
45 nvidia,num-lanes = <1>;
46 };
47
48 pci@3,0 {
49 status = "okay";
50 nvidia,num-lanes = <1>;
51 };
52 };
53
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame^]54 pinmux@70000868 {
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]55 pinctrl-names = "default";
56 pinctrl-0 = <&state_default>;
57
58 state_default: pinmux {
59 sdmmc1_clk_pz0 {
60 nvidia,pins = "sdmmc1_clk_pz0";
61 nvidia,function = "sdmmc1";
62 nvidia,pull = <0>;
63 nvidia,tristate = <0>;
64 };
65 sdmmc1_cmd_pz1 {
66 nvidia,pins = "sdmmc1_cmd_pz1",
67 "sdmmc1_dat0_py7",
68 "sdmmc1_dat1_py6",
69 "sdmmc1_dat2_py5",
70 "sdmmc1_dat3_py4";
71 nvidia,function = "sdmmc1";
72 nvidia,pull = <2>;
73 nvidia,tristate = <0>;
74 };
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]75 sdmmc3_clk_pa6 {
76 nvidia,pins = "sdmmc3_clk_pa6";
77 nvidia,function = "sdmmc3";
78 nvidia,pull = <0>;
79 nvidia,tristate = <0>;
80 };
81 sdmmc3_cmd_pa7 {
82 nvidia,pins = "sdmmc3_cmd_pa7",
83 "sdmmc3_dat0_pb7",
84 "sdmmc3_dat1_pb6",
85 "sdmmc3_dat2_pb5",
86 "sdmmc3_dat3_pb4";
87 nvidia,function = "sdmmc3";
88 nvidia,pull = <2>;
89 nvidia,tristate = <0>;
90 };
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]91 sdmmc4_clk_pcc4 {
92 nvidia,pins = "sdmmc4_clk_pcc4",
93 "sdmmc4_rst_n_pcc3";
94 nvidia,function = "sdmmc4";
95 nvidia,pull = <0>;
96 nvidia,tristate = <0>;
97 };
98 sdmmc4_dat0_paa0 {
99 nvidia,pins = "sdmmc4_dat0_paa0",
100 "sdmmc4_dat1_paa1",
101 "sdmmc4_dat2_paa2",
102 "sdmmc4_dat3_paa3",
103 "sdmmc4_dat4_paa4",
104 "sdmmc4_dat5_paa5",
105 "sdmmc4_dat6_paa6",
106 "sdmmc4_dat7_paa7";
107 nvidia,function = "sdmmc4";
108 nvidia,pull = <2>;
109 nvidia,tristate = <0>;
110 };
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]111 dap2_fs_pa2 {
112 nvidia,pins = "dap2_fs_pa2",
113 "dap2_sclk_pa3",
114 "dap2_din_pa4",
115 "dap2_dout_pa5";
116 nvidia,function = "i2s1";
117 nvidia,pull = <0>;
118 nvidia,tristate = <0>;
119 };
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]120 sdio3 {
121 nvidia,pins = "drive_sdio3";
122 nvidia,high-speed-mode = <0>;
123 nvidia,schmitt = <0>;
124 nvidia,pull-down-strength = <46>;
125 nvidia,pull-up-strength = <42>;
126 nvidia,slew-rate-rising = <1>;
127 nvidia,slew-rate-falling = <1>;
128 };
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]129 uart3_txd_pw6 {
130 nvidia,pins = "uart3_txd_pw6",
131 "uart3_cts_n_pa1",
132 "uart3_rts_n_pc0",
133 "uart3_rxd_pw7";
134 nvidia,function = "uartc";
135 nvidia,pull = <0>;
136 nvidia,tristate = <0>;
137 };
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]138 };
139 };
140
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]141 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]142 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]143 };
144
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]145 serial@70006200 {
146 compatible = "nvidia,tegra30-hsuart";
147 status = "okay";
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]148 };
149
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]150 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]151 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]152 clock-frequency = <100000>;
153 };
154
155 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]156 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]157 clock-frequency = <100000>;
158 };
159
160 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]161 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]162 clock-frequency = <100000>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530[diff] [blame]163
164 /* ALS and Proximity sensor */
165 isl29028@44 {
166 compatible = "isil,isl29028";
167 reg = <0x44>;
168 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]169 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530[diff] [blame]170 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]171 };
172
173 i2c@7000c700 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]174 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]175 clock-frequency = <100000>;
176 };
177
178 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]179 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]180 clock-frequency = <100000>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]181
182 wm8903: wm8903@1a {
183 compatible = "wlf,wm8903";
184 reg = <0x1a>;
185 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]186 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]187
188 gpio-controller;
189 #gpio-cells = <2>;
190
191 micdet-cfg = <0>;
192 micdet-delay = <100>;
193 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
194 };
Laxman Dewangan331da582012-05-10 20:38:45 +0000[diff] [blame]195
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]196 pmic: tps65911@2d {
197 compatible = "ti,tps65911";
198 reg = <0x2d>;
199
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]200 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]201 #interrupt-cells = <2>;
202 interrupt-controller;
203
Stephen Warren44b12ef2012-09-11 11:42:26 -0600[diff] [blame]204 ti,system-power-controller;
205
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]206 #gpio-cells = <2>;
207 gpio-controller;
208
209 vcc1-supply = <&vdd_ac_bat_reg>;
210 vcc2-supply = <&vdd_ac_bat_reg>;
211 vcc3-supply = <&vio_reg>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]212 vcc4-supply = <&vdd_5v0_reg>;
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]213 vcc5-supply = <&vdd_ac_bat_reg>;
214 vcc6-supply = <&vdd2_reg>;
215 vcc7-supply = <&vdd_ac_bat_reg>;
216 vccio-supply = <&vdd_ac_bat_reg>;
217
218 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]219 vdd1_reg: vdd1 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]220 regulator-name = "vddio_ddr_1v2";
221 regulator-min-microvolt = <1200000>;
222 regulator-max-microvolt = <1200000>;
223 regulator-always-on;
224 };
225
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]226 vdd2_reg: vdd2 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]227 regulator-name = "vdd_1v5_gen";
228 regulator-min-microvolt = <1500000>;
229 regulator-max-microvolt = <1500000>;
230 regulator-always-on;
231 };
232
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]233 vddctrl_reg: vddctrl {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]234 regulator-name = "vdd_cpu,vdd_sys";
235 regulator-min-microvolt = <1000000>;
236 regulator-max-microvolt = <1000000>;
237 regulator-always-on;
238 };
239
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]240 vio_reg: vio {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]241 regulator-name = "vdd_1v8_gen";
242 regulator-min-microvolt = <1800000>;
243 regulator-max-microvolt = <1800000>;
244 regulator-always-on;
245 };
246
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]247 ldo1_reg: ldo1 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]248 regulator-name = "vdd_pexa,vdd_pexb";
249 regulator-min-microvolt = <1050000>;
250 regulator-max-microvolt = <1050000>;
251 };
252
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]253 ldo2_reg: ldo2 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]254 regulator-name = "vdd_sata,avdd_plle";
255 regulator-min-microvolt = <1050000>;
256 regulator-max-microvolt = <1050000>;
257 };
258
259 /* LDO3 is not connected to anything */
260
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]261 ldo4_reg: ldo4 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]262 regulator-name = "vdd_rtc";
263 regulator-min-microvolt = <1200000>;
264 regulator-max-microvolt = <1200000>;
265 regulator-always-on;
266 };
267
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]268 ldo5_reg: ldo5 {
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]269 regulator-name = "vddio_sdmmc,avdd_vdac";
270 regulator-min-microvolt = <3300000>;
271 regulator-max-microvolt = <3300000>;
272 regulator-always-on;
273 };
274
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]275 ldo6_reg: ldo6 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]276 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
277 regulator-min-microvolt = <1200000>;
278 regulator-max-microvolt = <1200000>;
279 };
280
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]281 ldo7_reg: ldo7 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]282 regulator-name = "vdd_pllm,x,u,a_p_c_s";
283 regulator-min-microvolt = <1200000>;
284 regulator-max-microvolt = <1200000>;
285 regulator-always-on;
286 };
287
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]288 ldo8_reg: ldo8 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]289 regulator-name = "vdd_ddr_hs";
290 regulator-min-microvolt = <1000000>;
291 regulator-max-microvolt = <1000000>;
292 regulator-always-on;
293 };
294 };
295 };
Wei Ni74ecab22013-07-12 15:49:23 +0800[diff] [blame]296
Wei Ni7c7de6b2013-10-07 17:28:29 +0800[diff] [blame]297 temperature-sensor@4c {
Wei Ni74ecab22013-07-12 15:49:23 +0800[diff] [blame]298 compatible = "onnn,nct1008";
299 reg = <0x4c>;
Wei Ni7c7de6b2013-10-07 17:28:29 +0800[diff] [blame]300 vcc-supply = <&sys_3v3_reg>;
Wei Ni74ecab22013-07-12 15:49:23 +0800[diff] [blame]301 interrupt-parent = <&gpio>;
302 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
303 };
Stephen Warren2b8584d2013-07-15 10:33:53 -0600[diff] [blame]304
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame^]305 tps62361@60 {
Stephen Warren2b8584d2013-07-15 10:33:53 -0600[diff] [blame]306 compatible = "ti,tps62361";
307 reg = <0x60>;
308
309 regulator-name = "tps62361-vout";
310 regulator-min-microvolt = <500000>;
311 regulator-max-microvolt = <1500000>;
312 regulator-boot-on;
313 regulator-always-on;
314 ti,vsel0-state-high;
315 ti,vsel1-state-high;
316 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]317 };
Stephen Warren850c4c82012-02-01 16:29:57 -0700[diff] [blame]318
Laxman Dewanganc42cb1c2012-10-31 14:32:54 +0530[diff] [blame]319 spi@7000da00 {
320 status = "okay";
321 spi-max-frequency = <25000000>;
322 spi-flash@1 {
323 compatible = "winbond,w25q32";
324 reg = <1>;
325 spi-max-frequency = <20000000>;
326 };
327 };
328
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame^]329 ahub@70080000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]330 i2s@70080400 {
331 status = "okay";
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]332 };
333 };
334
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame^]335 pmc@7000e400 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]336 status = "okay";
337 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800[diff] [blame]338 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800[diff] [blame]339 nvidia,cpu-pwr-good-time = <2000>;
340 nvidia,cpu-pwr-off-time = <200>;
341 nvidia,core-pwr-good-time = <3845 3845>;
342 nvidia,core-pwr-off-time = <0>;
343 nvidia,core-power-req-active-high;
344 nvidia,sys-clock-req-active-high;
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]345 };
346
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]347 sdhci@78000000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]348 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]349 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
350 wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
351 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
Arnd Bergmann7f217792012-05-13 00:14:24 -0400[diff] [blame]352 bus-width = <4>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]353 };
354
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]355 sdhci@78000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]356 status = "okay";
Arnd Bergmann7f217792012-05-13 00:14:24 -0400[diff] [blame]357 bus-width = <8>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600[diff] [blame]358 non-removable;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]359 };
360
Tuomas Tynkkynencc34c9f2013-08-01 18:00:17 +0300[diff] [blame]361 usb@7d008000 {
362 status = "okay";
363 };
364
365 usb-phy@7d008000 {
366 vbus-supply = <&usb3_vbus_reg>;
367 status = "okay";
368 };
369
Joseph Lo7021d122013-04-03 19:31:27 +0800[diff] [blame]370 clocks {
371 compatible = "simple-bus";
372 #address-cells = <1>;
373 #size-cells = <0>;
374
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame^]375 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800[diff] [blame]376 compatible = "fixed-clock";
377 reg=<0>;
378 #clock-cells = <0>;
379 clock-frequency = <32768>;
380 };
381 };
382
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]383 regulators {
384 compatible = "simple-bus";
385 #address-cells = <1>;
386 #size-cells = <0>;
387
388 vdd_ac_bat_reg: regulator@0 {
389 compatible = "regulator-fixed";
390 reg = <0>;
391 regulator-name = "vdd_ac_bat";
392 regulator-min-microvolt = <5000000>;
393 regulator-max-microvolt = <5000000>;
394 regulator-always-on;
395 };
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]396
397 cam_1v8_reg: regulator@1 {
398 compatible = "regulator-fixed";
399 reg = <1>;
400 regulator-name = "cam_1v8";
401 regulator-min-microvolt = <1800000>;
402 regulator-max-microvolt = <1800000>;
403 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]404 gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]405 vin-supply = <&vio_reg>;
406 };
407
408 cp_5v_reg: regulator@2 {
409 compatible = "regulator-fixed";
410 reg = <2>;
411 regulator-name = "cp_5v";
412 regulator-min-microvolt = <5000000>;
413 regulator-max-microvolt = <5000000>;
414 regulator-boot-on;
415 regulator-always-on;
416 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]417 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]418 };
419
420 emmc_3v3_reg: regulator@3 {
421 compatible = "regulator-fixed";
422 reg = <3>;
423 regulator-name = "emmc_3v3";
424 regulator-min-microvolt = <3300000>;
425 regulator-max-microvolt = <3300000>;
426 regulator-always-on;
427 regulator-boot-on;
428 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]429 gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]430 vin-supply = <&sys_3v3_reg>;
431 };
432
433 modem_3v3_reg: regulator@4 {
434 compatible = "regulator-fixed";
435 reg = <4>;
436 regulator-name = "modem_3v3";
437 regulator-min-microvolt = <3300000>;
438 regulator-max-microvolt = <3300000>;
439 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]440 gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]441 };
442
443 pex_hvdd_3v3_reg: regulator@5 {
444 compatible = "regulator-fixed";
445 reg = <5>;
446 regulator-name = "pex_hvdd_3v3";
447 regulator-min-microvolt = <3300000>;
448 regulator-max-microvolt = <3300000>;
449 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]450 gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]451 vin-supply = <&sys_3v3_reg>;
452 };
453
454 vdd_cam1_ldo_reg: regulator@6 {
455 compatible = "regulator-fixed";
456 reg = <6>;
457 regulator-name = "vdd_cam1_ldo";
458 regulator-min-microvolt = <2800000>;
459 regulator-max-microvolt = <2800000>;
460 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]461 gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]462 vin-supply = <&sys_3v3_reg>;
463 };
464
465 vdd_cam2_ldo_reg: regulator@7 {
466 compatible = "regulator-fixed";
467 reg = <7>;
468 regulator-name = "vdd_cam2_ldo";
469 regulator-min-microvolt = <2800000>;
470 regulator-max-microvolt = <2800000>;
471 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]472 gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]473 vin-supply = <&sys_3v3_reg>;
474 };
475
476 vdd_cam3_ldo_reg: regulator@8 {
477 compatible = "regulator-fixed";
478 reg = <8>;
479 regulator-name = "vdd_cam3_ldo";
480 regulator-min-microvolt = <3300000>;
481 regulator-max-microvolt = <3300000>;
482 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]483 gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]484 vin-supply = <&sys_3v3_reg>;
485 };
486
487 vdd_com_reg: regulator@9 {
488 compatible = "regulator-fixed";
489 reg = <9>;
490 regulator-name = "vdd_com";
491 regulator-min-microvolt = <3300000>;
492 regulator-max-microvolt = <3300000>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]493 regulator-always-on;
494 regulator-boot-on;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]495 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]496 gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]497 vin-supply = <&sys_3v3_reg>;
498 };
499
500 vdd_fuse_3v3_reg: regulator@10 {
501 compatible = "regulator-fixed";
502 reg = <10>;
503 regulator-name = "vdd_fuse_3v3";
504 regulator-min-microvolt = <3300000>;
505 regulator-max-microvolt = <3300000>;
506 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]507 gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]508 vin-supply = <&sys_3v3_reg>;
509 };
510
511 vdd_pnl1_reg: regulator@11 {
512 compatible = "regulator-fixed";
513 reg = <11>;
514 regulator-name = "vdd_pnl1";
515 regulator-min-microvolt = <3300000>;
516 regulator-max-microvolt = <3300000>;
517 regulator-always-on;
518 regulator-boot-on;
519 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]520 gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]521 vin-supply = <&sys_3v3_reg>;
522 };
523
524 vdd_vid_reg: regulator@12 {
525 compatible = "regulator-fixed";
526 reg = <12>;
527 regulator-name = "vddio_vid";
528 regulator-min-microvolt = <5000000>;
529 regulator-max-microvolt = <5000000>;
530 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]531 gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]532 gpio-open-drain;
533 vin-supply = <&vdd_5v0_reg>;
534 };
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]535 };
536
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]537 sound {
538 compatible = "nvidia,tegra-audio-wm8903-cardhu",
539 "nvidia,tegra-audio-wm8903";
540 nvidia,model = "NVIDIA Tegra Cardhu";
541
542 nvidia,audio-routing =
543 "Headphone Jack", "HPOUTR",
544 "Headphone Jack", "HPOUTL",
545 "Int Spk", "ROP",
546 "Int Spk", "RON",
547 "Int Spk", "LOP",
548 "Int Spk", "LON",
549 "Mic Jack", "MICBIAS",
550 "IN1L", "Mic Jack";
551
552 nvidia,i2s-controller = <&tegra_i2s1>;
553 nvidia,audio-codec = <&wm8903>;
554
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]555 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
556 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
557 GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]558
Hiroshi Doyu05849c92013-05-22 19:45:34 +0300[diff] [blame]559 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
560 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
561 <&tegra_car TEGRA30_CLK_EXTERN1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]562 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]563 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]564};