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Yuanyuan Liud5ec14c2019-01-03 11:25:40 -08001/* SPDX-License-Identifier: GPL-2.0-only */
Yue Ma09f6b642020-03-24 07:26:50 +08002/* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. */
Yuanyuan Liud5ec14c2019-01-03 11:25:40 -08003
4#ifndef _CNSS_PCI_H
5#define _CNSS_PCI_H
6
7#include <asm/dma-iommu.h>
8#include <linux/iommu.h>
9#include <linux/mhi.h>
10#include <linux/msm_pcie.h>
11#include <linux/pci.h>
12
13#include "main.h"
14
15enum cnss_mhi_state {
16 CNSS_MHI_INIT,
17 CNSS_MHI_DEINIT,
18 CNSS_MHI_POWER_ON,
Yue Maafa7fca2019-09-27 12:49:39 -070019 CNSS_MHI_POWERING_OFF,
Yuanyuan Liud5ec14c2019-01-03 11:25:40 -080020 CNSS_MHI_POWER_OFF,
21 CNSS_MHI_FORCE_POWER_OFF,
22 CNSS_MHI_SUSPEND,
23 CNSS_MHI_RESUME,
24 CNSS_MHI_TRIGGER_RDDM,
25 CNSS_MHI_RDDM,
26 CNSS_MHI_RDDM_DONE,
27};
28
Yue Maf28455c2019-04-09 18:17:03 -070029enum pci_link_status {
30 PCI_GEN1,
31 PCI_GEN2,
32 PCI_DEF,
33};
34
Yuanyuan Liud5ec14c2019-01-03 11:25:40 -080035struct cnss_msi_user {
36 char *name;
37 int num_vectors;
38 u32 base_vector;
39};
40
41struct cnss_msi_config {
42 int total_vectors;
43 int total_users;
44 struct cnss_msi_user *users;
45};
46
Yue Mac9b8dca2019-02-05 18:06:49 -080047struct cnss_pci_reg {
48 char *name;
49 u32 offset;
50};
51
Yue Ma5d219732019-04-04 16:00:40 -070052struct cnss_pci_debug_reg {
53 u32 offset;
54 u32 val;
55};
56
Yuanyuan Liu26008522019-08-03 11:31:18 -070057struct cnss_misc_reg {
58 u8 wr;
59 u32 offset;
60 u32 val;
61};
62
Yuanyuan Liud5ec14c2019-01-03 11:25:40 -080063struct cnss_pci_data {
64 struct pci_dev *pci_dev;
65 struct cnss_plat_data *plat_priv;
66 const struct pci_device_id *pci_device_id;
67 u32 device_id;
68 u16 revision_id;
69 struct cnss_wlan_driver *driver_ops;
70 u8 pci_link_state;
71 u8 pci_link_down_ind;
72 struct pci_saved_state *saved_state;
73 struct pci_saved_state *default_state;
74 struct msm_pcie_register_event msm_pci_event;
75 atomic_t auto_suspended;
Yue Maf28455c2019-04-09 18:17:03 -070076 atomic_t drv_connected;
Yue Maa16423c2019-04-19 13:42:35 -070077 u8 drv_connected_last;
Yue Maf28455c2019-04-09 18:17:03 -070078 u16 def_link_speed;
79 u16 def_link_width;
Yuanyuan Liud5ec14c2019-01-03 11:25:40 -080080 u8 monitor_wake_intr;
Yuanyuan Liu3edf9fb2019-02-20 14:14:15 -080081 struct iommu_domain *iommu_domain;
Yuanyuan Liud5ec14c2019-01-03 11:25:40 -080082 u8 smmu_s1_enable;
83 dma_addr_t smmu_iova_start;
84 size_t smmu_iova_len;
85 dma_addr_t smmu_iova_ipa_start;
86 size_t smmu_iova_ipa_len;
87 void __iomem *bar;
88 struct cnss_msi_config *msi_config;
89 u32 msi_ep_base_data;
90 struct mhi_controller *mhi_ctrl;
91 unsigned long mhi_state;
Yue Mac9b8dca2019-02-05 18:06:49 -080092 u32 remap_window;
Yue Ma4738d5a2018-10-30 15:54:40 -070093 struct timer_list dev_rddm_timer;
Yue Mab02821f2019-05-09 17:29:19 -070094 struct delayed_work time_sync_work;
Yuanyuan Liud5ec14c2019-01-03 11:25:40 -080095 u8 disable_pc;
Yue Ma30ec0e02019-09-10 14:32:37 -070096 struct mutex bus_lock; /* mutex for suspend and resume bus */
Yue Ma5d219732019-04-04 16:00:40 -070097 struct cnss_pci_debug_reg *debug_reg;
Yuanyuan Liu26008522019-08-03 11:31:18 -070098 struct cnss_misc_reg *wcss_reg;
99 u32 wcss_reg_size;
100 struct cnss_misc_reg *pcie_reg;
101 u32 pcie_reg_size;
102 struct cnss_misc_reg *wlaon_reg;
103 u32 wlaon_reg_size;
Yuanyuan Liud5ec14c2019-01-03 11:25:40 -0800104};
105
106static inline void cnss_set_pci_priv(struct pci_dev *pci_dev, void *data)
107{
108 pci_set_drvdata(pci_dev, data);
109}
110
111static inline struct cnss_pci_data *cnss_get_pci_priv(struct pci_dev *pci_dev)
112{
113 return pci_get_drvdata(pci_dev);
114}
115
116static inline struct cnss_plat_data *cnss_pci_priv_to_plat_priv(void *bus_priv)
117{
118 struct cnss_pci_data *pci_priv = bus_priv;
119
120 return pci_priv->plat_priv;
121}
122
123static inline void cnss_pci_set_monitor_wake_intr(void *bus_priv, bool val)
124{
125 struct cnss_pci_data *pci_priv = bus_priv;
126
127 pci_priv->monitor_wake_intr = val;
128}
129
130static inline bool cnss_pci_get_monitor_wake_intr(void *bus_priv)
131{
132 struct cnss_pci_data *pci_priv = bus_priv;
133
134 return pci_priv->monitor_wake_intr;
135}
136
137static inline void cnss_pci_set_auto_suspended(void *bus_priv, int val)
138{
139 struct cnss_pci_data *pci_priv = bus_priv;
140
141 atomic_set(&pci_priv->auto_suspended, val);
142}
143
144static inline int cnss_pci_get_auto_suspended(void *bus_priv)
145{
146 struct cnss_pci_data *pci_priv = bus_priv;
147
148 return atomic_read(&pci_priv->auto_suspended);
149}
150
Yue Maf28455c2019-04-09 18:17:03 -0700151static inline void cnss_pci_set_drv_connected(void *bus_priv, int val)
152{
153 struct cnss_pci_data *pci_priv = bus_priv;
154
155 atomic_set(&pci_priv->drv_connected, val);
156}
157
158static inline int cnss_pci_get_drv_connected(void *bus_priv)
159{
160 struct cnss_pci_data *pci_priv = bus_priv;
161
162 return atomic_read(&pci_priv->drv_connected);
163}
164
Yue Maf51da692020-03-31 16:28:46 -0700165int cnss_pci_check_link_status(struct cnss_pci_data *pci_priv);
Yuanyuan Liud5ec14c2019-01-03 11:25:40 -0800166int cnss_suspend_pci_link(struct cnss_pci_data *pci_priv);
167int cnss_resume_pci_link(struct cnss_pci_data *pci_priv);
168int cnss_pci_init(struct cnss_plat_data *plat_priv);
169void cnss_pci_deinit(struct cnss_plat_data *plat_priv);
170int cnss_pci_alloc_fw_mem(struct cnss_pci_data *pci_priv);
Yuanyuan Liu36d1fba2019-01-02 14:13:15 -0800171int cnss_pci_alloc_qdss_mem(struct cnss_pci_data *pci_priv);
172void cnss_pci_free_qdss_mem(struct cnss_pci_data *pci_priv);
Yuanyuan Liud5ec14c2019-01-03 11:25:40 -0800173int cnss_pci_load_m3(struct cnss_pci_data *pci_priv);
Yuanyuan Liud5ec14c2019-01-03 11:25:40 -0800174int cnss_pci_start_mhi(struct cnss_pci_data *pci_priv);
Yuanyuan Liud5ec14c2019-01-03 11:25:40 -0800175void cnss_pci_collect_dump_info(struct cnss_pci_data *pci_priv, bool in_panic);
176void cnss_pci_clear_dump_info(struct cnss_pci_data *pci_priv);
Yuanyuan Liud5ec14c2019-01-03 11:25:40 -0800177u32 cnss_pci_get_wake_msi(struct cnss_pci_data *pci_priv);
178int cnss_pci_force_fw_assert_hdlr(struct cnss_pci_data *pci_priv);
Yue Ma30ec0e02019-09-10 14:32:37 -0700179int cnss_pci_qmi_send_get(struct cnss_pci_data *pci_priv);
180int cnss_pci_qmi_send_put(struct cnss_pci_data *pci_priv);
Yuanyuan Liud5ec14c2019-01-03 11:25:40 -0800181void cnss_pci_fw_boot_timeout_hdlr(struct cnss_pci_data *pci_priv);
182int cnss_pci_call_driver_probe(struct cnss_pci_data *pci_priv);
183int cnss_pci_call_driver_remove(struct cnss_pci_data *pci_priv);
184int cnss_pci_dev_powerup(struct cnss_pci_data *pci_priv);
185int cnss_pci_dev_shutdown(struct cnss_pci_data *pci_priv);
186int cnss_pci_dev_crash_shutdown(struct cnss_pci_data *pci_priv);
187int cnss_pci_dev_ramdump(struct cnss_pci_data *pci_priv);
188int cnss_pci_register_driver_hdlr(struct cnss_pci_data *pci_priv, void *data);
189int cnss_pci_unregister_driver_hdlr(struct cnss_pci_data *pci_priv);
190int cnss_pci_call_driver_modem_status(struct cnss_pci_data *pci_priv,
191 int modem_current_status);
192void cnss_pci_pm_runtime_show_usage_count(struct cnss_pci_data *pci_priv);
Yue Ma6476dc92019-05-03 11:21:37 -0700193int cnss_pci_pm_request_resume(struct cnss_pci_data *pci_priv);
194int cnss_pci_pm_runtime_resume(struct cnss_pci_data *pci_priv);
Yuanyuan Liud5ec14c2019-01-03 11:25:40 -0800195int cnss_pci_pm_runtime_get(struct cnss_pci_data *pci_priv);
Yue Ma8f0ea9e2019-05-28 12:35:13 -0700196int cnss_pci_pm_runtime_get_sync(struct cnss_pci_data *pci_priv);
Yuanyuan Liud5ec14c2019-01-03 11:25:40 -0800197void cnss_pci_pm_runtime_get_noresume(struct cnss_pci_data *pci_priv);
198int cnss_pci_pm_runtime_put_autosuspend(struct cnss_pci_data *pci_priv);
199void cnss_pci_pm_runtime_put_noidle(struct cnss_pci_data *pci_priv);
200void cnss_pci_pm_runtime_mark_last_busy(struct cnss_pci_data *pci_priv);
201int cnss_pci_update_status(struct cnss_pci_data *pci_priv,
202 enum cnss_driver_status status);
Mohammed Siddiqe55b24b2020-04-20 20:20:11 +0530203int cnss_call_driver_uevent(struct cnss_pci_data *pci_priv,
204 enum cnss_driver_status status, void *data);
Yue Ma25469982019-05-28 12:47:41 -0700205int cnss_pcie_is_device_down(struct cnss_pci_data *pci_priv);
Yue Macdd61612019-08-23 11:58:31 -0700206int cnss_pci_suspend_bus(struct cnss_pci_data *pci_priv);
207int cnss_pci_resume_bus(struct cnss_pci_data *pci_priv);
Yue Ma710d5222019-09-20 16:35:10 -0700208int cnss_pci_debug_reg_read(struct cnss_pci_data *pci_priv, u32 offset,
209 u32 *val);
210int cnss_pci_debug_reg_write(struct cnss_pci_data *pci_priv, u32 offset,
211 u32 val);
Yue Ma09f6b642020-03-24 07:26:50 +0800212int cnss_pci_get_iova(struct cnss_pci_data *pci_priv, u64 *addr, u64 *size);
213int cnss_pci_get_iova_ipa(struct cnss_pci_data *pci_priv, u64 *addr,
214 u64 *size);
Yuanyuan Liud5ec14c2019-01-03 11:25:40 -0800215
216#endif /* _CNSS_PCI_H */