Sascha Hauer | 6c7b06850 | 2012-03-07 21:01:28 +0100 | [diff] [blame] | 1 | #ifndef __MACH_IMX_CLK_H |
| 2 | #define __MACH_IMX_CLK_H |
| 3 | |
| 4 | #include <linux/spinlock.h> |
| 5 | #include <linux/clk-provider.h> |
Sascha Hauer | 3a84d17 | 2012-09-11 08:50:00 +0200 | [diff] [blame] | 6 | |
| 7 | extern spinlock_t imx_ccm_lock; |
Sascha Hauer | 6c7b06850 | 2012-03-07 21:01:28 +0100 | [diff] [blame] | 8 | |
Alexander Shiyan | 229be9c | 2014-06-10 19:40:26 +0400 | [diff] [blame] | 9 | void imx_check_clocks(struct clk *clks[], unsigned int count); |
Lucas Stach | 55adc61 | 2015-09-21 18:53:57 +0200 | [diff] [blame] | 10 | void imx_register_uart_clocks(struct clk ** const clks[]); |
Alexander Shiyan | 229be9c | 2014-06-10 19:40:26 +0400 | [diff] [blame] | 11 | |
Liu Ying | dfd8714 | 2013-07-04 17:57:17 +0800 | [diff] [blame] | 12 | extern void imx_cscmr1_fixup(u32 *val); |
| 13 | |
Shawn Guo | 3bec5f8 | 2015-04-26 13:33:39 +0800 | [diff] [blame] | 14 | enum imx_pllv1_type { |
| 15 | IMX_PLLV1_IMX1, |
| 16 | IMX_PLLV1_IMX21, |
| 17 | IMX_PLLV1_IMX25, |
| 18 | IMX_PLLV1_IMX27, |
| 19 | IMX_PLLV1_IMX31, |
| 20 | IMX_PLLV1_IMX35, |
| 21 | }; |
| 22 | |
| 23 | struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name, |
| 24 | const char *parent, void __iomem *base); |
Sascha Hauer | 6c7b06850 | 2012-03-07 21:01:28 +0100 | [diff] [blame] | 25 | |
Sascha Hauer | a547b81 | 2012-03-19 12:36:10 +0100 | [diff] [blame] | 26 | struct clk *imx_clk_pllv2(const char *name, const char *parent, |
| 27 | void __iomem *base); |
| 28 | |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 29 | enum imx_pllv3_type { |
| 30 | IMX_PLLV3_GENERIC, |
| 31 | IMX_PLLV3_SYS, |
| 32 | IMX_PLLV3_USB, |
Stefan Agner | 60ad846 | 2014-12-02 17:59:42 +0100 | [diff] [blame] | 33 | IMX_PLLV3_USB_VF610, |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 34 | IMX_PLLV3_AV, |
| 35 | IMX_PLLV3_ENET, |
Frank Li | f539474 | 2015-05-19 02:45:02 +0800 | [diff] [blame] | 36 | IMX_PLLV3_ENET_IMX7, |
Nikita Yushchenko | c77cbdd1 | 2016-12-19 11:12:09 +0300 | [diff] [blame] | 37 | IMX_PLLV3_SYS_VF610, |
Fabio Estevam | ad14972 | 2017-05-15 08:55:05 -0300 | [diff] [blame] | 38 | IMX_PLLV3_DDR_IMX7, |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 39 | }; |
| 40 | |
| 41 | struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, |
Sascha Hauer | 2b25469 | 2012-11-22 10:18:41 +0100 | [diff] [blame] | 42 | const char *parent_name, void __iomem *base, u32 div_mask); |
Shawn Guo | a3f6b9d | 2012-04-04 16:02:28 +0800 | [diff] [blame] | 43 | |
Sascha Hauer | b75c015 | 2011-04-19 08:33:45 +0200 | [diff] [blame] | 44 | struct clk *clk_register_gate2(struct device *dev, const char *name, |
| 45 | const char *parent_name, unsigned long flags, |
Stefan Agner | 4568292 | 2016-03-09 18:16:47 -0800 | [diff] [blame] | 46 | void __iomem *reg, u8 bit_idx, u8 cgr_val, |
Shawn Guo | f9f28cd | 2014-04-19 10:58:22 +0800 | [diff] [blame] | 47 | u8 clk_gate_flags, spinlock_t *lock, |
| 48 | unsigned int *share_count); |
Sascha Hauer | b75c015 | 2011-04-19 08:33:45 +0200 | [diff] [blame] | 49 | |
Martin Fuzzey | 75f83d0 | 2013-04-23 20:16:59 +0800 | [diff] [blame] | 50 | struct clk * imx_obtain_fixed_clock( |
| 51 | const char *name, unsigned long rate); |
| 52 | |
Shawn Guo | 19d8634 | 2014-08-26 15:06:33 +0800 | [diff] [blame] | 53 | struct clk *imx_clk_gate_exclusive(const char *name, const char *parent, |
| 54 | void __iomem *reg, u8 shift, u32 exclusive_mask); |
| 55 | |
Shawn Guo | a10bd67 | 2012-04-04 16:07:53 +0800 | [diff] [blame] | 56 | struct clk *imx_clk_pfd(const char *name, const char *parent_name, |
| 57 | void __iomem *reg, u8 idx); |
| 58 | |
Shawn Guo | 32af7a8 | 2012-04-04 16:20:56 +0800 | [diff] [blame] | 59 | struct clk *imx_clk_busy_divider(const char *name, const char *parent_name, |
| 60 | void __iomem *reg, u8 shift, u8 width, |
| 61 | void __iomem *busy_reg, u8 busy_shift); |
| 62 | |
| 63 | struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, |
| 64 | u8 width, void __iomem *busy_reg, u8 busy_shift, |
| 65 | const char **parent_names, int num_parents); |
| 66 | |
Liu Ying | cbe7fc8 | 2013-07-04 17:22:26 +0800 | [diff] [blame] | 67 | struct clk *imx_clk_fixup_divider(const char *name, const char *parent, |
| 68 | void __iomem *reg, u8 shift, u8 width, |
| 69 | void (*fixup)(u32 *val)); |
| 70 | |
Liu Ying | a49e6c4 | 2013-07-04 17:35:46 +0800 | [diff] [blame] | 71 | struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, |
| 72 | u8 shift, u8 width, const char **parents, |
| 73 | int num_parents, void (*fixup)(u32 *val)); |
| 74 | |
Sascha Hauer | 6c7b06850 | 2012-03-07 21:01:28 +0100 | [diff] [blame] | 75 | static inline struct clk *imx_clk_fixed(const char *name, int rate) |
| 76 | { |
Stephen Boyd | 38c7035 | 2016-03-01 10:59:49 -0800 | [diff] [blame] | 77 | return clk_register_fixed_rate(NULL, name, NULL, 0, rate); |
Sascha Hauer | 6c7b06850 | 2012-03-07 21:01:28 +0100 | [diff] [blame] | 78 | } |
| 79 | |
Philipp Zabel | 03d576f | 2016-10-17 22:29:13 -0200 | [diff] [blame] | 80 | static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg, |
| 81 | u8 shift, u8 width, const char **parents, int num_parents) |
| 82 | { |
| 83 | return clk_register_mux(NULL, name, parents, num_parents, |
| 84 | CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg, |
| 85 | shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock); |
| 86 | } |
| 87 | |
Dong Aisheng | 5afc994 | 2016-06-30 17:31:15 +0800 | [diff] [blame] | 88 | static inline struct clk *imx_clk_fixed_factor(const char *name, |
| 89 | const char *parent, unsigned int mult, unsigned int div) |
| 90 | { |
| 91 | return clk_register_fixed_factor(NULL, name, parent, |
| 92 | CLK_SET_RATE_PARENT, mult, div); |
| 93 | } |
| 94 | |
Sascha Hauer | 6c7b06850 | 2012-03-07 21:01:28 +0100 | [diff] [blame] | 95 | static inline struct clk *imx_clk_divider(const char *name, const char *parent, |
| 96 | void __iomem *reg, u8 shift, u8 width) |
| 97 | { |
| 98 | return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, |
| 99 | reg, shift, width, 0, &imx_ccm_lock); |
| 100 | } |
| 101 | |
Philipp Zabel | 3ce9217 | 2013-03-27 18:30:40 +0100 | [diff] [blame] | 102 | static inline struct clk *imx_clk_divider_flags(const char *name, |
| 103 | const char *parent, void __iomem *reg, u8 shift, u8 width, |
| 104 | unsigned long flags) |
| 105 | { |
| 106 | return clk_register_divider(NULL, name, parent, flags, |
| 107 | reg, shift, width, 0, &imx_ccm_lock); |
| 108 | } |
| 109 | |
Dong Aisheng | 39c2949 | 2016-06-30 17:31:16 +0800 | [diff] [blame] | 110 | static inline struct clk *imx_clk_divider2(const char *name, const char *parent, |
| 111 | void __iomem *reg, u8 shift, u8 width) |
| 112 | { |
| 113 | return clk_register_divider(NULL, name, parent, |
| 114 | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, |
| 115 | reg, shift, width, 0, &imx_ccm_lock); |
| 116 | } |
| 117 | |
Sascha Hauer | 6c7b06850 | 2012-03-07 21:01:28 +0100 | [diff] [blame] | 118 | static inline struct clk *imx_clk_gate(const char *name, const char *parent, |
| 119 | void __iomem *reg, u8 shift) |
| 120 | { |
| 121 | return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, |
| 122 | shift, 0, &imx_ccm_lock); |
| 123 | } |
| 124 | |
Alexander Shiyan | 6525169 | 2014-06-22 17:17:06 +0400 | [diff] [blame] | 125 | static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent, |
| 126 | void __iomem *reg, u8 shift) |
| 127 | { |
| 128 | return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, |
| 129 | shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock); |
| 130 | } |
| 131 | |
Dong Aisheng | 5afc994 | 2016-06-30 17:31:15 +0800 | [diff] [blame] | 132 | static inline struct clk *imx_clk_gate2(const char *name, const char *parent, |
| 133 | void __iomem *reg, u8 shift) |
| 134 | { |
| 135 | return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, |
| 136 | shift, 0x3, 0, &imx_ccm_lock, NULL); |
| 137 | } |
| 138 | |
| 139 | static inline struct clk *imx_clk_gate2_shared(const char *name, |
| 140 | const char *parent, void __iomem *reg, u8 shift, |
| 141 | unsigned int *share_count) |
| 142 | { |
| 143 | return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, |
| 144 | shift, 0x3, 0, &imx_ccm_lock, share_count); |
| 145 | } |
| 146 | |
Fabio Estevam | d5ebf5f | 2016-08-12 15:26:55 -0300 | [diff] [blame] | 147 | static inline struct clk *imx_clk_gate2_shared2(const char *name, |
| 148 | const char *parent, void __iomem *reg, u8 shift, |
| 149 | unsigned int *share_count) |
| 150 | { |
| 151 | return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT | |
| 152 | CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0, |
| 153 | &imx_ccm_lock, share_count); |
| 154 | } |
| 155 | |
Dong Aisheng | 5afc994 | 2016-06-30 17:31:15 +0800 | [diff] [blame] | 156 | static inline struct clk *imx_clk_gate2_cgr(const char *name, |
| 157 | const char *parent, void __iomem *reg, u8 shift, u8 cgr_val) |
| 158 | { |
| 159 | return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, |
| 160 | shift, cgr_val, 0, &imx_ccm_lock, NULL); |
| 161 | } |
| 162 | |
Dong Aisheng | 39c2949 | 2016-06-30 17:31:16 +0800 | [diff] [blame] | 163 | static inline struct clk *imx_clk_gate3(const char *name, const char *parent, |
| 164 | void __iomem *reg, u8 shift) |
| 165 | { |
| 166 | return clk_register_gate(NULL, name, parent, |
| 167 | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, |
| 168 | reg, shift, 0, &imx_ccm_lock); |
| 169 | } |
| 170 | |
| 171 | static inline struct clk *imx_clk_gate4(const char *name, const char *parent, |
| 172 | void __iomem *reg, u8 shift) |
| 173 | { |
| 174 | return clk_register_gate2(NULL, name, parent, |
| 175 | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, |
| 176 | reg, shift, 0x3, 0, &imx_ccm_lock, NULL); |
| 177 | } |
| 178 | |
Sascha Hauer | 6c7b06850 | 2012-03-07 21:01:28 +0100 | [diff] [blame] | 179 | static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, |
| 180 | u8 shift, u8 width, const char **parents, int num_parents) |
| 181 | { |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 182 | return clk_register_mux(NULL, name, parents, num_parents, |
| 183 | CLK_SET_RATE_NO_REPARENT, reg, shift, |
Sascha Hauer | 6c7b06850 | 2012-03-07 21:01:28 +0100 | [diff] [blame] | 184 | width, 0, &imx_ccm_lock); |
| 185 | } |
| 186 | |
Dong Aisheng | 39c2949 | 2016-06-30 17:31:16 +0800 | [diff] [blame] | 187 | static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg, |
| 188 | u8 shift, u8 width, const char **parents, int num_parents) |
| 189 | { |
| 190 | return clk_register_mux(NULL, name, parents, num_parents, |
| 191 | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, |
| 192 | reg, shift, width, 0, &imx_ccm_lock); |
| 193 | } |
| 194 | |
Philipp Zabel | 3ce9217 | 2013-03-27 18:30:40 +0100 | [diff] [blame] | 195 | static inline struct clk *imx_clk_mux_flags(const char *name, |
| 196 | void __iomem *reg, u8 shift, u8 width, const char **parents, |
| 197 | int num_parents, unsigned long flags) |
| 198 | { |
| 199 | return clk_register_mux(NULL, name, parents, num_parents, |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 200 | flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0, |
Philipp Zabel | 3ce9217 | 2013-03-27 18:30:40 +0100 | [diff] [blame] | 201 | &imx_ccm_lock); |
| 202 | } |
| 203 | |
Lucas Stach | e0fed51 | 2014-09-26 15:41:01 +0200 | [diff] [blame] | 204 | struct clk *imx_clk_cpu(const char *name, const char *parent_name, |
| 205 | struct clk *div, struct clk *mux, struct clk *pll, |
| 206 | struct clk *step); |
| 207 | |
Sascha Hauer | 6c7b06850 | 2012-03-07 21:01:28 +0100 | [diff] [blame] | 208 | #endif |