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gerrit-public.fairphone.software / kernel / msm-4.19 / 2cda1880f8c6b6a081ab78824d3742a229887b69 / . / arch / arm / boot / dts / tegra30-cardhu.dtsi
blob: cbf5a1ae0ca7261abb3642648a31802ac95230ed [file] [log] [blame]
Stephen Warren1bd0bd42012-10-17 16:38:21 -0600[diff] [blame]1#include "tegra30.dtsi"
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]2
Laxman Dewangan640a7af2012-08-09 16:30:38 +0530[diff] [blame]3/**
4 * This file contains common DT entry for all fab version of Cardhu.
5 * There is multiple fab version of Cardhu starting from A01 to A07.
6 * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
7 * A02 will have different sets of GPIOs for fixed regulator compare to
8 * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
9 * compatible with fab version A04. Based on Cardhu fab version, the
10 * related dts file need to be chosen like for Cardhu fab version A02,
11 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
12 * tegra30-cardhu-a04.dts.
13 * The identification of board is done in two ways, by looking the sticker
14 * on PCB and by reading board id eeprom.
15 * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
16 * number is the fab version like here it is 002 and hence fab version A02.
17 * The (downstream internal) U-Boot of Cardhu display the board-id as
18 * follows:
19 * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
20 * In this Fab version is 02 i.e. A02.
21 * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
22 * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
23 * wide.
24 */
25
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]26/ {
27 model = "NVIDIA Tegra30 Cardhu evaluation board";
28 compatible = "nvidia,cardhu", "nvidia,tegra30";
29
Stephen Warren553c0a22013-12-09 14:43:59 -0700[diff] [blame]30 aliases {
Stephen Warren763fbff2014-02-13 17:18:26 -0700[diff] [blame]31 rtc0 = "/i2c@7000d000/tps65911@2d";
Stephen Warren553c0a22013-12-09 14:43:59 -0700[diff] [blame]32 rtc1 = "/rtc@7000e000";
Olof Johanssonc4574aa2014-11-11 12:49:30 -0800[diff] [blame]33 serial0 = &uarta;
34 serial1 = &uartc;
Stephen Warren553c0a22013-12-09 14:43:59 -0700[diff] [blame]35 };
36
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]37 memory {
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]38 reg = <0x80000000 0x40000000>;
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]39 };
40
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]41 pcie-controller@00003000 {
Jay Agarwal89e7ada2013-08-09 16:49:27 +0200[diff] [blame]42 status = "okay";
Thierry Redingcca86142014-05-28 16:49:12 +0200[diff] [blame]43
44 /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */
45 avdd-pexb-supply = <&ldo1_reg>;
46 vdd-pexb-supply = <&ldo1_reg>;
47 avdd-pex-pll-supply = <&ldo1_reg>;
48 hvdd-pex-supply = <&pex_hvdd_3v3_reg>;
49 vddio-pex-ctl-supply = <&sys_3v3_reg>;
50 avdd-plle-supply = <&ldo2_reg>;
51
Jay Agarwal89e7ada2013-08-09 16:49:27 +0200[diff] [blame]52 pci@1,0 {
53 nvidia,num-lanes = <4>;
54 };
55
56 pci@2,0 {
57 nvidia,num-lanes = <1>;
58 };
59
60 pci@3,0 {
61 status = "okay";
62 nvidia,num-lanes = <1>;
63 };
64 };
65
Thierry Reding02b1fea2013-12-19 16:59:26 +0100[diff] [blame]66 host1x@50000000 {
67 dc@54200000 {
68 rgb {
69 status = "okay";
70
71 nvidia,panel = <&panel>;
72 };
73 };
74 };
75
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]76 pinmux@70000868 {
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]77 pinctrl-names = "default";
78 pinctrl-0 = <&state_default>;
79
80 state_default: pinmux {
81 sdmmc1_clk_pz0 {
82 nvidia,pins = "sdmmc1_clk_pz0";
83 nvidia,function = "sdmmc1";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]84 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
85 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]86 };
87 sdmmc1_cmd_pz1 {
88 nvidia,pins = "sdmmc1_cmd_pz1",
89 "sdmmc1_dat0_py7",
90 "sdmmc1_dat1_py6",
91 "sdmmc1_dat2_py5",
92 "sdmmc1_dat3_py4";
93 nvidia,function = "sdmmc1";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]94 nvidia,pull = <TEGRA_PIN_PULL_UP>;
95 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]96 };
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]97 sdmmc3_clk_pa6 {
98 nvidia,pins = "sdmmc3_clk_pa6";
99 nvidia,function = "sdmmc3";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]100 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
101 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]102 };
103 sdmmc3_cmd_pa7 {
104 nvidia,pins = "sdmmc3_cmd_pa7",
105 "sdmmc3_dat0_pb7",
106 "sdmmc3_dat1_pb6",
107 "sdmmc3_dat2_pb5",
108 "sdmmc3_dat3_pb4";
109 nvidia,function = "sdmmc3";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]110 nvidia,pull = <TEGRA_PIN_PULL_UP>;
111 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]112 };
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]113 sdmmc4_clk_pcc4 {
114 nvidia,pins = "sdmmc4_clk_pcc4",
115 "sdmmc4_rst_n_pcc3";
116 nvidia,function = "sdmmc4";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]117 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
118 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]119 };
120 sdmmc4_dat0_paa0 {
121 nvidia,pins = "sdmmc4_dat0_paa0",
122 "sdmmc4_dat1_paa1",
123 "sdmmc4_dat2_paa2",
124 "sdmmc4_dat3_paa3",
125 "sdmmc4_dat4_paa4",
126 "sdmmc4_dat5_paa5",
127 "sdmmc4_dat6_paa6",
128 "sdmmc4_dat7_paa7";
129 nvidia,function = "sdmmc4";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]130 nvidia,pull = <TEGRA_PIN_PULL_UP>;
131 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]132 };
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]133 dap2_fs_pa2 {
134 nvidia,pins = "dap2_fs_pa2",
135 "dap2_sclk_pa3",
136 "dap2_din_pa4",
137 "dap2_dout_pa5";
138 nvidia,function = "i2s1";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]139 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
140 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]141 };
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]142 sdio3 {
143 nvidia,pins = "drive_sdio3";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]144 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
145 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]146 nvidia,pull-down-strength = <46>;
147 nvidia,pull-up-strength = <42>;
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]148 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
149 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]150 };
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]151 uart3_txd_pw6 {
152 nvidia,pins = "uart3_txd_pw6",
153 "uart3_cts_n_pa1",
154 "uart3_rts_n_pc0",
155 "uart3_rxd_pw7";
156 nvidia,function = "uartc";
Laxman Dewangana47c6622013-12-05 16:14:09 +0530[diff] [blame]157 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
158 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]159 };
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]160 };
161 };
162
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]163 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]164 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]165 };
166
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]167 serial@70006200 {
168 compatible = "nvidia,tegra30-hsuart";
169 status = "okay";
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame]170 };
171
Thierry Reding02b1fea2013-12-19 16:59:26 +0100[diff] [blame]172 pwm@7000a000 {
173 status = "okay";
174 };
175
176 panelddc: i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]177 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]178 clock-frequency = <100000>;
179 };
180
181 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]182 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]183 clock-frequency = <100000>;
184 };
185
186 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]187 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]188 clock-frequency = <100000>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530[diff] [blame]189
190 /* ALS and Proximity sensor */
191 isl29028@44 {
Darshana Padmadased200bf2014-11-08 22:52:08 +0530[diff] [blame]192 compatible = "isl,isl29028";
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530[diff] [blame]193 reg = <0x44>;
194 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]195 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530[diff] [blame]196 };
Bryan Wu40431d12014-02-07 15:54:58 -0800[diff] [blame]197
198 i2cmux@70 {
199 compatible = "nxp,pca9546";
200 #address-cells = <1>;
201 #size-cells = <0>;
202 reg = <0x70>;
203 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]204 };
205
206 i2c@7000c700 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]207 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]208 clock-frequency = <100000>;
209 };
210
211 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]212 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]213 clock-frequency = <100000>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]214
215 wm8903: wm8903@1a {
216 compatible = "wlf,wm8903";
217 reg = <0x1a>;
218 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]219 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]220
221 gpio-controller;
222 #gpio-cells = <2>;
223
224 micdet-cfg = <0>;
225 micdet-delay = <100>;
226 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
227 };
Laxman Dewangan331da582012-05-10 20:38:45 +0000[diff] [blame]228
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]229 pmic: tps65911@2d {
230 compatible = "ti,tps65911";
231 reg = <0x2d>;
232
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]233 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]234 #interrupt-cells = <2>;
235 interrupt-controller;
236
Stephen Warren44b12ef2012-09-11 11:42:26 -0600[diff] [blame]237 ti,system-power-controller;
238
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]239 #gpio-cells = <2>;
240 gpio-controller;
241
242 vcc1-supply = <&vdd_ac_bat_reg>;
243 vcc2-supply = <&vdd_ac_bat_reg>;
244 vcc3-supply = <&vio_reg>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]245 vcc4-supply = <&vdd_5v0_reg>;
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]246 vcc5-supply = <&vdd_ac_bat_reg>;
247 vcc6-supply = <&vdd2_reg>;
248 vcc7-supply = <&vdd_ac_bat_reg>;
249 vccio-supply = <&vdd_ac_bat_reg>;
250
251 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]252 vdd1_reg: vdd1 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]253 regulator-name = "vddio_ddr_1v2";
254 regulator-min-microvolt = <1200000>;
255 regulator-max-microvolt = <1200000>;
256 regulator-always-on;
257 };
258
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]259 vdd2_reg: vdd2 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]260 regulator-name = "vdd_1v5_gen";
261 regulator-min-microvolt = <1500000>;
262 regulator-max-microvolt = <1500000>;
263 regulator-always-on;
264 };
265
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]266 vddctrl_reg: vddctrl {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]267 regulator-name = "vdd_cpu,vdd_sys";
268 regulator-min-microvolt = <1000000>;
269 regulator-max-microvolt = <1000000>;
270 regulator-always-on;
271 };
272
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]273 vio_reg: vio {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]274 regulator-name = "vdd_1v8_gen";
275 regulator-min-microvolt = <1800000>;
276 regulator-max-microvolt = <1800000>;
277 regulator-always-on;
278 };
279
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]280 ldo1_reg: ldo1 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]281 regulator-name = "vdd_pexa,vdd_pexb";
282 regulator-min-microvolt = <1050000>;
283 regulator-max-microvolt = <1050000>;
284 };
285
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]286 ldo2_reg: ldo2 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]287 regulator-name = "vdd_sata,avdd_plle";
288 regulator-min-microvolt = <1050000>;
289 regulator-max-microvolt = <1050000>;
290 };
291
292 /* LDO3 is not connected to anything */
293
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]294 ldo4_reg: ldo4 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]295 regulator-name = "vdd_rtc";
296 regulator-min-microvolt = <1200000>;
297 regulator-max-microvolt = <1200000>;
298 regulator-always-on;
299 };
300
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]301 ldo5_reg: ldo5 {
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]302 regulator-name = "vddio_sdmmc,avdd_vdac";
303 regulator-min-microvolt = <3300000>;
304 regulator-max-microvolt = <3300000>;
305 regulator-always-on;
306 };
307
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]308 ldo6_reg: ldo6 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]309 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
310 regulator-min-microvolt = <1200000>;
311 regulator-max-microvolt = <1200000>;
312 };
313
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]314 ldo7_reg: ldo7 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]315 regulator-name = "vdd_pllm,x,u,a_p_c_s";
316 regulator-min-microvolt = <1200000>;
317 regulator-max-microvolt = <1200000>;
318 regulator-always-on;
319 };
320
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]321 ldo8_reg: ldo8 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]322 regulator-name = "vdd_ddr_hs";
323 regulator-min-microvolt = <1000000>;
324 regulator-max-microvolt = <1000000>;
325 regulator-always-on;
326 };
327 };
328 };
Wei Ni74ecab22013-07-12 15:49:23 +0800[diff] [blame]329
Wei Ni7c7de6b2013-10-07 17:28:29 +0800[diff] [blame]330 temperature-sensor@4c {
Wei Ni74ecab22013-07-12 15:49:23 +0800[diff] [blame]331 compatible = "onnn,nct1008";
332 reg = <0x4c>;
Wei Ni7c7de6b2013-10-07 17:28:29 +0800[diff] [blame]333 vcc-supply = <&sys_3v3_reg>;
Wei Ni74ecab22013-07-12 15:49:23 +0800[diff] [blame]334 interrupt-parent = <&gpio>;
335 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
336 };
Stephen Warren2b8584d2013-07-15 10:33:53 -0600[diff] [blame]337
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]338 tps62361@60 {
Stephen Warren2b8584d2013-07-15 10:33:53 -0600[diff] [blame]339 compatible = "ti,tps62361";
340 reg = <0x60>;
341
342 regulator-name = "tps62361-vout";
343 regulator-min-microvolt = <500000>;
344 regulator-max-microvolt = <1500000>;
345 regulator-boot-on;
346 regulator-always-on;
347 ti,vsel0-state-high;
348 ti,vsel1-state-high;
349 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]350 };
Stephen Warren850c4c82012-02-01 16:29:57 -0700[diff] [blame]351
Laxman Dewanganc42cb1c2012-10-31 14:32:54 +0530[diff] [blame]352 spi@7000da00 {
353 status = "okay";
354 spi-max-frequency = <25000000>;
355 spi-flash@1 {
356 compatible = "winbond,w25q32";
357 reg = <1>;
358 spi-max-frequency = <20000000>;
359 };
360 };
361
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]362 pmc@7000e400 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]363 status = "okay";
364 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800[diff] [blame]365 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800[diff] [blame]366 nvidia,cpu-pwr-good-time = <2000>;
367 nvidia,cpu-pwr-off-time = <200>;
368 nvidia,core-pwr-good-time = <3845 3845>;
369 nvidia,core-pwr-off-time = <0>;
370 nvidia,core-power-req-active-high;
371 nvidia,sys-clock-req-active-high;
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]372 };
373
Stephen Warren57899052013-11-26 14:43:45 -0700[diff] [blame]374 ahub@70080000 {
375 i2s@70080400 {
376 status = "okay";
377 };
378 };
379
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]380 sdhci@78000000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]381 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]382 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
383 wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
384 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
Arnd Bergmann7f217792012-05-13 00:14:24 -0400[diff] [blame]385 bus-width = <4>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]386 };
387
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]388 sdhci@78000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]389 status = "okay";
Arnd Bergmann7f217792012-05-13 00:14:24 -0400[diff] [blame]390 bus-width = <8>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600[diff] [blame]391 non-removable;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]392 };
393
Tuomas Tynkkynencc34c9f2013-08-01 18:00:17 +0300[diff] [blame]394 usb@7d008000 {
395 status = "okay";
396 };
397
398 usb-phy@7d008000 {
399 vbus-supply = <&usb3_vbus_reg>;
400 status = "okay";
401 };
402
Thierry Reding02b1fea2013-12-19 16:59:26 +0100[diff] [blame]403 backlight: backlight {
404 compatible = "pwm-backlight";
405
406 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
407 power-supply = <&vdd_bl_reg>;
408 pwms = <&pwm 0 5000000>;
409
410 brightness-levels = <0 4 8 16 32 64 128 255>;
411 default-brightness-level = <6>;
412 };
413
Joseph Lo7021d122013-04-03 19:31:27 +0800[diff] [blame]414 clocks {
415 compatible = "simple-bus";
416 #address-cells = <1>;
417 #size-cells = <0>;
418
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]419 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800[diff] [blame]420 compatible = "fixed-clock";
421 reg=<0>;
422 #clock-cells = <0>;
423 clock-frequency = <32768>;
424 };
425 };
426
Thierry Reding02b1fea2013-12-19 16:59:26 +0100[diff] [blame]427 panel: panel {
428 compatible = "chunghwa,claa101wb01", "simple-panel";
429 ddc-i2c-bus = <&panelddc>;
430
431 power-supply = <&vdd_pnl1_reg>;
432 enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>;
433
434 backlight = <&backlight>;
435 };
436
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]437 regulators {
438 compatible = "simple-bus";
439 #address-cells = <1>;
440 #size-cells = <0>;
441
442 vdd_ac_bat_reg: regulator@0 {
443 compatible = "regulator-fixed";
444 reg = <0>;
445 regulator-name = "vdd_ac_bat";
446 regulator-min-microvolt = <5000000>;
447 regulator-max-microvolt = <5000000>;
448 regulator-always-on;
449 };
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]450
451 cam_1v8_reg: regulator@1 {
452 compatible = "regulator-fixed";
453 reg = <1>;
454 regulator-name = "cam_1v8";
455 regulator-min-microvolt = <1800000>;
456 regulator-max-microvolt = <1800000>;
457 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]458 gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]459 vin-supply = <&vio_reg>;
460 };
461
462 cp_5v_reg: regulator@2 {
463 compatible = "regulator-fixed";
464 reg = <2>;
465 regulator-name = "cp_5v";
466 regulator-min-microvolt = <5000000>;
467 regulator-max-microvolt = <5000000>;
468 regulator-boot-on;
469 regulator-always-on;
470 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]471 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]472 };
473
474 emmc_3v3_reg: regulator@3 {
475 compatible = "regulator-fixed";
476 reg = <3>;
477 regulator-name = "emmc_3v3";
478 regulator-min-microvolt = <3300000>;
479 regulator-max-microvolt = <3300000>;
480 regulator-always-on;
481 regulator-boot-on;
482 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]483 gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]484 vin-supply = <&sys_3v3_reg>;
485 };
486
487 modem_3v3_reg: regulator@4 {
488 compatible = "regulator-fixed";
489 reg = <4>;
490 regulator-name = "modem_3v3";
491 regulator-min-microvolt = <3300000>;
492 regulator-max-microvolt = <3300000>;
493 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]494 gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]495 };
496
497 pex_hvdd_3v3_reg: regulator@5 {
498 compatible = "regulator-fixed";
499 reg = <5>;
500 regulator-name = "pex_hvdd_3v3";
501 regulator-min-microvolt = <3300000>;
502 regulator-max-microvolt = <3300000>;
503 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]504 gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]505 vin-supply = <&sys_3v3_reg>;
506 };
507
508 vdd_cam1_ldo_reg: regulator@6 {
509 compatible = "regulator-fixed";
510 reg = <6>;
511 regulator-name = "vdd_cam1_ldo";
512 regulator-min-microvolt = <2800000>;
513 regulator-max-microvolt = <2800000>;
514 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]515 gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]516 vin-supply = <&sys_3v3_reg>;
517 };
518
519 vdd_cam2_ldo_reg: regulator@7 {
520 compatible = "regulator-fixed";
521 reg = <7>;
522 regulator-name = "vdd_cam2_ldo";
523 regulator-min-microvolt = <2800000>;
524 regulator-max-microvolt = <2800000>;
525 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]526 gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]527 vin-supply = <&sys_3v3_reg>;
528 };
529
530 vdd_cam3_ldo_reg: regulator@8 {
531 compatible = "regulator-fixed";
532 reg = <8>;
533 regulator-name = "vdd_cam3_ldo";
534 regulator-min-microvolt = <3300000>;
535 regulator-max-microvolt = <3300000>;
536 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]537 gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]538 vin-supply = <&sys_3v3_reg>;
539 };
540
541 vdd_com_reg: regulator@9 {
542 compatible = "regulator-fixed";
543 reg = <9>;
544 regulator-name = "vdd_com";
545 regulator-min-microvolt = <3300000>;
546 regulator-max-microvolt = <3300000>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]547 regulator-always-on;
548 regulator-boot-on;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]549 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]550 gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]551 vin-supply = <&sys_3v3_reg>;
552 };
553
554 vdd_fuse_3v3_reg: regulator@10 {
555 compatible = "regulator-fixed";
556 reg = <10>;
557 regulator-name = "vdd_fuse_3v3";
558 regulator-min-microvolt = <3300000>;
559 regulator-max-microvolt = <3300000>;
560 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]561 gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]562 vin-supply = <&sys_3v3_reg>;
563 };
564
565 vdd_pnl1_reg: regulator@11 {
566 compatible = "regulator-fixed";
567 reg = <11>;
568 regulator-name = "vdd_pnl1";
569 regulator-min-microvolt = <3300000>;
570 regulator-max-microvolt = <3300000>;
571 regulator-always-on;
572 regulator-boot-on;
573 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]574 gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]575 vin-supply = <&sys_3v3_reg>;
576 };
577
578 vdd_vid_reg: regulator@12 {
579 compatible = "regulator-fixed";
580 reg = <12>;
581 regulator-name = "vddio_vid";
582 regulator-min-microvolt = <5000000>;
583 regulator-max-microvolt = <5000000>;
584 enable-active-high;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]585 gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]586 gpio-open-drain;
587 vin-supply = <&vdd_5v0_reg>;
588 };
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]589 };
590
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]591 sound {
592 compatible = "nvidia,tegra-audio-wm8903-cardhu",
593 "nvidia,tegra-audio-wm8903";
594 nvidia,model = "NVIDIA Tegra Cardhu";
595
596 nvidia,audio-routing =
597 "Headphone Jack", "HPOUTR",
598 "Headphone Jack", "HPOUTL",
599 "Int Spk", "ROP",
600 "Int Spk", "RON",
601 "Int Spk", "LOP",
602 "Int Spk", "LON",
603 "Mic Jack", "MICBIAS",
604 "IN1L", "Mic Jack";
605
606 nvidia,i2s-controller = <&tegra_i2s1>;
607 nvidia,audio-codec = <&wm8903>;
608
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]609 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
610 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
611 GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]612
Hiroshi Doyu05849c92013-05-22 19:45:34 +0300[diff] [blame]613 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
614 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
615 <&tegra_car TEGRA30_CLK_EXTERN1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]616 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]617 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]618};