arch/arm64/boot/dts/qcom/kona.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
 */

#include "skeleton64.dtsi"

#include <dt-bindings/clock/qcom,aop-qmp.h>
#include <dt-bindings/clock/qcom,camcc-kona.h>
#include <dt-bindings/clock/qcom,cpucc-kona.h>
#include <dt-bindings/clock/qcom,dispcc-kona.h>
#include <dt-bindings/clock/qcom,gcc-kona.h>
#include <dt-bindings/clock/qcom,gpucc-kona.h>
#include <dt-bindings/clock/qcom,npucc-kona.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-kona.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/msm/msm-bus-ids.h>
#include <dt-bindings/soc/qcom,ipcc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/gpio/gpio.h>

#include "kona-regulators.dtsi"

/ {
	model = "Qualcomm Technologies, Inc. kona";
	compatible = "qcom,kona";
	qcom,msm-id = <356 0x10000>;
	interrupt-parent = <&intc>;

	aliases {
		ufshc1 = &ufshc_mem; /* Embedded UFS slot */
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x0>;
			enable-method = "spin-table";
			cache-size = <0x8000>;
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_0>;
			qcom,freq-domain = <&cpufreq_hw 0 4>;
			L2_0: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x20000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;

				L3_0: l3-cache {
				      compatible = "arm,arch-cache";
				      cache-size = <0x400000>;
				      cache-level = <3>;
				};
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x100>;
			enable-method = "spin-table";
			cache-size = <0x8000>;
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_1>;
			qcom,freq-domain = <&cpufreq_hw 0 4>;
			L2_1: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x20000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x200>;
			enable-method = "spin-table";
			cache-size = <0x8000>;
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_2>;
			qcom,freq-domain = <&cpufreq_hw 0 4>;
			L2_2: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x20000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x300>;
			enable-method = "spin-table";
			cache-size = <0x8000>;
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_3>;
			qcom,freq-domain = <&cpufreq_hw 0 4>;
			L2_3: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x20000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU4: cpu@400 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x400>;
			enable-method = "spin-table";
			cache-size = <0x10000>;
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_4>;
			qcom,freq-domain = <&cpufreq_hw 1 4>;
			L2_4: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x20000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU5: cpu@500 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x500>;
			enable-method = "spin-table";
			cache-size = <0x10000>;
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_5>;
			qcom,freq-domain = <&cpufreq_hw 1 4>;
			L2_5: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x20000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU6: cpu@600 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x600>;
			enable-method = "spin-table";
			cache-size = <0x10000>;
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_6>;
			qcom,freq-domain = <&cpufreq_hw 1 4>;
			L2_6: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x20000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU7: cpu@700 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x700>;
			enable-method = "spin-table";
			cache-size = <0x10000>;
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_7>;
			qcom,freq-domain = <&cpufreq_hw 2 4>;
			L2_7: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x80000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU4>;
				};

				core1 {
					cpu = <&CPU5>;
				};

				core2 {
					cpu = <&CPU6>;
				};

				core3 {
					cpu = <&CPU7>;
				};
			};
		};
	};


	cpu_pmu: cpu-pmu {
		compatible = "arm,armv8-pmuv3";
		qcom,irq-is-percpu;
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	soc: soc {
		cpufreq_hw: qcom,cpufreq-hw {
			compatible = "qcom,cpufreq-hw";
			reg = <0x18591000 0x1000>, <0x18592000 0x1000>,
				<0x18593000 0x1000>;
			reg-names = "freq-domain0", "freq-domain1",
				"freq-domain2";

			clocks = <&clock_xo>, <&clock_gcc GPLL0>;
			clock-names = "xo", "cpu_clk";

			#freq-domain-cells = <2>;
		};
	};

	firmware: firmware {
		android {
			compatible = "android,firmware";
			fstab {
				compatible = "android,fstab";
				vendor {
					compatible = "android,vendor";
					dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
					type = "ext4";
					mnt_flags = "ro,barrier=1,discard";
					fsmgr_flags = "wait,slotselect,avb";
					status = "ok";
				};
			};
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		hyp_mem: hyp_region@80000000 {
			no-map;
			reg = <0x0 0x80000000 0x0 0x600000>;
		};

		xbl_aop_mem: xbl_aop_region@80700000 {
			no-map;
			reg = <0x0 0x80700000 0x0 0x140000>;
		};

		cmd_db: reserved-memory@80820000 {
			reg = <0x0 0x80820000 0x0 0x20000>;
			compatible = "qcom,cmd-db";
			no-map;
		};

		smem_mem: smem_region@80900000 {
			no-map;
			reg = <0x0 0x80900000 0x0 0x200000>;
		};

		removed_mem: removed_region@80b00000 {
			no-map;
			reg = <0x0 0x80b00000 0x0 0xc00000>;
		};

		qtee_apps_mem: qtee_apps_region@81e00000 {
			no-map;
			reg = <0x0 0x81e00000 0x0 0x2600000>;
		};

		pil_camera_mem: pil_camera_region@86000000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x86000000 0x0 0x500000>;
		};

		pil_wlan_fw_mem: pil_wlan_fw_region@86500000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x86500000 0x0 0x100000>;
		};

		pil_ipa_fw_mem: pil_ipa_fw_region@86600000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x86600000 0x0 0x10000>;
		};

		pil_ipa_gsi_mem: pil_ipa_gsi_region@86610000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x86610000 0x0 0x5000>;
		};

		pil_gpu_mem: pil_gpu_region@86615000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x86615000 0x0 0x2000>;
		};

		pil_npu_mem: pil_npu_region@86680000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x86680000 0x0 0x80000>;
		};

		pil_video_mem: pil_video_region@86700000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x86700000 0x0 0x500000>;
		};

		pil_cvp_mem: pil_cvp_region@86c00000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x86c00000 0x0 0x500000>;
		};

		pil_cdsp_mem: pil_cdsp_region@87100000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x87100000 0x0 0x800000>;
		};

		pil_slpi_mem: pil_slpi_region@87900000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x87900000 0x0 0x1400000>;
		};

		pil_adsp_mem: pil_adsp_region@88d00000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x88d00000 0x0 0x1a00000>;
		};

		pil_spss_mem: pil_spss_region@8a700000 {
			compatible = "removed-dma-pool";
			no-map;
			reg = <0x0 0x8a700000 0x0 0x100000>;
		};

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
			reusable;
			alignment = <0x0 0x400000>;
			size = <0x0 0x2000000>;
			linux,cma-default;
		};
	};
};

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	intc: interrupt-controller@17a00000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-controller;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x20000>;
		reg = <0x17a00000 0x10000>,     /* GICD */
		      <0x17a60000 0x100000>;    /* GICR * 8 */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	qcom,chd_silver {
		compatible = "qcom,core-hang-detect";
		label = "silver";
		qcom,threshold-arr = <0x18000058 0x18010058
		0x18020058 0x18030058>;
		qcom,config-arr = <0x18000060 0x18010060
		0x18020060 0x18030060>;
	};

	qcom,chd_gold {
		compatible = "qcom,core-hang-detect";
		label = "gold";
		qcom,threshold-arr = <0x18040058 0x18050058
		0x18060058 0x18070058>;
		qcom,config-arr = <0x18040060 0x18050060
		0x18060060 0x18070060>;
	};

	cache-controller@9200000 {
		compatible = "qcom,kona-llcc";
		reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>;
		reg-names = "llcc_base", "llcc_broadcast_base";
		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
	};

	arch_timer: timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <19200000>;
	};

	memtimer: timer@17c20000 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0x17c20000 0x1000>;
		clock-frequency = <19200000>;

		frame@17c21000 {
			frame-number = <0>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c21000 0x1000>,
			      <0x17c22000 0x1000>;
		};

		frame@17c23000 {
			frame-number = <1>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c23000 0x1000>;
			status = "disabled";
		};

		frame@17c25000 {
			frame-number = <2>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c25000 0x1000>;
			status = "disabled";
		};

		frame@17c27000 {
			frame-number = <3>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c27000 0x1000>;
			status = "disabled";
		};

		frame@17c29000 {
			frame-number = <4>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c29000 0x1000>;
			status = "disabled";
		};

		frame@17c2b000 {
			frame-number = <5>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c2b000 0x1000>;
			status = "disabled";
		};

		frame@17c2d000 {
			frame-number = <6>;
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c2d000 0x1000>;
			status = "disabled";
		};
	};

	qcom,devfreq-l3 {
		compatible = "qcom,devfreq-fw";
		reg = <0x18590000 0x4>, <0x18590100 0xa0>, <0x18590320 0x4>;
		reg-names = "en-base", "ftbl-base", "perf-base";

		qcom,cpu0-l3 {
			compatible = "qcom,devfreq-fw-voter";
		};

		qcom,cpu4-l3 {
			compatible = "qcom,devfreq-fw-voter";
		};
	};

	qcom,msm-imem@146bf000 {
		compatible = "qcom,msm-imem";
		reg = <0x146bf000 0x1000>;
		ranges = <0x0 0x146bf000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		restart_reason@65c {
			compatible = "qcom,msm-imem-restart_reason";
			reg = <0x65c 0x4>;
		};

		dload_type@1c {
			compatible = "qcom,msm-imem-dload-type";
			reg = <0x1c 0x4>;
		};

		boot_stats@6b0 {
			compatible = "qcom,msm-imem-boot_stats";
			reg = <0x6b0 0x20>;
		};

		kaslr_offset@6d0 {
			compatible = "qcom,msm-imem-kaslr_offset";
			reg = <0x6d0 0xc>;
		};

		pil@94c {
			compatible = "qcom,msm-imem-pil";
			reg = <0x94c 0xc8>;
		};
	};

	mdm0: qcom,mdm0 {
		compatible = "qcom,ext-sdx50m";
		cell-index = <0>;
		#address-cells = <0>;
		interrupt-parent = <&mdm0>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xffffffff>;
		interrupt-names =
			"err_fatal_irq",
			"status_irq",
			"mdm2ap_vddmin_irq";
		/* modem attributes */
		qcom,ramdump-delay-ms = <3000>;
		qcom,ramdump-timeout-ms = <120000>;
		qcom,vddmin-modes = "normal";
		qcom,vddmin-drive-strength = <8>;
		qcom,sfr-query;
		qcom,sysmon-id = <20>;
		qcom,ssctl-instance-id = <0x10>;
		qcom,support-shutdown;
		qcom,pil-force-shutdown;
		qcom,esoc-skip-restart-for-mdm-crash;
		pinctrl-names = "default", "mdm_active", "mdm_suspend";
		pinctrl-0 = <&ap2mdm_pon_reset_default>;
		pinctrl-1 = <&ap2mdm_active &mdm2ap_active>;
		pinctrl-2 = <&ap2mdm_sleep &mdm2ap_sleep>;
		interrupt-map = <0 &tlmm 1 0x3
				1 &tlmm 3 0x3>;
		qcom,mdm2ap-errfatal-gpio = <&tlmm 1 0x00>;
		qcom,ap2mdm-errfatal-gpio = <&tlmm 57 0x00>;
		qcom,mdm2ap-status-gpio   = <&tlmm 3 0x00>;
		qcom,ap2mdm-status-gpio   = <&tlmm 56 0x00>;
		qcom,ap2mdm-soft-reset-gpio = <&tlmm 145 GPIO_ACTIVE_LOW>;
		qcom,mdm-link-info = "0306_02.01.00";
		status = "ok";
	};

	pdc: interrupt-controller@b220000 {
		compatible = "qcom,kona-pdc";
		reg = <0xb220000 0x30000>;
		qcom,pdc-ranges = <0 480 29>, <42 522 52>, <94 609 30>;
		#interrupt-cells = <2>;
		interrupt-parent = <&intc>;
		interrupt-controller;
	};

	clock_xo: bi_tcxo {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <19200000>;
		clock-output-names = "bi_tcxo";
	};

	clocks {
		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			clock-frequency = <32000>;
			clock-output-names = "chip_sleep_clk";
			#clock-cells = <1>;
		};
	};

	clock_rpmh: qcom,rpmhclk {
		compatible = "qcom,dummycc";
		clock-output-names = "rpmh_clocks";
		#clock-cells = <1>;
	};

	clock_aop: qcom,aopclk {
		compatible = "qcom,dummycc";
		clock-output-names = "qdss_clocks";
		#clock-cells = <1>;
	};

	clock_gcc: qcom,gcc@100000 {
		compatible = "qcom,gcc-kona";
		reg = <0x100000 0x1f0000>;
		reg-names = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
		vdd_mm-supply = <&VDD_MMCX_LEVEL>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	clock_npucc: qcom,npucc {
		compatible = "qcom,dummycc";
		clock-output-names = "npucc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	clock_videocc: qcom,videocc@abf0000 {
		compatible = "qcom,videocc-kona", "syscon";
		reg = <0xabf0000 0x10000>;
		reg-names = "cc_base";
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		vdd_mm-supply = <&VDD_MMCX_LEVEL>;
		clock-names = "cfg_ahb_clk";
		clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	clock_camcc: qcom,camcc {
		compatible = "qcom,dummycc";
		clock-output-names = "camcc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	clock_dispcc: qcom,dispcc {
		compatible = "qcom,dummycc";
		clock-output-names = "dispcc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	clock_gpucc: qcom,gpucc {
		compatible = "qcom,dummycc";
		clock-output-names = "gpucc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	clock_cpucc: qcom,cpucc {
		compatible = "qcom,dummycc";
		clock-output-names = "cpucc_clocks";
		#clock-cells = <1>;
	};

	/* GCC GDSCs */
	pcie_0_gdsc: qcom,gdsc@16b004 {
		compatible = "qcom,gdsc";
		reg = <0x16b004 0x4>;
		regulator-name = "pcie_0_gdsc";
	};

	pcie_1_gdsc: qcom,gdsc@18d004 {
		compatible = "qcom,gdsc";
		reg = <0x18d004 0x4>;
		regulator-name = "pcie_1_gdsc";
	};

	pcie_2_gdsc: qcom,gdsc@106004 {
		compatible = "qcom,gdsc";
		reg = <0x106004 0x4>;
		regulator-name = "pcie_2_gdsc";
	};

	ufs_card_gdsc: qcom,gdsc@175004 {
		compatible = "qcom,gdsc";
		reg = <0x175004 0x4>;
		regulator-name = "ufs_card_gdsc";
	};

	ufs_phy_gdsc: qcom,gdsc@177004 {
		compatible = "qcom,gdsc";
		reg = <0x177004 0x4>;
		regulator-name = "ufs_phy_gdsc";
	};

	usb30_prim_gdsc: qcom,gdsc@10f004 {
		compatible = "qcom,gdsc";
		reg = <0x10f004 0x4>;
		regulator-name = "usb30_prim_gdsc";
	};

	usb30_sec_gdsc: qcom,gdsc@110004 {
		compatible = "qcom,gdsc";
		reg = <0x110004 0x4>;
		regulator-name = "usb30_sec_gdsc";
	};

	hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 {
		compatible = "qcom,gdsc";
		reg = <0x17d050 0x4>;
		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
	};

	hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 {
		compatible = "qcom,gdsc";
		reg = <0x17d058 0x4>;
		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
	};

	hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc: qcom,gdsc@17d054 {
		compatible = "qcom,gdsc";
		reg = <0x17d054 0x4>;
		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc";
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
	};

	hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc: qcom,gdsc@17d06c {
		compatible = "qcom,gdsc";
		reg = <0x17d06c 0x4>;
		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc";
		qcom,no-status-check-on-disable;
		qcom,gds-timeout = <500>;
	};

	/* CAM_CC GDSCs */
	bps_gdsc: qcom,gdsc@ad07004 {
		compatible = "qcom,gdsc";
		reg = <0xad07004 0x4>;
		regulator-name = "bps_gdsc";
		clock-names = "ahb_clk";
		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
		parent-supply = <&VDD_MMCX_LEVEL>;
		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
		qcom,support-hw-trigger;
	};

	ife_0_gdsc: qcom,gdsc@ad0a004 {
		compatible = "qcom,gdsc";
		reg = <0xad0a004 0x4>;
		regulator-name = "ife_0_gdsc";
		clock-names = "ahb_clk";
		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
		parent-supply = <&VDD_MMCX_LEVEL>;
		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
	};

	ife_1_gdsc: qcom,gdsc@ad0b004 {
		compatible = "qcom,gdsc";
		reg = <0xad0b004 0x4>;
		regulator-name = "ife_1_gdsc";
		clock-names = "ahb_clk";
		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
		parent-supply = <&VDD_MMCX_LEVEL>;
		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
	};

	ipe_0_gdsc: qcom,gdsc@ad08004 {
		compatible = "qcom,gdsc";
		reg = <0xad08004 0x4>;
		regulator-name = "ipe_0_gdsc";
		clock-names = "ahb_clk";
		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
		parent-supply = <&VDD_MMCX_LEVEL>;
		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
		qcom,support-hw-trigger;
	};

	sbi_gdsc: qcom,gdsc@ad09004 {
		compatible = "qcom,gdsc";
		reg = <0xad09004 0x4>;
		regulator-name = "sbi_gdsc";
		clock-names = "ahb_clk";
		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
		parent-supply = <&VDD_MMCX_LEVEL>;
		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
	};

	titan_top_gdsc: qcom,gdsc@ad0c144 {
		compatible = "qcom,gdsc";
		reg = <0xad0c144 0x4>;
		regulator-name = "titan_top_gdsc";
		clock-names = "ahb_clk";
		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
		parent-supply = <&VDD_MMCX_LEVEL>;
		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
	};

	/* DISP_CC GDSC */
	mdss_core_gdsc: qcom,gdsc@af03000 {
		compatible = "qcom,gdsc";
		reg = <0xaf03000 0x4>;
		regulator-name = "mdss_core_gdsc";
		clock-names = "ahb_clk";
		clocks = <&clock_gcc GCC_DISP_AHB_CLK>;
		parent-supply = <&VDD_MMCX_LEVEL>;
		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
		qcom,support-hw-trigger;
	};

	/* GPU_CC GDSCs */
	gpu_cx_hw_ctrl: syscon@3d91540 {
		compatible = "syscon";
		reg = <0x3d91540 0x4>;
	};

	gpu_cx_gdsc: qcom,gdsc@3d9106c {
		compatible = "qcom,gdsc";
		reg = <0x3d9106c 0x4>;
		regulator-name = "gpu_cx_gdsc";
		hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
		parent-supply = <&VDD_CX_LEVEL>;
		qcom,no-status-check-on-disable;
		qcom,clk-dis-wait-val = <8>;
		qcom,gds-timeout = <500>;
	};

	gpu_gx_domain_addr: syscon@3d91508 {
		compatible = "syscon";
		reg = <0x3d91508 0x4>;
	};

	gpu_gx_sw_reset: syscon@3d91008 {
		compatible = "syscon";
		reg = <0x3d91008 0x4>;
	};

	gpu_gx_gdsc: qcom,gdsc@3d9100c {
		compatible = "qcom,gdsc";
		reg = <0x3d9100c 0x4>;
		regulator-name = "gpu_gx_gdsc";
		domain-addr = <&gpu_gx_domain_addr>;
		sw-reset = <&gpu_gx_sw_reset>;
		parent-supply = <&VDD_GFX_LEVEL>;
		vdd_parent-supply = <&VDD_GFX_LEVEL>;
		qcom,reset-aon-logic;
	};

	/* NPU GDSC */
	npu_core_gdsc: qcom,gdsc@9981004 {
		compatible = "qcom,gdsc";
		reg = <0x9981004 0x4>;
		regulator-name = "npu_core_gdsc";
		clock-names = "ahb_clk";
		clocks = <&clock_gcc GCC_NPU_CFG_AHB_CLK>;
	};

	/* VIDEO_CC GDSCs */
	mvs0_gdsc: qcom,gdsc@abf0d18 {
		compatible = "qcom,gdsc";
		reg = <0xabf0d18 0x4>;
		regulator-name = "mvs0_gdsc";
		clock-names = "ahb_clk";
		clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
		parent-supply = <&VDD_MMCX_LEVEL>;
		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
	};

	mvs0c_gdsc: qcom,gdsc@abf0bf8 {
		compatible = "qcom,gdsc";
		reg = <0xabf0bf8 0x4>;
		regulator-name = "mvs0c_gdsc";
		clock-names = "ahb_clk";
		clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
		parent-supply = <&VDD_MMCX_LEVEL>;
		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
	};

	mvs1_gdsc: qcom,gdsc@abf0d98 {
		compatible = "qcom,gdsc";
		reg = <0xabf0d98 0x4>;
		regulator-name = "mvs1_gdsc";
		clock-names = "ahb_clk";
		clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
		parent-supply = <&VDD_MMCX_LEVEL>;
		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
	};

	mvs1c_gdsc: qcom,gdsc@abf0c98 {
		compatible = "qcom,gdsc";
		reg = <0xabf0c98 0x4>;
		regulator-name = "mvs1c_gdsc";
		clock-names = "ahb_clk";
		clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
		parent-supply = <&VDD_MMCX_LEVEL>;
		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
	};

	ufsphy_mem: ufsphy_mem@1d87000 {
		reg = <0x1d87000 0xe00>; /* PHY regs */
		reg-names = "phy_mem";
		#phy-cells = <0>;

		lanes-per-direction = <2>;

		clock-names = "ref_clk_src",
			"ref_clk",
			"ref_aux_clk";
		clocks = <&clock_rpmh RPMH_CXO_CLK>,
			<&clock_gcc GCC_UFS_1X_CLKREF_EN>,
			<&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>;

		status = "disabled";
	};

	ufshc_mem: ufshc@1d84000 {
		compatible = "qcom,ufshc";
		reg = <0x1d84000 0x3000>;
		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
		phys = <&ufsphy_mem>;
		phy-names = "ufsphy";

		lanes-per-direction = <2>;
		dev-ref-clk-freq = <0>; /* 19.2 MHz */

		clock-names =
			"core_clk",
			"bus_aggr_clk",
			"iface_clk",
			"core_clk_unipro",
			"core_clk_ice",
			"ref_clk",
			"tx_lane0_sync_clk",
			"rx_lane0_sync_clk",
			"rx_lane1_sync_clk";
		clocks =
			<&clock_gcc GCC_UFS_PHY_AXI_CLK>,
			<&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
			<&clock_gcc GCC_UFS_PHY_AHB_CLK>,
			<&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
			<&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>,
			<&clock_rpmh RPMH_CXO_CLK>,
			<&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
		freq-table-hz =
			<37500000 300000000>,
			<0 0>,
			<0 0>,
			<37500000 300000000>,
			<75000000 300000000>,
			<0 0>,
			<0 0>,
			<0 0>,
			<0 0>;

		qcom,msm-bus,name = "ufshc_mem";
		qcom,msm-bus,num-cases = <22>;
		qcom,msm-bus,num-paths = <2>;
		qcom,msm-bus,vectors-KBps =
		/*
		 * During HS G3 UFS runs at nominal voltage corner, vote
		 * higher bandwidth to push other buses in the data path
		 * to run at nominal to achieve max throughput.
		 * 4GBps pushes BIMC to run at nominal.
		 * 200MBps pushes CNOC to run at nominal.
		 * Vote for half of this bandwidth for HS G3 1-lane.
		 * For max bandwidth, vote high enough to push the buses
		 * to run in turbo voltage corner.
		 */
		<123 512 0 0>, <1 757 0 0>,          /* No vote */
		<123 512 922 0>, <1 757 1000 0>,     /* PWM G1 */
		<123 512 1844 0>, <1 757 1000 0>,    /* PWM G2 */
		<123 512 3688 0>, <1 757 1000 0>,    /* PWM G3 */
		<123 512 7376 0>, <1 757 1000 0>,    /* PWM G4 */
		<123 512 1844 0>, <1 757 1000 0>,    /* PWM G1 L2 */
		<123 512 3688 0>, <1 757 1000 0>,    /* PWM G2 L2 */
		<123 512 7376 0>, <1 757 1000 0>,    /* PWM G3 L2 */
		<123 512 14752 0>, <1 757 1000 0>,   /* PWM G4 L2 */
		<123 512 127796 0>, <1 757 1000 0>,  /* HS G1 RA */
		<123 512 255591 0>, <1 757 1000 0>,  /* HS G2 RA */
		<123 512 2097152 0>, <1 757 102400 0>,  /* HS G3 RA */
		<123 512 255591 0>, <1 757 1000 0>,  /* HS G1 RA L2 */
		<123 512 511181 0>, <1 757 1000 0>,  /* HS G2 RA L2 */
		<123 512 4194304 0>, <1 757 204800 0>, /* HS G3 RA L2 */
		<123 512 149422 0>, <1 757 1000 0>,  /* HS G1 RB */
		<123 512 298189 0>, <1 757 1000 0>,  /* HS G2 RB */
		<123 512 2097152 0>, <1 757 102400 0>,  /* HS G3 RB */
		<123 512 298189 0>, <1 757 1000 0>,  /* HS G1 RB L2 */
		<123 512 596378 0>, <1 757 1000 0>,  /* HS G2 RB L2 */
		/* As UFS working in HS G3 RB L2 mode, aggregated
		 * bandwidth (AB) should take care of providing
		 * optimum throughput requested. However, as tested,
		 * in order to scale up CNOC clock, instantaneous
		 * bindwidth (IB) needs to be given a proper value too.
		 */
		<123 512 4194304 0>, <1 757 204800 409600>, /* HS G3 RB L2 */
		<123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",
		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
		"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
		"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2",
		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
		"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2",
		"MAX";

		/* PM QoS */
		qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
		qcom,pm-qos-cpu-group-latency-us = <44 44>;
		qcom,pm-qos-default-cpu = <0>;

		pinctrl-names = "dev-reset-assert", "dev-reset-deassert";
		pinctrl-0 = <&ufs_dev_reset_assert>;
		pinctrl-1 = <&ufs_dev_reset_deassert>;

		resets = <&clock_gcc GCC_UFS_PHY_BCR>;
		reset-names = "core_reset";

		status = "disabled";
	};

	ipcc_mproc: qcom,ipcc@408000 {
		compatible = "qcom,kona-ipcc";
		reg = <0x408000 0x1000>;
		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <3>;
		#mbox-cells = <2>;
	};

	ipcc_self_ping: ipcc-self-ping {
		compatible = "qcom,ipcc-self-ping";
		interrupts-extended = <&ipcc_mproc IPCC_CLIENT_APSS
				IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_LEVEL_HIGH>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_APSS IPCC_MPROC_SIGNAL_SMP2P>;
	};

	apps_rsc: rsc@18200000 {
		label = "apps_rsc";
		compatible = "qcom,rpmh-rsc";
		reg = <0x18200000 0x10000>,
		      <0x18210000 0x10000>,
		      <0x18220000 0x10000>;
		reg-names = "drv-0", "drv-1", "drv-2";
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
		qcom,tcs-offset = <0xd00>;
		qcom,drv-id = <2>;
		qcom,tcs-config = <ACTIVE_TCS  2>,
				  <SLEEP_TCS   3>,
				  <WAKE_TCS    3>,
				  <CONTROL_TCS 1>;
		status = "disabled";

		msm_bus_apps_rsc {
			compatible = "qcom,msm-bus-rsc";
			qcom,msm-bus-id = <MSM_BUS_RSC_APPS>;
		};
	};

	disp_rsc: rsc@af20000 {
		label = "disp_rsc";
		compatible = "qcom,rpmh-rsc";
		reg = <0xaf20000 0x10000>;
		reg-names = "drv-0";
		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
		qcom,tcs-offset = <0x1c00>;
		qcom,drv-id = <0>;
		qcom,tcs-config = <ACTIVE_TCS  0>,
				  <SLEEP_TCS   1>,
				  <WAKE_TCS    1>,
				  <CONTROL_TCS 0>;
		status = "disabled";
	};

	tcsr_mutex_block: syscon@1f40000 {
		compatible = "syscon";
		reg = <0x1f40000 0x20000>;
	};

	tcsr_mutex: hwlock {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_block 0 0x1000>;
		#hwlock-cells = <1>;
	};

	smem: qcom,smem {
		compatible = "qcom,smem";
		memory-region = <&smem_mem>;
		hwlocks = <&tcsr_mutex 3>;
	};

	kryo-erp {
		compatible = "arm,arm64-kryo-cpu-erp";
		interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "l1-l2-faultirq",
				  "l3-scu-faultirq";
	};

	qcom,glink {
		compatible = "qcom,glink";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		glink_adsp: adsp {
			qcom,remote-pid = <2>;
			transport = "smem";
			mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
			mbox-names = "adsp_smem";
			interrupt-parent = <&ipcc_mproc>;
			interrupts = <IPCC_CLIENT_LPASS
				      IPCC_MPROC_SIGNAL_GLINK_QMP
				      IRQ_TYPE_EDGE_RISING>;

			label = "adsp";
			qcom,glink-label = "lpass";

			qcom,adsp_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,adsp_glink_ssr {
				qcom,glink-channels = "glink_ssr";
				qcom,notify-edges = <&glink_slpi>,
						    <&glink_cdsp>;
			};
		};

		glink_slpi: dsps {
			qcom,remote-pid = <3>;
			transport = "smem";
			mboxes = <&ipcc_mproc IPCC_CLIENT_SLPI
				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
			mbox-names = "dsps_smem";
			interrupt-parent = <&ipcc_mproc>;
			interrupts = <IPCC_CLIENT_SLPI
				      IPCC_MPROC_SIGNAL_GLINK_QMP
				      IRQ_TYPE_EDGE_RISING>;

			label = "slpi";
			qcom,glink-label = "dsps";

			qcom,slpi_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,slpi_glink_ssr {
				qcom,glink-channels = "glink_ssr";
				qcom,notify-edges = <&glink_adsp>,
						    <&glink_cdsp>;
			};
		};

		glink_cdsp: cdsp {
			qcom,remote-pid = <5>;
			transport = "smem";
			mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP
				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
			mbox-names = "dsps_smem";
			interrupt-parent = <&ipcc_mproc>;
			interrupts = <IPCC_CLIENT_CDSP
				      IPCC_MPROC_SIGNAL_GLINK_QMP
				      IRQ_TYPE_EDGE_RISING>;

			label = "cdsp";
			qcom,glink-label = "cdsp";

			qcom,cdsp_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,cdsp_glink_ssr {
				qcom,glink-channels = "glink_ssr";
				qcom,notify-edges = <&glink_adsp>,
						    <&glink_slpi>;
			};
		};
	};

	qcom,lpass@17300000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0x17300000 0x00100>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;
		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
		qcom,proxy-reg-names = "vdd_cx";

		clocks = <&clock_rpmh RPMH_CXO_CLK>;
		clock-names = "xo";
		qcom,proxy-clock-names = "xo";

		qcom,pas-id = <1>;
		qcom,proxy-timeout-ms = <10000>;
		qcom,smem-id = <423>;
		qcom,sysmon-id = <1>;
		qcom,ssctl-instance-id = <0x14>;
		qcom,firmware-name = "adsp";
		memory-region = <&pil_adsp_mem>;
		qcom,complete-ramdump;

		/* Inputs from lpass */
		interrupts-extended = <&pdc 96 IRQ_TYPE_LEVEL_HIGH>,
				<&adsp_smp2p_in 0 0>,
				<&adsp_smp2p_in 2 0>,
				<&adsp_smp2p_in 1 0>,
				<&adsp_smp2p_in 3 0>;

		interrupt-names = "qcom,wdog",
				"qcom,err-fatal",
				"qcom,proxy-unvote",
				"qcom,err-ready",
				"qcom,stop-ack";

		/* Outputs to lpass */
		qcom,smem-states = <&adsp_smp2p_out 0>;
		qcom,smem-state-names = "qcom,force-stop";

		mbox-names = "adsp-pil";
	};

	qcom,turing@8300000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0x8300000 0x100000>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;
		qcom,proxy-reg-names = "vdd_cx";
		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;

		clocks = <&clock_rpmh RPMH_CXO_CLK>;
		clock-names = "xo";
		qcom,proxy-clock-names = "xo";

		qcom,pas-id = <18>;
		qcom,proxy-timeout-ms = <10000>;
		qcom,smem-id = <601>;
		qcom,sysmon-id = <7>;
		qcom,ssctl-instance-id = <0x17>;
		qcom,firmware-name = "cdsp";
		memory-region = <&pil_cdsp_mem>;
		qcom,complete-ramdump;

		qcom,msm-bus,name = "pil-cdsp";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			<154 10070 0 0>,
			<154 10070 0 1>;

		/* Inputs from turing */
		interrupts = <GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
				<&cdsp_smp2p_in 0 0>,
				<&cdsp_smp2p_in 2 0>,
				<&cdsp_smp2p_in 1 0>,
				<&cdsp_smp2p_in 3 0>;

		interrupt-names = "qcom,wdog",
				"qcom,err-fatal",
				"qcom,proxy-unvote",
				"qcom,err-ready",
				"qcom,stop-ack";

		/* Outputs to turing */
		qcom,smem-states = <&cdsp_smp2p_out 0>;
		qcom,smem-state-names = "qcom,force-stop";

		mbox-names = "cdsp-pil";
	};
};

#include "kona-bus.dtsi"
#include "kona-ion.dtsi"
#include "msm-arm-smmu-kona.dtsi"
#include "kona-pinctrl.dtsi"
#include "kona-smp2p.dtsi"
#include "kona-usb.dtsi"
#include "kona-sde.dtsi"
#include "kona-sde-pll.dtsi"
#include "kona-sde-display.dtsi"