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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Pierre Ossman70f10482007-07-11 20:04:50 +02002 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
Russell Kingc8ebae32011-01-11 19:35:53 +00005 * Copyright (C) 2010 ST-Ericsson SA
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070011#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/device.h>
16#include <linux/interrupt.h>
Russell King613b1522011-01-30 21:06:53 +000017#include <linux/kernel.h>
Lee Jones000bc9d2012-04-16 10:18:43 +010018#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070019#include <linux/delay.h>
20#include <linux/err.h>
21#include <linux/highmem.h>
Nicolas Pitre019a5f52007-10-11 01:06:03 -040022#include <linux/log2.h>
Ulf Hansson70be2082013-01-07 15:35:06 +010023#include <linux/mmc/pm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070024#include <linux/mmc/host.h>
Linus Walleij34177802010-10-19 12:43:58 +010025#include <linux/mmc/card.h>
Russell Kinga62c80e2006-01-07 13:52:45 +000026#include <linux/amba/bus.h>
Russell Kingf8ce2542006-01-07 16:15:52 +000027#include <linux/clk.h>
Jens Axboebd6dee62007-10-24 09:01:09 +020028#include <linux/scatterlist.h>
Russell King89001442009-07-09 15:16:07 +010029#include <linux/gpio.h>
Lee Jones9a597012012-04-12 16:51:13 +010030#include <linux/of_gpio.h>
Linus Walleij34e84f32009-09-22 14:41:40 +010031#include <linux/regulator/consumer.h>
Russell Kingc8ebae32011-01-11 19:35:53 +000032#include <linux/dmaengine.h>
33#include <linux/dma-mapping.h>
34#include <linux/amba/mmci.h>
Russell King1c3be362011-08-14 09:17:05 +010035#include <linux/pm_runtime.h>
Viresh Kumar258aea72012-02-01 16:12:19 +053036#include <linux/types.h>
Linus Walleija9a83782012-10-29 14:39:30 +010037#include <linux/pinctrl/consumer.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070038
Russell King7b09cda2005-07-01 12:02:59 +010039#include <asm/div64.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070040#include <asm/io.h>
Russell Kingc6b8fda2005-10-28 14:05:16 +010041#include <asm/sizes.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070042
43#include "mmci.h"
44
45#define DRIVER_NAME "mmci-pl18x"
46
Linus Torvalds1da177e2005-04-16 15:20:36 -070047static unsigned int fmax = 515633;
48
Rabin Vincent4956e102010-07-21 12:54:40 +010049/**
50 * struct variant_data - MMCI variant-specific quirks
51 * @clkreg: default value for MCICLOCK register
Rabin Vincent4380c142010-07-21 12:55:18 +010052 * @clkreg_enable: enable value for MMCICLOCK register
Rabin Vincent08458ef2010-07-21 12:55:59 +010053 * @datalength_bits: number of bits in the MMCIDATALENGTH register
Rabin Vincent8301bb62010-08-09 12:57:30 +010054 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
55 * is asserted (likewise for RX)
56 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
57 * is asserted (likewise for RX)
Linus Walleij34177802010-10-19 12:43:58 +010058 * @sdio: variant supports SDIO
Linus Walleijb70a67f2010-12-06 09:24:14 +010059 * @st_clkdiv: true if using a ST-specific clock divider algorithm
Philippe Langlais1784b152011-03-25 08:51:52 +010060 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
Ulf Hansson7d72a1d2011-12-13 16:54:55 +010061 * @pwrreg_powerup: power up value for MMCIPOWER register
Ulf Hansson4d1a3a02011-12-13 16:57:07 +010062 * @signal_direction: input/out direction of bus signals can be indicated
Ulf Hanssonf4670da2013-01-09 17:19:54 +010063 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
Rabin Vincent4956e102010-07-21 12:54:40 +010064 */
65struct variant_data {
66 unsigned int clkreg;
Rabin Vincent4380c142010-07-21 12:55:18 +010067 unsigned int clkreg_enable;
Rabin Vincent08458ef2010-07-21 12:55:59 +010068 unsigned int datalength_bits;
Rabin Vincent8301bb62010-08-09 12:57:30 +010069 unsigned int fifosize;
70 unsigned int fifohalfsize;
Linus Walleij34177802010-10-19 12:43:58 +010071 bool sdio;
Linus Walleijb70a67f2010-12-06 09:24:14 +010072 bool st_clkdiv;
Philippe Langlais1784b152011-03-25 08:51:52 +010073 bool blksz_datactrl16;
Ulf Hansson7d72a1d2011-12-13 16:54:55 +010074 u32 pwrreg_powerup;
Ulf Hansson4d1a3a02011-12-13 16:57:07 +010075 bool signal_direction;
Ulf Hanssonf4670da2013-01-09 17:19:54 +010076 bool pwrreg_clkgate;
Rabin Vincent4956e102010-07-21 12:54:40 +010077};
78
79static struct variant_data variant_arm = {
Rabin Vincent8301bb62010-08-09 12:57:30 +010080 .fifosize = 16 * 4,
81 .fifohalfsize = 8 * 4,
Rabin Vincent08458ef2010-07-21 12:55:59 +010082 .datalength_bits = 16,
Ulf Hansson7d72a1d2011-12-13 16:54:55 +010083 .pwrreg_powerup = MCI_PWR_UP,
Rabin Vincent4956e102010-07-21 12:54:40 +010084};
85
Pawel Moll768fbc12011-03-11 17:18:07 +000086static struct variant_data variant_arm_extended_fifo = {
87 .fifosize = 128 * 4,
88 .fifohalfsize = 64 * 4,
89 .datalength_bits = 16,
Ulf Hansson7d72a1d2011-12-13 16:54:55 +010090 .pwrreg_powerup = MCI_PWR_UP,
Pawel Moll768fbc12011-03-11 17:18:07 +000091};
92
Pawel Moll3a372982013-01-24 14:12:45 +010093static struct variant_data variant_arm_extended_fifo_hwfc = {
94 .fifosize = 128 * 4,
95 .fifohalfsize = 64 * 4,
96 .clkreg_enable = MCI_ARM_HWFCEN,
97 .datalength_bits = 16,
98 .pwrreg_powerup = MCI_PWR_UP,
99};
100
Rabin Vincent4956e102010-07-21 12:54:40 +0100101static struct variant_data variant_u300 = {
Rabin Vincent8301bb62010-08-09 12:57:30 +0100102 .fifosize = 16 * 4,
103 .fifohalfsize = 8 * 4,
Linus Walleij49ac2152011-03-04 14:54:16 +0100104 .clkreg_enable = MCI_ST_U300_HWFCEN,
Rabin Vincent08458ef2010-07-21 12:55:59 +0100105 .datalength_bits = 16,
Linus Walleij34177802010-10-19 12:43:58 +0100106 .sdio = true,
Ulf Hansson7d72a1d2011-12-13 16:54:55 +0100107 .pwrreg_powerup = MCI_PWR_ON,
Ulf Hansson4d1a3a02011-12-13 16:57:07 +0100108 .signal_direction = true,
Ulf Hanssonf4670da2013-01-09 17:19:54 +0100109 .pwrreg_clkgate = true,
Rabin Vincent4956e102010-07-21 12:54:40 +0100110};
111
Linus Walleij34fd4212012-04-10 17:43:59 +0100112static struct variant_data variant_nomadik = {
113 .fifosize = 16 * 4,
114 .fifohalfsize = 8 * 4,
115 .clkreg = MCI_CLK_ENABLE,
116 .datalength_bits = 24,
117 .sdio = true,
118 .st_clkdiv = true,
119 .pwrreg_powerup = MCI_PWR_ON,
120 .signal_direction = true,
Ulf Hanssonf4670da2013-01-09 17:19:54 +0100121 .pwrreg_clkgate = true,
Linus Walleij34fd4212012-04-10 17:43:59 +0100122};
123
Rabin Vincent4956e102010-07-21 12:54:40 +0100124static struct variant_data variant_ux500 = {
Rabin Vincent8301bb62010-08-09 12:57:30 +0100125 .fifosize = 30 * 4,
126 .fifohalfsize = 8 * 4,
Rabin Vincent4956e102010-07-21 12:54:40 +0100127 .clkreg = MCI_CLK_ENABLE,
Linus Walleij49ac2152011-03-04 14:54:16 +0100128 .clkreg_enable = MCI_ST_UX500_HWFCEN,
Rabin Vincent08458ef2010-07-21 12:55:59 +0100129 .datalength_bits = 24,
Linus Walleij34177802010-10-19 12:43:58 +0100130 .sdio = true,
Linus Walleijb70a67f2010-12-06 09:24:14 +0100131 .st_clkdiv = true,
Ulf Hansson7d72a1d2011-12-13 16:54:55 +0100132 .pwrreg_powerup = MCI_PWR_ON,
Ulf Hansson4d1a3a02011-12-13 16:57:07 +0100133 .signal_direction = true,
Ulf Hanssonf4670da2013-01-09 17:19:54 +0100134 .pwrreg_clkgate = true,
Rabin Vincent4956e102010-07-21 12:54:40 +0100135};
Linus Walleijb70a67f2010-12-06 09:24:14 +0100136
Philippe Langlais1784b152011-03-25 08:51:52 +0100137static struct variant_data variant_ux500v2 = {
138 .fifosize = 30 * 4,
139 .fifohalfsize = 8 * 4,
140 .clkreg = MCI_CLK_ENABLE,
141 .clkreg_enable = MCI_ST_UX500_HWFCEN,
142 .datalength_bits = 24,
143 .sdio = true,
144 .st_clkdiv = true,
145 .blksz_datactrl16 = true,
Ulf Hansson7d72a1d2011-12-13 16:54:55 +0100146 .pwrreg_powerup = MCI_PWR_ON,
Ulf Hansson4d1a3a02011-12-13 16:57:07 +0100147 .signal_direction = true,
Ulf Hanssonf4670da2013-01-09 17:19:54 +0100148 .pwrreg_clkgate = true,
Philippe Langlais1784b152011-03-25 08:51:52 +0100149};
150
Linus Walleija6a64642009-09-14 12:56:14 +0100151/*
Ulf Hansson653a7612013-01-21 21:29:34 +0100152 * Validate mmc prerequisites
153 */
154static int mmci_validate_data(struct mmci_host *host,
155 struct mmc_data *data)
156{
157 if (!data)
158 return 0;
159
160 if (!is_power_of_2(data->blksz)) {
161 dev_err(mmc_dev(host->mmc),
162 "unsupported block size (%d bytes)\n", data->blksz);
163 return -EINVAL;
164 }
165
166 return 0;
167}
168
169/*
Linus Walleija6a64642009-09-14 12:56:14 +0100170 * This must be called with host->lock held
171 */
Ulf Hansson7437cfa2012-01-18 09:17:27 +0100172static void mmci_write_clkreg(struct mmci_host *host, u32 clk)
173{
174 if (host->clk_reg != clk) {
175 host->clk_reg = clk;
176 writel(clk, host->base + MMCICLOCK);
177 }
178}
179
180/*
181 * This must be called with host->lock held
182 */
183static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
184{
185 if (host->pwr_reg != pwr) {
186 host->pwr_reg = pwr;
187 writel(pwr, host->base + MMCIPOWER);
188 }
189}
190
191/*
192 * This must be called with host->lock held
193 */
Linus Walleija6a64642009-09-14 12:56:14 +0100194static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
195{
Rabin Vincent4956e102010-07-21 12:54:40 +0100196 struct variant_data *variant = host->variant;
197 u32 clk = variant->clkreg;
Linus Walleija6a64642009-09-14 12:56:14 +0100198
199 if (desired) {
200 if (desired >= host->mclk) {
Linus Walleij991a86e2010-12-10 09:35:53 +0100201 clk = MCI_CLK_BYPASS;
Linus Walleij399bc482011-04-01 07:59:17 +0100202 if (variant->st_clkdiv)
203 clk |= MCI_ST_UX500_NEG_EDGE;
Linus Walleija6a64642009-09-14 12:56:14 +0100204 host->cclk = host->mclk;
Linus Walleijb70a67f2010-12-06 09:24:14 +0100205 } else if (variant->st_clkdiv) {
206 /*
207 * DB8500 TRM says f = mclk / (clkdiv + 2)
208 * => clkdiv = (mclk / f) - 2
209 * Round the divider up so we don't exceed the max
210 * frequency
211 */
212 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
213 if (clk >= 256)
214 clk = 255;
215 host->cclk = host->mclk / (clk + 2);
Linus Walleija6a64642009-09-14 12:56:14 +0100216 } else {
Linus Walleijb70a67f2010-12-06 09:24:14 +0100217 /*
218 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
219 * => clkdiv = mclk / (2 * f) - 1
220 */
Linus Walleija6a64642009-09-14 12:56:14 +0100221 clk = host->mclk / (2 * desired) - 1;
222 if (clk >= 256)
223 clk = 255;
224 host->cclk = host->mclk / (2 * (clk + 1));
225 }
Rabin Vincent4380c142010-07-21 12:55:18 +0100226
227 clk |= variant->clkreg_enable;
Linus Walleija6a64642009-09-14 12:56:14 +0100228 clk |= MCI_CLK_ENABLE;
229 /* This hasn't proven to be worthwhile */
230 /* clk |= MCI_CLK_PWRSAVE; */
231 }
232
Linus Walleij9e6c82c2009-09-14 12:57:11 +0100233 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
Linus Walleij771dc152010-04-08 07:38:52 +0100234 clk |= MCI_4BIT_BUS;
235 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
236 clk |= MCI_ST_8BIT_BUS;
Linus Walleij9e6c82c2009-09-14 12:57:11 +0100237
Ulf Hansson6dbb6ee2013-01-07 15:30:44 +0100238 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
239 clk |= MCI_ST_UX500_NEG_EDGE;
240
Ulf Hansson7437cfa2012-01-18 09:17:27 +0100241 mmci_write_clkreg(host, clk);
Linus Walleija6a64642009-09-14 12:56:14 +0100242}
243
Linus Torvalds1da177e2005-04-16 15:20:36 -0700244static void
245mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
246{
247 writel(0, host->base + MMCICOMMAND);
248
Russell Kinge47c2222007-01-08 16:42:51 +0000249 BUG_ON(host->data);
250
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251 host->mrq = NULL;
252 host->cmd = NULL;
253
Linus Torvalds1da177e2005-04-16 15:20:36 -0700254 mmc_request_done(host->mmc, mrq);
Ulf Hansson2cd976c2011-12-13 17:01:11 +0100255
256 pm_runtime_mark_last_busy(mmc_dev(host->mmc));
257 pm_runtime_put_autosuspend(mmc_dev(host->mmc));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258}
259
Linus Walleij2686b4b2010-10-19 12:39:48 +0100260static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
261{
262 void __iomem *base = host->base;
263
264 if (host->singleirq) {
265 unsigned int mask0 = readl(base + MMCIMASK0);
266
267 mask0 &= ~MCI_IRQ1MASK;
268 mask0 |= mask;
269
270 writel(mask0, base + MMCIMASK0);
271 }
272
273 writel(mask, base + MMCIMASK1);
274}
275
Linus Torvalds1da177e2005-04-16 15:20:36 -0700276static void mmci_stop_data(struct mmci_host *host)
277{
278 writel(0, host->base + MMCIDATACTRL);
Linus Walleij2686b4b2010-10-19 12:39:48 +0100279 mmci_set_mask1(host, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280 host->data = NULL;
281}
282
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +0100283static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
284{
285 unsigned int flags = SG_MITER_ATOMIC;
286
287 if (data->flags & MMC_DATA_READ)
288 flags |= SG_MITER_TO_SG;
289 else
290 flags |= SG_MITER_FROM_SG;
291
292 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
293}
294
Russell Kingc8ebae32011-01-11 19:35:53 +0000295/*
296 * All the DMA operation mode stuff goes inside this ifdef.
297 * This assumes that you have a generic DMA device interface,
298 * no custom DMA interfaces are supported.
299 */
300#ifdef CONFIG_DMA_ENGINE
Bill Pembertonc3be1ef2012-11-19 13:23:06 -0500301static void mmci_dma_setup(struct mmci_host *host)
Russell Kingc8ebae32011-01-11 19:35:53 +0000302{
303 struct mmci_platform_data *plat = host->plat;
304 const char *rxname, *txname;
305 dma_cap_mask_t mask;
306
307 if (!plat || !plat->dma_filter) {
308 dev_info(mmc_dev(host->mmc), "no DMA platform data\n");
309 return;
310 }
311
Per Forlin58c7ccb2011-07-01 18:55:24 +0200312 /* initialize pre request cookie */
313 host->next_data.cookie = 1;
314
Russell Kingc8ebae32011-01-11 19:35:53 +0000315 /* Try to acquire a generic DMA engine slave channel */
316 dma_cap_zero(mask);
317 dma_cap_set(DMA_SLAVE, mask);
318
319 /*
320 * If only an RX channel is specified, the driver will
321 * attempt to use it bidirectionally, however if it is
322 * is specified but cannot be located, DMA will be disabled.
323 */
324 if (plat->dma_rx_param) {
325 host->dma_rx_channel = dma_request_channel(mask,
326 plat->dma_filter,
327 plat->dma_rx_param);
328 /* E.g if no DMA hardware is present */
329 if (!host->dma_rx_channel)
330 dev_err(mmc_dev(host->mmc), "no RX DMA channel\n");
331 }
332
333 if (plat->dma_tx_param) {
334 host->dma_tx_channel = dma_request_channel(mask,
335 plat->dma_filter,
336 plat->dma_tx_param);
337 if (!host->dma_tx_channel)
338 dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n");
339 } else {
340 host->dma_tx_channel = host->dma_rx_channel;
341 }
342
343 if (host->dma_rx_channel)
344 rxname = dma_chan_name(host->dma_rx_channel);
345 else
346 rxname = "none";
347
348 if (host->dma_tx_channel)
349 txname = dma_chan_name(host->dma_tx_channel);
350 else
351 txname = "none";
352
353 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
354 rxname, txname);
355
356 /*
357 * Limit the maximum segment size in any SG entry according to
358 * the parameters of the DMA engine device.
359 */
360 if (host->dma_tx_channel) {
361 struct device *dev = host->dma_tx_channel->device->dev;
362 unsigned int max_seg_size = dma_get_max_seg_size(dev);
363
364 if (max_seg_size < host->mmc->max_seg_size)
365 host->mmc->max_seg_size = max_seg_size;
366 }
367 if (host->dma_rx_channel) {
368 struct device *dev = host->dma_rx_channel->device->dev;
369 unsigned int max_seg_size = dma_get_max_seg_size(dev);
370
371 if (max_seg_size < host->mmc->max_seg_size)
372 host->mmc->max_seg_size = max_seg_size;
373 }
374}
375
376/*
Bill Pemberton6e0ee712012-11-19 13:26:03 -0500377 * This is used in or so inline it
Russell Kingc8ebae32011-01-11 19:35:53 +0000378 * so it can be discarded.
379 */
380static inline void mmci_dma_release(struct mmci_host *host)
381{
382 struct mmci_platform_data *plat = host->plat;
383
384 if (host->dma_rx_channel)
385 dma_release_channel(host->dma_rx_channel);
386 if (host->dma_tx_channel && plat->dma_tx_param)
387 dma_release_channel(host->dma_tx_channel);
388 host->dma_rx_channel = host->dma_tx_channel = NULL;
389}
390
Ulf Hansson653a7612013-01-21 21:29:34 +0100391static void mmci_dma_data_error(struct mmci_host *host)
392{
393 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
394 dmaengine_terminate_all(host->dma_current);
395 host->dma_current = NULL;
396 host->dma_desc_current = NULL;
397 host->data->host_cookie = 0;
398}
399
Russell Kingc8ebae32011-01-11 19:35:53 +0000400static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
401{
Ulf Hansson653a7612013-01-21 21:29:34 +0100402 struct dma_chan *chan;
Russell Kingc8ebae32011-01-11 19:35:53 +0000403 enum dma_data_direction dir;
Ulf Hansson653a7612013-01-21 21:29:34 +0100404
405 if (data->flags & MMC_DATA_READ) {
406 dir = DMA_FROM_DEVICE;
407 chan = host->dma_rx_channel;
408 } else {
409 dir = DMA_TO_DEVICE;
410 chan = host->dma_tx_channel;
411 }
412
413 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
414}
415
416static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
417{
Russell Kingc8ebae32011-01-11 19:35:53 +0000418 u32 status;
419 int i;
420
421 /* Wait up to 1ms for the DMA to complete */
422 for (i = 0; ; i++) {
423 status = readl(host->base + MMCISTATUS);
424 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
425 break;
426 udelay(10);
427 }
428
429 /*
430 * Check to see whether we still have some data left in the FIFO -
431 * this catches DMA controllers which are unable to monitor the
432 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
433 * contiguous buffers. On TX, we'll get a FIFO underrun error.
434 */
435 if (status & MCI_RXDATAAVLBLMASK) {
Ulf Hansson653a7612013-01-21 21:29:34 +0100436 mmci_dma_data_error(host);
Russell Kingc8ebae32011-01-11 19:35:53 +0000437 if (!data->error)
438 data->error = -EIO;
439 }
440
Per Forlin58c7ccb2011-07-01 18:55:24 +0200441 if (!data->host_cookie)
Ulf Hansson653a7612013-01-21 21:29:34 +0100442 mmci_dma_unmap(host, data);
Russell Kingc8ebae32011-01-11 19:35:53 +0000443
444 /*
445 * Use of DMA with scatter-gather is impossible.
446 * Give up with DMA and switch back to PIO mode.
447 */
448 if (status & MCI_RXDATAAVLBLMASK) {
449 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
450 mmci_dma_release(host);
451 }
Ulf Hansson653a7612013-01-21 21:29:34 +0100452
453 host->dma_current = NULL;
454 host->dma_desc_current = NULL;
Russell Kingc8ebae32011-01-11 19:35:53 +0000455}
456
Ulf Hansson653a7612013-01-21 21:29:34 +0100457/* prepares DMA channel and DMA descriptor, returns non-zero on failure */
458static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data,
459 struct dma_chan **dma_chan,
460 struct dma_async_tx_descriptor **dma_desc)
Russell Kingc8ebae32011-01-11 19:35:53 +0000461{
462 struct variant_data *variant = host->variant;
463 struct dma_slave_config conf = {
464 .src_addr = host->phybase + MMCIFIFO,
465 .dst_addr = host->phybase + MMCIFIFO,
466 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
467 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
468 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
469 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
Viresh Kumar258aea72012-02-01 16:12:19 +0530470 .device_fc = false,
Russell Kingc8ebae32011-01-11 19:35:53 +0000471 };
Russell Kingc8ebae32011-01-11 19:35:53 +0000472 struct dma_chan *chan;
473 struct dma_device *device;
474 struct dma_async_tx_descriptor *desc;
Vinod Koul05f57992011-10-14 10:45:11 +0530475 enum dma_data_direction buffer_dirn;
Russell Kingc8ebae32011-01-11 19:35:53 +0000476 int nr_sg;
477
Russell Kingc8ebae32011-01-11 19:35:53 +0000478 if (data->flags & MMC_DATA_READ) {
Vinod Koul05f57992011-10-14 10:45:11 +0530479 conf.direction = DMA_DEV_TO_MEM;
480 buffer_dirn = DMA_FROM_DEVICE;
Russell Kingc8ebae32011-01-11 19:35:53 +0000481 chan = host->dma_rx_channel;
482 } else {
Vinod Koul05f57992011-10-14 10:45:11 +0530483 conf.direction = DMA_MEM_TO_DEV;
484 buffer_dirn = DMA_TO_DEVICE;
Russell Kingc8ebae32011-01-11 19:35:53 +0000485 chan = host->dma_tx_channel;
486 }
487
488 /* If there's no DMA channel, fall back to PIO */
489 if (!chan)
490 return -EINVAL;
491
492 /* If less than or equal to the fifo size, don't bother with DMA */
Per Forlin58c7ccb2011-07-01 18:55:24 +0200493 if (data->blksz * data->blocks <= variant->fifosize)
Russell Kingc8ebae32011-01-11 19:35:53 +0000494 return -EINVAL;
495
496 device = chan->device;
Vinod Koul05f57992011-10-14 10:45:11 +0530497 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
Russell Kingc8ebae32011-01-11 19:35:53 +0000498 if (nr_sg == 0)
499 return -EINVAL;
500
501 dmaengine_slave_config(chan, &conf);
Alexandre Bounine16052822012-03-08 16:11:18 -0500502 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
Russell Kingc8ebae32011-01-11 19:35:53 +0000503 conf.direction, DMA_CTRL_ACK);
504 if (!desc)
505 goto unmap_exit;
506
Ulf Hansson653a7612013-01-21 21:29:34 +0100507 *dma_chan = chan;
508 *dma_desc = desc;
Russell Kingc8ebae32011-01-11 19:35:53 +0000509
Per Forlin58c7ccb2011-07-01 18:55:24 +0200510 return 0;
511
512 unmap_exit:
Vinod Koul05f57992011-10-14 10:45:11 +0530513 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
Per Forlin58c7ccb2011-07-01 18:55:24 +0200514 return -ENOMEM;
515}
516
Ulf Hansson653a7612013-01-21 21:29:34 +0100517static inline int mmci_dma_prep_data(struct mmci_host *host,
518 struct mmc_data *data)
519{
520 /* Check if next job is already prepared. */
521 if (host->dma_current && host->dma_desc_current)
522 return 0;
523
524 /* No job were prepared thus do it now. */
525 return __mmci_dma_prep_data(host, data, &host->dma_current,
526 &host->dma_desc_current);
527}
528
529static inline int mmci_dma_prep_next(struct mmci_host *host,
530 struct mmc_data *data)
531{
532 struct mmci_host_next *nd = &host->next_data;
533 return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc);
534}
535
Per Forlin58c7ccb2011-07-01 18:55:24 +0200536static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
537{
538 int ret;
539 struct mmc_data *data = host->data;
540
Ulf Hansson653a7612013-01-21 21:29:34 +0100541 ret = mmci_dma_prep_data(host, host->data);
Per Forlin58c7ccb2011-07-01 18:55:24 +0200542 if (ret)
543 return ret;
544
545 /* Okay, go for it. */
Russell Kingc8ebae32011-01-11 19:35:53 +0000546 dev_vdbg(mmc_dev(host->mmc),
547 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
548 data->sg_len, data->blksz, data->blocks, data->flags);
Per Forlin58c7ccb2011-07-01 18:55:24 +0200549 dmaengine_submit(host->dma_desc_current);
550 dma_async_issue_pending(host->dma_current);
Russell Kingc8ebae32011-01-11 19:35:53 +0000551
552 datactrl |= MCI_DPSM_DMAENABLE;
553
554 /* Trigger the DMA transfer */
555 writel(datactrl, host->base + MMCIDATACTRL);
556
557 /*
558 * Let the MMCI say when the data is ended and it's time
559 * to fire next DMA request. When that happens, MMCI will
560 * call mmci_data_end()
561 */
562 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
563 host->base + MMCIMASK0);
564 return 0;
Russell Kingc8ebae32011-01-11 19:35:53 +0000565}
Per Forlin58c7ccb2011-07-01 18:55:24 +0200566
567static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
568{
569 struct mmci_host_next *next = &host->next_data;
570
Ulf Hansson653a7612013-01-21 21:29:34 +0100571 WARN_ON(data->host_cookie && data->host_cookie != next->cookie);
572 WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan));
Per Forlin58c7ccb2011-07-01 18:55:24 +0200573
574 host->dma_desc_current = next->dma_desc;
575 host->dma_current = next->dma_chan;
Per Forlin58c7ccb2011-07-01 18:55:24 +0200576 next->dma_desc = NULL;
577 next->dma_chan = NULL;
578}
579
580static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq,
581 bool is_first_req)
582{
583 struct mmci_host *host = mmc_priv(mmc);
584 struct mmc_data *data = mrq->data;
585 struct mmci_host_next *nd = &host->next_data;
586
587 if (!data)
588 return;
589
Ulf Hansson653a7612013-01-21 21:29:34 +0100590 BUG_ON(data->host_cookie);
Per Forlin58c7ccb2011-07-01 18:55:24 +0200591
Ulf Hansson653a7612013-01-21 21:29:34 +0100592 if (mmci_validate_data(host, data))
593 return;
594
595 if (!mmci_dma_prep_next(host, data))
596 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie;
Per Forlin58c7ccb2011-07-01 18:55:24 +0200597}
598
599static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
600 int err)
601{
602 struct mmci_host *host = mmc_priv(mmc);
603 struct mmc_data *data = mrq->data;
Per Forlin58c7ccb2011-07-01 18:55:24 +0200604
Ulf Hansson653a7612013-01-21 21:29:34 +0100605 if (!data || !data->host_cookie)
Per Forlin58c7ccb2011-07-01 18:55:24 +0200606 return;
607
Ulf Hansson653a7612013-01-21 21:29:34 +0100608 mmci_dma_unmap(host, data);
Per Forlin58c7ccb2011-07-01 18:55:24 +0200609
Ulf Hansson653a7612013-01-21 21:29:34 +0100610 if (err) {
611 struct mmci_host_next *next = &host->next_data;
612 struct dma_chan *chan;
613 if (data->flags & MMC_DATA_READ)
614 chan = host->dma_rx_channel;
615 else
616 chan = host->dma_tx_channel;
617 dmaengine_terminate_all(chan);
Per Forlin58c7ccb2011-07-01 18:55:24 +0200618
Ulf Hansson653a7612013-01-21 21:29:34 +0100619 next->dma_desc = NULL;
620 next->dma_chan = NULL;
Per Forlin58c7ccb2011-07-01 18:55:24 +0200621 }
622}
623
Russell Kingc8ebae32011-01-11 19:35:53 +0000624#else
625/* Blank functions if the DMA engine is not available */
Per Forlin58c7ccb2011-07-01 18:55:24 +0200626static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
627{
628}
Russell Kingc8ebae32011-01-11 19:35:53 +0000629static inline void mmci_dma_setup(struct mmci_host *host)
630{
631}
632
633static inline void mmci_dma_release(struct mmci_host *host)
634{
635}
636
637static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
638{
639}
640
Ulf Hansson653a7612013-01-21 21:29:34 +0100641static inline void mmci_dma_finalize(struct mmci_host *host,
642 struct mmc_data *data)
643{
644}
645
Russell Kingc8ebae32011-01-11 19:35:53 +0000646static inline void mmci_dma_data_error(struct mmci_host *host)
647{
648}
649
650static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
651{
652 return -ENOSYS;
653}
Per Forlin58c7ccb2011-07-01 18:55:24 +0200654
655#define mmci_pre_request NULL
656#define mmci_post_request NULL
657
Russell Kingc8ebae32011-01-11 19:35:53 +0000658#endif
659
Linus Torvalds1da177e2005-04-16 15:20:36 -0700660static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
661{
Rabin Vincent8301bb62010-08-09 12:57:30 +0100662 struct variant_data *variant = host->variant;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700663 unsigned int datactrl, timeout, irqmask;
Russell King7b09cda2005-07-01 12:02:59 +0100664 unsigned long long clks;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700665 void __iomem *base;
Russell King3bc87f22006-08-27 13:51:28 +0100666 int blksz_bits;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700667
Linus Walleij64de0282010-02-19 01:09:10 +0100668 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
669 data->blksz, data->blocks, data->flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700670
671 host->data = data;
Rabin Vincent528320d2010-07-21 12:49:49 +0100672 host->size = data->blksz * data->blocks;
Russell King51d43752011-01-27 10:56:52 +0000673 data->bytes_xfered = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700674
Russell King7b09cda2005-07-01 12:02:59 +0100675 clks = (unsigned long long)data->timeout_ns * host->cclk;
676 do_div(clks, 1000000000UL);
677
678 timeout = data->timeout_clks + (unsigned int)clks;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700679
680 base = host->base;
681 writel(timeout, base + MMCIDATATIMER);
682 writel(host->size, base + MMCIDATALENGTH);
683
Russell King3bc87f22006-08-27 13:51:28 +0100684 blksz_bits = ffs(data->blksz) - 1;
685 BUG_ON(1 << blksz_bits != data->blksz);
686
Philippe Langlais1784b152011-03-25 08:51:52 +0100687 if (variant->blksz_datactrl16)
688 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
689 else
690 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
Russell Kingc8ebae32011-01-11 19:35:53 +0000691
692 if (data->flags & MMC_DATA_READ)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700693 datactrl |= MCI_DPSM_DIRECTION;
Russell Kingc8ebae32011-01-11 19:35:53 +0000694
Ulf Hansson7258db72011-12-13 17:05:28 +0100695 /* The ST Micro variants has a special bit to enable SDIO */
696 if (variant->sdio && host->mmc->card)
Ulf Hansson06c1a122012-10-12 14:01:50 +0100697 if (mmc_card_sdio(host->mmc->card)) {
698 /*
699 * The ST Micro variants has a special bit
700 * to enable SDIO.
701 */
702 u32 clk;
703
Ulf Hansson7258db72011-12-13 17:05:28 +0100704 datactrl |= MCI_ST_DPSM_SDIOEN;
705
Ulf Hansson06c1a122012-10-12 14:01:50 +0100706 /*
Ulf Hansson70ac0932012-10-12 14:07:36 +0100707 * The ST Micro variant for SDIO small write transfers
708 * needs to have clock H/W flow control disabled,
709 * otherwise the transfer will not start. The threshold
710 * depends on the rate of MCLK.
Ulf Hansson06c1a122012-10-12 14:01:50 +0100711 */
Ulf Hansson70ac0932012-10-12 14:07:36 +0100712 if (data->flags & MMC_DATA_WRITE &&
713 (host->size < 8 ||
714 (host->size <= 8 && host->mclk > 50000000)))
Ulf Hansson06c1a122012-10-12 14:01:50 +0100715 clk = host->clk_reg & ~variant->clkreg_enable;
716 else
717 clk = host->clk_reg | variant->clkreg_enable;
718
719 mmci_write_clkreg(host, clk);
720 }
721
Ulf Hansson6dbb6ee2013-01-07 15:30:44 +0100722 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
723 datactrl |= MCI_ST_DPSM_DDRMODE;
724
Russell Kingc8ebae32011-01-11 19:35:53 +0000725 /*
726 * Attempt to use DMA operation mode, if this
727 * should fail, fall back to PIO mode
728 */
729 if (!mmci_dma_start_data(host, datactrl))
730 return;
731
732 /* IRQ mode, map the SG list for CPU reading/writing */
733 mmci_init_sg(host, data);
734
735 if (data->flags & MMC_DATA_READ) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700736 irqmask = MCI_RXFIFOHALFFULLMASK;
Russell King0425a142006-02-16 16:48:31 +0000737
738 /*
Russell Kingc4d877c2011-01-27 09:50:13 +0000739 * If we have less than the fifo 'half-full' threshold to
740 * transfer, trigger a PIO interrupt as soon as any data
741 * is available.
Russell King0425a142006-02-16 16:48:31 +0000742 */
Russell Kingc4d877c2011-01-27 09:50:13 +0000743 if (host->size < variant->fifohalfsize)
Russell King0425a142006-02-16 16:48:31 +0000744 irqmask |= MCI_RXDATAAVLBLMASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700745 } else {
746 /*
747 * We don't actually need to include "FIFO empty" here
748 * since its implicit in "FIFO half empty".
749 */
750 irqmask = MCI_TXFIFOHALFEMPTYMASK;
751 }
752
753 writel(datactrl, base + MMCIDATACTRL);
754 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
Linus Walleij2686b4b2010-10-19 12:39:48 +0100755 mmci_set_mask1(host, irqmask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700756}
757
758static void
759mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
760{
761 void __iomem *base = host->base;
762
Linus Walleij64de0282010-02-19 01:09:10 +0100763 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700764 cmd->opcode, cmd->arg, cmd->flags);
765
766 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
767 writel(0, base + MMCICOMMAND);
768 udelay(1);
769 }
770
771 c |= cmd->opcode | MCI_CPSM_ENABLE;
Russell Kinge9225172006-02-02 12:23:12 +0000772 if (cmd->flags & MMC_RSP_PRESENT) {
773 if (cmd->flags & MMC_RSP_136)
774 c |= MCI_CPSM_LONGRSP;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700775 c |= MCI_CPSM_RESPONSE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700776 }
777 if (/*interrupt*/0)
778 c |= MCI_CPSM_INTERRUPT;
779
780 host->cmd = cmd;
781
782 writel(cmd->arg, base + MMCIARGUMENT);
783 writel(c, base + MMCICOMMAND);
784}
785
786static void
787mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
788 unsigned int status)
789{
Linus Walleijf20f8f22010-10-19 13:41:24 +0100790 /* First check for errors */
Ulf Hanssonb63038d2011-12-13 16:51:04 +0100791 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
792 MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
Linus Walleij8cb28152011-01-24 15:22:13 +0100793 u32 remain, success;
Linus Walleijf20f8f22010-10-19 13:41:24 +0100794
Russell Kingc8ebae32011-01-11 19:35:53 +0000795 /* Terminate the DMA transfer */
Ulf Hansson653a7612013-01-21 21:29:34 +0100796 if (dma_inprogress(host)) {
Russell Kingc8ebae32011-01-11 19:35:53 +0000797 mmci_dma_data_error(host);
Ulf Hansson653a7612013-01-21 21:29:34 +0100798 mmci_dma_unmap(host, data);
799 }
Russell Kingc8ebae32011-01-11 19:35:53 +0000800
Russell Kingc8afc9d2011-02-04 09:19:46 +0000801 /*
802 * Calculate how far we are into the transfer. Note that
803 * the data counter gives the number of bytes transferred
804 * on the MMC bus, not on the host side. On reads, this
805 * can be as much as a FIFO-worth of data ahead. This
806 * matters for FIFO overruns only.
807 */
Linus Walleijf5a106d2011-01-27 17:44:34 +0100808 remain = readl(host->base + MMCIDATACNT);
Linus Walleij8cb28152011-01-24 15:22:13 +0100809 success = data->blksz * data->blocks - remain;
810
Russell Kingc8afc9d2011-02-04 09:19:46 +0000811 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
812 status, success);
Linus Walleij8cb28152011-01-24 15:22:13 +0100813 if (status & MCI_DATACRCFAIL) {
814 /* Last block was not successful */
Russell Kingc8afc9d2011-02-04 09:19:46 +0000815 success -= 1;
Pierre Ossman17b04292007-07-22 22:18:46 +0200816 data->error = -EILSEQ;
Linus Walleij8cb28152011-01-24 15:22:13 +0100817 } else if (status & MCI_DATATIMEOUT) {
Pierre Ossman17b04292007-07-22 22:18:46 +0200818 data->error = -ETIMEDOUT;
Linus Walleij757df742011-06-30 15:10:21 +0100819 } else if (status & MCI_STARTBITERR) {
820 data->error = -ECOMM;
Russell Kingc8afc9d2011-02-04 09:19:46 +0000821 } else if (status & MCI_TXUNDERRUN) {
Pierre Ossman17b04292007-07-22 22:18:46 +0200822 data->error = -EIO;
Russell Kingc8afc9d2011-02-04 09:19:46 +0000823 } else if (status & MCI_RXOVERRUN) {
824 if (success > host->variant->fifosize)
825 success -= host->variant->fifosize;
826 else
827 success = 0;
Linus Walleij8cb28152011-01-24 15:22:13 +0100828 data->error = -EIO;
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +0100829 }
Russell King51d43752011-01-27 10:56:52 +0000830 data->bytes_xfered = round_down(success, data->blksz);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700831 }
Linus Walleijf20f8f22010-10-19 13:41:24 +0100832
Linus Walleij8cb28152011-01-24 15:22:13 +0100833 if (status & MCI_DATABLOCKEND)
834 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
Linus Walleijf20f8f22010-10-19 13:41:24 +0100835
Russell Kingccff9b52011-01-30 21:03:50 +0000836 if (status & MCI_DATAEND || data->error) {
Russell Kingc8ebae32011-01-11 19:35:53 +0000837 if (dma_inprogress(host))
Ulf Hansson653a7612013-01-21 21:29:34 +0100838 mmci_dma_finalize(host, data);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700839 mmci_stop_data(host);
840
Linus Walleij8cb28152011-01-24 15:22:13 +0100841 if (!data->error)
842 /* The error clause is handled above, success! */
Russell King51d43752011-01-27 10:56:52 +0000843 data->bytes_xfered = data->blksz * data->blocks;
Linus Walleijf20f8f22010-10-19 13:41:24 +0100844
Linus Torvalds1da177e2005-04-16 15:20:36 -0700845 if (!data->stop) {
846 mmci_request_end(host, data->mrq);
847 } else {
848 mmci_start_command(host, data->stop, 0);
849 }
850 }
851}
852
853static void
854mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
855 unsigned int status)
856{
857 void __iomem *base = host->base;
858
859 host->cmd = NULL;
860
Linus Torvalds1da177e2005-04-16 15:20:36 -0700861 if (status & MCI_CMDTIMEOUT) {
Pierre Ossman17b04292007-07-22 22:18:46 +0200862 cmd->error = -ETIMEDOUT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700863 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
Pierre Ossman17b04292007-07-22 22:18:46 +0200864 cmd->error = -EILSEQ;
Russell King - ARM Linux9047b432011-01-11 16:35:56 +0000865 } else {
866 cmd->resp[0] = readl(base + MMCIRESPONSE0);
867 cmd->resp[1] = readl(base + MMCIRESPONSE1);
868 cmd->resp[2] = readl(base + MMCIRESPONSE2);
869 cmd->resp[3] = readl(base + MMCIRESPONSE3);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700870 }
871
Pierre Ossman17b04292007-07-22 22:18:46 +0200872 if (!cmd->data || cmd->error) {
Ulf Hansson3b6e3c72011-12-13 16:58:43 +0100873 if (host->data) {
874 /* Terminate the DMA transfer */
Ulf Hansson653a7612013-01-21 21:29:34 +0100875 if (dma_inprogress(host)) {
Ulf Hansson3b6e3c72011-12-13 16:58:43 +0100876 mmci_dma_data_error(host);
Ulf Hansson653a7612013-01-21 21:29:34 +0100877 mmci_dma_unmap(host, host->data);
878 }
Russell Kinge47c2222007-01-08 16:42:51 +0000879 mmci_stop_data(host);
Ulf Hansson3b6e3c72011-12-13 16:58:43 +0100880 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700881 mmci_request_end(host, cmd->mrq);
882 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
883 mmci_start_data(host, cmd->data);
884 }
885}
886
887static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
888{
889 void __iomem *base = host->base;
890 char *ptr = buffer;
891 u32 status;
Linus Walleij26eed9a2008-04-26 23:39:44 +0100892 int host_remain = host->size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700893
894 do {
Linus Walleij26eed9a2008-04-26 23:39:44 +0100895 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700896
897 if (count > remain)
898 count = remain;
899
900 if (count <= 0)
901 break;
902
Ulf Hansson393e5e22011-12-13 17:08:04 +0100903 /*
904 * SDIO especially may want to send something that is
905 * not divisible by 4 (as opposed to card sectors
906 * etc). Therefore make sure to always read the last bytes
907 * while only doing full 32-bit reads towards the FIFO.
908 */
909 if (unlikely(count & 0x3)) {
910 if (count < 4) {
911 unsigned char buf[4];
Davide Ciminaghi4b85da02012-12-10 14:47:21 +0100912 ioread32_rep(base + MMCIFIFO, buf, 1);
Ulf Hansson393e5e22011-12-13 17:08:04 +0100913 memcpy(ptr, buf, count);
914 } else {
Davide Ciminaghi4b85da02012-12-10 14:47:21 +0100915 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
Ulf Hansson393e5e22011-12-13 17:08:04 +0100916 count &= ~0x3;
917 }
918 } else {
Davide Ciminaghi4b85da02012-12-10 14:47:21 +0100919 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
Ulf Hansson393e5e22011-12-13 17:08:04 +0100920 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700921
922 ptr += count;
923 remain -= count;
Linus Walleij26eed9a2008-04-26 23:39:44 +0100924 host_remain -= count;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700925
926 if (remain == 0)
927 break;
928
929 status = readl(base + MMCISTATUS);
930 } while (status & MCI_RXDATAAVLBL);
931
932 return ptr - buffer;
933}
934
935static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
936{
Rabin Vincent8301bb62010-08-09 12:57:30 +0100937 struct variant_data *variant = host->variant;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700938 void __iomem *base = host->base;
939 char *ptr = buffer;
940
941 do {
942 unsigned int count, maxcnt;
943
Rabin Vincent8301bb62010-08-09 12:57:30 +0100944 maxcnt = status & MCI_TXFIFOEMPTY ?
945 variant->fifosize : variant->fifohalfsize;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700946 count = min(remain, maxcnt);
947
Linus Walleij34177802010-10-19 12:43:58 +0100948 /*
Linus Walleij34177802010-10-19 12:43:58 +0100949 * SDIO especially may want to send something that is
950 * not divisible by 4 (as opposed to card sectors
951 * etc), and the FIFO only accept full 32-bit writes.
952 * So compensate by adding +3 on the count, a single
953 * byte become a 32bit write, 7 bytes will be two
954 * 32bit writes etc.
955 */
Davide Ciminaghi4b85da02012-12-10 14:47:21 +0100956 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700957
958 ptr += count;
959 remain -= count;
960
961 if (remain == 0)
962 break;
963
964 status = readl(base + MMCISTATUS);
965 } while (status & MCI_TXFIFOHALFEMPTY);
966
967 return ptr - buffer;
968}
969
970/*
971 * PIO data transfer IRQ handler.
972 */
David Howells7d12e782006-10-05 14:55:46 +0100973static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700974{
975 struct mmci_host *host = dev_id;
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +0100976 struct sg_mapping_iter *sg_miter = &host->sg_miter;
Rabin Vincent8301bb62010-08-09 12:57:30 +0100977 struct variant_data *variant = host->variant;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700978 void __iomem *base = host->base;
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +0100979 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700980 u32 status;
981
982 status = readl(base + MMCISTATUS);
983
Linus Walleij64de0282010-02-19 01:09:10 +0100984 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700985
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +0100986 local_irq_save(flags);
987
Linus Torvalds1da177e2005-04-16 15:20:36 -0700988 do {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700989 unsigned int remain, len;
990 char *buffer;
991
992 /*
993 * For write, we only need to test the half-empty flag
994 * here - if the FIFO is completely empty, then by
995 * definition it is more than half empty.
996 *
997 * For read, check for data available.
998 */
999 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
1000 break;
1001
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +01001002 if (!sg_miter_next(sg_miter))
1003 break;
1004
1005 buffer = sg_miter->addr;
1006 remain = sg_miter->length;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001007
1008 len = 0;
1009 if (status & MCI_RXACTIVE)
1010 len = mmci_pio_read(host, buffer, remain);
1011 if (status & MCI_TXACTIVE)
1012 len = mmci_pio_write(host, buffer, remain, status);
1013
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +01001014 sg_miter->consumed = len;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001015
Linus Torvalds1da177e2005-04-16 15:20:36 -07001016 host->size -= len;
1017 remain -= len;
1018
1019 if (remain)
1020 break;
1021
Linus Torvalds1da177e2005-04-16 15:20:36 -07001022 status = readl(base + MMCISTATUS);
1023 } while (1);
1024
Rabin Vincent4ce1d6c2010-07-21 12:44:58 +01001025 sg_miter_stop(sg_miter);
1026
1027 local_irq_restore(flags);
1028
Linus Torvalds1da177e2005-04-16 15:20:36 -07001029 /*
Russell Kingc4d877c2011-01-27 09:50:13 +00001030 * If we have less than the fifo 'half-full' threshold to transfer,
1031 * trigger a PIO interrupt as soon as any data is available.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001032 */
Russell Kingc4d877c2011-01-27 09:50:13 +00001033 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
Linus Walleij2686b4b2010-10-19 12:39:48 +01001034 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001035
1036 /*
1037 * If we run out of data, disable the data IRQs; this
1038 * prevents a race where the FIFO becomes empty before
1039 * the chip itself has disabled the data path, and
1040 * stops us racing with our data end IRQ.
1041 */
1042 if (host->size == 0) {
Linus Walleij2686b4b2010-10-19 12:39:48 +01001043 mmci_set_mask1(host, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001044 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
1045 }
1046
1047 return IRQ_HANDLED;
1048}
1049
1050/*
1051 * Handle completion of command and data transfers.
1052 */
David Howells7d12e782006-10-05 14:55:46 +01001053static irqreturn_t mmci_irq(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001054{
1055 struct mmci_host *host = dev_id;
1056 u32 status;
1057 int ret = 0;
1058
1059 spin_lock(&host->lock);
1060
1061 do {
1062 struct mmc_command *cmd;
1063 struct mmc_data *data;
1064
1065 status = readl(host->base + MMCISTATUS);
Linus Walleij2686b4b2010-10-19 12:39:48 +01001066
1067 if (host->singleirq) {
1068 if (status & readl(host->base + MMCIMASK1))
1069 mmci_pio_irq(irq, dev_id);
1070
1071 status &= ~MCI_IRQ1MASK;
1072 }
1073
Linus Torvalds1da177e2005-04-16 15:20:36 -07001074 status &= readl(host->base + MMCIMASK0);
1075 writel(status, host->base + MMCICLEAR);
1076
Linus Walleij64de0282010-02-19 01:09:10 +01001077 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001078
1079 data = host->data;
Ulf Hanssonb63038d2011-12-13 16:51:04 +01001080 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
1081 MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND|
1082 MCI_DATABLOCKEND) && data)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001083 mmci_data_irq(host, data, status);
1084
1085 cmd = host->cmd;
1086 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
1087 mmci_cmd_irq(host, cmd, status);
1088
1089 ret = 1;
1090 } while (status);
1091
1092 spin_unlock(&host->lock);
1093
1094 return IRQ_RETVAL(ret);
1095}
1096
1097static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1098{
1099 struct mmci_host *host = mmc_priv(mmc);
Linus Walleij9e943022008-10-24 21:17:50 +01001100 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001101
1102 WARN_ON(host->mrq != NULL);
1103
Ulf Hansson653a7612013-01-21 21:29:34 +01001104 mrq->cmd->error = mmci_validate_data(host, mrq->data);
1105 if (mrq->cmd->error) {
Pierre Ossman255d01a2007-07-24 20:38:53 +02001106 mmc_request_done(mmc, mrq);
1107 return;
1108 }
1109
Russell King1c3be362011-08-14 09:17:05 +01001110 pm_runtime_get_sync(mmc_dev(mmc));
1111
Linus Walleij9e943022008-10-24 21:17:50 +01001112 spin_lock_irqsave(&host->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001113
1114 host->mrq = mrq;
1115
Per Forlin58c7ccb2011-07-01 18:55:24 +02001116 if (mrq->data)
1117 mmci_get_next_data(host, mrq->data);
1118
Linus Torvalds1da177e2005-04-16 15:20:36 -07001119 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
1120 mmci_start_data(host, mrq->data);
1121
1122 mmci_start_command(host, mrq->cmd, 0);
1123
Linus Walleij9e943022008-10-24 21:17:50 +01001124 spin_unlock_irqrestore(&host->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001125}
1126
1127static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1128{
1129 struct mmci_host *host = mmc_priv(mmc);
Ulf Hansson7d72a1d2011-12-13 16:54:55 +01001130 struct variant_data *variant = host->variant;
Linus Walleija6a64642009-09-14 12:56:14 +01001131 u32 pwr = 0;
1132 unsigned long flags;
Lee Jonesdb90f912013-05-03 12:52:12 +01001133 int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001134
Ulf Hansson2cd976c2011-12-13 17:01:11 +01001135 pm_runtime_get_sync(mmc_dev(mmc));
1136
Ulf Hanssonbc521812011-12-13 16:57:55 +01001137 if (host->plat->ios_handler &&
1138 host->plat->ios_handler(mmc_dev(mmc), ios))
1139 dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
1140
Linus Torvalds1da177e2005-04-16 15:20:36 -07001141 switch (ios->power_mode) {
1142 case MMC_POWER_OFF:
Ulf Hansson599c1d52013-01-07 16:22:50 +01001143 if (!IS_ERR(mmc->supply.vmmc))
1144 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
Lee Jones237fb5e2013-01-31 11:27:52 +00001145
1146 if (!IS_ERR(mmc->supply.vqmmc) &&
1147 regulator_is_enabled(mmc->supply.vqmmc))
1148 regulator_disable(mmc->supply.vqmmc);
1149
Linus Torvalds1da177e2005-04-16 15:20:36 -07001150 break;
1151 case MMC_POWER_UP:
Ulf Hansson599c1d52013-01-07 16:22:50 +01001152 if (!IS_ERR(mmc->supply.vmmc))
1153 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1154
Ulf Hansson7d72a1d2011-12-13 16:54:55 +01001155 /*
1156 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1157 * and instead uses MCI_PWR_ON so apply whatever value is
1158 * configured in the variant data.
1159 */
1160 pwr |= variant->pwrreg_powerup;
1161
1162 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001163 case MMC_POWER_ON:
Lee Jones237fb5e2013-01-31 11:27:52 +00001164 if (!IS_ERR(mmc->supply.vqmmc) &&
Lee Jonesdb90f912013-05-03 12:52:12 +01001165 !regulator_is_enabled(mmc->supply.vqmmc)) {
1166 ret = regulator_enable(mmc->supply.vqmmc);
1167 if (ret < 0)
1168 dev_err(mmc_dev(mmc),
1169 "failed to enable vqmmc regulator\n");
1170 }
Lee Jones237fb5e2013-01-31 11:27:52 +00001171
Linus Torvalds1da177e2005-04-16 15:20:36 -07001172 pwr |= MCI_PWR_ON;
1173 break;
1174 }
1175
Ulf Hansson4d1a3a02011-12-13 16:57:07 +01001176 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1177 /*
1178 * The ST Micro variant has some additional bits
1179 * indicating signal direction for the signals in
1180 * the SD/MMC bus and feedback-clock usage.
1181 */
1182 pwr |= host->plat->sigdir;
1183
1184 if (ios->bus_width == MMC_BUS_WIDTH_4)
1185 pwr &= ~MCI_ST_DATA74DIREN;
1186 else if (ios->bus_width == MMC_BUS_WIDTH_1)
1187 pwr &= (~MCI_ST_DATA74DIREN &
1188 ~MCI_ST_DATA31DIREN &
1189 ~MCI_ST_DATA2DIREN);
1190 }
1191
Linus Walleijcc30d602009-01-04 15:18:54 +01001192 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
Linus Walleijf17a1f02009-08-04 01:01:02 +01001193 if (host->hw_designer != AMBA_VENDOR_ST)
Linus Walleijcc30d602009-01-04 15:18:54 +01001194 pwr |= MCI_ROD;
1195 else {
1196 /*
1197 * The ST Micro variant use the ROD bit for something
1198 * else and only has OD (Open Drain).
1199 */
1200 pwr |= MCI_OD;
1201 }
1202 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001203
Ulf Hanssonf4670da2013-01-09 17:19:54 +01001204 /*
1205 * If clock = 0 and the variant requires the MMCIPOWER to be used for
1206 * gating the clock, the MCI_PWR_ON bit is cleared.
1207 */
1208 if (!ios->clock && variant->pwrreg_clkgate)
1209 pwr &= ~MCI_PWR_ON;
1210
Linus Walleija6a64642009-09-14 12:56:14 +01001211 spin_lock_irqsave(&host->lock, flags);
1212
1213 mmci_set_clkreg(host, ios->clock);
Ulf Hansson7437cfa2012-01-18 09:17:27 +01001214 mmci_write_pwrreg(host, pwr);
Linus Walleija6a64642009-09-14 12:56:14 +01001215
1216 spin_unlock_irqrestore(&host->lock, flags);
Ulf Hansson2cd976c2011-12-13 17:01:11 +01001217
Ulf Hansson2cd976c2011-12-13 17:01:11 +01001218 pm_runtime_mark_last_busy(mmc_dev(mmc));
1219 pm_runtime_put_autosuspend(mmc_dev(mmc));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001220}
1221
Russell King89001442009-07-09 15:16:07 +01001222static int mmci_get_ro(struct mmc_host *mmc)
1223{
1224 struct mmci_host *host = mmc_priv(mmc);
1225
1226 if (host->gpio_wp == -ENOSYS)
1227 return -ENOSYS;
1228
Linus Walleij18a063012010-09-12 12:56:44 +01001229 return gpio_get_value_cansleep(host->gpio_wp);
Russell King89001442009-07-09 15:16:07 +01001230}
1231
1232static int mmci_get_cd(struct mmc_host *mmc)
1233{
1234 struct mmci_host *host = mmc_priv(mmc);
Rabin Vincent29719442010-08-09 12:54:43 +01001235 struct mmci_platform_data *plat = host->plat;
Russell King89001442009-07-09 15:16:07 +01001236 unsigned int status;
1237
Rabin Vincent4b8caec2010-08-09 12:56:40 +01001238 if (host->gpio_cd == -ENOSYS) {
1239 if (!plat->status)
1240 return 1; /* Assume always present */
1241
Rabin Vincent29719442010-08-09 12:54:43 +01001242 status = plat->status(mmc_dev(host->mmc));
Rabin Vincent4b8caec2010-08-09 12:56:40 +01001243 } else
Linus Walleij18a063012010-09-12 12:56:44 +01001244 status = !!gpio_get_value_cansleep(host->gpio_cd)
1245 ^ plat->cd_invert;
Russell King89001442009-07-09 15:16:07 +01001246
Russell King74bc8092010-07-29 15:58:59 +01001247 /*
1248 * Use positive logic throughout - status is zero for no card,
1249 * non-zero for card inserted.
1250 */
1251 return status;
Russell King89001442009-07-09 15:16:07 +01001252}
1253
Rabin Vincent148b8b32010-08-09 12:55:48 +01001254static irqreturn_t mmci_cd_irq(int irq, void *dev_id)
1255{
1256 struct mmci_host *host = dev_id;
1257
1258 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1259
1260 return IRQ_HANDLED;
1261}
1262
David Brownellab7aefd2006-11-12 17:55:30 -08001263static const struct mmc_host_ops mmci_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001264 .request = mmci_request,
Per Forlin58c7ccb2011-07-01 18:55:24 +02001265 .pre_req = mmci_pre_request,
1266 .post_req = mmci_post_request,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001267 .set_ios = mmci_set_ios,
Russell King89001442009-07-09 15:16:07 +01001268 .get_ro = mmci_get_ro,
1269 .get_cd = mmci_get_cd,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001270};
1271
Lee Jones000bc9d2012-04-16 10:18:43 +01001272#ifdef CONFIG_OF
1273static void mmci_dt_populate_generic_pdata(struct device_node *np,
1274 struct mmci_platform_data *pdata)
1275{
1276 int bus_width = 0;
1277
Lee Jones9a597012012-04-12 16:51:13 +01001278 pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
Lee Jones9a597012012-04-12 16:51:13 +01001279 pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0);
Lee Jones000bc9d2012-04-16 10:18:43 +01001280
1281 if (of_get_property(np, "cd-inverted", NULL))
1282 pdata->cd_invert = true;
1283 else
1284 pdata->cd_invert = false;
1285
1286 of_property_read_u32(np, "max-frequency", &pdata->f_max);
1287 if (!pdata->f_max)
1288 pr_warn("%s has no 'max-frequency' property\n", np->full_name);
1289
1290 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
1291 pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED;
1292 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
1293 pdata->capabilities |= MMC_CAP_SD_HIGHSPEED;
1294
1295 of_property_read_u32(np, "bus-width", &bus_width);
1296 switch (bus_width) {
1297 case 0 :
1298 /* No bus-width supplied. */
1299 break;
1300 case 4 :
1301 pdata->capabilities |= MMC_CAP_4_BIT_DATA;
1302 break;
1303 case 8 :
1304 pdata->capabilities |= MMC_CAP_8_BIT_DATA;
1305 break;
1306 default :
1307 pr_warn("%s: Unsupported bus width\n", np->full_name);
1308 }
1309}
Lee Jonesc0a120a2012-05-08 13:59:38 +01001310#else
1311static void mmci_dt_populate_generic_pdata(struct device_node *np,
1312 struct mmci_platform_data *pdata)
1313{
1314 return;
1315}
Lee Jones000bc9d2012-04-16 10:18:43 +01001316#endif
1317
Bill Pembertonc3be1ef2012-11-19 13:23:06 -05001318static int mmci_probe(struct amba_device *dev,
Russell Kingaa25afa2011-02-19 15:55:00 +00001319 const struct amba_id *id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001320{
Linus Walleij6ef297f2009-09-22 14:29:36 +01001321 struct mmci_platform_data *plat = dev->dev.platform_data;
Lee Jones000bc9d2012-04-16 10:18:43 +01001322 struct device_node *np = dev->dev.of_node;
Rabin Vincent4956e102010-07-21 12:54:40 +01001323 struct variant_data *variant = id->data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001324 struct mmci_host *host;
1325 struct mmc_host *mmc;
1326 int ret;
1327
Lee Jones000bc9d2012-04-16 10:18:43 +01001328 /* Must have platform data or Device Tree. */
1329 if (!plat && !np) {
1330 dev_err(&dev->dev, "No plat data or DT found\n");
1331 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001332 }
1333
Lee Jonesb9b52912012-06-12 10:49:51 +01001334 if (!plat) {
1335 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
1336 if (!plat)
1337 return -ENOMEM;
1338 }
1339
Lee Jones000bc9d2012-04-16 10:18:43 +01001340 if (np)
1341 mmci_dt_populate_generic_pdata(np, plat);
1342
Linus Torvalds1da177e2005-04-16 15:20:36 -07001343 ret = amba_request_regions(dev, DRIVER_NAME);
1344 if (ret)
1345 goto out;
1346
1347 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1348 if (!mmc) {
1349 ret = -ENOMEM;
1350 goto rel_regions;
1351 }
1352
1353 host = mmc_priv(mmc);
Rabin Vincent4ea580f2009-04-17 08:44:19 +05301354 host->mmc = mmc;
Russell King012b7d32009-07-09 15:13:56 +01001355
Russell King89001442009-07-09 15:16:07 +01001356 host->gpio_wp = -ENOSYS;
1357 host->gpio_cd = -ENOSYS;
Rabin Vincent148b8b32010-08-09 12:55:48 +01001358 host->gpio_cd_irq = -1;
Russell King89001442009-07-09 15:16:07 +01001359
Russell King012b7d32009-07-09 15:13:56 +01001360 host->hw_designer = amba_manf(dev);
1361 host->hw_revision = amba_rev(dev);
Linus Walleij64de0282010-02-19 01:09:10 +01001362 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1363 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
Russell King012b7d32009-07-09 15:13:56 +01001364
Russell Kingee569c42008-11-30 17:38:14 +00001365 host->clk = clk_get(&dev->dev, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001366 if (IS_ERR(host->clk)) {
1367 ret = PTR_ERR(host->clk);
1368 host->clk = NULL;
1369 goto host_free;
1370 }
1371
Julia Lawallac940932012-08-26 16:00:59 +00001372 ret = clk_prepare_enable(host->clk);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001373 if (ret)
Russell Kinga8d35842006-01-03 18:41:37 +00001374 goto clk_free;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001375
1376 host->plat = plat;
Rabin Vincent4956e102010-07-21 12:54:40 +01001377 host->variant = variant;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001378 host->mclk = clk_get_rate(host->clk);
Linus Walleijc8df9a52008-04-29 09:34:07 +01001379 /*
1380 * According to the spec, mclk is max 100 MHz,
1381 * so we try to adjust the clock down to this,
1382 * (if possible).
1383 */
1384 if (host->mclk > 100000000) {
1385 ret = clk_set_rate(host->clk, 100000000);
1386 if (ret < 0)
1387 goto clk_disable;
1388 host->mclk = clk_get_rate(host->clk);
Linus Walleij64de0282010-02-19 01:09:10 +01001389 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1390 host->mclk);
Linus Walleijc8df9a52008-04-29 09:34:07 +01001391 }
Russell Kingc8ebae32011-01-11 19:35:53 +00001392 host->phybase = dev->res.start;
Linus Walleijdc890c22009-06-07 23:27:31 +01001393 host->base = ioremap(dev->res.start, resource_size(&dev->res));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001394 if (!host->base) {
1395 ret = -ENOMEM;
1396 goto clk_disable;
1397 }
1398
1399 mmc->ops = &mmci_ops;
Linus Walleij7f294e42011-07-08 09:57:15 +01001400 /*
1401 * The ARM and ST versions of the block have slightly different
1402 * clock divider equations which means that the minimum divider
1403 * differs too.
1404 */
1405 if (variant->st_clkdiv)
1406 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
1407 else
1408 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
Linus Walleij808d97c2010-04-08 07:39:38 +01001409 /*
1410 * If the platform data supplies a maximum operating
1411 * frequency, this takes precedence. Else, we fall back
1412 * to using the module parameter, which has a (low)
1413 * default value in case it is not specified. Either
1414 * value must not exceed the clock rate into the block,
1415 * of course.
1416 */
1417 if (plat->f_max)
1418 mmc->f_max = min(host->mclk, plat->f_max);
1419 else
1420 mmc->f_max = min(host->mclk, fmax);
Linus Walleij64de0282010-02-19 01:09:10 +01001421 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1422
Linus Walleija9a83782012-10-29 14:39:30 +01001423 host->pinctrl = devm_pinctrl_get(&dev->dev);
1424 if (IS_ERR(host->pinctrl)) {
1425 ret = PTR_ERR(host->pinctrl);
1426 goto clk_disable;
1427 }
1428
1429 host->pins_default = pinctrl_lookup_state(host->pinctrl,
1430 PINCTRL_STATE_DEFAULT);
1431
1432 /* enable pins to be muxed in and configured */
1433 if (!IS_ERR(host->pins_default)) {
1434 ret = pinctrl_select_state(host->pinctrl, host->pins_default);
1435 if (ret)
1436 dev_warn(&dev->dev, "could not set default pins\n");
1437 } else
1438 dev_warn(&dev->dev, "could not get default pinstate\n");
1439
Ulf Hansson599c1d52013-01-07 16:22:50 +01001440 /* Get regulators and the supported OCR mask */
1441 mmc_regulator_get_supply(mmc);
1442 if (!mmc->ocr_avail)
Linus Walleij34e84f32009-09-22 14:41:40 +01001443 mmc->ocr_avail = plat->ocr_mask;
Ulf Hansson599c1d52013-01-07 16:22:50 +01001444 else if (plat->ocr_mask)
1445 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1446
Linus Walleij9e6c82c2009-09-14 12:57:11 +01001447 mmc->caps = plat->capabilities;
Per Forlin5a092622011-11-14 12:02:28 +01001448 mmc->caps2 = plat->capabilities2;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001449
Ulf Hansson70be2082013-01-07 15:35:06 +01001450 /* We support these PM capabilities. */
1451 mmc->pm_caps = MMC_PM_KEEP_POWER;
1452
Linus Torvalds1da177e2005-04-16 15:20:36 -07001453 /*
1454 * We can do SGIO
1455 */
Martin K. Petersena36274e2010-09-10 01:33:59 -04001456 mmc->max_segs = NR_SG;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001457
1458 /*
Rabin Vincent08458ef2010-07-21 12:55:59 +01001459 * Since only a certain number of bits are valid in the data length
1460 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1461 * single request.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001462 */
Rabin Vincent08458ef2010-07-21 12:55:59 +01001463 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001464
1465 /*
1466 * Set the maximum segment size. Since we aren't doing DMA
1467 * (yet) we are only limited by the data length register.
1468 */
Pierre Ossman55db8902006-11-21 17:55:45 +01001469 mmc->max_seg_size = mmc->max_req_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001470
Pierre Ossmanfe4a3c72006-11-21 17:54:23 +01001471 /*
1472 * Block size can be up to 2048 bytes, but must be a power of two.
1473 */
Will Deacon8f7f6b72012-02-24 11:25:21 +00001474 mmc->max_blk_size = 1 << 11;
Pierre Ossmanfe4a3c72006-11-21 17:54:23 +01001475
Pierre Ossman55db8902006-11-21 17:55:45 +01001476 /*
Will Deacon8f7f6b72012-02-24 11:25:21 +00001477 * Limit the number of blocks transferred so that we don't overflow
1478 * the maximum request size.
Pierre Ossman55db8902006-11-21 17:55:45 +01001479 */
Will Deacon8f7f6b72012-02-24 11:25:21 +00001480 mmc->max_blk_count = mmc->max_req_size >> 11;
Pierre Ossman55db8902006-11-21 17:55:45 +01001481
Linus Torvalds1da177e2005-04-16 15:20:36 -07001482 spin_lock_init(&host->lock);
1483
1484 writel(0, host->base + MMCIMASK0);
1485 writel(0, host->base + MMCIMASK1);
1486 writel(0xfff, host->base + MMCICLEAR);
1487
Roland Stigge2805b9a2012-06-17 21:14:27 +01001488 if (plat->gpio_cd == -EPROBE_DEFER) {
1489 ret = -EPROBE_DEFER;
1490 goto err_gpio_cd;
1491 }
Russell King89001442009-07-09 15:16:07 +01001492 if (gpio_is_valid(plat->gpio_cd)) {
1493 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
1494 if (ret == 0)
1495 ret = gpio_direction_input(plat->gpio_cd);
1496 if (ret == 0)
1497 host->gpio_cd = plat->gpio_cd;
1498 else if (ret != -ENOSYS)
1499 goto err_gpio_cd;
Rabin Vincent148b8b32010-08-09 12:55:48 +01001500
Linus Walleij17ee0832011-05-05 17:23:10 +01001501 /*
1502 * A gpio pin that will detect cards when inserted and removed
1503 * will most likely want to trigger on the edges if it is
1504 * 0 when ejected and 1 when inserted (or mutatis mutandis
1505 * for the inverted case) so we request triggers on both
1506 * edges.
1507 */
Rabin Vincent148b8b32010-08-09 12:55:48 +01001508 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd),
Linus Walleij17ee0832011-05-05 17:23:10 +01001509 mmci_cd_irq,
1510 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1511 DRIVER_NAME " (cd)", host);
Rabin Vincent148b8b32010-08-09 12:55:48 +01001512 if (ret >= 0)
1513 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd);
Russell King89001442009-07-09 15:16:07 +01001514 }
Roland Stigge2805b9a2012-06-17 21:14:27 +01001515 if (plat->gpio_wp == -EPROBE_DEFER) {
1516 ret = -EPROBE_DEFER;
1517 goto err_gpio_wp;
1518 }
Russell King89001442009-07-09 15:16:07 +01001519 if (gpio_is_valid(plat->gpio_wp)) {
1520 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
1521 if (ret == 0)
1522 ret = gpio_direction_input(plat->gpio_wp);
1523 if (ret == 0)
1524 host->gpio_wp = plat->gpio_wp;
1525 else if (ret != -ENOSYS)
1526 goto err_gpio_wp;
1527 }
1528
Rabin Vincent4b8caec2010-08-09 12:56:40 +01001529 if ((host->plat->status || host->gpio_cd != -ENOSYS)
1530 && host->gpio_cd_irq < 0)
Rabin Vincent148b8b32010-08-09 12:55:48 +01001531 mmc->caps |= MMC_CAP_NEEDS_POLL;
1532
Thomas Gleixnerdace1452006-07-01 19:29:38 -07001533 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001534 if (ret)
1535 goto unmap;
1536
Russell Kingdfb851852012-05-03 11:33:15 +01001537 if (!dev->irq[1])
Linus Walleij2686b4b2010-10-19 12:39:48 +01001538 host->singleirq = true;
1539 else {
1540 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED,
1541 DRIVER_NAME " (pio)", host);
1542 if (ret)
1543 goto irq0_free;
1544 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001545
Linus Walleij8cb28152011-01-24 15:22:13 +01001546 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001547
1548 amba_set_drvdata(dev, mmc);
1549
Russell Kingc8ebae32011-01-11 19:35:53 +00001550 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1551 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1552 amba_rev(dev), (unsigned long long)dev->res.start,
1553 dev->irq[0], dev->irq[1]);
1554
1555 mmci_dma_setup(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001556
Ulf Hansson2cd976c2011-12-13 17:01:11 +01001557 pm_runtime_set_autosuspend_delay(&dev->dev, 50);
1558 pm_runtime_use_autosuspend(&dev->dev);
Russell King1c3be362011-08-14 09:17:05 +01001559 pm_runtime_put(&dev->dev);
1560
Russell King8c11a942010-12-28 19:40:40 +00001561 mmc_add_host(mmc);
1562
Linus Torvalds1da177e2005-04-16 15:20:36 -07001563 return 0;
1564
1565 irq0_free:
1566 free_irq(dev->irq[0], host);
1567 unmap:
Russell King89001442009-07-09 15:16:07 +01001568 if (host->gpio_wp != -ENOSYS)
1569 gpio_free(host->gpio_wp);
1570 err_gpio_wp:
Rabin Vincent148b8b32010-08-09 12:55:48 +01001571 if (host->gpio_cd_irq >= 0)
1572 free_irq(host->gpio_cd_irq, host);
Russell King89001442009-07-09 15:16:07 +01001573 if (host->gpio_cd != -ENOSYS)
1574 gpio_free(host->gpio_cd);
1575 err_gpio_cd:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001576 iounmap(host->base);
1577 clk_disable:
Julia Lawallac940932012-08-26 16:00:59 +00001578 clk_disable_unprepare(host->clk);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001579 clk_free:
1580 clk_put(host->clk);
1581 host_free:
1582 mmc_free_host(mmc);
1583 rel_regions:
1584 amba_release_regions(dev);
1585 out:
1586 return ret;
1587}
1588
Bill Pemberton6e0ee712012-11-19 13:26:03 -05001589static int mmci_remove(struct amba_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001590{
1591 struct mmc_host *mmc = amba_get_drvdata(dev);
1592
1593 amba_set_drvdata(dev, NULL);
1594
1595 if (mmc) {
1596 struct mmci_host *host = mmc_priv(mmc);
1597
Russell King1c3be362011-08-14 09:17:05 +01001598 /*
1599 * Undo pm_runtime_put() in probe. We use the _sync
1600 * version here so that we can access the primecell.
1601 */
1602 pm_runtime_get_sync(&dev->dev);
1603
Linus Torvalds1da177e2005-04-16 15:20:36 -07001604 mmc_remove_host(mmc);
1605
1606 writel(0, host->base + MMCIMASK0);
1607 writel(0, host->base + MMCIMASK1);
1608
1609 writel(0, host->base + MMCICOMMAND);
1610 writel(0, host->base + MMCIDATACTRL);
1611
Russell Kingc8ebae32011-01-11 19:35:53 +00001612 mmci_dma_release(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001613 free_irq(dev->irq[0], host);
Linus Walleij2686b4b2010-10-19 12:39:48 +01001614 if (!host->singleirq)
1615 free_irq(dev->irq[1], host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001616
Russell King89001442009-07-09 15:16:07 +01001617 if (host->gpio_wp != -ENOSYS)
1618 gpio_free(host->gpio_wp);
Rabin Vincent148b8b32010-08-09 12:55:48 +01001619 if (host->gpio_cd_irq >= 0)
1620 free_irq(host->gpio_cd_irq, host);
Russell King89001442009-07-09 15:16:07 +01001621 if (host->gpio_cd != -ENOSYS)
1622 gpio_free(host->gpio_cd);
1623
Linus Torvalds1da177e2005-04-16 15:20:36 -07001624 iounmap(host->base);
Julia Lawallac940932012-08-26 16:00:59 +00001625 clk_disable_unprepare(host->clk);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001626 clk_put(host->clk);
1627
1628 mmc_free_host(mmc);
1629
1630 amba_release_regions(dev);
1631 }
1632
1633 return 0;
1634}
1635
Ulf Hansson48fa7002011-12-13 16:59:34 +01001636#ifdef CONFIG_SUSPEND
1637static int mmci_suspend(struct device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001638{
Ulf Hansson48fa7002011-12-13 16:59:34 +01001639 struct amba_device *adev = to_amba_device(dev);
1640 struct mmc_host *mmc = amba_get_drvdata(adev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001641 int ret = 0;
1642
1643 if (mmc) {
1644 struct mmci_host *host = mmc_priv(mmc);
1645
Matt Fleming1a13f8f2010-05-26 14:42:08 -07001646 ret = mmc_suspend_host(mmc);
Ulf Hansson2cd976c2011-12-13 17:01:11 +01001647 if (ret == 0) {
1648 pm_runtime_get_sync(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001649 writel(0, host->base + MMCIMASK0);
Ulf Hansson2cd976c2011-12-13 17:01:11 +01001650 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001651 }
1652
1653 return ret;
1654}
1655
Ulf Hansson48fa7002011-12-13 16:59:34 +01001656static int mmci_resume(struct device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001657{
Ulf Hansson48fa7002011-12-13 16:59:34 +01001658 struct amba_device *adev = to_amba_device(dev);
1659 struct mmc_host *mmc = amba_get_drvdata(adev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001660 int ret = 0;
1661
1662 if (mmc) {
1663 struct mmci_host *host = mmc_priv(mmc);
1664
1665 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
Ulf Hansson2cd976c2011-12-13 17:01:11 +01001666 pm_runtime_put(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001667
1668 ret = mmc_resume_host(mmc);
1669 }
1670
1671 return ret;
1672}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001673#endif
1674
Ulf Hansson82592932013-01-09 11:15:26 +01001675#ifdef CONFIG_PM_RUNTIME
1676static int mmci_runtime_suspend(struct device *dev)
1677{
1678 struct amba_device *adev = to_amba_device(dev);
1679 struct mmc_host *mmc = amba_get_drvdata(adev);
1680
1681 if (mmc) {
1682 struct mmci_host *host = mmc_priv(mmc);
1683 clk_disable_unprepare(host->clk);
1684 }
1685
1686 return 0;
1687}
1688
1689static int mmci_runtime_resume(struct device *dev)
1690{
1691 struct amba_device *adev = to_amba_device(dev);
1692 struct mmc_host *mmc = amba_get_drvdata(adev);
1693
1694 if (mmc) {
1695 struct mmci_host *host = mmc_priv(mmc);
1696 clk_prepare_enable(host->clk);
1697 }
1698
1699 return 0;
1700}
1701#endif
1702
Ulf Hansson48fa7002011-12-13 16:59:34 +01001703static const struct dev_pm_ops mmci_dev_pm_ops = {
1704 SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume)
Ulf Hansson82592932013-01-09 11:15:26 +01001705 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL)
Ulf Hansson48fa7002011-12-13 16:59:34 +01001706};
1707
Linus Torvalds1da177e2005-04-16 15:20:36 -07001708static struct amba_id mmci_ids[] = {
1709 {
1710 .id = 0x00041180,
Pawel Moll768fbc12011-03-11 17:18:07 +00001711 .mask = 0xff0fffff,
Rabin Vincent4956e102010-07-21 12:54:40 +01001712 .data = &variant_arm,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001713 },
1714 {
Pawel Moll768fbc12011-03-11 17:18:07 +00001715 .id = 0x01041180,
1716 .mask = 0xff0fffff,
1717 .data = &variant_arm_extended_fifo,
1718 },
1719 {
Pawel Moll3a372982013-01-24 14:12:45 +01001720 .id = 0x02041180,
1721 .mask = 0xff0fffff,
1722 .data = &variant_arm_extended_fifo_hwfc,
1723 },
1724 {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001725 .id = 0x00041181,
1726 .mask = 0x000fffff,
Rabin Vincent4956e102010-07-21 12:54:40 +01001727 .data = &variant_arm,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001728 },
Linus Walleijcc30d602009-01-04 15:18:54 +01001729 /* ST Micro variants */
1730 {
1731 .id = 0x00180180,
1732 .mask = 0x00ffffff,
Rabin Vincent4956e102010-07-21 12:54:40 +01001733 .data = &variant_u300,
Linus Walleijcc30d602009-01-04 15:18:54 +01001734 },
1735 {
Linus Walleij34fd4212012-04-10 17:43:59 +01001736 .id = 0x10180180,
1737 .mask = 0xf0ffffff,
1738 .data = &variant_nomadik,
1739 },
1740 {
Linus Walleijcc30d602009-01-04 15:18:54 +01001741 .id = 0x00280180,
1742 .mask = 0x00ffffff,
Rabin Vincent4956e102010-07-21 12:54:40 +01001743 .data = &variant_u300,
1744 },
1745 {
1746 .id = 0x00480180,
Philippe Langlais1784b152011-03-25 08:51:52 +01001747 .mask = 0xf0ffffff,
Rabin Vincent4956e102010-07-21 12:54:40 +01001748 .data = &variant_ux500,
Linus Walleijcc30d602009-01-04 15:18:54 +01001749 },
Philippe Langlais1784b152011-03-25 08:51:52 +01001750 {
1751 .id = 0x10480180,
1752 .mask = 0xf0ffffff,
1753 .data = &variant_ux500v2,
1754 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001755 { 0, 0 },
1756};
1757
Dave Martin9f998352011-10-05 15:15:21 +01001758MODULE_DEVICE_TABLE(amba, mmci_ids);
1759
Linus Torvalds1da177e2005-04-16 15:20:36 -07001760static struct amba_driver mmci_driver = {
1761 .drv = {
1762 .name = DRIVER_NAME,
Ulf Hansson48fa7002011-12-13 16:59:34 +01001763 .pm = &mmci_dev_pm_ops,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001764 },
1765 .probe = mmci_probe,
Bill Pemberton0433c142012-11-19 13:20:26 -05001766 .remove = mmci_remove,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001767 .id_table = mmci_ids,
1768};
1769
viresh kumar9e5ed092012-03-15 10:40:38 +01001770module_amba_driver(mmci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001771
Linus Torvalds1da177e2005-04-16 15:20:36 -07001772module_param(fmax, uint, 0444);
1773
1774MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1775MODULE_LICENSE("GPL");