Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Pierre Ossman | 70f1048 | 2007-07-11 20:04:50 +0200 | [diff] [blame] | 2 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 5 | * Copyright (C) 2010 ST-Ericsson SA |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11 | #include <linux/module.h> |
| 12 | #include <linux/moduleparam.h> |
| 13 | #include <linux/init.h> |
| 14 | #include <linux/ioport.h> |
| 15 | #include <linux/device.h> |
| 16 | #include <linux/interrupt.h> |
Russell King | 613b152 | 2011-01-30 21:06:53 +0000 | [diff] [blame] | 17 | #include <linux/kernel.h> |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 18 | #include <linux/slab.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 19 | #include <linux/delay.h> |
| 20 | #include <linux/err.h> |
| 21 | #include <linux/highmem.h> |
Nicolas Pitre | 019a5f5 | 2007-10-11 01:06:03 -0400 | [diff] [blame] | 22 | #include <linux/log2.h> |
Ulf Hansson | 70be208 | 2013-01-07 15:35:06 +0100 | [diff] [blame] | 23 | #include <linux/mmc/pm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | #include <linux/mmc/host.h> |
Linus Walleij | 3417780 | 2010-10-19 12:43:58 +0100 | [diff] [blame] | 25 | #include <linux/mmc/card.h> |
Russell King | a62c80e | 2006-01-07 13:52:45 +0000 | [diff] [blame] | 26 | #include <linux/amba/bus.h> |
Russell King | f8ce254 | 2006-01-07 16:15:52 +0000 | [diff] [blame] | 27 | #include <linux/clk.h> |
Jens Axboe | bd6dee6 | 2007-10-24 09:01:09 +0200 | [diff] [blame] | 28 | #include <linux/scatterlist.h> |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 29 | #include <linux/gpio.h> |
Lee Jones | 9a59701 | 2012-04-12 16:51:13 +0100 | [diff] [blame] | 30 | #include <linux/of_gpio.h> |
Linus Walleij | 34e84f3 | 2009-09-22 14:41:40 +0100 | [diff] [blame] | 31 | #include <linux/regulator/consumer.h> |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 32 | #include <linux/dmaengine.h> |
| 33 | #include <linux/dma-mapping.h> |
| 34 | #include <linux/amba/mmci.h> |
Russell King | 1c3be36 | 2011-08-14 09:17:05 +0100 | [diff] [blame] | 35 | #include <linux/pm_runtime.h> |
Viresh Kumar | 258aea7 | 2012-02-01 16:12:19 +0530 | [diff] [blame] | 36 | #include <linux/types.h> |
Linus Walleij | a9a8378 | 2012-10-29 14:39:30 +0100 | [diff] [blame] | 37 | #include <linux/pinctrl/consumer.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | |
Russell King | 7b09cda | 2005-07-01 12:02:59 +0100 | [diff] [blame] | 39 | #include <asm/div64.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 40 | #include <asm/io.h> |
Russell King | c6b8fda | 2005-10-28 14:05:16 +0100 | [diff] [blame] | 41 | #include <asm/sizes.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 42 | |
| 43 | #include "mmci.h" |
| 44 | |
| 45 | #define DRIVER_NAME "mmci-pl18x" |
| 46 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | static unsigned int fmax = 515633; |
| 48 | |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 49 | /** |
| 50 | * struct variant_data - MMCI variant-specific quirks |
| 51 | * @clkreg: default value for MCICLOCK register |
Rabin Vincent | 4380c14 | 2010-07-21 12:55:18 +0100 | [diff] [blame] | 52 | * @clkreg_enable: enable value for MMCICLOCK register |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 53 | * @datalength_bits: number of bits in the MMCIDATALENGTH register |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 54 | * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY |
| 55 | * is asserted (likewise for RX) |
| 56 | * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY |
| 57 | * is asserted (likewise for RX) |
Linus Walleij | 3417780 | 2010-10-19 12:43:58 +0100 | [diff] [blame] | 58 | * @sdio: variant supports SDIO |
Linus Walleij | b70a67f | 2010-12-06 09:24:14 +0100 | [diff] [blame] | 59 | * @st_clkdiv: true if using a ST-specific clock divider algorithm |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 60 | * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 61 | * @pwrreg_powerup: power up value for MMCIPOWER register |
Ulf Hansson | 4d1a3a0 | 2011-12-13 16:57:07 +0100 | [diff] [blame] | 62 | * @signal_direction: input/out direction of bus signals can be indicated |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 63 | * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 64 | */ |
| 65 | struct variant_data { |
| 66 | unsigned int clkreg; |
Rabin Vincent | 4380c14 | 2010-07-21 12:55:18 +0100 | [diff] [blame] | 67 | unsigned int clkreg_enable; |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 68 | unsigned int datalength_bits; |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 69 | unsigned int fifosize; |
| 70 | unsigned int fifohalfsize; |
Linus Walleij | 3417780 | 2010-10-19 12:43:58 +0100 | [diff] [blame] | 71 | bool sdio; |
Linus Walleij | b70a67f | 2010-12-06 09:24:14 +0100 | [diff] [blame] | 72 | bool st_clkdiv; |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 73 | bool blksz_datactrl16; |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 74 | u32 pwrreg_powerup; |
Ulf Hansson | 4d1a3a0 | 2011-12-13 16:57:07 +0100 | [diff] [blame] | 75 | bool signal_direction; |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 76 | bool pwrreg_clkgate; |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 77 | }; |
| 78 | |
| 79 | static struct variant_data variant_arm = { |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 80 | .fifosize = 16 * 4, |
| 81 | .fifohalfsize = 8 * 4, |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 82 | .datalength_bits = 16, |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 83 | .pwrreg_powerup = MCI_PWR_UP, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 84 | }; |
| 85 | |
Pawel Moll | 768fbc1 | 2011-03-11 17:18:07 +0000 | [diff] [blame] | 86 | static struct variant_data variant_arm_extended_fifo = { |
| 87 | .fifosize = 128 * 4, |
| 88 | .fifohalfsize = 64 * 4, |
| 89 | .datalength_bits = 16, |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 90 | .pwrreg_powerup = MCI_PWR_UP, |
Pawel Moll | 768fbc1 | 2011-03-11 17:18:07 +0000 | [diff] [blame] | 91 | }; |
| 92 | |
Pawel Moll | 3a37298 | 2013-01-24 14:12:45 +0100 | [diff] [blame] | 93 | static struct variant_data variant_arm_extended_fifo_hwfc = { |
| 94 | .fifosize = 128 * 4, |
| 95 | .fifohalfsize = 64 * 4, |
| 96 | .clkreg_enable = MCI_ARM_HWFCEN, |
| 97 | .datalength_bits = 16, |
| 98 | .pwrreg_powerup = MCI_PWR_UP, |
| 99 | }; |
| 100 | |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 101 | static struct variant_data variant_u300 = { |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 102 | .fifosize = 16 * 4, |
| 103 | .fifohalfsize = 8 * 4, |
Linus Walleij | 49ac215 | 2011-03-04 14:54:16 +0100 | [diff] [blame] | 104 | .clkreg_enable = MCI_ST_U300_HWFCEN, |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 105 | .datalength_bits = 16, |
Linus Walleij | 3417780 | 2010-10-19 12:43:58 +0100 | [diff] [blame] | 106 | .sdio = true, |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 107 | .pwrreg_powerup = MCI_PWR_ON, |
Ulf Hansson | 4d1a3a0 | 2011-12-13 16:57:07 +0100 | [diff] [blame] | 108 | .signal_direction = true, |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 109 | .pwrreg_clkgate = true, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 110 | }; |
| 111 | |
Linus Walleij | 34fd421 | 2012-04-10 17:43:59 +0100 | [diff] [blame] | 112 | static struct variant_data variant_nomadik = { |
| 113 | .fifosize = 16 * 4, |
| 114 | .fifohalfsize = 8 * 4, |
| 115 | .clkreg = MCI_CLK_ENABLE, |
| 116 | .datalength_bits = 24, |
| 117 | .sdio = true, |
| 118 | .st_clkdiv = true, |
| 119 | .pwrreg_powerup = MCI_PWR_ON, |
| 120 | .signal_direction = true, |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 121 | .pwrreg_clkgate = true, |
Linus Walleij | 34fd421 | 2012-04-10 17:43:59 +0100 | [diff] [blame] | 122 | }; |
| 123 | |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 124 | static struct variant_data variant_ux500 = { |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 125 | .fifosize = 30 * 4, |
| 126 | .fifohalfsize = 8 * 4, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 127 | .clkreg = MCI_CLK_ENABLE, |
Linus Walleij | 49ac215 | 2011-03-04 14:54:16 +0100 | [diff] [blame] | 128 | .clkreg_enable = MCI_ST_UX500_HWFCEN, |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 129 | .datalength_bits = 24, |
Linus Walleij | 3417780 | 2010-10-19 12:43:58 +0100 | [diff] [blame] | 130 | .sdio = true, |
Linus Walleij | b70a67f | 2010-12-06 09:24:14 +0100 | [diff] [blame] | 131 | .st_clkdiv = true, |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 132 | .pwrreg_powerup = MCI_PWR_ON, |
Ulf Hansson | 4d1a3a0 | 2011-12-13 16:57:07 +0100 | [diff] [blame] | 133 | .signal_direction = true, |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 134 | .pwrreg_clkgate = true, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 135 | }; |
Linus Walleij | b70a67f | 2010-12-06 09:24:14 +0100 | [diff] [blame] | 136 | |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 137 | static struct variant_data variant_ux500v2 = { |
| 138 | .fifosize = 30 * 4, |
| 139 | .fifohalfsize = 8 * 4, |
| 140 | .clkreg = MCI_CLK_ENABLE, |
| 141 | .clkreg_enable = MCI_ST_UX500_HWFCEN, |
| 142 | .datalength_bits = 24, |
| 143 | .sdio = true, |
| 144 | .st_clkdiv = true, |
| 145 | .blksz_datactrl16 = true, |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 146 | .pwrreg_powerup = MCI_PWR_ON, |
Ulf Hansson | 4d1a3a0 | 2011-12-13 16:57:07 +0100 | [diff] [blame] | 147 | .signal_direction = true, |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 148 | .pwrreg_clkgate = true, |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 149 | }; |
| 150 | |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 151 | /* |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 152 | * Validate mmc prerequisites |
| 153 | */ |
| 154 | static int mmci_validate_data(struct mmci_host *host, |
| 155 | struct mmc_data *data) |
| 156 | { |
| 157 | if (!data) |
| 158 | return 0; |
| 159 | |
| 160 | if (!is_power_of_2(data->blksz)) { |
| 161 | dev_err(mmc_dev(host->mmc), |
| 162 | "unsupported block size (%d bytes)\n", data->blksz); |
| 163 | return -EINVAL; |
| 164 | } |
| 165 | |
| 166 | return 0; |
| 167 | } |
| 168 | |
| 169 | /* |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 170 | * This must be called with host->lock held |
| 171 | */ |
Ulf Hansson | 7437cfa | 2012-01-18 09:17:27 +0100 | [diff] [blame] | 172 | static void mmci_write_clkreg(struct mmci_host *host, u32 clk) |
| 173 | { |
| 174 | if (host->clk_reg != clk) { |
| 175 | host->clk_reg = clk; |
| 176 | writel(clk, host->base + MMCICLOCK); |
| 177 | } |
| 178 | } |
| 179 | |
| 180 | /* |
| 181 | * This must be called with host->lock held |
| 182 | */ |
| 183 | static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) |
| 184 | { |
| 185 | if (host->pwr_reg != pwr) { |
| 186 | host->pwr_reg = pwr; |
| 187 | writel(pwr, host->base + MMCIPOWER); |
| 188 | } |
| 189 | } |
| 190 | |
| 191 | /* |
| 192 | * This must be called with host->lock held |
| 193 | */ |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 194 | static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) |
| 195 | { |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 196 | struct variant_data *variant = host->variant; |
| 197 | u32 clk = variant->clkreg; |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 198 | |
| 199 | if (desired) { |
| 200 | if (desired >= host->mclk) { |
Linus Walleij | 991a86e | 2010-12-10 09:35:53 +0100 | [diff] [blame] | 201 | clk = MCI_CLK_BYPASS; |
Linus Walleij | 399bc48 | 2011-04-01 07:59:17 +0100 | [diff] [blame] | 202 | if (variant->st_clkdiv) |
| 203 | clk |= MCI_ST_UX500_NEG_EDGE; |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 204 | host->cclk = host->mclk; |
Linus Walleij | b70a67f | 2010-12-06 09:24:14 +0100 | [diff] [blame] | 205 | } else if (variant->st_clkdiv) { |
| 206 | /* |
| 207 | * DB8500 TRM says f = mclk / (clkdiv + 2) |
| 208 | * => clkdiv = (mclk / f) - 2 |
| 209 | * Round the divider up so we don't exceed the max |
| 210 | * frequency |
| 211 | */ |
| 212 | clk = DIV_ROUND_UP(host->mclk, desired) - 2; |
| 213 | if (clk >= 256) |
| 214 | clk = 255; |
| 215 | host->cclk = host->mclk / (clk + 2); |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 216 | } else { |
Linus Walleij | b70a67f | 2010-12-06 09:24:14 +0100 | [diff] [blame] | 217 | /* |
| 218 | * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) |
| 219 | * => clkdiv = mclk / (2 * f) - 1 |
| 220 | */ |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 221 | clk = host->mclk / (2 * desired) - 1; |
| 222 | if (clk >= 256) |
| 223 | clk = 255; |
| 224 | host->cclk = host->mclk / (2 * (clk + 1)); |
| 225 | } |
Rabin Vincent | 4380c14 | 2010-07-21 12:55:18 +0100 | [diff] [blame] | 226 | |
| 227 | clk |= variant->clkreg_enable; |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 228 | clk |= MCI_CLK_ENABLE; |
| 229 | /* This hasn't proven to be worthwhile */ |
| 230 | /* clk |= MCI_CLK_PWRSAVE; */ |
| 231 | } |
| 232 | |
Linus Walleij | 9e6c82c | 2009-09-14 12:57:11 +0100 | [diff] [blame] | 233 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
Linus Walleij | 771dc15 | 2010-04-08 07:38:52 +0100 | [diff] [blame] | 234 | clk |= MCI_4BIT_BUS; |
| 235 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) |
| 236 | clk |= MCI_ST_8BIT_BUS; |
Linus Walleij | 9e6c82c | 2009-09-14 12:57:11 +0100 | [diff] [blame] | 237 | |
Ulf Hansson | 6dbb6ee | 2013-01-07 15:30:44 +0100 | [diff] [blame] | 238 | if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) |
| 239 | clk |= MCI_ST_UX500_NEG_EDGE; |
| 240 | |
Ulf Hansson | 7437cfa | 2012-01-18 09:17:27 +0100 | [diff] [blame] | 241 | mmci_write_clkreg(host, clk); |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 242 | } |
| 243 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 244 | static void |
| 245 | mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) |
| 246 | { |
| 247 | writel(0, host->base + MMCICOMMAND); |
| 248 | |
Russell King | e47c222 | 2007-01-08 16:42:51 +0000 | [diff] [blame] | 249 | BUG_ON(host->data); |
| 250 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 251 | host->mrq = NULL; |
| 252 | host->cmd = NULL; |
| 253 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 254 | mmc_request_done(host->mmc, mrq); |
Ulf Hansson | 2cd976c | 2011-12-13 17:01:11 +0100 | [diff] [blame] | 255 | |
| 256 | pm_runtime_mark_last_busy(mmc_dev(host->mmc)); |
| 257 | pm_runtime_put_autosuspend(mmc_dev(host->mmc)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 258 | } |
| 259 | |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 260 | static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) |
| 261 | { |
| 262 | void __iomem *base = host->base; |
| 263 | |
| 264 | if (host->singleirq) { |
| 265 | unsigned int mask0 = readl(base + MMCIMASK0); |
| 266 | |
| 267 | mask0 &= ~MCI_IRQ1MASK; |
| 268 | mask0 |= mask; |
| 269 | |
| 270 | writel(mask0, base + MMCIMASK0); |
| 271 | } |
| 272 | |
| 273 | writel(mask, base + MMCIMASK1); |
| 274 | } |
| 275 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 276 | static void mmci_stop_data(struct mmci_host *host) |
| 277 | { |
| 278 | writel(0, host->base + MMCIDATACTRL); |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 279 | mmci_set_mask1(host, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 280 | host->data = NULL; |
| 281 | } |
| 282 | |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 283 | static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) |
| 284 | { |
| 285 | unsigned int flags = SG_MITER_ATOMIC; |
| 286 | |
| 287 | if (data->flags & MMC_DATA_READ) |
| 288 | flags |= SG_MITER_TO_SG; |
| 289 | else |
| 290 | flags |= SG_MITER_FROM_SG; |
| 291 | |
| 292 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); |
| 293 | } |
| 294 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 295 | /* |
| 296 | * All the DMA operation mode stuff goes inside this ifdef. |
| 297 | * This assumes that you have a generic DMA device interface, |
| 298 | * no custom DMA interfaces are supported. |
| 299 | */ |
| 300 | #ifdef CONFIG_DMA_ENGINE |
Bill Pemberton | c3be1ef | 2012-11-19 13:23:06 -0500 | [diff] [blame] | 301 | static void mmci_dma_setup(struct mmci_host *host) |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 302 | { |
| 303 | struct mmci_platform_data *plat = host->plat; |
| 304 | const char *rxname, *txname; |
| 305 | dma_cap_mask_t mask; |
| 306 | |
| 307 | if (!plat || !plat->dma_filter) { |
| 308 | dev_info(mmc_dev(host->mmc), "no DMA platform data\n"); |
| 309 | return; |
| 310 | } |
| 311 | |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 312 | /* initialize pre request cookie */ |
| 313 | host->next_data.cookie = 1; |
| 314 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 315 | /* Try to acquire a generic DMA engine slave channel */ |
| 316 | dma_cap_zero(mask); |
| 317 | dma_cap_set(DMA_SLAVE, mask); |
| 318 | |
| 319 | /* |
| 320 | * If only an RX channel is specified, the driver will |
| 321 | * attempt to use it bidirectionally, however if it is |
| 322 | * is specified but cannot be located, DMA will be disabled. |
| 323 | */ |
| 324 | if (plat->dma_rx_param) { |
| 325 | host->dma_rx_channel = dma_request_channel(mask, |
| 326 | plat->dma_filter, |
| 327 | plat->dma_rx_param); |
| 328 | /* E.g if no DMA hardware is present */ |
| 329 | if (!host->dma_rx_channel) |
| 330 | dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); |
| 331 | } |
| 332 | |
| 333 | if (plat->dma_tx_param) { |
| 334 | host->dma_tx_channel = dma_request_channel(mask, |
| 335 | plat->dma_filter, |
| 336 | plat->dma_tx_param); |
| 337 | if (!host->dma_tx_channel) |
| 338 | dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); |
| 339 | } else { |
| 340 | host->dma_tx_channel = host->dma_rx_channel; |
| 341 | } |
| 342 | |
| 343 | if (host->dma_rx_channel) |
| 344 | rxname = dma_chan_name(host->dma_rx_channel); |
| 345 | else |
| 346 | rxname = "none"; |
| 347 | |
| 348 | if (host->dma_tx_channel) |
| 349 | txname = dma_chan_name(host->dma_tx_channel); |
| 350 | else |
| 351 | txname = "none"; |
| 352 | |
| 353 | dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", |
| 354 | rxname, txname); |
| 355 | |
| 356 | /* |
| 357 | * Limit the maximum segment size in any SG entry according to |
| 358 | * the parameters of the DMA engine device. |
| 359 | */ |
| 360 | if (host->dma_tx_channel) { |
| 361 | struct device *dev = host->dma_tx_channel->device->dev; |
| 362 | unsigned int max_seg_size = dma_get_max_seg_size(dev); |
| 363 | |
| 364 | if (max_seg_size < host->mmc->max_seg_size) |
| 365 | host->mmc->max_seg_size = max_seg_size; |
| 366 | } |
| 367 | if (host->dma_rx_channel) { |
| 368 | struct device *dev = host->dma_rx_channel->device->dev; |
| 369 | unsigned int max_seg_size = dma_get_max_seg_size(dev); |
| 370 | |
| 371 | if (max_seg_size < host->mmc->max_seg_size) |
| 372 | host->mmc->max_seg_size = max_seg_size; |
| 373 | } |
| 374 | } |
| 375 | |
| 376 | /* |
Bill Pemberton | 6e0ee71 | 2012-11-19 13:26:03 -0500 | [diff] [blame] | 377 | * This is used in or so inline it |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 378 | * so it can be discarded. |
| 379 | */ |
| 380 | static inline void mmci_dma_release(struct mmci_host *host) |
| 381 | { |
| 382 | struct mmci_platform_data *plat = host->plat; |
| 383 | |
| 384 | if (host->dma_rx_channel) |
| 385 | dma_release_channel(host->dma_rx_channel); |
| 386 | if (host->dma_tx_channel && plat->dma_tx_param) |
| 387 | dma_release_channel(host->dma_tx_channel); |
| 388 | host->dma_rx_channel = host->dma_tx_channel = NULL; |
| 389 | } |
| 390 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 391 | static void mmci_dma_data_error(struct mmci_host *host) |
| 392 | { |
| 393 | dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); |
| 394 | dmaengine_terminate_all(host->dma_current); |
| 395 | host->dma_current = NULL; |
| 396 | host->dma_desc_current = NULL; |
| 397 | host->data->host_cookie = 0; |
| 398 | } |
| 399 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 400 | static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) |
| 401 | { |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 402 | struct dma_chan *chan; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 403 | enum dma_data_direction dir; |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 404 | |
| 405 | if (data->flags & MMC_DATA_READ) { |
| 406 | dir = DMA_FROM_DEVICE; |
| 407 | chan = host->dma_rx_channel; |
| 408 | } else { |
| 409 | dir = DMA_TO_DEVICE; |
| 410 | chan = host->dma_tx_channel; |
| 411 | } |
| 412 | |
| 413 | dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); |
| 414 | } |
| 415 | |
| 416 | static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) |
| 417 | { |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 418 | u32 status; |
| 419 | int i; |
| 420 | |
| 421 | /* Wait up to 1ms for the DMA to complete */ |
| 422 | for (i = 0; ; i++) { |
| 423 | status = readl(host->base + MMCISTATUS); |
| 424 | if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) |
| 425 | break; |
| 426 | udelay(10); |
| 427 | } |
| 428 | |
| 429 | /* |
| 430 | * Check to see whether we still have some data left in the FIFO - |
| 431 | * this catches DMA controllers which are unable to monitor the |
| 432 | * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- |
| 433 | * contiguous buffers. On TX, we'll get a FIFO underrun error. |
| 434 | */ |
| 435 | if (status & MCI_RXDATAAVLBLMASK) { |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 436 | mmci_dma_data_error(host); |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 437 | if (!data->error) |
| 438 | data->error = -EIO; |
| 439 | } |
| 440 | |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 441 | if (!data->host_cookie) |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 442 | mmci_dma_unmap(host, data); |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 443 | |
| 444 | /* |
| 445 | * Use of DMA with scatter-gather is impossible. |
| 446 | * Give up with DMA and switch back to PIO mode. |
| 447 | */ |
| 448 | if (status & MCI_RXDATAAVLBLMASK) { |
| 449 | dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); |
| 450 | mmci_dma_release(host); |
| 451 | } |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 452 | |
| 453 | host->dma_current = NULL; |
| 454 | host->dma_desc_current = NULL; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 455 | } |
| 456 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 457 | /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ |
| 458 | static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, |
| 459 | struct dma_chan **dma_chan, |
| 460 | struct dma_async_tx_descriptor **dma_desc) |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 461 | { |
| 462 | struct variant_data *variant = host->variant; |
| 463 | struct dma_slave_config conf = { |
| 464 | .src_addr = host->phybase + MMCIFIFO, |
| 465 | .dst_addr = host->phybase + MMCIFIFO, |
| 466 | .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, |
| 467 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, |
| 468 | .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ |
| 469 | .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ |
Viresh Kumar | 258aea7 | 2012-02-01 16:12:19 +0530 | [diff] [blame] | 470 | .device_fc = false, |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 471 | }; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 472 | struct dma_chan *chan; |
| 473 | struct dma_device *device; |
| 474 | struct dma_async_tx_descriptor *desc; |
Vinod Koul | 05f5799 | 2011-10-14 10:45:11 +0530 | [diff] [blame] | 475 | enum dma_data_direction buffer_dirn; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 476 | int nr_sg; |
| 477 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 478 | if (data->flags & MMC_DATA_READ) { |
Vinod Koul | 05f5799 | 2011-10-14 10:45:11 +0530 | [diff] [blame] | 479 | conf.direction = DMA_DEV_TO_MEM; |
| 480 | buffer_dirn = DMA_FROM_DEVICE; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 481 | chan = host->dma_rx_channel; |
| 482 | } else { |
Vinod Koul | 05f5799 | 2011-10-14 10:45:11 +0530 | [diff] [blame] | 483 | conf.direction = DMA_MEM_TO_DEV; |
| 484 | buffer_dirn = DMA_TO_DEVICE; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 485 | chan = host->dma_tx_channel; |
| 486 | } |
| 487 | |
| 488 | /* If there's no DMA channel, fall back to PIO */ |
| 489 | if (!chan) |
| 490 | return -EINVAL; |
| 491 | |
| 492 | /* If less than or equal to the fifo size, don't bother with DMA */ |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 493 | if (data->blksz * data->blocks <= variant->fifosize) |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 494 | return -EINVAL; |
| 495 | |
| 496 | device = chan->device; |
Vinod Koul | 05f5799 | 2011-10-14 10:45:11 +0530 | [diff] [blame] | 497 | nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 498 | if (nr_sg == 0) |
| 499 | return -EINVAL; |
| 500 | |
| 501 | dmaengine_slave_config(chan, &conf); |
Alexandre Bounine | 1605282 | 2012-03-08 16:11:18 -0500 | [diff] [blame] | 502 | desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 503 | conf.direction, DMA_CTRL_ACK); |
| 504 | if (!desc) |
| 505 | goto unmap_exit; |
| 506 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 507 | *dma_chan = chan; |
| 508 | *dma_desc = desc; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 509 | |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 510 | return 0; |
| 511 | |
| 512 | unmap_exit: |
Vinod Koul | 05f5799 | 2011-10-14 10:45:11 +0530 | [diff] [blame] | 513 | dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 514 | return -ENOMEM; |
| 515 | } |
| 516 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 517 | static inline int mmci_dma_prep_data(struct mmci_host *host, |
| 518 | struct mmc_data *data) |
| 519 | { |
| 520 | /* Check if next job is already prepared. */ |
| 521 | if (host->dma_current && host->dma_desc_current) |
| 522 | return 0; |
| 523 | |
| 524 | /* No job were prepared thus do it now. */ |
| 525 | return __mmci_dma_prep_data(host, data, &host->dma_current, |
| 526 | &host->dma_desc_current); |
| 527 | } |
| 528 | |
| 529 | static inline int mmci_dma_prep_next(struct mmci_host *host, |
| 530 | struct mmc_data *data) |
| 531 | { |
| 532 | struct mmci_host_next *nd = &host->next_data; |
| 533 | return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc); |
| 534 | } |
| 535 | |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 536 | static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) |
| 537 | { |
| 538 | int ret; |
| 539 | struct mmc_data *data = host->data; |
| 540 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 541 | ret = mmci_dma_prep_data(host, host->data); |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 542 | if (ret) |
| 543 | return ret; |
| 544 | |
| 545 | /* Okay, go for it. */ |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 546 | dev_vdbg(mmc_dev(host->mmc), |
| 547 | "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", |
| 548 | data->sg_len, data->blksz, data->blocks, data->flags); |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 549 | dmaengine_submit(host->dma_desc_current); |
| 550 | dma_async_issue_pending(host->dma_current); |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 551 | |
| 552 | datactrl |= MCI_DPSM_DMAENABLE; |
| 553 | |
| 554 | /* Trigger the DMA transfer */ |
| 555 | writel(datactrl, host->base + MMCIDATACTRL); |
| 556 | |
| 557 | /* |
| 558 | * Let the MMCI say when the data is ended and it's time |
| 559 | * to fire next DMA request. When that happens, MMCI will |
| 560 | * call mmci_data_end() |
| 561 | */ |
| 562 | writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, |
| 563 | host->base + MMCIMASK0); |
| 564 | return 0; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 565 | } |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 566 | |
| 567 | static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
| 568 | { |
| 569 | struct mmci_host_next *next = &host->next_data; |
| 570 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 571 | WARN_ON(data->host_cookie && data->host_cookie != next->cookie); |
| 572 | WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan)); |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 573 | |
| 574 | host->dma_desc_current = next->dma_desc; |
| 575 | host->dma_current = next->dma_chan; |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 576 | next->dma_desc = NULL; |
| 577 | next->dma_chan = NULL; |
| 578 | } |
| 579 | |
| 580 | static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, |
| 581 | bool is_first_req) |
| 582 | { |
| 583 | struct mmci_host *host = mmc_priv(mmc); |
| 584 | struct mmc_data *data = mrq->data; |
| 585 | struct mmci_host_next *nd = &host->next_data; |
| 586 | |
| 587 | if (!data) |
| 588 | return; |
| 589 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 590 | BUG_ON(data->host_cookie); |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 591 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 592 | if (mmci_validate_data(host, data)) |
| 593 | return; |
| 594 | |
| 595 | if (!mmci_dma_prep_next(host, data)) |
| 596 | data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 597 | } |
| 598 | |
| 599 | static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, |
| 600 | int err) |
| 601 | { |
| 602 | struct mmci_host *host = mmc_priv(mmc); |
| 603 | struct mmc_data *data = mrq->data; |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 604 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 605 | if (!data || !data->host_cookie) |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 606 | return; |
| 607 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 608 | mmci_dma_unmap(host, data); |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 609 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 610 | if (err) { |
| 611 | struct mmci_host_next *next = &host->next_data; |
| 612 | struct dma_chan *chan; |
| 613 | if (data->flags & MMC_DATA_READ) |
| 614 | chan = host->dma_rx_channel; |
| 615 | else |
| 616 | chan = host->dma_tx_channel; |
| 617 | dmaengine_terminate_all(chan); |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 618 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 619 | next->dma_desc = NULL; |
| 620 | next->dma_chan = NULL; |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 621 | } |
| 622 | } |
| 623 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 624 | #else |
| 625 | /* Blank functions if the DMA engine is not available */ |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 626 | static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
| 627 | { |
| 628 | } |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 629 | static inline void mmci_dma_setup(struct mmci_host *host) |
| 630 | { |
| 631 | } |
| 632 | |
| 633 | static inline void mmci_dma_release(struct mmci_host *host) |
| 634 | { |
| 635 | } |
| 636 | |
| 637 | static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) |
| 638 | { |
| 639 | } |
| 640 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 641 | static inline void mmci_dma_finalize(struct mmci_host *host, |
| 642 | struct mmc_data *data) |
| 643 | { |
| 644 | } |
| 645 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 646 | static inline void mmci_dma_data_error(struct mmci_host *host) |
| 647 | { |
| 648 | } |
| 649 | |
| 650 | static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) |
| 651 | { |
| 652 | return -ENOSYS; |
| 653 | } |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 654 | |
| 655 | #define mmci_pre_request NULL |
| 656 | #define mmci_post_request NULL |
| 657 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 658 | #endif |
| 659 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 660 | static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) |
| 661 | { |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 662 | struct variant_data *variant = host->variant; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 663 | unsigned int datactrl, timeout, irqmask; |
Russell King | 7b09cda | 2005-07-01 12:02:59 +0100 | [diff] [blame] | 664 | unsigned long long clks; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 665 | void __iomem *base; |
Russell King | 3bc87f2 | 2006-08-27 13:51:28 +0100 | [diff] [blame] | 666 | int blksz_bits; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 667 | |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 668 | dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", |
| 669 | data->blksz, data->blocks, data->flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 670 | |
| 671 | host->data = data; |
Rabin Vincent | 528320d | 2010-07-21 12:49:49 +0100 | [diff] [blame] | 672 | host->size = data->blksz * data->blocks; |
Russell King | 51d4375 | 2011-01-27 10:56:52 +0000 | [diff] [blame] | 673 | data->bytes_xfered = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 674 | |
Russell King | 7b09cda | 2005-07-01 12:02:59 +0100 | [diff] [blame] | 675 | clks = (unsigned long long)data->timeout_ns * host->cclk; |
| 676 | do_div(clks, 1000000000UL); |
| 677 | |
| 678 | timeout = data->timeout_clks + (unsigned int)clks; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 679 | |
| 680 | base = host->base; |
| 681 | writel(timeout, base + MMCIDATATIMER); |
| 682 | writel(host->size, base + MMCIDATALENGTH); |
| 683 | |
Russell King | 3bc87f2 | 2006-08-27 13:51:28 +0100 | [diff] [blame] | 684 | blksz_bits = ffs(data->blksz) - 1; |
| 685 | BUG_ON(1 << blksz_bits != data->blksz); |
| 686 | |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 687 | if (variant->blksz_datactrl16) |
| 688 | datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); |
| 689 | else |
| 690 | datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 691 | |
| 692 | if (data->flags & MMC_DATA_READ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 693 | datactrl |= MCI_DPSM_DIRECTION; |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 694 | |
Ulf Hansson | 7258db7 | 2011-12-13 17:05:28 +0100 | [diff] [blame] | 695 | /* The ST Micro variants has a special bit to enable SDIO */ |
| 696 | if (variant->sdio && host->mmc->card) |
Ulf Hansson | 06c1a12 | 2012-10-12 14:01:50 +0100 | [diff] [blame] | 697 | if (mmc_card_sdio(host->mmc->card)) { |
| 698 | /* |
| 699 | * The ST Micro variants has a special bit |
| 700 | * to enable SDIO. |
| 701 | */ |
| 702 | u32 clk; |
| 703 | |
Ulf Hansson | 7258db7 | 2011-12-13 17:05:28 +0100 | [diff] [blame] | 704 | datactrl |= MCI_ST_DPSM_SDIOEN; |
| 705 | |
Ulf Hansson | 06c1a12 | 2012-10-12 14:01:50 +0100 | [diff] [blame] | 706 | /* |
Ulf Hansson | 70ac093 | 2012-10-12 14:07:36 +0100 | [diff] [blame] | 707 | * The ST Micro variant for SDIO small write transfers |
| 708 | * needs to have clock H/W flow control disabled, |
| 709 | * otherwise the transfer will not start. The threshold |
| 710 | * depends on the rate of MCLK. |
Ulf Hansson | 06c1a12 | 2012-10-12 14:01:50 +0100 | [diff] [blame] | 711 | */ |
Ulf Hansson | 70ac093 | 2012-10-12 14:07:36 +0100 | [diff] [blame] | 712 | if (data->flags & MMC_DATA_WRITE && |
| 713 | (host->size < 8 || |
| 714 | (host->size <= 8 && host->mclk > 50000000))) |
Ulf Hansson | 06c1a12 | 2012-10-12 14:01:50 +0100 | [diff] [blame] | 715 | clk = host->clk_reg & ~variant->clkreg_enable; |
| 716 | else |
| 717 | clk = host->clk_reg | variant->clkreg_enable; |
| 718 | |
| 719 | mmci_write_clkreg(host, clk); |
| 720 | } |
| 721 | |
Ulf Hansson | 6dbb6ee | 2013-01-07 15:30:44 +0100 | [diff] [blame] | 722 | if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) |
| 723 | datactrl |= MCI_ST_DPSM_DDRMODE; |
| 724 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 725 | /* |
| 726 | * Attempt to use DMA operation mode, if this |
| 727 | * should fail, fall back to PIO mode |
| 728 | */ |
| 729 | if (!mmci_dma_start_data(host, datactrl)) |
| 730 | return; |
| 731 | |
| 732 | /* IRQ mode, map the SG list for CPU reading/writing */ |
| 733 | mmci_init_sg(host, data); |
| 734 | |
| 735 | if (data->flags & MMC_DATA_READ) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 736 | irqmask = MCI_RXFIFOHALFFULLMASK; |
Russell King | 0425a14 | 2006-02-16 16:48:31 +0000 | [diff] [blame] | 737 | |
| 738 | /* |
Russell King | c4d877c | 2011-01-27 09:50:13 +0000 | [diff] [blame] | 739 | * If we have less than the fifo 'half-full' threshold to |
| 740 | * transfer, trigger a PIO interrupt as soon as any data |
| 741 | * is available. |
Russell King | 0425a14 | 2006-02-16 16:48:31 +0000 | [diff] [blame] | 742 | */ |
Russell King | c4d877c | 2011-01-27 09:50:13 +0000 | [diff] [blame] | 743 | if (host->size < variant->fifohalfsize) |
Russell King | 0425a14 | 2006-02-16 16:48:31 +0000 | [diff] [blame] | 744 | irqmask |= MCI_RXDATAAVLBLMASK; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 745 | } else { |
| 746 | /* |
| 747 | * We don't actually need to include "FIFO empty" here |
| 748 | * since its implicit in "FIFO half empty". |
| 749 | */ |
| 750 | irqmask = MCI_TXFIFOHALFEMPTYMASK; |
| 751 | } |
| 752 | |
| 753 | writel(datactrl, base + MMCIDATACTRL); |
| 754 | writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 755 | mmci_set_mask1(host, irqmask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 756 | } |
| 757 | |
| 758 | static void |
| 759 | mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) |
| 760 | { |
| 761 | void __iomem *base = host->base; |
| 762 | |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 763 | dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 764 | cmd->opcode, cmd->arg, cmd->flags); |
| 765 | |
| 766 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { |
| 767 | writel(0, base + MMCICOMMAND); |
| 768 | udelay(1); |
| 769 | } |
| 770 | |
| 771 | c |= cmd->opcode | MCI_CPSM_ENABLE; |
Russell King | e922517 | 2006-02-02 12:23:12 +0000 | [diff] [blame] | 772 | if (cmd->flags & MMC_RSP_PRESENT) { |
| 773 | if (cmd->flags & MMC_RSP_136) |
| 774 | c |= MCI_CPSM_LONGRSP; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 775 | c |= MCI_CPSM_RESPONSE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 776 | } |
| 777 | if (/*interrupt*/0) |
| 778 | c |= MCI_CPSM_INTERRUPT; |
| 779 | |
| 780 | host->cmd = cmd; |
| 781 | |
| 782 | writel(cmd->arg, base + MMCIARGUMENT); |
| 783 | writel(c, base + MMCICOMMAND); |
| 784 | } |
| 785 | |
| 786 | static void |
| 787 | mmci_data_irq(struct mmci_host *host, struct mmc_data *data, |
| 788 | unsigned int status) |
| 789 | { |
Linus Walleij | f20f8f2 | 2010-10-19 13:41:24 +0100 | [diff] [blame] | 790 | /* First check for errors */ |
Ulf Hansson | b63038d | 2011-12-13 16:51:04 +0100 | [diff] [blame] | 791 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| |
| 792 | MCI_TXUNDERRUN|MCI_RXOVERRUN)) { |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 793 | u32 remain, success; |
Linus Walleij | f20f8f2 | 2010-10-19 13:41:24 +0100 | [diff] [blame] | 794 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 795 | /* Terminate the DMA transfer */ |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 796 | if (dma_inprogress(host)) { |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 797 | mmci_dma_data_error(host); |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 798 | mmci_dma_unmap(host, data); |
| 799 | } |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 800 | |
Russell King | c8afc9d | 2011-02-04 09:19:46 +0000 | [diff] [blame] | 801 | /* |
| 802 | * Calculate how far we are into the transfer. Note that |
| 803 | * the data counter gives the number of bytes transferred |
| 804 | * on the MMC bus, not on the host side. On reads, this |
| 805 | * can be as much as a FIFO-worth of data ahead. This |
| 806 | * matters for FIFO overruns only. |
| 807 | */ |
Linus Walleij | f5a106d | 2011-01-27 17:44:34 +0100 | [diff] [blame] | 808 | remain = readl(host->base + MMCIDATACNT); |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 809 | success = data->blksz * data->blocks - remain; |
| 810 | |
Russell King | c8afc9d | 2011-02-04 09:19:46 +0000 | [diff] [blame] | 811 | dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", |
| 812 | status, success); |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 813 | if (status & MCI_DATACRCFAIL) { |
| 814 | /* Last block was not successful */ |
Russell King | c8afc9d | 2011-02-04 09:19:46 +0000 | [diff] [blame] | 815 | success -= 1; |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 816 | data->error = -EILSEQ; |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 817 | } else if (status & MCI_DATATIMEOUT) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 818 | data->error = -ETIMEDOUT; |
Linus Walleij | 757df74 | 2011-06-30 15:10:21 +0100 | [diff] [blame] | 819 | } else if (status & MCI_STARTBITERR) { |
| 820 | data->error = -ECOMM; |
Russell King | c8afc9d | 2011-02-04 09:19:46 +0000 | [diff] [blame] | 821 | } else if (status & MCI_TXUNDERRUN) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 822 | data->error = -EIO; |
Russell King | c8afc9d | 2011-02-04 09:19:46 +0000 | [diff] [blame] | 823 | } else if (status & MCI_RXOVERRUN) { |
| 824 | if (success > host->variant->fifosize) |
| 825 | success -= host->variant->fifosize; |
| 826 | else |
| 827 | success = 0; |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 828 | data->error = -EIO; |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 829 | } |
Russell King | 51d4375 | 2011-01-27 10:56:52 +0000 | [diff] [blame] | 830 | data->bytes_xfered = round_down(success, data->blksz); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 831 | } |
Linus Walleij | f20f8f2 | 2010-10-19 13:41:24 +0100 | [diff] [blame] | 832 | |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 833 | if (status & MCI_DATABLOCKEND) |
| 834 | dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); |
Linus Walleij | f20f8f2 | 2010-10-19 13:41:24 +0100 | [diff] [blame] | 835 | |
Russell King | ccff9b5 | 2011-01-30 21:03:50 +0000 | [diff] [blame] | 836 | if (status & MCI_DATAEND || data->error) { |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 837 | if (dma_inprogress(host)) |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 838 | mmci_dma_finalize(host, data); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 839 | mmci_stop_data(host); |
| 840 | |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 841 | if (!data->error) |
| 842 | /* The error clause is handled above, success! */ |
Russell King | 51d4375 | 2011-01-27 10:56:52 +0000 | [diff] [blame] | 843 | data->bytes_xfered = data->blksz * data->blocks; |
Linus Walleij | f20f8f2 | 2010-10-19 13:41:24 +0100 | [diff] [blame] | 844 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 845 | if (!data->stop) { |
| 846 | mmci_request_end(host, data->mrq); |
| 847 | } else { |
| 848 | mmci_start_command(host, data->stop, 0); |
| 849 | } |
| 850 | } |
| 851 | } |
| 852 | |
| 853 | static void |
| 854 | mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, |
| 855 | unsigned int status) |
| 856 | { |
| 857 | void __iomem *base = host->base; |
| 858 | |
| 859 | host->cmd = NULL; |
| 860 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 861 | if (status & MCI_CMDTIMEOUT) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 862 | cmd->error = -ETIMEDOUT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 863 | } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 864 | cmd->error = -EILSEQ; |
Russell King - ARM Linux | 9047b43 | 2011-01-11 16:35:56 +0000 | [diff] [blame] | 865 | } else { |
| 866 | cmd->resp[0] = readl(base + MMCIRESPONSE0); |
| 867 | cmd->resp[1] = readl(base + MMCIRESPONSE1); |
| 868 | cmd->resp[2] = readl(base + MMCIRESPONSE2); |
| 869 | cmd->resp[3] = readl(base + MMCIRESPONSE3); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 870 | } |
| 871 | |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 872 | if (!cmd->data || cmd->error) { |
Ulf Hansson | 3b6e3c7 | 2011-12-13 16:58:43 +0100 | [diff] [blame] | 873 | if (host->data) { |
| 874 | /* Terminate the DMA transfer */ |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 875 | if (dma_inprogress(host)) { |
Ulf Hansson | 3b6e3c7 | 2011-12-13 16:58:43 +0100 | [diff] [blame] | 876 | mmci_dma_data_error(host); |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 877 | mmci_dma_unmap(host, host->data); |
| 878 | } |
Russell King | e47c222 | 2007-01-08 16:42:51 +0000 | [diff] [blame] | 879 | mmci_stop_data(host); |
Ulf Hansson | 3b6e3c7 | 2011-12-13 16:58:43 +0100 | [diff] [blame] | 880 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 881 | mmci_request_end(host, cmd->mrq); |
| 882 | } else if (!(cmd->data->flags & MMC_DATA_READ)) { |
| 883 | mmci_start_data(host, cmd->data); |
| 884 | } |
| 885 | } |
| 886 | |
| 887 | static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) |
| 888 | { |
| 889 | void __iomem *base = host->base; |
| 890 | char *ptr = buffer; |
| 891 | u32 status; |
Linus Walleij | 26eed9a | 2008-04-26 23:39:44 +0100 | [diff] [blame] | 892 | int host_remain = host->size; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 893 | |
| 894 | do { |
Linus Walleij | 26eed9a | 2008-04-26 23:39:44 +0100 | [diff] [blame] | 895 | int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 896 | |
| 897 | if (count > remain) |
| 898 | count = remain; |
| 899 | |
| 900 | if (count <= 0) |
| 901 | break; |
| 902 | |
Ulf Hansson | 393e5e2 | 2011-12-13 17:08:04 +0100 | [diff] [blame] | 903 | /* |
| 904 | * SDIO especially may want to send something that is |
| 905 | * not divisible by 4 (as opposed to card sectors |
| 906 | * etc). Therefore make sure to always read the last bytes |
| 907 | * while only doing full 32-bit reads towards the FIFO. |
| 908 | */ |
| 909 | if (unlikely(count & 0x3)) { |
| 910 | if (count < 4) { |
| 911 | unsigned char buf[4]; |
Davide Ciminaghi | 4b85da0 | 2012-12-10 14:47:21 +0100 | [diff] [blame] | 912 | ioread32_rep(base + MMCIFIFO, buf, 1); |
Ulf Hansson | 393e5e2 | 2011-12-13 17:08:04 +0100 | [diff] [blame] | 913 | memcpy(ptr, buf, count); |
| 914 | } else { |
Davide Ciminaghi | 4b85da0 | 2012-12-10 14:47:21 +0100 | [diff] [blame] | 915 | ioread32_rep(base + MMCIFIFO, ptr, count >> 2); |
Ulf Hansson | 393e5e2 | 2011-12-13 17:08:04 +0100 | [diff] [blame] | 916 | count &= ~0x3; |
| 917 | } |
| 918 | } else { |
Davide Ciminaghi | 4b85da0 | 2012-12-10 14:47:21 +0100 | [diff] [blame] | 919 | ioread32_rep(base + MMCIFIFO, ptr, count >> 2); |
Ulf Hansson | 393e5e2 | 2011-12-13 17:08:04 +0100 | [diff] [blame] | 920 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 921 | |
| 922 | ptr += count; |
| 923 | remain -= count; |
Linus Walleij | 26eed9a | 2008-04-26 23:39:44 +0100 | [diff] [blame] | 924 | host_remain -= count; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 925 | |
| 926 | if (remain == 0) |
| 927 | break; |
| 928 | |
| 929 | status = readl(base + MMCISTATUS); |
| 930 | } while (status & MCI_RXDATAAVLBL); |
| 931 | |
| 932 | return ptr - buffer; |
| 933 | } |
| 934 | |
| 935 | static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) |
| 936 | { |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 937 | struct variant_data *variant = host->variant; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 938 | void __iomem *base = host->base; |
| 939 | char *ptr = buffer; |
| 940 | |
| 941 | do { |
| 942 | unsigned int count, maxcnt; |
| 943 | |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 944 | maxcnt = status & MCI_TXFIFOEMPTY ? |
| 945 | variant->fifosize : variant->fifohalfsize; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 946 | count = min(remain, maxcnt); |
| 947 | |
Linus Walleij | 3417780 | 2010-10-19 12:43:58 +0100 | [diff] [blame] | 948 | /* |
Linus Walleij | 3417780 | 2010-10-19 12:43:58 +0100 | [diff] [blame] | 949 | * SDIO especially may want to send something that is |
| 950 | * not divisible by 4 (as opposed to card sectors |
| 951 | * etc), and the FIFO only accept full 32-bit writes. |
| 952 | * So compensate by adding +3 on the count, a single |
| 953 | * byte become a 32bit write, 7 bytes will be two |
| 954 | * 32bit writes etc. |
| 955 | */ |
Davide Ciminaghi | 4b85da0 | 2012-12-10 14:47:21 +0100 | [diff] [blame] | 956 | iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 957 | |
| 958 | ptr += count; |
| 959 | remain -= count; |
| 960 | |
| 961 | if (remain == 0) |
| 962 | break; |
| 963 | |
| 964 | status = readl(base + MMCISTATUS); |
| 965 | } while (status & MCI_TXFIFOHALFEMPTY); |
| 966 | |
| 967 | return ptr - buffer; |
| 968 | } |
| 969 | |
| 970 | /* |
| 971 | * PIO data transfer IRQ handler. |
| 972 | */ |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 973 | static irqreturn_t mmci_pio_irq(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 974 | { |
| 975 | struct mmci_host *host = dev_id; |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 976 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
Rabin Vincent | 8301bb6 | 2010-08-09 12:57:30 +0100 | [diff] [blame] | 977 | struct variant_data *variant = host->variant; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 978 | void __iomem *base = host->base; |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 979 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 980 | u32 status; |
| 981 | |
| 982 | status = readl(base + MMCISTATUS); |
| 983 | |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 984 | dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 985 | |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 986 | local_irq_save(flags); |
| 987 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 988 | do { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 989 | unsigned int remain, len; |
| 990 | char *buffer; |
| 991 | |
| 992 | /* |
| 993 | * For write, we only need to test the half-empty flag |
| 994 | * here - if the FIFO is completely empty, then by |
| 995 | * definition it is more than half empty. |
| 996 | * |
| 997 | * For read, check for data available. |
| 998 | */ |
| 999 | if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) |
| 1000 | break; |
| 1001 | |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 1002 | if (!sg_miter_next(sg_miter)) |
| 1003 | break; |
| 1004 | |
| 1005 | buffer = sg_miter->addr; |
| 1006 | remain = sg_miter->length; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1007 | |
| 1008 | len = 0; |
| 1009 | if (status & MCI_RXACTIVE) |
| 1010 | len = mmci_pio_read(host, buffer, remain); |
| 1011 | if (status & MCI_TXACTIVE) |
| 1012 | len = mmci_pio_write(host, buffer, remain, status); |
| 1013 | |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 1014 | sg_miter->consumed = len; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1015 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1016 | host->size -= len; |
| 1017 | remain -= len; |
| 1018 | |
| 1019 | if (remain) |
| 1020 | break; |
| 1021 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1022 | status = readl(base + MMCISTATUS); |
| 1023 | } while (1); |
| 1024 | |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame] | 1025 | sg_miter_stop(sg_miter); |
| 1026 | |
| 1027 | local_irq_restore(flags); |
| 1028 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1029 | /* |
Russell King | c4d877c | 2011-01-27 09:50:13 +0000 | [diff] [blame] | 1030 | * If we have less than the fifo 'half-full' threshold to transfer, |
| 1031 | * trigger a PIO interrupt as soon as any data is available. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1032 | */ |
Russell King | c4d877c | 2011-01-27 09:50:13 +0000 | [diff] [blame] | 1033 | if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 1034 | mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1035 | |
| 1036 | /* |
| 1037 | * If we run out of data, disable the data IRQs; this |
| 1038 | * prevents a race where the FIFO becomes empty before |
| 1039 | * the chip itself has disabled the data path, and |
| 1040 | * stops us racing with our data end IRQ. |
| 1041 | */ |
| 1042 | if (host->size == 0) { |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 1043 | mmci_set_mask1(host, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1044 | writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); |
| 1045 | } |
| 1046 | |
| 1047 | return IRQ_HANDLED; |
| 1048 | } |
| 1049 | |
| 1050 | /* |
| 1051 | * Handle completion of command and data transfers. |
| 1052 | */ |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1053 | static irqreturn_t mmci_irq(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1054 | { |
| 1055 | struct mmci_host *host = dev_id; |
| 1056 | u32 status; |
| 1057 | int ret = 0; |
| 1058 | |
| 1059 | spin_lock(&host->lock); |
| 1060 | |
| 1061 | do { |
| 1062 | struct mmc_command *cmd; |
| 1063 | struct mmc_data *data; |
| 1064 | |
| 1065 | status = readl(host->base + MMCISTATUS); |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 1066 | |
| 1067 | if (host->singleirq) { |
| 1068 | if (status & readl(host->base + MMCIMASK1)) |
| 1069 | mmci_pio_irq(irq, dev_id); |
| 1070 | |
| 1071 | status &= ~MCI_IRQ1MASK; |
| 1072 | } |
| 1073 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1074 | status &= readl(host->base + MMCIMASK0); |
| 1075 | writel(status, host->base + MMCICLEAR); |
| 1076 | |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 1077 | dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1078 | |
| 1079 | data = host->data; |
Ulf Hansson | b63038d | 2011-12-13 16:51:04 +0100 | [diff] [blame] | 1080 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| |
| 1081 | MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| |
| 1082 | MCI_DATABLOCKEND) && data) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1083 | mmci_data_irq(host, data, status); |
| 1084 | |
| 1085 | cmd = host->cmd; |
| 1086 | if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) |
| 1087 | mmci_cmd_irq(host, cmd, status); |
| 1088 | |
| 1089 | ret = 1; |
| 1090 | } while (status); |
| 1091 | |
| 1092 | spin_unlock(&host->lock); |
| 1093 | |
| 1094 | return IRQ_RETVAL(ret); |
| 1095 | } |
| 1096 | |
| 1097 | static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) |
| 1098 | { |
| 1099 | struct mmci_host *host = mmc_priv(mmc); |
Linus Walleij | 9e94302 | 2008-10-24 21:17:50 +0100 | [diff] [blame] | 1100 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1101 | |
| 1102 | WARN_ON(host->mrq != NULL); |
| 1103 | |
Ulf Hansson | 653a761 | 2013-01-21 21:29:34 +0100 | [diff] [blame] | 1104 | mrq->cmd->error = mmci_validate_data(host, mrq->data); |
| 1105 | if (mrq->cmd->error) { |
Pierre Ossman | 255d01a | 2007-07-24 20:38:53 +0200 | [diff] [blame] | 1106 | mmc_request_done(mmc, mrq); |
| 1107 | return; |
| 1108 | } |
| 1109 | |
Russell King | 1c3be36 | 2011-08-14 09:17:05 +0100 | [diff] [blame] | 1110 | pm_runtime_get_sync(mmc_dev(mmc)); |
| 1111 | |
Linus Walleij | 9e94302 | 2008-10-24 21:17:50 +0100 | [diff] [blame] | 1112 | spin_lock_irqsave(&host->lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1113 | |
| 1114 | host->mrq = mrq; |
| 1115 | |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 1116 | if (mrq->data) |
| 1117 | mmci_get_next_data(host, mrq->data); |
| 1118 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1119 | if (mrq->data && mrq->data->flags & MMC_DATA_READ) |
| 1120 | mmci_start_data(host, mrq->data); |
| 1121 | |
| 1122 | mmci_start_command(host, mrq->cmd, 0); |
| 1123 | |
Linus Walleij | 9e94302 | 2008-10-24 21:17:50 +0100 | [diff] [blame] | 1124 | spin_unlock_irqrestore(&host->lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1125 | } |
| 1126 | |
| 1127 | static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
| 1128 | { |
| 1129 | struct mmci_host *host = mmc_priv(mmc); |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 1130 | struct variant_data *variant = host->variant; |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 1131 | u32 pwr = 0; |
| 1132 | unsigned long flags; |
Lee Jones | db90f91 | 2013-05-03 12:52:12 +0100 | [diff] [blame] | 1133 | int ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1134 | |
Ulf Hansson | 2cd976c | 2011-12-13 17:01:11 +0100 | [diff] [blame] | 1135 | pm_runtime_get_sync(mmc_dev(mmc)); |
| 1136 | |
Ulf Hansson | bc52181 | 2011-12-13 16:57:55 +0100 | [diff] [blame] | 1137 | if (host->plat->ios_handler && |
| 1138 | host->plat->ios_handler(mmc_dev(mmc), ios)) |
| 1139 | dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); |
| 1140 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1141 | switch (ios->power_mode) { |
| 1142 | case MMC_POWER_OFF: |
Ulf Hansson | 599c1d5 | 2013-01-07 16:22:50 +0100 | [diff] [blame] | 1143 | if (!IS_ERR(mmc->supply.vmmc)) |
| 1144 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); |
Lee Jones | 237fb5e | 2013-01-31 11:27:52 +0000 | [diff] [blame] | 1145 | |
| 1146 | if (!IS_ERR(mmc->supply.vqmmc) && |
| 1147 | regulator_is_enabled(mmc->supply.vqmmc)) |
| 1148 | regulator_disable(mmc->supply.vqmmc); |
| 1149 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1150 | break; |
| 1151 | case MMC_POWER_UP: |
Ulf Hansson | 599c1d5 | 2013-01-07 16:22:50 +0100 | [diff] [blame] | 1152 | if (!IS_ERR(mmc->supply.vmmc)) |
| 1153 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); |
| 1154 | |
Ulf Hansson | 7d72a1d | 2011-12-13 16:54:55 +0100 | [diff] [blame] | 1155 | /* |
| 1156 | * The ST Micro variant doesn't have the PL180s MCI_PWR_UP |
| 1157 | * and instead uses MCI_PWR_ON so apply whatever value is |
| 1158 | * configured in the variant data. |
| 1159 | */ |
| 1160 | pwr |= variant->pwrreg_powerup; |
| 1161 | |
| 1162 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1163 | case MMC_POWER_ON: |
Lee Jones | 237fb5e | 2013-01-31 11:27:52 +0000 | [diff] [blame] | 1164 | if (!IS_ERR(mmc->supply.vqmmc) && |
Lee Jones | db90f91 | 2013-05-03 12:52:12 +0100 | [diff] [blame] | 1165 | !regulator_is_enabled(mmc->supply.vqmmc)) { |
| 1166 | ret = regulator_enable(mmc->supply.vqmmc); |
| 1167 | if (ret < 0) |
| 1168 | dev_err(mmc_dev(mmc), |
| 1169 | "failed to enable vqmmc regulator\n"); |
| 1170 | } |
Lee Jones | 237fb5e | 2013-01-31 11:27:52 +0000 | [diff] [blame] | 1171 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1172 | pwr |= MCI_PWR_ON; |
| 1173 | break; |
| 1174 | } |
| 1175 | |
Ulf Hansson | 4d1a3a0 | 2011-12-13 16:57:07 +0100 | [diff] [blame] | 1176 | if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { |
| 1177 | /* |
| 1178 | * The ST Micro variant has some additional bits |
| 1179 | * indicating signal direction for the signals in |
| 1180 | * the SD/MMC bus and feedback-clock usage. |
| 1181 | */ |
| 1182 | pwr |= host->plat->sigdir; |
| 1183 | |
| 1184 | if (ios->bus_width == MMC_BUS_WIDTH_4) |
| 1185 | pwr &= ~MCI_ST_DATA74DIREN; |
| 1186 | else if (ios->bus_width == MMC_BUS_WIDTH_1) |
| 1187 | pwr &= (~MCI_ST_DATA74DIREN & |
| 1188 | ~MCI_ST_DATA31DIREN & |
| 1189 | ~MCI_ST_DATA2DIREN); |
| 1190 | } |
| 1191 | |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 1192 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { |
Linus Walleij | f17a1f0 | 2009-08-04 01:01:02 +0100 | [diff] [blame] | 1193 | if (host->hw_designer != AMBA_VENDOR_ST) |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 1194 | pwr |= MCI_ROD; |
| 1195 | else { |
| 1196 | /* |
| 1197 | * The ST Micro variant use the ROD bit for something |
| 1198 | * else and only has OD (Open Drain). |
| 1199 | */ |
| 1200 | pwr |= MCI_OD; |
| 1201 | } |
| 1202 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1203 | |
Ulf Hansson | f4670da | 2013-01-09 17:19:54 +0100 | [diff] [blame] | 1204 | /* |
| 1205 | * If clock = 0 and the variant requires the MMCIPOWER to be used for |
| 1206 | * gating the clock, the MCI_PWR_ON bit is cleared. |
| 1207 | */ |
| 1208 | if (!ios->clock && variant->pwrreg_clkgate) |
| 1209 | pwr &= ~MCI_PWR_ON; |
| 1210 | |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 1211 | spin_lock_irqsave(&host->lock, flags); |
| 1212 | |
| 1213 | mmci_set_clkreg(host, ios->clock); |
Ulf Hansson | 7437cfa | 2012-01-18 09:17:27 +0100 | [diff] [blame] | 1214 | mmci_write_pwrreg(host, pwr); |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 1215 | |
| 1216 | spin_unlock_irqrestore(&host->lock, flags); |
Ulf Hansson | 2cd976c | 2011-12-13 17:01:11 +0100 | [diff] [blame] | 1217 | |
Ulf Hansson | 2cd976c | 2011-12-13 17:01:11 +0100 | [diff] [blame] | 1218 | pm_runtime_mark_last_busy(mmc_dev(mmc)); |
| 1219 | pm_runtime_put_autosuspend(mmc_dev(mmc)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1220 | } |
| 1221 | |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1222 | static int mmci_get_ro(struct mmc_host *mmc) |
| 1223 | { |
| 1224 | struct mmci_host *host = mmc_priv(mmc); |
| 1225 | |
| 1226 | if (host->gpio_wp == -ENOSYS) |
| 1227 | return -ENOSYS; |
| 1228 | |
Linus Walleij | 18a06301 | 2010-09-12 12:56:44 +0100 | [diff] [blame] | 1229 | return gpio_get_value_cansleep(host->gpio_wp); |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1230 | } |
| 1231 | |
| 1232 | static int mmci_get_cd(struct mmc_host *mmc) |
| 1233 | { |
| 1234 | struct mmci_host *host = mmc_priv(mmc); |
Rabin Vincent | 2971944 | 2010-08-09 12:54:43 +0100 | [diff] [blame] | 1235 | struct mmci_platform_data *plat = host->plat; |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1236 | unsigned int status; |
| 1237 | |
Rabin Vincent | 4b8caec | 2010-08-09 12:56:40 +0100 | [diff] [blame] | 1238 | if (host->gpio_cd == -ENOSYS) { |
| 1239 | if (!plat->status) |
| 1240 | return 1; /* Assume always present */ |
| 1241 | |
Rabin Vincent | 2971944 | 2010-08-09 12:54:43 +0100 | [diff] [blame] | 1242 | status = plat->status(mmc_dev(host->mmc)); |
Rabin Vincent | 4b8caec | 2010-08-09 12:56:40 +0100 | [diff] [blame] | 1243 | } else |
Linus Walleij | 18a06301 | 2010-09-12 12:56:44 +0100 | [diff] [blame] | 1244 | status = !!gpio_get_value_cansleep(host->gpio_cd) |
| 1245 | ^ plat->cd_invert; |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1246 | |
Russell King | 74bc809 | 2010-07-29 15:58:59 +0100 | [diff] [blame] | 1247 | /* |
| 1248 | * Use positive logic throughout - status is zero for no card, |
| 1249 | * non-zero for card inserted. |
| 1250 | */ |
| 1251 | return status; |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1252 | } |
| 1253 | |
Rabin Vincent | 148b8b3 | 2010-08-09 12:55:48 +0100 | [diff] [blame] | 1254 | static irqreturn_t mmci_cd_irq(int irq, void *dev_id) |
| 1255 | { |
| 1256 | struct mmci_host *host = dev_id; |
| 1257 | |
| 1258 | mmc_detect_change(host->mmc, msecs_to_jiffies(500)); |
| 1259 | |
| 1260 | return IRQ_HANDLED; |
| 1261 | } |
| 1262 | |
David Brownell | ab7aefd | 2006-11-12 17:55:30 -0800 | [diff] [blame] | 1263 | static const struct mmc_host_ops mmci_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1264 | .request = mmci_request, |
Per Forlin | 58c7ccb | 2011-07-01 18:55:24 +0200 | [diff] [blame] | 1265 | .pre_req = mmci_pre_request, |
| 1266 | .post_req = mmci_post_request, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1267 | .set_ios = mmci_set_ios, |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1268 | .get_ro = mmci_get_ro, |
| 1269 | .get_cd = mmci_get_cd, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1270 | }; |
| 1271 | |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1272 | #ifdef CONFIG_OF |
| 1273 | static void mmci_dt_populate_generic_pdata(struct device_node *np, |
| 1274 | struct mmci_platform_data *pdata) |
| 1275 | { |
| 1276 | int bus_width = 0; |
| 1277 | |
Lee Jones | 9a59701 | 2012-04-12 16:51:13 +0100 | [diff] [blame] | 1278 | pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0); |
Lee Jones | 9a59701 | 2012-04-12 16:51:13 +0100 | [diff] [blame] | 1279 | pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0); |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1280 | |
| 1281 | if (of_get_property(np, "cd-inverted", NULL)) |
| 1282 | pdata->cd_invert = true; |
| 1283 | else |
| 1284 | pdata->cd_invert = false; |
| 1285 | |
| 1286 | of_property_read_u32(np, "max-frequency", &pdata->f_max); |
| 1287 | if (!pdata->f_max) |
| 1288 | pr_warn("%s has no 'max-frequency' property\n", np->full_name); |
| 1289 | |
| 1290 | if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) |
| 1291 | pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED; |
| 1292 | if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) |
| 1293 | pdata->capabilities |= MMC_CAP_SD_HIGHSPEED; |
| 1294 | |
| 1295 | of_property_read_u32(np, "bus-width", &bus_width); |
| 1296 | switch (bus_width) { |
| 1297 | case 0 : |
| 1298 | /* No bus-width supplied. */ |
| 1299 | break; |
| 1300 | case 4 : |
| 1301 | pdata->capabilities |= MMC_CAP_4_BIT_DATA; |
| 1302 | break; |
| 1303 | case 8 : |
| 1304 | pdata->capabilities |= MMC_CAP_8_BIT_DATA; |
| 1305 | break; |
| 1306 | default : |
| 1307 | pr_warn("%s: Unsupported bus width\n", np->full_name); |
| 1308 | } |
| 1309 | } |
Lee Jones | c0a120a | 2012-05-08 13:59:38 +0100 | [diff] [blame] | 1310 | #else |
| 1311 | static void mmci_dt_populate_generic_pdata(struct device_node *np, |
| 1312 | struct mmci_platform_data *pdata) |
| 1313 | { |
| 1314 | return; |
| 1315 | } |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1316 | #endif |
| 1317 | |
Bill Pemberton | c3be1ef | 2012-11-19 13:23:06 -0500 | [diff] [blame] | 1318 | static int mmci_probe(struct amba_device *dev, |
Russell King | aa25afa | 2011-02-19 15:55:00 +0000 | [diff] [blame] | 1319 | const struct amba_id *id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1320 | { |
Linus Walleij | 6ef297f | 2009-09-22 14:29:36 +0100 | [diff] [blame] | 1321 | struct mmci_platform_data *plat = dev->dev.platform_data; |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1322 | struct device_node *np = dev->dev.of_node; |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 1323 | struct variant_data *variant = id->data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1324 | struct mmci_host *host; |
| 1325 | struct mmc_host *mmc; |
| 1326 | int ret; |
| 1327 | |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1328 | /* Must have platform data or Device Tree. */ |
| 1329 | if (!plat && !np) { |
| 1330 | dev_err(&dev->dev, "No plat data or DT found\n"); |
| 1331 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1332 | } |
| 1333 | |
Lee Jones | b9b5291 | 2012-06-12 10:49:51 +0100 | [diff] [blame] | 1334 | if (!plat) { |
| 1335 | plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); |
| 1336 | if (!plat) |
| 1337 | return -ENOMEM; |
| 1338 | } |
| 1339 | |
Lee Jones | 000bc9d | 2012-04-16 10:18:43 +0100 | [diff] [blame] | 1340 | if (np) |
| 1341 | mmci_dt_populate_generic_pdata(np, plat); |
| 1342 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1343 | ret = amba_request_regions(dev, DRIVER_NAME); |
| 1344 | if (ret) |
| 1345 | goto out; |
| 1346 | |
| 1347 | mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); |
| 1348 | if (!mmc) { |
| 1349 | ret = -ENOMEM; |
| 1350 | goto rel_regions; |
| 1351 | } |
| 1352 | |
| 1353 | host = mmc_priv(mmc); |
Rabin Vincent | 4ea580f | 2009-04-17 08:44:19 +0530 | [diff] [blame] | 1354 | host->mmc = mmc; |
Russell King | 012b7d3 | 2009-07-09 15:13:56 +0100 | [diff] [blame] | 1355 | |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1356 | host->gpio_wp = -ENOSYS; |
| 1357 | host->gpio_cd = -ENOSYS; |
Rabin Vincent | 148b8b3 | 2010-08-09 12:55:48 +0100 | [diff] [blame] | 1358 | host->gpio_cd_irq = -1; |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1359 | |
Russell King | 012b7d3 | 2009-07-09 15:13:56 +0100 | [diff] [blame] | 1360 | host->hw_designer = amba_manf(dev); |
| 1361 | host->hw_revision = amba_rev(dev); |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 1362 | dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); |
| 1363 | dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); |
Russell King | 012b7d3 | 2009-07-09 15:13:56 +0100 | [diff] [blame] | 1364 | |
Russell King | ee569c4 | 2008-11-30 17:38:14 +0000 | [diff] [blame] | 1365 | host->clk = clk_get(&dev->dev, NULL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1366 | if (IS_ERR(host->clk)) { |
| 1367 | ret = PTR_ERR(host->clk); |
| 1368 | host->clk = NULL; |
| 1369 | goto host_free; |
| 1370 | } |
| 1371 | |
Julia Lawall | ac94093 | 2012-08-26 16:00:59 +0000 | [diff] [blame] | 1372 | ret = clk_prepare_enable(host->clk); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1373 | if (ret) |
Russell King | a8d3584 | 2006-01-03 18:41:37 +0000 | [diff] [blame] | 1374 | goto clk_free; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1375 | |
| 1376 | host->plat = plat; |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 1377 | host->variant = variant; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1378 | host->mclk = clk_get_rate(host->clk); |
Linus Walleij | c8df9a5 | 2008-04-29 09:34:07 +0100 | [diff] [blame] | 1379 | /* |
| 1380 | * According to the spec, mclk is max 100 MHz, |
| 1381 | * so we try to adjust the clock down to this, |
| 1382 | * (if possible). |
| 1383 | */ |
| 1384 | if (host->mclk > 100000000) { |
| 1385 | ret = clk_set_rate(host->clk, 100000000); |
| 1386 | if (ret < 0) |
| 1387 | goto clk_disable; |
| 1388 | host->mclk = clk_get_rate(host->clk); |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 1389 | dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", |
| 1390 | host->mclk); |
Linus Walleij | c8df9a5 | 2008-04-29 09:34:07 +0100 | [diff] [blame] | 1391 | } |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 1392 | host->phybase = dev->res.start; |
Linus Walleij | dc890c2 | 2009-06-07 23:27:31 +0100 | [diff] [blame] | 1393 | host->base = ioremap(dev->res.start, resource_size(&dev->res)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1394 | if (!host->base) { |
| 1395 | ret = -ENOMEM; |
| 1396 | goto clk_disable; |
| 1397 | } |
| 1398 | |
| 1399 | mmc->ops = &mmci_ops; |
Linus Walleij | 7f294e4 | 2011-07-08 09:57:15 +0100 | [diff] [blame] | 1400 | /* |
| 1401 | * The ARM and ST versions of the block have slightly different |
| 1402 | * clock divider equations which means that the minimum divider |
| 1403 | * differs too. |
| 1404 | */ |
| 1405 | if (variant->st_clkdiv) |
| 1406 | mmc->f_min = DIV_ROUND_UP(host->mclk, 257); |
| 1407 | else |
| 1408 | mmc->f_min = DIV_ROUND_UP(host->mclk, 512); |
Linus Walleij | 808d97c | 2010-04-08 07:39:38 +0100 | [diff] [blame] | 1409 | /* |
| 1410 | * If the platform data supplies a maximum operating |
| 1411 | * frequency, this takes precedence. Else, we fall back |
| 1412 | * to using the module parameter, which has a (low) |
| 1413 | * default value in case it is not specified. Either |
| 1414 | * value must not exceed the clock rate into the block, |
| 1415 | * of course. |
| 1416 | */ |
| 1417 | if (plat->f_max) |
| 1418 | mmc->f_max = min(host->mclk, plat->f_max); |
| 1419 | else |
| 1420 | mmc->f_max = min(host->mclk, fmax); |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 1421 | dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); |
| 1422 | |
Linus Walleij | a9a8378 | 2012-10-29 14:39:30 +0100 | [diff] [blame] | 1423 | host->pinctrl = devm_pinctrl_get(&dev->dev); |
| 1424 | if (IS_ERR(host->pinctrl)) { |
| 1425 | ret = PTR_ERR(host->pinctrl); |
| 1426 | goto clk_disable; |
| 1427 | } |
| 1428 | |
| 1429 | host->pins_default = pinctrl_lookup_state(host->pinctrl, |
| 1430 | PINCTRL_STATE_DEFAULT); |
| 1431 | |
| 1432 | /* enable pins to be muxed in and configured */ |
| 1433 | if (!IS_ERR(host->pins_default)) { |
| 1434 | ret = pinctrl_select_state(host->pinctrl, host->pins_default); |
| 1435 | if (ret) |
| 1436 | dev_warn(&dev->dev, "could not set default pins\n"); |
| 1437 | } else |
| 1438 | dev_warn(&dev->dev, "could not get default pinstate\n"); |
| 1439 | |
Ulf Hansson | 599c1d5 | 2013-01-07 16:22:50 +0100 | [diff] [blame] | 1440 | /* Get regulators and the supported OCR mask */ |
| 1441 | mmc_regulator_get_supply(mmc); |
| 1442 | if (!mmc->ocr_avail) |
Linus Walleij | 34e84f3 | 2009-09-22 14:41:40 +0100 | [diff] [blame] | 1443 | mmc->ocr_avail = plat->ocr_mask; |
Ulf Hansson | 599c1d5 | 2013-01-07 16:22:50 +0100 | [diff] [blame] | 1444 | else if (plat->ocr_mask) |
| 1445 | dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); |
| 1446 | |
Linus Walleij | 9e6c82c | 2009-09-14 12:57:11 +0100 | [diff] [blame] | 1447 | mmc->caps = plat->capabilities; |
Per Forlin | 5a09262 | 2011-11-14 12:02:28 +0100 | [diff] [blame] | 1448 | mmc->caps2 = plat->capabilities2; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1449 | |
Ulf Hansson | 70be208 | 2013-01-07 15:35:06 +0100 | [diff] [blame] | 1450 | /* We support these PM capabilities. */ |
| 1451 | mmc->pm_caps = MMC_PM_KEEP_POWER; |
| 1452 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1453 | /* |
| 1454 | * We can do SGIO |
| 1455 | */ |
Martin K. Petersen | a36274e | 2010-09-10 01:33:59 -0400 | [diff] [blame] | 1456 | mmc->max_segs = NR_SG; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1457 | |
| 1458 | /* |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 1459 | * Since only a certain number of bits are valid in the data length |
| 1460 | * register, we must ensure that we don't exceed 2^num-1 bytes in a |
| 1461 | * single request. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1462 | */ |
Rabin Vincent | 08458ef | 2010-07-21 12:55:59 +0100 | [diff] [blame] | 1463 | mmc->max_req_size = (1 << variant->datalength_bits) - 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1464 | |
| 1465 | /* |
| 1466 | * Set the maximum segment size. Since we aren't doing DMA |
| 1467 | * (yet) we are only limited by the data length register. |
| 1468 | */ |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 1469 | mmc->max_seg_size = mmc->max_req_size; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1470 | |
Pierre Ossman | fe4a3c7 | 2006-11-21 17:54:23 +0100 | [diff] [blame] | 1471 | /* |
| 1472 | * Block size can be up to 2048 bytes, but must be a power of two. |
| 1473 | */ |
Will Deacon | 8f7f6b7 | 2012-02-24 11:25:21 +0000 | [diff] [blame] | 1474 | mmc->max_blk_size = 1 << 11; |
Pierre Ossman | fe4a3c7 | 2006-11-21 17:54:23 +0100 | [diff] [blame] | 1475 | |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 1476 | /* |
Will Deacon | 8f7f6b7 | 2012-02-24 11:25:21 +0000 | [diff] [blame] | 1477 | * Limit the number of blocks transferred so that we don't overflow |
| 1478 | * the maximum request size. |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 1479 | */ |
Will Deacon | 8f7f6b7 | 2012-02-24 11:25:21 +0000 | [diff] [blame] | 1480 | mmc->max_blk_count = mmc->max_req_size >> 11; |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 1481 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1482 | spin_lock_init(&host->lock); |
| 1483 | |
| 1484 | writel(0, host->base + MMCIMASK0); |
| 1485 | writel(0, host->base + MMCIMASK1); |
| 1486 | writel(0xfff, host->base + MMCICLEAR); |
| 1487 | |
Roland Stigge | 2805b9a | 2012-06-17 21:14:27 +0100 | [diff] [blame] | 1488 | if (plat->gpio_cd == -EPROBE_DEFER) { |
| 1489 | ret = -EPROBE_DEFER; |
| 1490 | goto err_gpio_cd; |
| 1491 | } |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1492 | if (gpio_is_valid(plat->gpio_cd)) { |
| 1493 | ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); |
| 1494 | if (ret == 0) |
| 1495 | ret = gpio_direction_input(plat->gpio_cd); |
| 1496 | if (ret == 0) |
| 1497 | host->gpio_cd = plat->gpio_cd; |
| 1498 | else if (ret != -ENOSYS) |
| 1499 | goto err_gpio_cd; |
Rabin Vincent | 148b8b3 | 2010-08-09 12:55:48 +0100 | [diff] [blame] | 1500 | |
Linus Walleij | 17ee083 | 2011-05-05 17:23:10 +0100 | [diff] [blame] | 1501 | /* |
| 1502 | * A gpio pin that will detect cards when inserted and removed |
| 1503 | * will most likely want to trigger on the edges if it is |
| 1504 | * 0 when ejected and 1 when inserted (or mutatis mutandis |
| 1505 | * for the inverted case) so we request triggers on both |
| 1506 | * edges. |
| 1507 | */ |
Rabin Vincent | 148b8b3 | 2010-08-09 12:55:48 +0100 | [diff] [blame] | 1508 | ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), |
Linus Walleij | 17ee083 | 2011-05-05 17:23:10 +0100 | [diff] [blame] | 1509 | mmci_cd_irq, |
| 1510 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, |
| 1511 | DRIVER_NAME " (cd)", host); |
Rabin Vincent | 148b8b3 | 2010-08-09 12:55:48 +0100 | [diff] [blame] | 1512 | if (ret >= 0) |
| 1513 | host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1514 | } |
Roland Stigge | 2805b9a | 2012-06-17 21:14:27 +0100 | [diff] [blame] | 1515 | if (plat->gpio_wp == -EPROBE_DEFER) { |
| 1516 | ret = -EPROBE_DEFER; |
| 1517 | goto err_gpio_wp; |
| 1518 | } |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1519 | if (gpio_is_valid(plat->gpio_wp)) { |
| 1520 | ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); |
| 1521 | if (ret == 0) |
| 1522 | ret = gpio_direction_input(plat->gpio_wp); |
| 1523 | if (ret == 0) |
| 1524 | host->gpio_wp = plat->gpio_wp; |
| 1525 | else if (ret != -ENOSYS) |
| 1526 | goto err_gpio_wp; |
| 1527 | } |
| 1528 | |
Rabin Vincent | 4b8caec | 2010-08-09 12:56:40 +0100 | [diff] [blame] | 1529 | if ((host->plat->status || host->gpio_cd != -ENOSYS) |
| 1530 | && host->gpio_cd_irq < 0) |
Rabin Vincent | 148b8b3 | 2010-08-09 12:55:48 +0100 | [diff] [blame] | 1531 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
| 1532 | |
Thomas Gleixner | dace145 | 2006-07-01 19:29:38 -0700 | [diff] [blame] | 1533 | ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1534 | if (ret) |
| 1535 | goto unmap; |
| 1536 | |
Russell King | dfb85185 | 2012-05-03 11:33:15 +0100 | [diff] [blame] | 1537 | if (!dev->irq[1]) |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 1538 | host->singleirq = true; |
| 1539 | else { |
| 1540 | ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, |
| 1541 | DRIVER_NAME " (pio)", host); |
| 1542 | if (ret) |
| 1543 | goto irq0_free; |
| 1544 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1545 | |
Linus Walleij | 8cb2815 | 2011-01-24 15:22:13 +0100 | [diff] [blame] | 1546 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1547 | |
| 1548 | amba_set_drvdata(dev, mmc); |
| 1549 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 1550 | dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", |
| 1551 | mmc_hostname(mmc), amba_part(dev), amba_manf(dev), |
| 1552 | amba_rev(dev), (unsigned long long)dev->res.start, |
| 1553 | dev->irq[0], dev->irq[1]); |
| 1554 | |
| 1555 | mmci_dma_setup(host); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1556 | |
Ulf Hansson | 2cd976c | 2011-12-13 17:01:11 +0100 | [diff] [blame] | 1557 | pm_runtime_set_autosuspend_delay(&dev->dev, 50); |
| 1558 | pm_runtime_use_autosuspend(&dev->dev); |
Russell King | 1c3be36 | 2011-08-14 09:17:05 +0100 | [diff] [blame] | 1559 | pm_runtime_put(&dev->dev); |
| 1560 | |
Russell King | 8c11a94 | 2010-12-28 19:40:40 +0000 | [diff] [blame] | 1561 | mmc_add_host(mmc); |
| 1562 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1563 | return 0; |
| 1564 | |
| 1565 | irq0_free: |
| 1566 | free_irq(dev->irq[0], host); |
| 1567 | unmap: |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1568 | if (host->gpio_wp != -ENOSYS) |
| 1569 | gpio_free(host->gpio_wp); |
| 1570 | err_gpio_wp: |
Rabin Vincent | 148b8b3 | 2010-08-09 12:55:48 +0100 | [diff] [blame] | 1571 | if (host->gpio_cd_irq >= 0) |
| 1572 | free_irq(host->gpio_cd_irq, host); |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1573 | if (host->gpio_cd != -ENOSYS) |
| 1574 | gpio_free(host->gpio_cd); |
| 1575 | err_gpio_cd: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1576 | iounmap(host->base); |
| 1577 | clk_disable: |
Julia Lawall | ac94093 | 2012-08-26 16:00:59 +0000 | [diff] [blame] | 1578 | clk_disable_unprepare(host->clk); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1579 | clk_free: |
| 1580 | clk_put(host->clk); |
| 1581 | host_free: |
| 1582 | mmc_free_host(mmc); |
| 1583 | rel_regions: |
| 1584 | amba_release_regions(dev); |
| 1585 | out: |
| 1586 | return ret; |
| 1587 | } |
| 1588 | |
Bill Pemberton | 6e0ee71 | 2012-11-19 13:26:03 -0500 | [diff] [blame] | 1589 | static int mmci_remove(struct amba_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1590 | { |
| 1591 | struct mmc_host *mmc = amba_get_drvdata(dev); |
| 1592 | |
| 1593 | amba_set_drvdata(dev, NULL); |
| 1594 | |
| 1595 | if (mmc) { |
| 1596 | struct mmci_host *host = mmc_priv(mmc); |
| 1597 | |
Russell King | 1c3be36 | 2011-08-14 09:17:05 +0100 | [diff] [blame] | 1598 | /* |
| 1599 | * Undo pm_runtime_put() in probe. We use the _sync |
| 1600 | * version here so that we can access the primecell. |
| 1601 | */ |
| 1602 | pm_runtime_get_sync(&dev->dev); |
| 1603 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1604 | mmc_remove_host(mmc); |
| 1605 | |
| 1606 | writel(0, host->base + MMCIMASK0); |
| 1607 | writel(0, host->base + MMCIMASK1); |
| 1608 | |
| 1609 | writel(0, host->base + MMCICOMMAND); |
| 1610 | writel(0, host->base + MMCIDATACTRL); |
| 1611 | |
Russell King | c8ebae3 | 2011-01-11 19:35:53 +0000 | [diff] [blame] | 1612 | mmci_dma_release(host); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1613 | free_irq(dev->irq[0], host); |
Linus Walleij | 2686b4b | 2010-10-19 12:39:48 +0100 | [diff] [blame] | 1614 | if (!host->singleirq) |
| 1615 | free_irq(dev->irq[1], host); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1616 | |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1617 | if (host->gpio_wp != -ENOSYS) |
| 1618 | gpio_free(host->gpio_wp); |
Rabin Vincent | 148b8b3 | 2010-08-09 12:55:48 +0100 | [diff] [blame] | 1619 | if (host->gpio_cd_irq >= 0) |
| 1620 | free_irq(host->gpio_cd_irq, host); |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 1621 | if (host->gpio_cd != -ENOSYS) |
| 1622 | gpio_free(host->gpio_cd); |
| 1623 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1624 | iounmap(host->base); |
Julia Lawall | ac94093 | 2012-08-26 16:00:59 +0000 | [diff] [blame] | 1625 | clk_disable_unprepare(host->clk); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1626 | clk_put(host->clk); |
| 1627 | |
| 1628 | mmc_free_host(mmc); |
| 1629 | |
| 1630 | amba_release_regions(dev); |
| 1631 | } |
| 1632 | |
| 1633 | return 0; |
| 1634 | } |
| 1635 | |
Ulf Hansson | 48fa700 | 2011-12-13 16:59:34 +0100 | [diff] [blame] | 1636 | #ifdef CONFIG_SUSPEND |
| 1637 | static int mmci_suspend(struct device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1638 | { |
Ulf Hansson | 48fa700 | 2011-12-13 16:59:34 +0100 | [diff] [blame] | 1639 | struct amba_device *adev = to_amba_device(dev); |
| 1640 | struct mmc_host *mmc = amba_get_drvdata(adev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1641 | int ret = 0; |
| 1642 | |
| 1643 | if (mmc) { |
| 1644 | struct mmci_host *host = mmc_priv(mmc); |
| 1645 | |
Matt Fleming | 1a13f8f | 2010-05-26 14:42:08 -0700 | [diff] [blame] | 1646 | ret = mmc_suspend_host(mmc); |
Ulf Hansson | 2cd976c | 2011-12-13 17:01:11 +0100 | [diff] [blame] | 1647 | if (ret == 0) { |
| 1648 | pm_runtime_get_sync(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1649 | writel(0, host->base + MMCIMASK0); |
Ulf Hansson | 2cd976c | 2011-12-13 17:01:11 +0100 | [diff] [blame] | 1650 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1651 | } |
| 1652 | |
| 1653 | return ret; |
| 1654 | } |
| 1655 | |
Ulf Hansson | 48fa700 | 2011-12-13 16:59:34 +0100 | [diff] [blame] | 1656 | static int mmci_resume(struct device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1657 | { |
Ulf Hansson | 48fa700 | 2011-12-13 16:59:34 +0100 | [diff] [blame] | 1658 | struct amba_device *adev = to_amba_device(dev); |
| 1659 | struct mmc_host *mmc = amba_get_drvdata(adev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1660 | int ret = 0; |
| 1661 | |
| 1662 | if (mmc) { |
| 1663 | struct mmci_host *host = mmc_priv(mmc); |
| 1664 | |
| 1665 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); |
Ulf Hansson | 2cd976c | 2011-12-13 17:01:11 +0100 | [diff] [blame] | 1666 | pm_runtime_put(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1667 | |
| 1668 | ret = mmc_resume_host(mmc); |
| 1669 | } |
| 1670 | |
| 1671 | return ret; |
| 1672 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1673 | #endif |
| 1674 | |
Ulf Hansson | 8259293 | 2013-01-09 11:15:26 +0100 | [diff] [blame] | 1675 | #ifdef CONFIG_PM_RUNTIME |
| 1676 | static int mmci_runtime_suspend(struct device *dev) |
| 1677 | { |
| 1678 | struct amba_device *adev = to_amba_device(dev); |
| 1679 | struct mmc_host *mmc = amba_get_drvdata(adev); |
| 1680 | |
| 1681 | if (mmc) { |
| 1682 | struct mmci_host *host = mmc_priv(mmc); |
| 1683 | clk_disable_unprepare(host->clk); |
| 1684 | } |
| 1685 | |
| 1686 | return 0; |
| 1687 | } |
| 1688 | |
| 1689 | static int mmci_runtime_resume(struct device *dev) |
| 1690 | { |
| 1691 | struct amba_device *adev = to_amba_device(dev); |
| 1692 | struct mmc_host *mmc = amba_get_drvdata(adev); |
| 1693 | |
| 1694 | if (mmc) { |
| 1695 | struct mmci_host *host = mmc_priv(mmc); |
| 1696 | clk_prepare_enable(host->clk); |
| 1697 | } |
| 1698 | |
| 1699 | return 0; |
| 1700 | } |
| 1701 | #endif |
| 1702 | |
Ulf Hansson | 48fa700 | 2011-12-13 16:59:34 +0100 | [diff] [blame] | 1703 | static const struct dev_pm_ops mmci_dev_pm_ops = { |
| 1704 | SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume) |
Ulf Hansson | 8259293 | 2013-01-09 11:15:26 +0100 | [diff] [blame] | 1705 | SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) |
Ulf Hansson | 48fa700 | 2011-12-13 16:59:34 +0100 | [diff] [blame] | 1706 | }; |
| 1707 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1708 | static struct amba_id mmci_ids[] = { |
| 1709 | { |
| 1710 | .id = 0x00041180, |
Pawel Moll | 768fbc1 | 2011-03-11 17:18:07 +0000 | [diff] [blame] | 1711 | .mask = 0xff0fffff, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 1712 | .data = &variant_arm, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1713 | }, |
| 1714 | { |
Pawel Moll | 768fbc1 | 2011-03-11 17:18:07 +0000 | [diff] [blame] | 1715 | .id = 0x01041180, |
| 1716 | .mask = 0xff0fffff, |
| 1717 | .data = &variant_arm_extended_fifo, |
| 1718 | }, |
| 1719 | { |
Pawel Moll | 3a37298 | 2013-01-24 14:12:45 +0100 | [diff] [blame] | 1720 | .id = 0x02041180, |
| 1721 | .mask = 0xff0fffff, |
| 1722 | .data = &variant_arm_extended_fifo_hwfc, |
| 1723 | }, |
| 1724 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1725 | .id = 0x00041181, |
| 1726 | .mask = 0x000fffff, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 1727 | .data = &variant_arm, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1728 | }, |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 1729 | /* ST Micro variants */ |
| 1730 | { |
| 1731 | .id = 0x00180180, |
| 1732 | .mask = 0x00ffffff, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 1733 | .data = &variant_u300, |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 1734 | }, |
| 1735 | { |
Linus Walleij | 34fd421 | 2012-04-10 17:43:59 +0100 | [diff] [blame] | 1736 | .id = 0x10180180, |
| 1737 | .mask = 0xf0ffffff, |
| 1738 | .data = &variant_nomadik, |
| 1739 | }, |
| 1740 | { |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 1741 | .id = 0x00280180, |
| 1742 | .mask = 0x00ffffff, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 1743 | .data = &variant_u300, |
| 1744 | }, |
| 1745 | { |
| 1746 | .id = 0x00480180, |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 1747 | .mask = 0xf0ffffff, |
Rabin Vincent | 4956e10 | 2010-07-21 12:54:40 +0100 | [diff] [blame] | 1748 | .data = &variant_ux500, |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 1749 | }, |
Philippe Langlais | 1784b15 | 2011-03-25 08:51:52 +0100 | [diff] [blame] | 1750 | { |
| 1751 | .id = 0x10480180, |
| 1752 | .mask = 0xf0ffffff, |
| 1753 | .data = &variant_ux500v2, |
| 1754 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1755 | { 0, 0 }, |
| 1756 | }; |
| 1757 | |
Dave Martin | 9f99835 | 2011-10-05 15:15:21 +0100 | [diff] [blame] | 1758 | MODULE_DEVICE_TABLE(amba, mmci_ids); |
| 1759 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1760 | static struct amba_driver mmci_driver = { |
| 1761 | .drv = { |
| 1762 | .name = DRIVER_NAME, |
Ulf Hansson | 48fa700 | 2011-12-13 16:59:34 +0100 | [diff] [blame] | 1763 | .pm = &mmci_dev_pm_ops, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1764 | }, |
| 1765 | .probe = mmci_probe, |
Bill Pemberton | 0433c14 | 2012-11-19 13:20:26 -0500 | [diff] [blame] | 1766 | .remove = mmci_remove, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1767 | .id_table = mmci_ids, |
| 1768 | }; |
| 1769 | |
viresh kumar | 9e5ed09 | 2012-03-15 10:40:38 +0100 | [diff] [blame] | 1770 | module_amba_driver(mmci_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1771 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1772 | module_param(fmax, uint, 0444); |
| 1773 | |
| 1774 | MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); |
| 1775 | MODULE_LICENSE("GPL"); |