Alex Elder | 1f27f15 | 2014-02-14 12:29:18 -0600 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Broadcom Corporation |
| 3 | * Copyright 2013 Linaro Limited |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License as |
| 7 | * published by the Free Software Foundation version 2. |
| 8 | * |
| 9 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
| 10 | * kind, whether express or implied; without even the implied warranty |
| 11 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | #ifndef _CLK_KONA_H |
| 16 | #define _CLK_KONA_H |
| 17 | |
| 18 | #include <linux/kernel.h> |
| 19 | #include <linux/list.h> |
| 20 | #include <linux/spinlock.h> |
| 21 | #include <linux/slab.h> |
| 22 | #include <linux/device.h> |
| 23 | #include <linux/of.h> |
| 24 | #include <linux/clk-provider.h> |
| 25 | |
| 26 | #define BILLION 1000000000 |
| 27 | |
| 28 | /* The common clock framework uses u8 to represent a parent index */ |
| 29 | #define PARENT_COUNT_MAX ((u32)U8_MAX) |
| 30 | |
| 31 | #define BAD_CLK_INDEX U8_MAX /* Can't ever be valid */ |
| 32 | #define BAD_CLK_NAME ((const char *)-1) |
| 33 | |
| 34 | #define BAD_SCALED_DIV_VALUE U64_MAX |
| 35 | |
| 36 | /* |
| 37 | * Utility macros for object flag management. If possible, flags |
| 38 | * should be defined such that 0 is the desired default value. |
| 39 | */ |
| 40 | #define FLAG(type, flag) BCM_CLK_ ## type ## _FLAGS_ ## flag |
| 41 | #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag)) |
| 42 | #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag))) |
| 43 | #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag)) |
| 44 | #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag))) |
| 45 | |
Alex Elder | a597fac | 2014-04-21 16:11:42 -0500 | [diff] [blame] | 46 | /* CCU field state tests */ |
| 47 | |
| 48 | #define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0) |
| 49 | |
Alex Elder | 1f27f15 | 2014-02-14 12:29:18 -0600 | [diff] [blame] | 50 | /* Clock field state tests */ |
| 51 | |
Alex Elder | a597fac | 2014-04-21 16:11:42 -0500 | [diff] [blame] | 52 | #define policy_exists(policy) ((policy)->offset != 0) |
| 53 | |
Alex Elder | 1f27f15 | 2014-02-14 12:29:18 -0600 | [diff] [blame] | 54 | #define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS) |
| 55 | #define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED) |
| 56 | #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW) |
| 57 | #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW) |
| 58 | #define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED) |
| 59 | #define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE) |
| 60 | |
| 61 | #define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED) |
| 62 | |
Alex Elder | dc61384 | 2014-04-21 16:11:43 -0500 | [diff] [blame] | 63 | #define hyst_exists(hyst) ((hyst)->offset != 0) |
| 64 | |
Alex Elder | 1f27f15 | 2014-02-14 12:29:18 -0600 | [diff] [blame] | 65 | #define divider_exists(div) FLAG_TEST(div, DIV, EXISTS) |
| 66 | #define divider_is_fixed(div) FLAG_TEST(div, DIV, FIXED) |
| 67 | #define divider_has_fraction(div) (!divider_is_fixed(div) && \ |
Alex Elder | e813d49 | 2014-04-07 08:22:12 -0500 | [diff] [blame] | 68 | (div)->u.s.frac_width > 0) |
Alex Elder | 1f27f15 | 2014-02-14 12:29:18 -0600 | [diff] [blame] | 69 | |
| 70 | #define selector_exists(sel) ((sel)->width != 0) |
| 71 | #define trigger_exists(trig) FLAG_TEST(trig, TRIG, EXISTS) |
| 72 | |
Alex Elder | a597fac | 2014-04-21 16:11:42 -0500 | [diff] [blame] | 73 | #define policy_lvm_en_exists(enable) ((enable)->offset != 0) |
| 74 | #define policy_ctl_exists(control) ((control)->offset != 0) |
| 75 | |
Alex Elder | 1f27f15 | 2014-02-14 12:29:18 -0600 | [diff] [blame] | 76 | /* Clock type, used to tell common block what it's part of */ |
| 77 | enum bcm_clk_type { |
| 78 | bcm_clk_none, /* undefined clock type */ |
| 79 | bcm_clk_bus, |
| 80 | bcm_clk_core, |
| 81 | bcm_clk_peri |
| 82 | }; |
| 83 | |
| 84 | /* |
Alex Elder | a597fac | 2014-04-21 16:11:42 -0500 | [diff] [blame] | 85 | * CCU policy control for clocks. Clocks can be enabled or disabled |
| 86 | * based on the CCU policy in effect. One bit in each policy mask |
| 87 | * register (one per CCU policy) represents whether the clock is |
| 88 | * enabled when that policy is effect or not. The CCU policy engine |
| 89 | * must be stopped to update these bits, and must be restarted again |
| 90 | * afterward. |
| 91 | */ |
| 92 | struct bcm_clk_policy { |
| 93 | u32 offset; /* first policy mask register offset */ |
| 94 | u32 bit; /* bit used in all mask registers */ |
| 95 | }; |
| 96 | |
| 97 | /* Policy initialization macro */ |
| 98 | |
| 99 | #define POLICY(_offset, _bit) \ |
| 100 | { \ |
| 101 | .offset = (_offset), \ |
| 102 | .bit = (_bit), \ |
| 103 | } |
| 104 | |
| 105 | /* |
Alex Elder | 1f27f15 | 2014-02-14 12:29:18 -0600 | [diff] [blame] | 106 | * Gating control and status is managed by a 32-bit gate register. |
| 107 | * |
| 108 | * There are several types of gating available: |
| 109 | * - (no gate) |
| 110 | * A clock with no gate is assumed to be always enabled. |
| 111 | * - hardware-only gating (auto-gating) |
| 112 | * Enabling or disabling clocks with this type of gate is |
| 113 | * managed automatically by the hardware. Such clocks can be |
| 114 | * considered by the software to be enabled. The current status |
| 115 | * of auto-gated clocks can be read from the gate status bit. |
| 116 | * - software-only gating |
| 117 | * Auto-gating is not available for this type of clock. |
| 118 | * Instead, software manages whether it's enabled by setting or |
| 119 | * clearing the enable bit. The current gate status of a gate |
| 120 | * under software control can be read from the gate status bit. |
| 121 | * To ensure a change to the gating status is complete, the |
| 122 | * status bit can be polled to verify that the gate has entered |
| 123 | * the desired state. |
| 124 | * - selectable hardware or software gating |
| 125 | * Gating for this type of clock can be configured to be either |
| 126 | * under software or hardware control. Which type is in use is |
| 127 | * determined by the hw_sw_sel bit of the gate register. |
| 128 | */ |
| 129 | struct bcm_clk_gate { |
| 130 | u32 offset; /* gate register offset */ |
| 131 | u32 status_bit; /* 0: gate is disabled; 0: gatge is enabled */ |
| 132 | u32 en_bit; /* 0: disable; 1: enable */ |
| 133 | u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */ |
| 134 | u32 flags; /* BCM_CLK_GATE_FLAGS_* below */ |
| 135 | }; |
| 136 | |
| 137 | /* |
| 138 | * Gate flags: |
| 139 | * HW means this gate can be auto-gated |
| 140 | * SW means the state of this gate can be software controlled |
| 141 | * NO_DISABLE means this gate is (only) enabled if under software control |
| 142 | * SW_MANAGED means the status of this gate is under software control |
| 143 | * ENABLED means this software-managed gate is *supposed* to be enabled |
| 144 | */ |
| 145 | #define BCM_CLK_GATE_FLAGS_EXISTS ((u32)1 << 0) /* Gate is valid */ |
| 146 | #define BCM_CLK_GATE_FLAGS_HW ((u32)1 << 1) /* Can auto-gate */ |
| 147 | #define BCM_CLK_GATE_FLAGS_SW ((u32)1 << 2) /* Software control */ |
| 148 | #define BCM_CLK_GATE_FLAGS_NO_DISABLE ((u32)1 << 3) /* HW or enabled */ |
| 149 | #define BCM_CLK_GATE_FLAGS_SW_MANAGED ((u32)1 << 4) /* SW now in control */ |
| 150 | #define BCM_CLK_GATE_FLAGS_ENABLED ((u32)1 << 5) /* If SW_MANAGED */ |
| 151 | |
| 152 | /* |
| 153 | * Gate initialization macros. |
| 154 | * |
| 155 | * Any gate initially under software control will be enabled. |
| 156 | */ |
| 157 | |
| 158 | /* A hardware/software gate initially under software control */ |
| 159 | #define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ |
| 160 | { \ |
| 161 | .offset = (_offset), \ |
| 162 | .status_bit = (_status_bit), \ |
| 163 | .en_bit = (_en_bit), \ |
| 164 | .hw_sw_sel_bit = (_hw_sw_sel_bit), \ |
| 165 | .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ |
| 166 | FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)| \ |
| 167 | FLAG(GATE, EXISTS), \ |
| 168 | } |
| 169 | |
| 170 | /* A hardware/software gate initially under hardware control */ |
| 171 | #define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ |
| 172 | { \ |
| 173 | .offset = (_offset), \ |
| 174 | .status_bit = (_status_bit), \ |
| 175 | .en_bit = (_en_bit), \ |
| 176 | .hw_sw_sel_bit = (_hw_sw_sel_bit), \ |
| 177 | .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ |
| 178 | FLAG(GATE, EXISTS), \ |
| 179 | } |
| 180 | |
| 181 | /* A hardware-or-enabled gate (enabled if not under hardware control) */ |
| 182 | #define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ |
| 183 | { \ |
| 184 | .offset = (_offset), \ |
| 185 | .status_bit = (_status_bit), \ |
| 186 | .en_bit = (_en_bit), \ |
| 187 | .hw_sw_sel_bit = (_hw_sw_sel_bit), \ |
| 188 | .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ |
| 189 | FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS), \ |
| 190 | } |
| 191 | |
| 192 | /* A software-only gate */ |
| 193 | #define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \ |
| 194 | { \ |
| 195 | .offset = (_offset), \ |
| 196 | .status_bit = (_status_bit), \ |
| 197 | .en_bit = (_en_bit), \ |
| 198 | .flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \ |
| 199 | FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS), \ |
| 200 | } |
| 201 | |
| 202 | /* A hardware-only gate */ |
| 203 | #define HW_ONLY_GATE(_offset, _status_bit) \ |
| 204 | { \ |
| 205 | .offset = (_offset), \ |
| 206 | .status_bit = (_status_bit), \ |
| 207 | .flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \ |
| 208 | } |
| 209 | |
Alex Elder | dc61384 | 2014-04-21 16:11:43 -0500 | [diff] [blame] | 210 | /* Gate hysteresis for clocks */ |
| 211 | struct bcm_clk_hyst { |
| 212 | u32 offset; /* hyst register offset (normally CLKGATE) */ |
| 213 | u32 en_bit; /* bit used to enable hysteresis */ |
| 214 | u32 val_bit; /* if enabled: 0 = low delay; 1 = high delay */ |
| 215 | }; |
| 216 | |
| 217 | /* Hysteresis initialization macro */ |
| 218 | |
| 219 | #define HYST(_offset, _en_bit, _val_bit) \ |
| 220 | { \ |
| 221 | .offset = (_offset), \ |
| 222 | .en_bit = (_en_bit), \ |
| 223 | .val_bit = (_val_bit), \ |
| 224 | } |
| 225 | |
Alex Elder | 1f27f15 | 2014-02-14 12:29:18 -0600 | [diff] [blame] | 226 | /* |
| 227 | * Each clock can have zero, one, or two dividers which change the |
| 228 | * output rate of the clock. Each divider can be either fixed or |
| 229 | * variable. If there are two dividers, they are the "pre-divider" |
| 230 | * and the "regular" or "downstream" divider. If there is only one, |
| 231 | * there is no pre-divider. |
| 232 | * |
| 233 | * A fixed divider is any non-zero (positive) value, and it |
| 234 | * indicates how the input rate is affected by the divider. |
| 235 | * |
| 236 | * The value of a variable divider is maintained in a sub-field of a |
| 237 | * 32-bit divider register. The position of the field in the |
| 238 | * register is defined by its offset and width. The value recorded |
| 239 | * in this field is always 1 less than the value it represents. |
| 240 | * |
| 241 | * In addition, a variable divider can indicate that some subset |
| 242 | * of its bits represent a "fractional" part of the divider. Such |
| 243 | * bits comprise the low-order portion of the divider field, and can |
| 244 | * be viewed as representing the portion of the divider that lies to |
| 245 | * the right of the decimal point. Most variable dividers have zero |
| 246 | * fractional bits. Variable dividers with non-zero fraction width |
| 247 | * still record a value 1 less than the value they represent; the |
| 248 | * added 1 does *not* affect the low-order bit in this case, it |
| 249 | * affects the bits above the fractional part only. (Often in this |
| 250 | * code a divider field value is distinguished from the value it |
| 251 | * represents by referring to the latter as a "divisor".) |
| 252 | * |
| 253 | * In order to avoid dealing with fractions, divider arithmetic is |
| 254 | * performed using "scaled" values. A scaled value is one that's |
| 255 | * been left-shifted by the fractional width of a divider. Dividing |
| 256 | * a scaled value by a scaled divisor produces the desired quotient |
| 257 | * without loss of precision and without any other special handling |
| 258 | * for fractions. |
| 259 | * |
| 260 | * The recorded value of a variable divider can be modified. To |
| 261 | * modify either divider (or both), a clock must be enabled (i.e., |
| 262 | * using its gate). In addition, a trigger register (described |
| 263 | * below) must be used to commit the change, and polled to verify |
| 264 | * the change is complete. |
| 265 | */ |
| 266 | struct bcm_clk_div { |
| 267 | union { |
| 268 | struct { /* variable divider */ |
| 269 | u32 offset; /* divider register offset */ |
| 270 | u32 shift; /* field shift */ |
| 271 | u32 width; /* field width */ |
| 272 | u32 frac_width; /* field fraction width */ |
| 273 | |
| 274 | u64 scaled_div; /* scaled divider value */ |
Alex Elder | e813d49 | 2014-04-07 08:22:12 -0500 | [diff] [blame] | 275 | } s; |
Alex Elder | 1f27f15 | 2014-02-14 12:29:18 -0600 | [diff] [blame] | 276 | u32 fixed; /* non-zero fixed divider value */ |
Alex Elder | e813d49 | 2014-04-07 08:22:12 -0500 | [diff] [blame] | 277 | } u; |
Alex Elder | 1f27f15 | 2014-02-14 12:29:18 -0600 | [diff] [blame] | 278 | u32 flags; /* BCM_CLK_DIV_FLAGS_* below */ |
| 279 | }; |
| 280 | |
| 281 | /* |
| 282 | * Divider flags: |
| 283 | * EXISTS means this divider exists |
| 284 | * FIXED means it is a fixed-rate divider |
| 285 | */ |
| 286 | #define BCM_CLK_DIV_FLAGS_EXISTS ((u32)1 << 0) /* Divider is valid */ |
| 287 | #define BCM_CLK_DIV_FLAGS_FIXED ((u32)1 << 1) /* Fixed-value */ |
| 288 | |
| 289 | /* Divider initialization macros */ |
| 290 | |
| 291 | /* A fixed (non-zero) divider */ |
| 292 | #define FIXED_DIVIDER(_value) \ |
| 293 | { \ |
Alex Elder | e813d49 | 2014-04-07 08:22:12 -0500 | [diff] [blame] | 294 | .u.fixed = (_value), \ |
Alex Elder | 1f27f15 | 2014-02-14 12:29:18 -0600 | [diff] [blame] | 295 | .flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED), \ |
| 296 | } |
| 297 | |
| 298 | /* A divider with an integral divisor */ |
| 299 | #define DIVIDER(_offset, _shift, _width) \ |
| 300 | { \ |
Alex Elder | e813d49 | 2014-04-07 08:22:12 -0500 | [diff] [blame] | 301 | .u.s.offset = (_offset), \ |
| 302 | .u.s.shift = (_shift), \ |
| 303 | .u.s.width = (_width), \ |
| 304 | .u.s.scaled_div = BAD_SCALED_DIV_VALUE, \ |
Alex Elder | 1f27f15 | 2014-02-14 12:29:18 -0600 | [diff] [blame] | 305 | .flags = FLAG(DIV, EXISTS), \ |
| 306 | } |
| 307 | |
| 308 | /* A divider whose divisor has an integer and fractional part */ |
| 309 | #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ |
| 310 | { \ |
Alex Elder | e813d49 | 2014-04-07 08:22:12 -0500 | [diff] [blame] | 311 | .u.s.offset = (_offset), \ |
| 312 | .u.s.shift = (_shift), \ |
| 313 | .u.s.width = (_width), \ |
| 314 | .u.s.frac_width = (_frac_width), \ |
| 315 | .u.s.scaled_div = BAD_SCALED_DIV_VALUE, \ |
Alex Elder | 1f27f15 | 2014-02-14 12:29:18 -0600 | [diff] [blame] | 316 | .flags = FLAG(DIV, EXISTS), \ |
| 317 | } |
| 318 | |
| 319 | /* |
| 320 | * Clocks may have multiple "parent" clocks. If there is more than |
| 321 | * one, a selector must be specified to define which of the parent |
| 322 | * clocks is currently in use. The selected clock is indicated in a |
| 323 | * sub-field of a 32-bit selector register. The range of |
| 324 | * representable selector values typically exceeds the number of |
| 325 | * available parent clocks. Occasionally the reset value of a |
| 326 | * selector field is explicitly set to a (specific) value that does |
| 327 | * not correspond to a defined input clock. |
| 328 | * |
| 329 | * We register all known parent clocks with the common clock code |
| 330 | * using a packed array (i.e., no empty slots) of (parent) clock |
| 331 | * names, and refer to them later using indexes into that array. |
| 332 | * We maintain an array of selector values indexed by common clock |
| 333 | * index values in order to map between these common clock indexes |
| 334 | * and the selector values used by the hardware. |
| 335 | * |
| 336 | * Like dividers, a selector can be modified, but to do so a clock |
| 337 | * must be enabled, and a trigger must be used to commit the change. |
| 338 | */ |
| 339 | struct bcm_clk_sel { |
| 340 | u32 offset; /* selector register offset */ |
| 341 | u32 shift; /* field shift */ |
| 342 | u32 width; /* field width */ |
| 343 | |
| 344 | u32 parent_count; /* number of entries in parent_sel[] */ |
| 345 | u32 *parent_sel; /* array of parent selector values */ |
| 346 | u8 clk_index; /* current selected index in parent_sel[] */ |
| 347 | }; |
| 348 | |
| 349 | /* Selector initialization macro */ |
| 350 | #define SELECTOR(_offset, _shift, _width) \ |
| 351 | { \ |
| 352 | .offset = (_offset), \ |
| 353 | .shift = (_shift), \ |
| 354 | .width = (_width), \ |
| 355 | .clk_index = BAD_CLK_INDEX, \ |
| 356 | } |
| 357 | |
| 358 | /* |
| 359 | * Making changes to a variable divider or a selector for a clock |
| 360 | * requires the use of a trigger. A trigger is defined by a single |
| 361 | * bit within a register. To signal a change, a 1 is written into |
| 362 | * that bit. To determine when the change has been completed, that |
| 363 | * trigger bit is polled; the read value will be 1 while the change |
| 364 | * is in progress, and 0 when it is complete. |
| 365 | * |
| 366 | * Occasionally a clock will have more than one trigger. In this |
| 367 | * case, the "pre-trigger" will be used when changing a clock's |
| 368 | * selector and/or its pre-divider. |
| 369 | */ |
| 370 | struct bcm_clk_trig { |
| 371 | u32 offset; /* trigger register offset */ |
| 372 | u32 bit; /* trigger bit */ |
| 373 | u32 flags; /* BCM_CLK_TRIG_FLAGS_* below */ |
| 374 | }; |
| 375 | |
| 376 | /* |
| 377 | * Trigger flags: |
| 378 | * EXISTS means this trigger exists |
| 379 | */ |
| 380 | #define BCM_CLK_TRIG_FLAGS_EXISTS ((u32)1 << 0) /* Trigger is valid */ |
| 381 | |
| 382 | /* Trigger initialization macro */ |
| 383 | #define TRIGGER(_offset, _bit) \ |
| 384 | { \ |
| 385 | .offset = (_offset), \ |
| 386 | .bit = (_bit), \ |
| 387 | .flags = FLAG(TRIG, EXISTS), \ |
| 388 | } |
| 389 | |
| 390 | struct peri_clk_data { |
Alex Elder | a597fac | 2014-04-21 16:11:42 -0500 | [diff] [blame] | 391 | struct bcm_clk_policy policy; |
Alex Elder | 1f27f15 | 2014-02-14 12:29:18 -0600 | [diff] [blame] | 392 | struct bcm_clk_gate gate; |
Alex Elder | dc61384 | 2014-04-21 16:11:43 -0500 | [diff] [blame] | 393 | struct bcm_clk_hyst hyst; |
Alex Elder | 1f27f15 | 2014-02-14 12:29:18 -0600 | [diff] [blame] | 394 | struct bcm_clk_trig pre_trig; |
| 395 | struct bcm_clk_div pre_div; |
| 396 | struct bcm_clk_trig trig; |
| 397 | struct bcm_clk_div div; |
| 398 | struct bcm_clk_sel sel; |
| 399 | const char *clocks[]; /* must be last; use CLOCKS() to declare */ |
| 400 | }; |
| 401 | #define CLOCKS(...) { __VA_ARGS__, NULL, } |
| 402 | #define NO_CLOCKS { NULL, } /* Must use of no parent clocks */ |
| 403 | |
| 404 | struct kona_clk { |
| 405 | struct clk_hw hw; |
Alex Elder | e756325 | 2014-04-21 16:11:38 -0500 | [diff] [blame] | 406 | struct clk_init_data init_data; /* includes name of this clock */ |
Alex Elder | 1f27f15 | 2014-02-14 12:29:18 -0600 | [diff] [blame] | 407 | struct ccu_data *ccu; /* ccu this clock is associated with */ |
| 408 | enum bcm_clk_type type; |
| 409 | union { |
| 410 | void *data; |
| 411 | struct peri_clk_data *peri; |
Alex Elder | e813d49 | 2014-04-07 08:22:12 -0500 | [diff] [blame] | 412 | } u; |
Alex Elder | 1f27f15 | 2014-02-14 12:29:18 -0600 | [diff] [blame] | 413 | }; |
| 414 | #define to_kona_clk(_hw) \ |
| 415 | container_of(_hw, struct kona_clk, hw) |
| 416 | |
Alex Elder | 03548ec | 2014-04-21 16:11:41 -0500 | [diff] [blame] | 417 | /* Initialization macro for an entry in a CCU's kona_clks[] array. */ |
| 418 | #define KONA_CLK(_ccu_name, _clk_name, _type) \ |
| 419 | { \ |
| 420 | .init_data = { \ |
| 421 | .name = #_clk_name, \ |
| 422 | .ops = &kona_ ## _type ## _clk_ops, \ |
| 423 | }, \ |
| 424 | .ccu = &_ccu_name ## _ccu_data, \ |
| 425 | .type = bcm_clk_ ## _type, \ |
| 426 | .u.data = &_clk_name ## _data, \ |
| 427 | } |
| 428 | #define LAST_KONA_CLK { .type = bcm_clk_none } |
| 429 | |
| 430 | /* |
Alex Elder | a597fac | 2014-04-21 16:11:42 -0500 | [diff] [blame] | 431 | * CCU policy control. To enable software update of the policy |
| 432 | * tables the CCU policy engine must be stopped by setting the |
| 433 | * software update enable bit (LVM_EN). After an update the engine |
| 434 | * is restarted using the GO bit and either the GO_ATL or GO_AC bit. |
| 435 | */ |
| 436 | struct bcm_lvm_en { |
| 437 | u32 offset; /* LVM_EN register offset */ |
| 438 | u32 bit; /* POLICY_CONFIG_EN bit in register */ |
| 439 | }; |
| 440 | |
| 441 | /* Policy enable initialization macro */ |
| 442 | #define CCU_LVM_EN(_offset, _bit) \ |
| 443 | { \ |
| 444 | .offset = (_offset), \ |
| 445 | .bit = (_bit), \ |
| 446 | } |
| 447 | |
| 448 | struct bcm_policy_ctl { |
| 449 | u32 offset; /* POLICY_CTL register offset */ |
| 450 | u32 go_bit; |
| 451 | u32 atl_bit; /* GO, GO_ATL, and GO_AC bits */ |
| 452 | u32 ac_bit; |
| 453 | }; |
| 454 | |
| 455 | /* Policy control initialization macro */ |
| 456 | #define CCU_POLICY_CTL(_offset, _go_bit, _ac_bit, _atl_bit) \ |
| 457 | { \ |
| 458 | .offset = (_offset), \ |
| 459 | .go_bit = (_go_bit), \ |
| 460 | .ac_bit = (_ac_bit), \ |
| 461 | .atl_bit = (_atl_bit), \ |
| 462 | } |
| 463 | |
| 464 | struct ccu_policy { |
| 465 | struct bcm_lvm_en enable; |
| 466 | struct bcm_policy_ctl control; |
| 467 | }; |
| 468 | |
| 469 | /* |
Alex Elder | 03548ec | 2014-04-21 16:11:41 -0500 | [diff] [blame] | 470 | * Each CCU defines a mapped area of memory containing registers |
| 471 | * used to manage clocks implemented by the CCU. Access to memory |
| 472 | * within the CCU's space is serialized by a spinlock. Before any |
| 473 | * (other) address can be written, a special access "password" value |
| 474 | * must be written to its WR_ACCESS register (located at the base |
| 475 | * address of the range). We keep track of the name of each CCU as |
| 476 | * it is set up, and maintain them in a list. |
| 477 | */ |
| 478 | struct ccu_data { |
| 479 | void __iomem *base; /* base of mapped address space */ |
| 480 | spinlock_t lock; /* serialization lock */ |
| 481 | bool write_enabled; /* write access is currently enabled */ |
Alex Elder | a597fac | 2014-04-21 16:11:42 -0500 | [diff] [blame] | 482 | struct ccu_policy policy; |
Alex Elder | 03548ec | 2014-04-21 16:11:41 -0500 | [diff] [blame] | 483 | struct device_node *node; |
| 484 | struct clk_onecell_data clk_data; |
| 485 | const char *name; |
| 486 | u32 range; /* byte range of address space */ |
| 487 | struct kona_clk kona_clks[]; /* must be last */ |
| 488 | }; |
| 489 | |
| 490 | /* Initialization for common fields in a Kona ccu_data structure */ |
| 491 | #define KONA_CCU_COMMON(_prefix, _name, _ccuname) \ |
| 492 | .name = #_name "_ccu", \ |
| 493 | .lock = __SPIN_LOCK_UNLOCKED(_name ## _ccu_data.lock), \ |
Alex Elder | 03548ec | 2014-04-21 16:11:41 -0500 | [diff] [blame] | 494 | .clk_data = { \ |
| 495 | .clk_num = _prefix ## _ ## _ccuname ## _CCU_CLOCK_COUNT, \ |
| 496 | } |
| 497 | |
Alex Elder | 1f27f15 | 2014-02-14 12:29:18 -0600 | [diff] [blame] | 498 | /* Exported globals */ |
| 499 | |
| 500 | extern struct clk_ops kona_peri_clk_ops; |
| 501 | |
Alex Elder | 1f27f15 | 2014-02-14 12:29:18 -0600 | [diff] [blame] | 502 | /* Externally visible functions */ |
| 503 | |
Alex Elder | 1f27f15 | 2014-02-14 12:29:18 -0600 | [diff] [blame] | 504 | extern u64 scaled_div_max(struct bcm_clk_div *div); |
| 505 | extern u64 scaled_div_build(struct bcm_clk_div *div, u32 div_value, |
| 506 | u32 billionths); |
| 507 | |
Alex Elder | 03548ec | 2014-04-21 16:11:41 -0500 | [diff] [blame] | 508 | extern struct clk *kona_clk_setup(struct kona_clk *bcm_clk); |
Alex Elder | b12151c | 2014-04-21 16:11:40 -0500 | [diff] [blame] | 509 | extern void __init kona_dt_ccu_setup(struct ccu_data *ccu, |
Alex Elder | 03548ec | 2014-04-21 16:11:41 -0500 | [diff] [blame] | 510 | struct device_node *node); |
Alex Elder | 1f27f15 | 2014-02-14 12:29:18 -0600 | [diff] [blame] | 511 | extern bool __init kona_ccu_init(struct ccu_data *ccu); |
| 512 | |
| 513 | #endif /* _CLK_KONA_H */ |