blob: 0ed36d1f536d54c8d91a31d06952e31b114b6af7 [file] [log] [blame]
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01001config ARM64
2 def_bool y
Arun Chandran92980402014-10-10 12:31:24 +01003 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
Catalin Marinas8c2c3df2012-04-20 14:45:54 +01004 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
Riku Voipio957e3fa2014-12-12 16:57:44 -08005 select ARCH_HAS_GCOV_PROFILE_ALL
Laura Abbott308c09f2014-08-08 14:23:25 -07006 select ARCH_HAS_SG_CHAIN
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +01007 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
Sudeep Hollac63c8702014-05-09 10:33:01 +01008 select ARCH_USE_CMPXCHG_LOCKREF
Peter Zijlstra4badad32014-06-06 19:53:16 +02009 select ARCH_SUPPORTS_ATOMIC_RMW
Arnd Bergmann91701002013-02-21 11:42:57 +010010 select ARCH_WANT_OPTIONAL_GPIOLIB
Will Deacon6212a512012-11-07 14:16:28 +000011 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
Catalin Marinasb6f35982013-01-29 18:25:41 +000012 select ARCH_WANT_FRAME_POINTERS
Catalin Marinas25c92a32012-12-18 15:26:13 +000013 select ARM_AMBA
Mark Rutland1aee5d72012-11-20 10:06:00 +000014 select ARM_ARCH_TIMER
Catalin Marinasc4188ed2013-01-14 12:39:31 +000015 select ARM_GIC
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010016 select AUDIT_ARCH_COMPAT_GENERIC
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000017 select ARM_GIC_V2M if PCI_MSI
Marc Zyngier021f6532014-06-30 16:01:31 +010018 select ARM_GIC_V3
Marc Zyngier19812722014-11-24 14:35:19 +000019 select ARM_GIC_V3_ITS if PCI_MSI
Will Deaconadace892013-05-08 17:29:24 +010020 select BUILDTIME_EXTABLE_SORT
Catalin Marinasdb2789b2012-12-18 15:27:25 +000021 select CLONE_BACKWARDS
Deepak Saxena7ca2ef32012-09-22 10:33:36 -070022 select COMMON_CLK
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +000023 select CPU_PM if (SUSPEND || CPU_IDLE)
Will Deacon7bc13fd2013-11-06 19:32:13 +000024 select DCACHE_WORD_ACCESS
Laura Abbottd4932f92014-10-09 15:26:44 -070025 select GENERIC_ALLOCATOR
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010026 select GENERIC_CLOCKEVENTS
Lorenzo Pieralisi1f850082013-09-04 10:55:17 +010027 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
Ard Biesheuvel3be1a5c2014-03-04 01:10:04 +000028 select GENERIC_CPU_AUTOPROBE
Mark Salterbf4b5582014-04-07 15:39:52 -070029 select GENERIC_EARLY_IOREMAP
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010030 select GENERIC_IRQ_PROBE
31 select GENERIC_IRQ_SHOW
Arnd Bergmanncb61f672014-11-19 14:09:07 +010032 select GENERIC_PCI_IOMAP
Stephen Boyd65cd4f62013-07-18 16:21:18 -070033 select GENERIC_SCHED_CLOCK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010034 select GENERIC_SMP_IDLE_THREAD
Will Deacon12a0ef72013-11-06 17:20:22 +000035 select GENERIC_STRNCPY_FROM_USER
36 select GENERIC_STRNLEN_USER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010037 select GENERIC_TIME_VSYSCALL
Marc Zyngiera1ddc742014-08-26 11:03:17 +010038 select HANDLE_DOMAIN_IRQ
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010039 select HARDIRQS_SW_RESEND
Steve Capper5284e1b2014-10-24 13:22:20 +010040 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
AKASHI Takahiro875cbf32014-07-04 08:28:30 +010041 select HAVE_ARCH_AUDITSYSCALL
Yalin Wang8e7a4ce2014-11-03 03:02:23 +010042 select HAVE_ARCH_BITREVERSE
Jiang Liu9732caf2014-01-07 22:17:13 +080043 select HAVE_ARCH_JUMP_LABEL
Vijaya Kumar K95292472014-01-28 11:20:22 +000044 select HAVE_ARCH_KGDB
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +000045 select HAVE_ARCH_SECCOMP_FILTER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010046 select HAVE_ARCH_TRACEHOOK
Zi Shen Lime54bcde2014-08-26 21:15:30 -070047 select HAVE_BPF_JIT
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010048 select HAVE_C_RECORDMCOUNT
Laura Abbottc0c264a2014-06-25 23:55:03 +010049 select HAVE_CC_STACKPROTECTOR
Steve Capper5284e1b2014-10-24 13:22:20 +010050 select HAVE_CMPXCHG_DOUBLE
Catalin Marinas9b2a60c2012-10-08 16:28:13 -070051 select HAVE_DEBUG_BUGVERBOSE
Catalin Marinasb69ec422012-10-08 16:28:11 -070052 select HAVE_DEBUG_KMEMLEAK
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010053 select HAVE_DMA_API_DEBUG
54 select HAVE_DMA_ATTRS
Laura Abbott6ac21042013-12-12 19:28:33 +000055 select HAVE_DMA_CONTIGUOUS
AKASHI Takahirobd7d38d2014-04-30 10:54:34 +010056 select HAVE_DYNAMIC_FTRACE
Will Deacon50afc332013-12-16 17:50:08 +000057 select HAVE_EFFICIENT_UNALIGNED_ACCESS
AKASHI Takahiroaf64d2a2014-04-30 10:54:32 +010058 select HAVE_FTRACE_MCOUNT_RECORD
AKASHI Takahiro819e50e2014-04-30 18:54:33 +090059 select HAVE_FUNCTION_TRACER
60 select HAVE_FUNCTION_GRAPH_TRACER
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010061 select HAVE_GENERIC_DMA_COHERENT
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010062 select HAVE_HW_BREAKPOINT if PERF_EVENTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010063 select HAVE_MEMBLOCK
Mark Rutland55834a72014-02-07 17:12:45 +000064 select HAVE_PATA_PLATFORM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010065 select HAVE_PERF_EVENTS
Jean Pihet2ee0d7f2014-02-03 19:18:27 +010066 select HAVE_PERF_REGS
67 select HAVE_PERF_USER_STACK_DUMP
Steve Capper5e5f6dc2014-10-09 15:29:23 -070068 select HAVE_RCU_TABLE_FREE
AKASHI Takahiro055b1212014-04-30 10:54:36 +010069 select HAVE_SYSCALL_TRACEPOINTS
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010070 select IRQ_DOMAIN
Catalin Marinasfea2aca2012-10-16 11:26:57 +010071 select MODULES_USE_ELF_RELA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010072 select NO_BOOTMEM
73 select OF
74 select OF_EARLY_FLATTREE
Marek Szyprowski9bf14b72014-02-28 14:42:55 +010075 select OF_RESERVED_MEM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010076 select PERF_USE_VMALLOC
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +000077 select POWER_RESET
78 select POWER_SUPPLY
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010079 select RTC_LIB
80 select SPARSE_IRQ
Catalin Marinas7ac57a82012-10-08 16:28:16 -070081 select SYSCTL_EXCEPTION_TRACE
Larry Bassel6c81fe72014-05-30 12:34:15 -070082 select HAVE_CONTEXT_TRACKING
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010083 help
84 ARM 64-bit (AArch64) Linux support.
85
86config 64BIT
87 def_bool y
88
89config ARCH_PHYS_ADDR_T_64BIT
90 def_bool y
91
92config MMU
93 def_bool y
94
Uwe Kleine-Königce816fa2014-04-07 15:39:19 -070095config NO_IOPORT_MAP
Liviu Dudaud1e6dc92014-09-29 15:29:31 +010096 def_bool y if !PCI
Catalin Marinas8c2c3df2012-04-20 14:45:54 +010097
98config STACKTRACE_SUPPORT
99 def_bool y
100
101config LOCKDEP_SUPPORT
102 def_bool y
103
104config TRACE_IRQFLAGS_SUPPORT
105 def_bool y
106
Will Deaconc209f792014-03-14 17:47:05 +0000107config RWSEM_XCHGADD_ALGORITHM
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100108 def_bool y
109
110config GENERIC_HWEIGHT
111 def_bool y
112
113config GENERIC_CSUM
114 def_bool y
115
116config GENERIC_CALIBRATE_DELAY
117 def_bool y
118
Catalin Marinas19e76402014-02-27 12:09:22 +0000119config ZONE_DMA
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100120 def_bool y
121
Steve Capper29e56942014-10-09 15:29:25 -0700122config HAVE_GENERIC_RCU_GUP
123 def_bool y
124
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100125config ARCH_DMA_ADDR_T_64BIT
126 def_bool y
127
128config NEED_DMA_MAP_STATE
129 def_bool y
130
131config NEED_SG_DMA_LENGTH
132 def_bool y
133
134config SWIOTLB
135 def_bool y
136
137config IOMMU_HELPER
138 def_bool SWIOTLB
139
Ard Biesheuvel4cfb3612013-07-09 14:18:12 +0100140config KERNEL_MODE_NEON
141 def_bool y
142
Rob Herring92cc15f2014-04-18 17:19:59 -0500143config FIX_EARLYCON_MEM
144 def_bool y
145
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100146source "init/Kconfig"
147
148source "kernel/Kconfig.freezer"
149
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100150menu "Platform selection"
151
Suravee Suthikulpanit41904362014-11-26 11:51:09 +0700152config ARCH_SEATTLE
153 bool "AMD Seattle SoC Family"
154 help
155 This enables support for AMD Seattle SOC Family
156
Radha Mohan Chintakuntla28f74202014-04-08 18:47:51 +0530157config ARCH_THUNDER
158 bool "Cavium Inc. Thunder SoC Family"
159 help
160 This enables support for Cavium's Thunder Family of SoCs.
161
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100162config ARCH_VEXPRESS
163 bool "ARMv8 software model (Versatile Express)"
164 select ARCH_REQUIRE_GPIOLIB
165 select COMMON_CLK_VERSATILE
Catalin Marinasaa1e8ec2013-02-28 18:14:37 +0000166 select POWER_RESET_VEXPRESS
Catalin Marinas1ae90e72012-09-05 17:47:44 +0100167 select VEXPRESS_CONFIG
168 help
169 This enables support for the ARMv8 software model (Versatile
170 Express).
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100171
Vinayak Kale15942852013-04-24 10:06:57 +0100172config ARCH_XGENE
173 bool "AppliedMicro X-Gene SOC Family"
174 help
175 This enables support for AppliedMicro X-Gene SOC Family
176
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100177endmenu
178
179menu "Bus support"
180
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100181config PCI
182 bool "PCI support"
183 help
184 This feature enables support for PCI bus system. If you say Y
185 here, the kernel will include drivers and infrastructure code
186 to support PCI bus devices.
187
188config PCI_DOMAINS
189 def_bool PCI
190
191config PCI_DOMAINS_GENERIC
192 def_bool PCI
193
194config PCI_SYSCALL
195 def_bool PCI
196
197source "drivers/pci/Kconfig"
198source "drivers/pci/pcie/Kconfig"
199source "drivers/pci/hotplug/Kconfig"
200
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100201endmenu
202
203menu "Kernel Features"
204
Andre Przywarac0a01b82014-11-14 15:54:12 +0000205menu "ARM errata workarounds via the alternatives framework"
206
207config ARM64_ERRATUM_826319
208 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
209 default y
210 help
211 This option adds an alternative code sequence to work around ARM
212 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
213 AXI master interface and an L2 cache.
214
215 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
216 and is unable to accept a certain write via this interface, it will
217 not progress on read data presented on the read data channel and the
218 system can deadlock.
219
220 The workaround promotes data cache clean instructions to
221 data cache clean-and-invalidate.
222 Please note that this does not necessarily enable the workaround,
223 as it depends on the alternative framework, which will only patch
224 the kernel if an affected CPU is detected.
225
226 If unsure, say Y.
227
228config ARM64_ERRATUM_827319
229 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
230 default y
231 help
232 This option adds an alternative code sequence to work around ARM
233 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
234 master interface and an L2 cache.
235
236 Under certain conditions this erratum can cause a clean line eviction
237 to occur at the same time as another transaction to the same address
238 on the AMBA 5 CHI interface, which can cause data corruption if the
239 interconnect reorders the two transactions.
240
241 The workaround promotes data cache clean instructions to
242 data cache clean-and-invalidate.
243 Please note that this does not necessarily enable the workaround,
244 as it depends on the alternative framework, which will only patch
245 the kernel if an affected CPU is detected.
246
247 If unsure, say Y.
248
249config ARM64_ERRATUM_824069
250 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
251 default y
252 help
253 This option adds an alternative code sequence to work around ARM
254 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
255 to a coherent interconnect.
256
257 If a Cortex-A53 processor is executing a store or prefetch for
258 write instruction at the same time as a processor in another
259 cluster is executing a cache maintenance operation to the same
260 address, then this erratum might cause a clean cache line to be
261 incorrectly marked as dirty.
262
263 The workaround promotes data cache clean instructions to
264 data cache clean-and-invalidate.
265 Please note that this option does not necessarily enable the
266 workaround, as it depends on the alternative framework, which will
267 only patch the kernel if an affected CPU is detected.
268
269 If unsure, say Y.
270
271config ARM64_ERRATUM_819472
272 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
273 default y
274 help
275 This option adds an alternative code sequence to work around ARM
276 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
277 present when it is connected to a coherent interconnect.
278
279 If the processor is executing a load and store exclusive sequence at
280 the same time as a processor in another cluster is executing a cache
281 maintenance operation to the same address, then this erratum might
282 cause data corruption.
283
284 The workaround promotes data cache clean instructions to
285 data cache clean-and-invalidate.
286 Please note that this does not necessarily enable the workaround,
287 as it depends on the alternative framework, which will only patch
288 the kernel if an affected CPU is detected.
289
290 If unsure, say Y.
291
292config ARM64_ERRATUM_832075
293 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
294 default y
295 help
296 This option adds an alternative code sequence to work around ARM
297 erratum 832075 on Cortex-A57 parts up to r1p2.
298
299 Affected Cortex-A57 parts might deadlock when exclusive load/store
300 instructions to Write-Back memory are mixed with Device loads.
301
302 The workaround is to promote device loads to use Load-Acquire
303 semantics.
304 Please note that this does not necessarily enable the workaround,
305 as it depends on the alternative framework, which will only patch
306 the kernel if an affected CPU is detected.
307
308 If unsure, say Y.
309
310endmenu
311
312
Jungseok Leee41ceed2014-05-12 10:40:38 +0100313choice
314 prompt "Page size"
315 default ARM64_4K_PAGES
316 help
317 Page size (translation granule) configuration.
318
319config ARM64_4K_PAGES
320 bool "4KB"
321 help
322 This feature enables 4KB pages support.
323
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100324config ARM64_64K_PAGES
Jungseok Leee41ceed2014-05-12 10:40:38 +0100325 bool "64KB"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100326 help
327 This feature enables 64KB pages support (4KB by default)
328 allowing only two levels of page tables and faster TLB
329 look-up. AArch32 emulation is not available when this feature
330 is enabled.
331
Jungseok Leee41ceed2014-05-12 10:40:38 +0100332endchoice
333
334choice
335 prompt "Virtual address space size"
336 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
337 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
338 help
339 Allows choosing one of multiple possible virtual address
340 space sizes. The level of translation table is determined by
341 a combination of page size and virtual address space size.
342
343config ARM64_VA_BITS_39
344 bool "39-bit"
345 depends on ARM64_4K_PAGES
346
347config ARM64_VA_BITS_42
348 bool "42-bit"
349 depends on ARM64_64K_PAGES
350
Jungseok Leec79b9542014-05-12 18:40:51 +0900351config ARM64_VA_BITS_48
352 bool "48-bit"
Christoffer Dall04f905a2014-10-10 11:14:30 +0100353 depends on !ARM_SMMU
Jungseok Leec79b9542014-05-12 18:40:51 +0900354
Jungseok Leee41ceed2014-05-12 10:40:38 +0100355endchoice
356
357config ARM64_VA_BITS
358 int
359 default 39 if ARM64_VA_BITS_39
360 default 42 if ARM64_VA_BITS_42
Jungseok Leec79b9542014-05-12 18:40:51 +0900361 default 48 if ARM64_VA_BITS_48
Jungseok Leee41ceed2014-05-12 10:40:38 +0100362
Catalin Marinasabe669d2014-07-15 15:37:21 +0100363config ARM64_PGTABLE_LEVELS
364 int
365 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
Catalin Marinas383c2792014-07-21 15:54:50 +0100366 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
Catalin Marinasabe669d2014-07-15 15:37:21 +0100367 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
368 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
Jungseok Leec79b9542014-05-12 18:40:51 +0900369
Will Deacona8720132013-10-11 14:52:19 +0100370config CPU_BIG_ENDIAN
371 bool "Build big-endian kernel"
372 help
373 Say Y if you plan on running a kernel in big-endian mode.
374
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100375config SMP
376 bool "Symmetric Multi-Processing"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100377 help
378 This enables support for systems with more than one CPU. If
379 you say N here, the kernel will run on single and
380 multiprocessor machines, but will use only one CPU of a
381 multiprocessor machine. If you say Y here, the kernel will run
382 on many, but not all, single processor machines. On a single
383 processor machine, the kernel will run faster if you say N
384 here.
385
386 If you don't know what to do here, say N.
387
Mark Brownf6e763b2014-03-04 07:51:17 +0000388config SCHED_MC
389 bool "Multi-core scheduler support"
390 depends on SMP
391 help
392 Multi-core scheduler support improves the CPU scheduler's decision
393 making when dealing with multi-core CPU chips at a cost of slightly
394 increased overhead in some places. If unsure say N here.
395
396config SCHED_SMT
397 bool "SMT scheduler support"
398 depends on SMP
399 help
400 Improves the CPU scheduler's decision making when dealing with
401 MultiThreading at a cost of slightly increased overhead in some
402 places. If unsure say N here.
403
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100404config NR_CPUS
Robert Richtere3672642014-09-08 12:44:48 +0100405 int "Maximum number of CPUs (2-64)"
406 range 2 64
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100407 depends on SMP
Vinayak Kale15942852013-04-24 10:06:57 +0100408 # These have to remain sorted largest to smallest
Robert Richtere3672642014-09-08 12:44:48 +0100409 default "64"
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100410
Mark Rutland9327e2c2013-10-24 20:30:18 +0100411config HOTPLUG_CPU
412 bool "Support for hot-pluggable CPUs"
413 depends on SMP
414 help
415 Say Y here to experiment with turning CPUs off and on. CPUs
416 can be controlled through /sys/devices/system/cpu.
417
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100418source kernel/Kconfig.preempt
419
420config HZ
421 int
422 default 100
423
424config ARCH_HAS_HOLES_MEMORYMODEL
425 def_bool y if SPARSEMEM
426
427config ARCH_SPARSEMEM_ENABLE
428 def_bool y
429 select SPARSEMEM_VMEMMAP_ENABLE
430
431config ARCH_SPARSEMEM_DEFAULT
432 def_bool ARCH_SPARSEMEM_ENABLE
433
434config ARCH_SELECT_MEMORY_MODEL
435 def_bool ARCH_SPARSEMEM_ENABLE
436
437config HAVE_ARCH_PFN_VALID
438 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
439
440config HW_PERF_EVENTS
441 bool "Enable hardware performance counter support for perf events"
442 depends on PERF_EVENTS
443 default y
444 help
445 Enable hardware performance counter support for perf events. If
446 disabled, perf events will use software events only.
447
Steve Capper084bd292013-04-10 13:48:00 +0100448config SYS_SUPPORTS_HUGETLBFS
449 def_bool y
450
451config ARCH_WANT_GENERAL_HUGETLB
452 def_bool y
453
454config ARCH_WANT_HUGE_PMD_SHARE
455 def_bool y if !ARM64_64K_PAGES
456
Steve Capperaf074842013-04-19 16:23:57 +0100457config HAVE_ARCH_TRANSPARENT_HUGEPAGE
458 def_bool y
459
Catalin Marinasa41dc0e2014-04-03 17:48:54 +0100460config ARCH_HAS_CACHE_LINE_SIZE
461 def_bool y
462
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100463source "mm/Kconfig"
464
AKASHI Takahiroa1ae65b2014-11-28 05:26:39 +0000465config SECCOMP
466 bool "Enable seccomp to safely compute untrusted bytecode"
467 ---help---
468 This kernel feature is useful for number crunching applications
469 that may need to compute untrusted bytecode during their
470 execution. By using pipes or other transports made available to
471 the process as file descriptors supporting the read/write
472 syscalls, it's possible to isolate those applications in
473 their own address space using seccomp. Once seccomp is
474 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
475 and the task is only allowed to execute a few safe syscalls
476 defined by each seccomp mode.
477
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000478config XEN_DOM0
479 def_bool y
480 depends on XEN
481
482config XEN
Julien Grallc2ba1f72014-09-17 14:07:06 -0700483 bool "Xen guest support on ARM64"
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000484 depends on ARM64 && OF
Stefano Stabellini83862cc2013-10-10 13:40:44 +0000485 select SWIOTLB_XEN
Stefano Stabelliniaa42aa12013-06-03 17:05:43 +0000486 help
487 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
488
Steve Capperd03bb142013-04-25 15:19:21 +0100489config FORCE_MAX_ZONEORDER
490 int
491 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
492 default "11"
493
Will Deacon1b907f42014-11-20 16:51:10 +0000494menuconfig ARMV8_DEPRECATED
495 bool "Emulate deprecated/obsolete ARMv8 instructions"
496 depends on COMPAT
497 help
498 Legacy software support may require certain instructions
499 that have been deprecated or obsoleted in the architecture.
500
501 Enable this config to enable selective emulation of these
502 features.
503
504 If unsure, say Y
505
506if ARMV8_DEPRECATED
507
508config SWP_EMULATION
509 bool "Emulate SWP/SWPB instructions"
510 help
511 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
512 they are always undefined. Say Y here to enable software
513 emulation of these instructions for userspace using LDXR/STXR.
514
515 In some older versions of glibc [<=2.8] SWP is used during futex
516 trylock() operations with the assumption that the code will not
517 be preempted. This invalid assumption may be more likely to fail
518 with SWP emulation enabled, leading to deadlock of the user
519 application.
520
521 NOTE: when accessing uncached shared regions, LDXR/STXR rely
522 on an external transaction monitoring block called a global
523 monitor to maintain update atomicity. If your system does not
524 implement a global monitor, this option can cause programs that
525 perform SWP operations to uncached memory to deadlock.
526
527 If unsure, say Y
528
529config CP15_BARRIER_EMULATION
530 bool "Emulate CP15 Barrier instructions"
531 help
532 The CP15 barrier instructions - CP15ISB, CP15DSB, and
533 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
534 strongly recommended to use the ISB, DSB, and DMB
535 instructions instead.
536
537 Say Y here to enable software emulation of these
538 instructions for AArch32 userspace code. When this option is
539 enabled, CP15 barrier usage is traced which can help
540 identify software that needs updating.
541
542 If unsure, say Y
543
544endif
545
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100546endmenu
547
548menu "Boot options"
549
550config CMDLINE
551 string "Default kernel command string"
552 default ""
553 help
554 Provide a set of default command-line options at build time by
555 entering them here. As a minimum, you should specify the the
556 root device (e.g. root=/dev/nfs).
557
558config CMDLINE_FORCE
559 bool "Always use the default kernel command string"
560 help
561 Always use the default kernel command string, even if the boot
562 loader passes other arguments to the kernel.
563 This is useful if you cannot or don't want to change the
564 command-line options your boot loader passes to the kernel.
565
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200566config EFI_STUB
567 bool
568
Mark Salterf84d0272014-04-15 21:59:30 -0400569config EFI
570 bool "UEFI runtime support"
571 depends on OF && !CPU_BIG_ENDIAN
572 select LIBFDT
573 select UCS2_STRING
574 select EFI_PARAMS_FROM_FDT
Ard Biesheuvele15dd492014-07-04 19:41:53 +0200575 select EFI_RUNTIME_WRAPPERS
Ard Biesheuvelf4f75ad52014-07-02 14:54:43 +0200576 select EFI_STUB
577 select EFI_ARMSTUB
Mark Salterf84d0272014-04-15 21:59:30 -0400578 default y
579 help
580 This option provides support for runtime services provided
581 by UEFI firmware (such as non-volatile variables, realtime
Mark Salter3c7f2552014-04-15 22:47:52 -0400582 clock, and platform reset). A UEFI stub is also provided to
583 allow the kernel to be booted as an EFI application. This
584 is only useful on systems that have UEFI firmware.
Mark Salterf84d0272014-04-15 21:59:30 -0400585
Yi Lid1ae8c02014-10-04 23:46:43 +0800586config DMI
587 bool "Enable support for SMBIOS (DMI) tables"
588 depends on EFI
589 default y
590 help
591 This enables SMBIOS/DMI feature for systems.
592
593 This option is only useful on systems that have UEFI firmware.
594 However, even with this option, the resultant kernel should
595 continue to boot on existing non-UEFI platforms.
596
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100597endmenu
598
599menu "Userspace binary formats"
600
601source "fs/Kconfig.binfmt"
602
603config COMPAT
604 bool "Kernel support for 32-bit EL0"
605 depends on !ARM64_64K_PAGES
606 select COMPAT_BINFMT_ELF
Catalin Marinasaf1839e2012-10-08 16:28:08 -0700607 select HAVE_UID16
Al Viro84b9e9b2012-12-25 16:29:11 -0500608 select OLD_SIGSUSPEND3
Al Viro51682032012-12-25 19:31:29 -0500609 select COMPAT_OLD_SIGACTION
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100610 help
611 This option enables support for a 32-bit EL0 running under a 64-bit
612 kernel at EL1. AArch32-specific components such as system calls,
613 the user helper functions, VFP support and the ptrace interface are
614 handled appropriately by the kernel.
615
616 If you want to execute 32-bit userspace applications, say Y.
617
618config SYSVIPC_COMPAT
619 def_bool y
620 depends on COMPAT && SYSVIPC
621
622endmenu
623
Lorenzo Pieralisi166936b2013-11-07 18:37:14 +0000624menu "Power management options"
625
626source "kernel/power/Kconfig"
627
628config ARCH_SUSPEND_POSSIBLE
629 def_bool y
630
631config ARM64_CPU_SUSPEND
632 def_bool PM_SLEEP
633
634endmenu
635
Lorenzo Pieralisi13072202013-07-17 14:54:21 +0100636menu "CPU Power Management"
637
638source "drivers/cpuidle/Kconfig"
639
Rob Herring52e7e812014-02-24 11:27:57 +0900640source "drivers/cpufreq/Kconfig"
641
642endmenu
643
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100644source "net/Kconfig"
645
646source "drivers/Kconfig"
647
Mark Salterf84d0272014-04-15 21:59:30 -0400648source "drivers/firmware/Kconfig"
649
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100650source "fs/Kconfig"
651
Marc Zyngierc3eb5b12013-07-04 13:34:32 +0100652source "arch/arm64/kvm/Kconfig"
653
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100654source "arch/arm64/Kconfig.debug"
655
656source "security/Kconfig"
657
658source "crypto/Kconfig"
Ard Biesheuvel2c988332014-03-06 16:23:33 +0800659if CRYPTO
660source "arch/arm64/crypto/Kconfig"
661endif
Catalin Marinas8c2c3df2012-04-20 14:45:54 +0100662
663source "lib/Kconfig"