Blame - drivers/irqchip/Kconfig - kernel/msm-4.19

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Thomas Petazzoni	f6e916b	2012-11-20 23:00:52 +0100	[diff] [blame]	1	config IRQCHIP
				2	def_bool y
				3	depends on OF_IRQ
				4
Rob Herring	81243e4	2012-11-20 21:21:40 -0600	[diff] [blame]	5	config ARM_GIC
				6	bool
				7	select IRQ_DOMAIN
Yingjoe Chen	9a1091e	2014-11-25 16:04:19 +0800	[diff] [blame^]	8	select IRQ_DOMAIN_HIERARCHY
Rob Herring	81243e4	2012-11-20 21:21:40 -0600	[diff] [blame]	9	select MULTI_IRQ_HANDLER
				10
				11	config GIC_NON_BANKED
				12	bool
				13
Marc Zyngier	021f653	2014-06-30 16:01:31 +0100	[diff] [blame]	14	config ARM_GIC_V3
				15	bool
				16	select IRQ_DOMAIN
				17	select MULTI_IRQ_HANDLER
Marc Zyngier	443acc4	2014-11-24 14:35:09 +0000	[diff] [blame]	18	select IRQ_DOMAIN_HIERARCHY
Marc Zyngier	021f653	2014-06-30 16:01:31 +0100	[diff] [blame]	19
Marc Zyngier	1981272	2014-11-24 14:35:19 +0000	[diff] [blame]	20	config ARM_GIC_V3_ITS
				21	bool
				22	select PCI_MSI_IRQ_DOMAIN
				23
Uwe Kleine-König	292ec08	2013-06-26 09:18:48 +0200	[diff] [blame]	24	config ARM_NVIC
				25	bool
				26	select IRQ_DOMAIN
				27	select GENERIC_IRQ_CHIP
				28
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	29	config ARM_VIC
				30	bool
				31	select IRQ_DOMAIN
				32	select MULTI_IRQ_HANDLER
				33
				34	config ARM_VIC_NR
				35	int
				36	default 4 if ARCH_S5PV210
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	37	default 2
				38	depends on ARM_VIC
				39	help
				40	The maximum number of VICs available in the system, for
				41	power management.
				42
Boris BREZILLON	b1479eb	2014-07-10 19:14:18 +0200	[diff] [blame]	43	config ATMEL_AIC_IRQ
				44	bool
				45	select GENERIC_IRQ_CHIP
				46	select IRQ_DOMAIN
				47	select MULTI_IRQ_HANDLER
				48	select SPARSE_IRQ
				49
				50	config ATMEL_AIC5_IRQ
				51	bool
				52	select GENERIC_IRQ_CHIP
				53	select IRQ_DOMAIN
				54	select MULTI_IRQ_HANDLER
				55	select SPARSE_IRQ
				56
Florian Fainelli	7f646e9	2014-05-23 17:40:53 -0700	[diff] [blame]	57	config BRCMSTB_L2_IRQ
				58	bool
				59	depends on ARM
				60	select GENERIC_IRQ_CHIP
				61	select IRQ_DOMAIN
				62
Sebastian Hesselbarth	350d71b9	2013-09-09 14:01:20 +0200	[diff] [blame]	63	config DW_APB_ICTL
				64	bool
				65	select IRQ_DOMAIN
				66
James Hogan	b6ef916	2013-04-22 15:43:50 +0100	[diff] [blame]	67	config IMGPDC_IRQ
				68	bool
				69	select GENERIC_IRQ_CHIP
				70	select IRQ_DOMAIN
				71
Alexander Shiyan	afc98d9	2014-02-02 12:07:46 +0400	[diff] [blame]	72	config CLPS711X_IRQCHIP
				73	bool
				74	depends on ARCH_CLPS711X
				75	select IRQ_DOMAIN
				76	select MULTI_IRQ_HANDLER
				77	select SPARSE_IRQ
				78	default y
				79
Stefan Kristiansson	4db8e6d	2014-05-26 23:31:42 +0300	[diff] [blame]	80	config OR1K_PIC
				81	bool
				82	select IRQ_DOMAIN
				83
Felipe Balbi	8598066	2014-09-15 16:15:02 -0500	[diff] [blame]	84	config OMAP_IRQCHIP
				85	bool
				86	select GENERIC_IRQ_CHIP
				87	select IRQ_DOMAIN
				88
Sebastian Hesselbarth	9dbd90f	2013-06-06 18:27:09 +0200	[diff] [blame]	89	config ORION_IRQCHIP
				90	bool
				91	select IRQ_DOMAIN
				92	select MULTI_IRQ_HANDLER
				93
Magnus Damm	4435804	2013-02-18 23:28:34 +0900	[diff] [blame]	94	config RENESAS_INTC_IRQPIN
				95	bool
				96	select IRQ_DOMAIN
				97
Magnus Damm	fbc83b7	2013-02-27 17:15:01 +0900	[diff] [blame]	98	config RENESAS_IRQC
				99	bool
				100	select IRQ_DOMAIN
				101
Christian Ruppert	b06eb01	2013-06-25 18:29:57 +0200	[diff] [blame]	102	config TB10X_IRQC
				103	bool
				104	select IRQ_DOMAIN
				105	select GENERIC_IRQ_CHIP
				106
Linus Walleij	2389d50	2012-10-31 22:04:31 +0100	[diff] [blame]	107	config VERSATILE_FPGA_IRQ
				108	bool
				109	select IRQ_DOMAIN
				110
				111	config VERSATILE_FPGA_IRQ_NR
				112	int
				113	default 4
				114	depends on VERSATILE_FPGA_IRQ
Max Filippov	26a8e96	2013-12-01 12:04:57 +0400	[diff] [blame]	115
				116	config XTENSA_MX
				117	bool
				118	select IRQ_DOMAIN
Sricharan R	96ca848	2013-12-03 15:57:23 +0530	[diff] [blame]	119
				120	config IRQ_CROSSBAR
				121	bool
				122	help
Masanari Iida	f54619f	2014-09-18 12:09:42 +0900	[diff] [blame]	123	Support for a CROSSBAR ip that precedes the main interrupt controller.
Sricharan R	96ca848	2013-12-03 15:57:23 +0530	[diff] [blame]	124	The primary irqchip invokes the crossbar's callback which inturn allocates
				125	a free irq and configures the IP. Thus the peripheral interrupts are
				126	routed to one of the free irqchip interrupt lines.
Grygorii Strashko	89323f8	2014-07-23 17:40:30 +0300	[diff] [blame]	127
				128	config KEYSTONE_IRQ
				129	tristate "Keystone 2 IRQ controller IP"
				130	depends on ARCH_KEYSTONE
				131	help
				132	Support for Texas Instruments Keystone 2 IRQ controller IP which
				133	is part of the Keystone 2 IPC mechanism