blob: 7ef0f868b3e07bf48941075e269ef3976d3efcf1 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * probe.c - PCI detection and setup code
3 */
4
5#include <linux/kernel.h>
6#include <linux/delay.h>
7#include <linux/init.h>
8#include <linux/pci.h>
9#include <linux/slab.h>
10#include <linux/module.h>
11#include <linux/cpumask.h>
Shaohua Li7d715a62008-02-25 09:46:41 +080012#include <linux/pci-aspm.h>
Bjorn Helgaas284f5f92012-04-30 15:21:02 -060013#include <asm-generic/pci-bridge.h>
Greg KHbc56b9e2005-04-08 14:53:31 +090014#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070015
16#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
17#define CARDBUS_RESERVE_BUSNR 3
Linus Torvalds1da177e2005-04-16 15:20:36 -070018
Yinghai Lu67cdc822012-05-17 18:51:12 -070019struct resource busn_resource = {
20 .name = "PCI busn",
21 .start = 0,
22 .end = 255,
23 .flags = IORESOURCE_BUS,
24};
25
Linus Torvalds1da177e2005-04-16 15:20:36 -070026/* Ugh. Need to stop exporting this to modules. */
27LIST_HEAD(pci_root_buses);
28EXPORT_SYMBOL(pci_root_buses);
29
Yinghai Lu5cc62c22012-05-17 18:51:11 -070030static LIST_HEAD(pci_domain_busn_res_list);
31
32struct pci_domain_busn_res {
33 struct list_head list;
34 struct resource res;
35 int domain_nr;
36};
37
38static struct resource *get_pci_domain_busn_res(int domain_nr)
39{
40 struct pci_domain_busn_res *r;
41
42 list_for_each_entry(r, &pci_domain_busn_res_list, list)
43 if (r->domain_nr == domain_nr)
44 return &r->res;
45
46 r = kzalloc(sizeof(*r), GFP_KERNEL);
47 if (!r)
48 return NULL;
49
50 r->domain_nr = domain_nr;
51 r->res.start = 0;
52 r->res.end = 0xff;
53 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
54
55 list_add_tail(&r->list, &pci_domain_busn_res_list);
56
57 return &r->res;
58}
59
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080060static int find_anything(struct device *dev, void *data)
61{
62 return 1;
63}
Linus Torvalds1da177e2005-04-16 15:20:36 -070064
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070065/*
66 * Some device drivers need know if pci is initiated.
67 * Basically, we think pci is not initiated when there
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080068 * is no device to be found on the pci_bus_type.
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070069 */
70int no_pci_devices(void)
71{
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080072 struct device *dev;
73 int no_devices;
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070074
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080075 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
76 no_devices = (dev == NULL);
77 put_device(dev);
78 return no_devices;
79}
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070080EXPORT_SYMBOL(no_pci_devices);
81
Linus Torvalds1da177e2005-04-16 15:20:36 -070082/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070083 * PCI Bus Class
84 */
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040085static void release_pcibus_dev(struct device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -070086{
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040087 struct pci_bus *pci_bus = to_pci_bus(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -070088
89 if (pci_bus->bridge)
90 put_device(pci_bus->bridge);
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -070091 pci_bus_remove_resources(pci_bus);
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +100092 pci_release_bus_of_node(pci_bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -070093 kfree(pci_bus);
94}
95
96static struct class pcibus_class = {
97 .name = "pci_bus",
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040098 .dev_release = &release_pcibus_dev,
Greg Kroah-Hartman56039e62013-07-24 15:05:17 -070099 .dev_groups = pcibus_groups,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100};
101
102static int __init pcibus_class_init(void)
103{
104 return class_register(&pcibus_class);
105}
106postcore_initcall(pcibus_class_init);
107
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400108static u64 pci_size(u64 base, u64 maxbase, u64 mask)
Yinghai Lu07eddf32006-11-29 13:53:10 -0800109{
110 u64 size = mask & maxbase; /* Find the significant bits */
111 if (!size)
112 return 0;
113
114 /* Get the lowest of them to find the decode size, and
115 from that the extent. */
116 size = (size & ~(size-1)) - 1;
117
118 /* base == maxbase can be valid only if the BAR has
119 already been programmed with all 1s. */
120 if (base == maxbase && ((base | size) & mask) != mask)
121 return 0;
122
123 return size;
124}
125
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600126static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
Yinghai Lu07eddf32006-11-29 13:53:10 -0800127{
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600128 u32 mem_type;
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600129 unsigned long flags;
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600130
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400131 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600132 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
133 flags |= IORESOURCE_IO;
134 return flags;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400135 }
136
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600137 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
138 flags |= IORESOURCE_MEM;
139 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
140 flags |= IORESOURCE_PREFETCH;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400141
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600142 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
143 switch (mem_type) {
144 case PCI_BASE_ADDRESS_MEM_TYPE_32:
145 break;
146 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600147 /* 1M mem BAR treated as 32-bit BAR */
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600148 break;
149 case PCI_BASE_ADDRESS_MEM_TYPE_64:
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600150 flags |= IORESOURCE_MEM_64;
151 break;
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600152 default:
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600153 /* mem unknown type treated as 32-bit BAR */
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600154 break;
155 }
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600156 return flags;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400157}
158
Zoltan Kiss808e34e2013-08-22 23:19:18 +0100159#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
160
Yu Zhao0b400c72008-11-22 02:40:40 +0800161/**
162 * pci_read_base - read a PCI BAR
163 * @dev: the PCI device
164 * @type: type of the BAR
165 * @res: resource buffer to be filled in
166 * @pos: BAR position in the config space
167 *
168 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400169 */
Yu Zhao0b400c72008-11-22 02:40:40 +0800170int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400171 struct resource *res, unsigned int pos)
172{
173 u32 l, sz, mask;
Jacob Pan253d2e52010-07-16 10:19:22 -0700174 u16 orig_cmd;
Kevin Haocf4d1cf2013-05-25 19:36:27 +0800175 struct pci_bus_region region, inverted_region;
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600176 bool bar_too_big = false, bar_disabled = false;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400177
Michael S. Tsirkin1ed67432009-10-29 17:24:59 +0200178 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400179
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600180 /* No printks while decoding is disabled! */
Jacob Pan253d2e52010-07-16 10:19:22 -0700181 if (!dev->mmio_always_on) {
182 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
Zoltan Kiss808e34e2013-08-22 23:19:18 +0100183 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
184 pci_write_config_word(dev, PCI_COMMAND,
185 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
186 }
Jacob Pan253d2e52010-07-16 10:19:22 -0700187 }
188
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400189 res->name = pci_name(dev);
190
191 pci_read_config_dword(dev, pos, &l);
Michael S. Tsirkin1ed67432009-10-29 17:24:59 +0200192 pci_write_config_dword(dev, pos, l | mask);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400193 pci_read_config_dword(dev, pos, &sz);
194 pci_write_config_dword(dev, pos, l);
195
196 /*
197 * All bits set in sz means the device isn't working properly.
Bjorn Helgaas45aa23b2010-04-22 09:02:43 -0600198 * If the BAR isn't implemented, all bits must be 0. If it's a
199 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
200 * 1 must be clear.
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400201 */
Bjorn Helgaas45aa23b2010-04-22 09:02:43 -0600202 if (!sz || sz == 0xffffffff)
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400203 goto fail;
204
205 /*
206 * I don't know how l can have all bits set. Copied from old code.
207 * Maybe it fixes a bug on some ancient platform.
208 */
209 if (l == 0xffffffff)
210 l = 0;
211
212 if (type == pci_bar_unknown) {
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600213 res->flags = decode_bar(dev, l);
214 res->flags |= IORESOURCE_SIZEALIGN;
215 if (res->flags & IORESOURCE_IO) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400216 l &= PCI_BASE_ADDRESS_IO_MASK;
David S. Miller5aceca92011-05-23 17:12:22 -0700217 mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400218 } else {
219 l &= PCI_BASE_ADDRESS_MEM_MASK;
220 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
221 }
222 } else {
223 res->flags |= (l & IORESOURCE_ROM_ENABLE);
224 l &= PCI_ROM_ADDRESS_MASK;
225 mask = (u32)PCI_ROM_ADDRESS_MASK;
226 }
227
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600228 if (res->flags & IORESOURCE_MEM_64) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400229 u64 l64 = l;
230 u64 sz64 = sz;
231 u64 mask64 = mask | (u64)~0 << 32;
232
233 pci_read_config_dword(dev, pos + 4, &l);
234 pci_write_config_dword(dev, pos + 4, ~0);
235 pci_read_config_dword(dev, pos + 4, &sz);
236 pci_write_config_dword(dev, pos + 4, l);
237
238 l64 |= ((u64)l << 32);
239 sz64 |= ((u64)sz << 32);
240
241 sz64 = pci_size(l64, sz64, mask64);
242
243 if (!sz64)
244 goto fail;
245
Matthew Wilcoxcc5499c2008-07-28 13:39:00 -0400246 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600247 bar_too_big = true;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400248 goto fail;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600249 }
250
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600251 if ((sizeof(resource_size_t) < 8) && l) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400252 /* Address above 32-bit boundary; disable the BAR */
253 pci_write_config_dword(dev, pos, 0);
254 pci_write_config_dword(dev, pos + 4, 0);
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700255 region.start = 0;
256 region.end = sz64;
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600257 bar_disabled = true;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400258 } else {
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700259 region.start = l64;
260 region.end = l64 + sz64;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400261 }
262 } else {
Bjorn Helgaas45aa23b2010-04-22 09:02:43 -0600263 sz = pci_size(l, sz, mask);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400264
Bjorn Helgaas45aa23b2010-04-22 09:02:43 -0600265 if (!sz)
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400266 goto fail;
267
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700268 region.start = l;
269 region.end = l + sz;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400270 }
271
Kevin Hao96ddef22013-05-25 19:36:26 +0800272 pcibios_bus_to_resource(dev, res, &region);
Kevin Haocf4d1cf2013-05-25 19:36:27 +0800273 pcibios_resource_to_bus(dev, &inverted_region, res);
274
275 /*
276 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
277 * the corresponding resource address (the physical address used by
278 * the CPU. Converting that resource address back to a bus address
279 * should yield the original BAR value:
280 *
281 * resource_to_bus(bus_to_resource(A)) == A
282 *
283 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
284 * be claimed by the device.
285 */
286 if (inverted_region.start != region.start) {
287 dev_info(&dev->dev, "reg 0x%x: initial BAR value %pa invalid; forcing reassignment\n",
288 pos, &region.start);
289 res->flags |= IORESOURCE_UNSET;
290 res->end -= res->start;
291 res->start = 0;
292 }
Kevin Hao96ddef22013-05-25 19:36:26 +0800293
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600294 goto out;
295
296
297fail:
298 res->flags = 0;
299out:
Zoltan Kiss808e34e2013-08-22 23:19:18 +0100300 if (!dev->mmio_always_on &&
301 (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
Bjorn Helgaasbbffe432012-07-06 12:08:18 -0600302 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
303
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600304 if (bar_too_big)
Kevin Hao33963e302013-05-25 19:36:25 +0800305 dev_err(&dev->dev, "reg 0x%x: can't handle 64-bit BAR\n", pos);
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600306 if (res->flags && !bar_disabled)
Kevin Hao33963e302013-05-25 19:36:25 +0800307 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600308
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600309 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
Yinghai Lu07eddf32006-11-29 13:53:10 -0800310}
311
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
313{
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400314 unsigned int pos, reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700315
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400316 for (pos = 0; pos < howmany; pos++) {
317 struct resource *res = &dev->resource[pos];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700318 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400319 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320 }
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400321
Linus Torvalds1da177e2005-04-16 15:20:36 -0700322 if (rom) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400323 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700324 dev->rom_base_reg = rom;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400325 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
326 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
327 IORESOURCE_SIZEALIGN;
328 __pci_read_base(dev, pci_bar_mem32, res, rom);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329 }
330}
331
Bill Pemberton15856ad2012-11-21 15:35:00 -0500332static void pci_read_bridge_io(struct pci_bus *child)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333{
334 struct pci_dev *dev = child->self;
335 u8 io_base_lo, io_limit_lo;
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -0600336 unsigned long io_mask, io_granularity, base, limit;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700337 struct pci_bus_region region;
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -0600338 struct resource *res;
339
340 io_mask = PCI_IO_RANGE_MASK;
341 io_granularity = 0x1000;
342 if (dev->io_window_1k) {
343 /* Support 1K I/O space granularity */
344 io_mask = PCI_IO_1K_RANGE_MASK;
345 io_granularity = 0x400;
346 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700347
Linus Torvalds1da177e2005-04-16 15:20:36 -0700348 res = child->resource[0];
349 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
350 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -0600351 base = (io_base_lo & io_mask) << 8;
352 limit = (io_limit_lo & io_mask) << 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353
354 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
355 u16 io_base_hi, io_limit_hi;
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600356
Linus Torvalds1da177e2005-04-16 15:20:36 -0700357 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
358 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600359 base |= ((unsigned long) io_base_hi << 16);
360 limit |= ((unsigned long) io_limit_hi << 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700361 }
362
Bjorn Helgaas5dde3832012-07-09 13:38:41 -0600363 if (base <= limit) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700364 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700365 region.start = base;
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -0600366 region.end = limit + io_granularity - 1;
367 pcibios_bus_to_resource(dev, res, &region);
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600368 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700369 }
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700370}
371
Bill Pemberton15856ad2012-11-21 15:35:00 -0500372static void pci_read_bridge_mmio(struct pci_bus *child)
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700373{
374 struct pci_dev *dev = child->self;
375 u16 mem_base_lo, mem_limit_lo;
376 unsigned long base, limit;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700377 struct pci_bus_region region;
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700378 struct resource *res;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700379
380 res = child->resource[1];
381 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
382 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600383 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
384 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
Bjorn Helgaas5dde3832012-07-09 13:38:41 -0600385 if (base <= limit) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700386 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700387 region.start = base;
388 region.end = limit + 0xfffff;
Bjorn Helgaasfb127cb2012-02-23 20:19:04 -0700389 pcibios_bus_to_resource(dev, res, &region);
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600390 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700391 }
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700392}
393
Bill Pemberton15856ad2012-11-21 15:35:00 -0500394static void pci_read_bridge_mmio_pref(struct pci_bus *child)
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700395{
396 struct pci_dev *dev = child->self;
397 u16 mem_base_lo, mem_limit_lo;
398 unsigned long base, limit;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700399 struct pci_bus_region region;
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700400 struct resource *res;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700401
402 res = child->resource[2];
403 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
404 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600405 base = ((unsigned long) mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
406 limit = ((unsigned long) mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700407
408 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
409 u32 mem_base_hi, mem_limit_hi;
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600410
Linus Torvalds1da177e2005-04-16 15:20:36 -0700411 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
412 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
413
414 /*
415 * Some bridges set the base > limit by default, and some
416 * (broken) BIOSes do not initialize them. If we find
417 * this, just assume they are not being used.
418 */
419 if (mem_base_hi <= mem_limit_hi) {
420#if BITS_PER_LONG == 64
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600421 base |= ((unsigned long) mem_base_hi) << 32;
422 limit |= ((unsigned long) mem_limit_hi) << 32;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700423#else
424 if (mem_base_hi || mem_limit_hi) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600425 dev_err(&dev->dev, "can't handle 64-bit "
426 "address space for bridge\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700427 return;
428 }
429#endif
430 }
431 }
Bjorn Helgaas5dde3832012-07-09 13:38:41 -0600432 if (base <= limit) {
Yinghai Lu1f82de12009-04-23 20:48:32 -0700433 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
434 IORESOURCE_MEM | IORESOURCE_PREFETCH;
435 if (res->flags & PCI_PREF_RANGE_TYPE_64)
436 res->flags |= IORESOURCE_MEM_64;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700437 region.start = base;
438 region.end = limit + 0xfffff;
Bjorn Helgaasfb127cb2012-02-23 20:19:04 -0700439 pcibios_bus_to_resource(dev, res, &region);
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600440 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700441 }
442}
443
Bill Pemberton15856ad2012-11-21 15:35:00 -0500444void pci_read_bridge_bases(struct pci_bus *child)
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700445{
446 struct pci_dev *dev = child->self;
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700447 struct resource *res;
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700448 int i;
449
450 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
451 return;
452
Yinghai Lub918c622012-05-17 18:51:11 -0700453 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
454 &child->busn_res,
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700455 dev->transparent ? " (subtractive decode)" : "");
456
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700457 pci_bus_remove_resources(child);
458 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
459 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
460
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700461 pci_read_bridge_io(child);
462 pci_read_bridge_mmio(child);
463 pci_read_bridge_mmio_pref(child);
Bjorn Helgaas2adf7512010-02-23 10:24:26 -0700464
465 if (dev->transparent) {
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700466 pci_bus_for_each_resource(child->parent, res, i) {
467 if (res) {
468 pci_bus_add_resource(child, res,
469 PCI_SUBTRACTIVE_DECODE);
Bjorn Helgaas2adf7512010-02-23 10:24:26 -0700470 dev_printk(KERN_DEBUG, &dev->dev,
471 " bridge window %pR (subtractive decode)\n",
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700472 res);
473 }
Bjorn Helgaas2adf7512010-02-23 10:24:26 -0700474 }
475 }
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700476}
477
Bjorn Helgaas05013482013-06-05 14:22:11 -0600478static struct pci_bus *pci_alloc_bus(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700479{
480 struct pci_bus *b;
481
Eric Sesterhennf5afe802006-02-28 15:34:49 +0100482 b = kzalloc(sizeof(*b), GFP_KERNEL);
Bjorn Helgaas05013482013-06-05 14:22:11 -0600483 if (!b)
484 return NULL;
485
486 INIT_LIST_HEAD(&b->node);
487 INIT_LIST_HEAD(&b->children);
488 INIT_LIST_HEAD(&b->devices);
489 INIT_LIST_HEAD(&b->slots);
490 INIT_LIST_HEAD(&b->resources);
491 b->max_bus_speed = PCI_SPEED_UNKNOWN;
492 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700493 return b;
494}
495
Jiang Liu70efde22013-06-07 16:16:51 -0600496static void pci_release_host_bridge_dev(struct device *dev)
497{
498 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
499
500 if (bridge->release_fn)
501 bridge->release_fn(bridge);
502
503 pci_free_resource_list(&bridge->windows);
504
505 kfree(bridge);
506}
507
Yinghai Lu7b543662012-04-02 18:31:53 -0700508static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
509{
510 struct pci_host_bridge *bridge;
511
512 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
Bjorn Helgaas05013482013-06-05 14:22:11 -0600513 if (!bridge)
514 return NULL;
Yinghai Lu7b543662012-04-02 18:31:53 -0700515
Bjorn Helgaas05013482013-06-05 14:22:11 -0600516 INIT_LIST_HEAD(&bridge->windows);
517 bridge->bus = b;
Yinghai Lu7b543662012-04-02 18:31:53 -0700518 return bridge;
519}
520
Jacob Keller343e51a2013-07-31 06:53:16 +0000521const unsigned char pcix_bus_speed[] = {
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500522 PCI_SPEED_UNKNOWN, /* 0 */
523 PCI_SPEED_66MHz_PCIX, /* 1 */
524 PCI_SPEED_100MHz_PCIX, /* 2 */
525 PCI_SPEED_133MHz_PCIX, /* 3 */
526 PCI_SPEED_UNKNOWN, /* 4 */
527 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
528 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
529 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
530 PCI_SPEED_UNKNOWN, /* 8 */
531 PCI_SPEED_66MHz_PCIX_266, /* 9 */
532 PCI_SPEED_100MHz_PCIX_266, /* A */
533 PCI_SPEED_133MHz_PCIX_266, /* B */
534 PCI_SPEED_UNKNOWN, /* C */
535 PCI_SPEED_66MHz_PCIX_533, /* D */
536 PCI_SPEED_100MHz_PCIX_533, /* E */
537 PCI_SPEED_133MHz_PCIX_533 /* F */
538};
539
Jacob Keller343e51a2013-07-31 06:53:16 +0000540const unsigned char pcie_link_speed[] = {
Matthew Wilcox3749c512009-12-13 08:11:32 -0500541 PCI_SPEED_UNKNOWN, /* 0 */
542 PCIE_SPEED_2_5GT, /* 1 */
543 PCIE_SPEED_5_0GT, /* 2 */
Matthew Wilcox9dfd97f2009-12-13 08:11:35 -0500544 PCIE_SPEED_8_0GT, /* 3 */
Matthew Wilcox3749c512009-12-13 08:11:32 -0500545 PCI_SPEED_UNKNOWN, /* 4 */
546 PCI_SPEED_UNKNOWN, /* 5 */
547 PCI_SPEED_UNKNOWN, /* 6 */
548 PCI_SPEED_UNKNOWN, /* 7 */
549 PCI_SPEED_UNKNOWN, /* 8 */
550 PCI_SPEED_UNKNOWN, /* 9 */
551 PCI_SPEED_UNKNOWN, /* A */
552 PCI_SPEED_UNKNOWN, /* B */
553 PCI_SPEED_UNKNOWN, /* C */
554 PCI_SPEED_UNKNOWN, /* D */
555 PCI_SPEED_UNKNOWN, /* E */
556 PCI_SPEED_UNKNOWN /* F */
557};
558
559void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
560{
Bjorn Helgaas231afea2012-12-05 13:51:18 -0700561 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
Matthew Wilcox3749c512009-12-13 08:11:32 -0500562}
563EXPORT_SYMBOL_GPL(pcie_update_link_speed);
564
Matthew Wilcox45b4cdd52009-12-13 08:11:34 -0500565static unsigned char agp_speeds[] = {
566 AGP_UNKNOWN,
567 AGP_1X,
568 AGP_2X,
569 AGP_4X,
570 AGP_8X
571};
572
573static enum pci_bus_speed agp_speed(int agp3, int agpstat)
574{
575 int index = 0;
576
577 if (agpstat & 4)
578 index = 3;
579 else if (agpstat & 2)
580 index = 2;
581 else if (agpstat & 1)
582 index = 1;
583 else
584 goto out;
585
586 if (agp3) {
587 index += 2;
588 if (index == 5)
589 index = 0;
590 }
591
592 out:
593 return agp_speeds[index];
594}
595
596
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500597static void pci_set_bus_speed(struct pci_bus *bus)
598{
599 struct pci_dev *bridge = bus->self;
600 int pos;
601
Matthew Wilcox45b4cdd52009-12-13 08:11:34 -0500602 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
603 if (!pos)
604 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
605 if (pos) {
606 u32 agpstat, agpcmd;
607
608 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
609 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
610
611 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
612 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
613 }
614
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500615 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
616 if (pos) {
617 u16 status;
618 enum pci_bus_speed max;
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500619
Bjorn Helgaas7793eea2012-12-05 13:51:17 -0700620 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
621 &status);
622
623 if (status & PCI_X_SSTATUS_533MHZ) {
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500624 max = PCI_SPEED_133MHz_PCIX_533;
Bjorn Helgaas7793eea2012-12-05 13:51:17 -0700625 } else if (status & PCI_X_SSTATUS_266MHZ) {
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500626 max = PCI_SPEED_133MHz_PCIX_266;
Bjorn Helgaas7793eea2012-12-05 13:51:17 -0700627 } else if (status & PCI_X_SSTATUS_133MHZ) {
628 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) {
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500629 max = PCI_SPEED_133MHz_PCIX_ECC;
630 } else {
631 max = PCI_SPEED_133MHz_PCIX;
632 }
633 } else {
634 max = PCI_SPEED_66MHz_PCIX;
635 }
636
637 bus->max_bus_speed = max;
Bjorn Helgaas7793eea2012-12-05 13:51:17 -0700638 bus->cur_bus_speed = pcix_bus_speed[
639 (status & PCI_X_SSTATUS_FREQ) >> 6];
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500640
641 return;
642 }
643
644 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
645 if (pos) {
646 u32 linkcap;
647 u16 linksta;
648
Jiang Liu59875ae2012-07-24 17:20:06 +0800649 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
Bjorn Helgaas231afea2012-12-05 13:51:18 -0700650 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500651
Jiang Liu59875ae2012-07-24 17:20:06 +0800652 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500653 pcie_update_link_speed(bus, linksta);
654 }
655}
656
657
Adrian Bunkcbd4e052008-04-18 13:53:55 -0700658static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
659 struct pci_dev *bridge, int busnr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700660{
661 struct pci_bus *child;
662 int i;
Yinghai Lu4f535092013-01-21 13:20:52 -0800663 int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700664
665 /*
666 * Allocate a new bus, and inherit stuff from the parent..
667 */
668 child = pci_alloc_bus();
669 if (!child)
670 return NULL;
671
Linus Torvalds1da177e2005-04-16 15:20:36 -0700672 child->parent = parent;
673 child->ops = parent->ops;
Thierry Reding0cbdcfc2013-08-09 22:27:08 +0200674 child->msi = parent->msi;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700675 child->sysdata = parent->sysdata;
Michael S. Tsirkin6e325a62006-02-14 18:52:22 +0200676 child->bus_flags = parent->bus_flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700677
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -0400678 /* initialize some portions of the bus device, but don't register it
Yinghai Lu4f535092013-01-21 13:20:52 -0800679 * now as the parent is not properly set up yet.
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -0400680 */
681 child->dev.class = &pcibus_class;
Kay Sievers1a927132008-10-30 02:17:49 +0100682 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700683
684 /*
685 * Set up the primary, secondary and subordinate
686 * bus numbers.
687 */
Yinghai Lub918c622012-05-17 18:51:11 -0700688 child->number = child->busn_res.start = busnr;
689 child->primary = parent->busn_res.start;
690 child->busn_res.end = 0xff;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700691
Yinghai Lu4f535092013-01-21 13:20:52 -0800692 if (!bridge) {
693 child->dev.parent = parent->bridge;
694 goto add_dev;
695 }
Yu Zhao3789fa82008-11-22 02:41:07 +0800696
697 child->self = bridge;
698 child->bridge = get_device(&bridge->dev);
Yinghai Lu4f535092013-01-21 13:20:52 -0800699 child->dev.parent = child->bridge;
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +1000700 pci_set_bus_of_node(child);
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500701 pci_set_bus_speed(child);
702
Linus Torvalds1da177e2005-04-16 15:20:36 -0700703 /* Set up default resource pointers and names.. */
Yu Zhaofde09c62008-11-22 02:39:32 +0800704 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700705 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
706 child->resource[i]->name = child->name;
707 }
708 bridge->subordinate = child;
709
Yinghai Lu4f535092013-01-21 13:20:52 -0800710add_dev:
711 ret = device_register(&child->dev);
712 WARN_ON(ret < 0);
713
Jiang Liu10a95742013-04-12 05:44:20 +0000714 pcibios_add_bus(child);
715
Yinghai Lu4f535092013-01-21 13:20:52 -0800716 /* Create legacy_io and legacy_mem files for this bus */
717 pci_create_legacy_files(child);
718
Linus Torvalds1da177e2005-04-16 15:20:36 -0700719 return child;
720}
721
Sam Ravnborg451124a2008-02-02 22:33:43 +0100722struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700723{
724 struct pci_bus *child;
725
726 child = pci_alloc_child_bus(parent, dev, busnr);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -0700727 if (child) {
Zhang Yanmind71374d2006-06-02 12:35:43 +0800728 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700729 list_add_tail(&child->node, &parent->children);
Zhang Yanmind71374d2006-06-02 12:35:43 +0800730 up_write(&pci_bus_sem);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -0700731 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700732 return child;
733}
734
Sam Ravnborg96bde062007-03-26 21:53:30 -0800735static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700736{
737 struct pci_bus *parent = child->parent;
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700738
739 /* Attempts to fix that up are really dangerous unless
740 we're going to re-assign all bus numbers. */
741 if (!pcibios_assign_all_busses())
742 return;
743
Yinghai Lub918c622012-05-17 18:51:11 -0700744 while (parent->parent && parent->busn_res.end < max) {
745 parent->busn_res.end = max;
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700746 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
747 parent = parent->parent;
748 }
749}
750
Linus Torvalds1da177e2005-04-16 15:20:36 -0700751/*
752 * If it's a bridge, configure it and scan the bus behind it.
753 * For CardBus bridges, we don't scan behind as the devices will
754 * be handled by the bridge driver itself.
755 *
756 * We need to process bridges in two passes -- first we scan those
757 * already configured by the BIOS and after we are done with all of
758 * them, we proceed to assigning numbers to the remaining buses in
759 * order to avoid overlaps between old and new bus numbers.
760 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500761int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700762{
763 struct pci_bus *child;
764 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
Dominik Brodowski49887942005-12-08 16:53:12 +0100765 u32 buses, i, j = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700766 u16 bctl;
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600767 u8 primary, secondary, subordinate;
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100768 int broken = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700769
770 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600771 primary = buses & 0xFF;
772 secondary = (buses >> 8) & 0xFF;
773 subordinate = (buses >> 16) & 0xFF;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700774
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600775 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
776 secondary, subordinate, pass);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700777
Yinghai Lu71f6bd42012-01-30 12:25:24 +0100778 if (!primary && (primary != bus->number) && secondary && subordinate) {
779 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
780 primary = bus->number;
781 }
782
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100783 /* Check if setup is sensible at all */
784 if (!pass &&
Yinghai Lu1965f662012-09-10 17:19:33 -0700785 (primary != bus->number || secondary <= bus->number ||
786 secondary > subordinate)) {
787 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
788 secondary, subordinate);
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100789 broken = 1;
790 }
791
Linus Torvalds1da177e2005-04-16 15:20:36 -0700792 /* Disable MasterAbortMode during probing to avoid reporting
793 of bus errors (in some architectures) */
794 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
795 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
796 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
797
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600798 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
799 !is_cardbus && !broken) {
800 unsigned int cmax;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700801 /*
802 * Bus already configured by firmware, process it in the first
803 * pass and just note the configuration.
804 */
805 if (pass)
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000806 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807
808 /*
809 * If we already got to this bus through a different bridge,
Alex Chiang74710de2009-03-20 14:56:10 -0600810 * don't re-add it. This can happen with the i450NX chipset.
811 *
812 * However, we continue to descend down the hierarchy and
813 * scan remaining child buses.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814 */
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600815 child = pci_find_bus(pci_domain_nr(bus), secondary);
Alex Chiang74710de2009-03-20 14:56:10 -0600816 if (!child) {
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600817 child = pci_add_new_bus(bus, dev, secondary);
Alex Chiang74710de2009-03-20 14:56:10 -0600818 if (!child)
819 goto out;
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600820 child->primary = primary;
Yinghai Lubc76b732012-05-17 18:51:13 -0700821 pci_bus_insert_busn_res(child, secondary, subordinate);
Alex Chiang74710de2009-03-20 14:56:10 -0600822 child->bridge_ctl = bctl;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700823 }
824
Linus Torvalds1da177e2005-04-16 15:20:36 -0700825 cmax = pci_scan_child_bus(child);
826 if (cmax > max)
827 max = cmax;
Yinghai Lub918c622012-05-17 18:51:11 -0700828 if (child->busn_res.end > max)
829 max = child->busn_res.end;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700830 } else {
831 /*
832 * We need to assign a number to this bus which we always
833 * do in the second pass.
834 */
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700835 if (!pass) {
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100836 if (pcibios_assign_all_busses() || broken)
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700837 /* Temporarily disable forwarding of the
838 configuration cycles on all bridges in
839 this bus segment to avoid possible
840 conflicts in the second pass between two
841 bridges programmed with overlapping
842 bus ranges. */
843 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
844 buses & ~0xffffff);
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000845 goto out;
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700846 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700847
848 /* Clear errors */
849 pci_write_config_word(dev, PCI_STATUS, 0xffff);
850
Rajesh Shahcc574502005-04-28 00:25:47 -0700851 /* Prevent assigning a bus number that already exists.
Tiejun Chenb1a98b62011-06-02 11:02:50 +0800852 * This can happen when a bridge is hot-plugged, so in
853 * this case we only re-scan this bus. */
854 child = pci_find_bus(pci_domain_nr(bus), max+1);
855 if (!child) {
856 child = pci_add_new_bus(bus, dev, ++max);
857 if (!child)
858 goto out;
Yinghai Lubc76b732012-05-17 18:51:13 -0700859 pci_bus_insert_busn_res(child, max, 0xff);
Tiejun Chenb1a98b62011-06-02 11:02:50 +0800860 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700861 buses = (buses & 0xff000000)
862 | ((unsigned int)(child->primary) << 0)
Yinghai Lub918c622012-05-17 18:51:11 -0700863 | ((unsigned int)(child->busn_res.start) << 8)
864 | ((unsigned int)(child->busn_res.end) << 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700865
866 /*
867 * yenta.c forces a secondary latency timer of 176.
868 * Copy that behaviour here.
869 */
870 if (is_cardbus) {
871 buses &= ~0xff000000;
872 buses |= CARDBUS_LATENCY_TIMER << 24;
873 }
Jesper Juhl7c867c82011-01-24 21:14:33 +0100874
Linus Torvalds1da177e2005-04-16 15:20:36 -0700875 /*
876 * We need to blast all three values with a single write.
877 */
878 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
879
880 if (!is_cardbus) {
Gary Hade11949252007-10-08 16:24:16 -0700881 child->bridge_ctl = bctl;
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700882 /*
883 * Adjust subordinate busnr in parent buses.
884 * We do this before scanning for children because
885 * some devices may not be detected if the bios
886 * was lazy.
887 */
888 pci_fixup_parent_subordinate_busnr(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700889 /* Now we can scan all subordinate buses... */
890 max = pci_scan_child_bus(child);
Kristen Accardie3ac86d2006-01-17 16:57:01 -0800891 /*
892 * now fix it up again since we have found
893 * the real value of max.
894 */
895 pci_fixup_parent_subordinate_busnr(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700896 } else {
897 /*
898 * For CardBus bridges, we leave 4 bus numbers
899 * as cards with a PCI-to-PCI bridge can be
900 * inserted later.
901 */
Dominik Brodowski49887942005-12-08 16:53:12 +0100902 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
903 struct pci_bus *parent = bus;
Rajesh Shahcc574502005-04-28 00:25:47 -0700904 if (pci_find_bus(pci_domain_nr(bus),
905 max+i+1))
906 break;
Dominik Brodowski49887942005-12-08 16:53:12 +0100907 while (parent->parent) {
908 if ((!pcibios_assign_all_busses()) &&
Yinghai Lub918c622012-05-17 18:51:11 -0700909 (parent->busn_res.end > max) &&
910 (parent->busn_res.end <= max+i)) {
Dominik Brodowski49887942005-12-08 16:53:12 +0100911 j = 1;
912 }
913 parent = parent->parent;
914 }
915 if (j) {
916 /*
917 * Often, there are two cardbus bridges
918 * -- try to leave one valid bus number
919 * for each one.
920 */
921 i /= 2;
922 break;
923 }
924 }
Rajesh Shahcc574502005-04-28 00:25:47 -0700925 max += i;
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700926 pci_fixup_parent_subordinate_busnr(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700927 }
928 /*
929 * Set the subordinate bus number to its real value.
930 */
Yinghai Lubc76b732012-05-17 18:51:13 -0700931 pci_bus_update_busn_res_end(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700932 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
933 }
934
Gary Hadecb3576f2008-02-08 14:00:52 -0800935 sprintf(child->name,
936 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
937 pci_domain_nr(bus), child->number);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700938
Bernhard Kaindld55bef512007-07-30 20:35:13 +0200939 /* Has only triggered on CardBus, fixup is in yenta_socket */
Dominik Brodowski49887942005-12-08 16:53:12 +0100940 while (bus->parent) {
Yinghai Lub918c622012-05-17 18:51:11 -0700941 if ((child->busn_res.end > bus->busn_res.end) ||
942 (child->number > bus->busn_res.end) ||
Dominik Brodowski49887942005-12-08 16:53:12 +0100943 (child->number < bus->number) ||
Yinghai Lub918c622012-05-17 18:51:11 -0700944 (child->busn_res.end < bus->number)) {
945 dev_info(&child->dev, "%pR %s "
946 "hidden behind%s bridge %s %pR\n",
947 &child->busn_res,
948 (bus->number > child->busn_res.end &&
949 bus->busn_res.end < child->number) ?
Joe Perchesa6f29a92007-11-19 17:48:29 -0800950 "wholly" : "partially",
951 bus->self->transparent ? " transparent" : "",
Bjorn Helgaas865df572009-11-04 10:32:57 -0700952 dev_name(&bus->dev),
Yinghai Lub918c622012-05-17 18:51:11 -0700953 &bus->busn_res);
Dominik Brodowski49887942005-12-08 16:53:12 +0100954 }
955 bus = bus->parent;
956 }
957
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000958out:
959 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
960
Linus Torvalds1da177e2005-04-16 15:20:36 -0700961 return max;
962}
963
964/*
965 * Read interrupt line and base address registers.
966 * The architecture-dependent code can tweak these, of course.
967 */
968static void pci_read_irq(struct pci_dev *dev)
969{
970 unsigned char irq;
971
972 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
Kristen Accardiffeff782005-11-02 16:24:32 -0800973 dev->pin = irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700974 if (irq)
975 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
976 dev->irq = irq;
977}
978
Benjamin Herrenschmidtbb209c82010-01-26 17:10:03 +0000979void set_pcie_port_type(struct pci_dev *pdev)
Yu Zhao480b93b2009-03-20 11:25:14 +0800980{
981 int pos;
982 u16 reg16;
983
984 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
985 if (!pos)
986 return;
987 pdev->is_pcie = 1;
Kenji Kaneshige0efea002009-11-05 12:05:11 +0900988 pdev->pcie_cap = pos;
Yu Zhao480b93b2009-03-20 11:25:14 +0800989 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
Yijing Wang786e2282012-07-24 17:20:02 +0800990 pdev->pcie_flags_reg = reg16;
Jon Masonb03e7492011-07-20 15:20:54 -0500991 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
992 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
Yu Zhao480b93b2009-03-20 11:25:14 +0800993}
994
Benjamin Herrenschmidtbb209c82010-01-26 17:10:03 +0000995void set_pcie_hotplug_bridge(struct pci_dev *pdev)
Eric W. Biederman28760482009-09-09 14:09:24 -0700996{
Eric W. Biederman28760482009-09-09 14:09:24 -0700997 u32 reg32;
998
Jiang Liu59875ae2012-07-24 17:20:06 +0800999 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &reg32);
Eric W. Biederman28760482009-09-09 14:09:24 -07001000 if (reg32 & PCI_EXP_SLTCAP_HPC)
1001 pdev->is_hotplug_bridge = 1;
1002}
1003
Bartlomiej Zolnierkiewicz01abc2a2007-04-23 23:19:36 +02001004#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
Randy Dunlap76e6a1d2006-12-29 16:47:29 -08001005
Linus Torvalds1da177e2005-04-16 15:20:36 -07001006/**
1007 * pci_setup_device - fill in class and map information of a device
1008 * @dev: the device structure to fill
1009 *
1010 * Initialize the device structure with information about the device's
1011 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1012 * Called at initialisation of the PCI subsystem and by CardBus services.
Yu Zhao480b93b2009-03-20 11:25:14 +08001013 * Returns 0 on success and negative if unknown type of device (not normal,
1014 * bridge or CardBus).
Linus Torvalds1da177e2005-04-16 15:20:36 -07001015 */
Yu Zhao480b93b2009-03-20 11:25:14 +08001016int pci_setup_device(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001017{
1018 u32 class;
Yu Zhao480b93b2009-03-20 11:25:14 +08001019 u8 hdr_type;
1020 struct pci_slot *slot;
Gabe Blackbc577d22009-10-06 10:45:19 -05001021 int pos = 0;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001022 struct pci_bus_region region;
1023 struct resource *res;
Yu Zhao480b93b2009-03-20 11:25:14 +08001024
1025 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1026 return -EIO;
1027
1028 dev->sysdata = dev->bus->sysdata;
1029 dev->dev.parent = dev->bus->bridge;
1030 dev->dev.bus = &pci_bus_type;
1031 dev->hdr_type = hdr_type & 0x7f;
1032 dev->multifunction = !!(hdr_type & 0x80);
Yu Zhao480b93b2009-03-20 11:25:14 +08001033 dev->error_state = pci_channel_io_normal;
1034 set_pcie_port_type(dev);
1035
1036 list_for_each_entry(slot, &dev->bus->slots, list)
1037 if (PCI_SLOT(dev->devfn) == slot->number)
1038 dev->slot = slot;
1039
1040 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1041 set this higher, assuming the system even supports it. */
1042 dev->dma_mask = 0xffffffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001043
Greg Kroah-Hartmaneebfcfb2008-07-02 13:24:49 -07001044 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1045 dev->bus->number, PCI_SLOT(dev->devfn),
1046 PCI_FUNC(dev->devfn));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001047
1048 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
Auke Kokb8a3a522007-06-08 15:46:30 -07001049 dev->revision = class & 0xff;
Yinghai Lu2dd8ba92012-02-19 14:50:12 -08001050 dev->class = class >> 8; /* upper 3 bytes */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001051
Yinghai Lu2dd8ba92012-02-19 14:50:12 -08001052 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1053 dev->vendor, dev->device, dev->hdr_type, dev->class);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001054
Yu Zhao853346e2009-03-21 22:05:11 +08001055 /* need to have dev->class ready */
1056 dev->cfg_size = pci_cfg_space_size(dev);
1057
Linus Torvalds1da177e2005-04-16 15:20:36 -07001058 /* "Unknown power state" */
Daniel Ritz3fe9d192005-08-17 15:32:19 -07001059 dev->current_state = PCI_UNKNOWN;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001060
1061 /* Early fixups, before probing the BARs */
1062 pci_fixup_device(pci_fixup_early, dev);
Yu Zhaof79b1b12009-05-28 00:25:05 +08001063 /* device class may be changed after fixup */
1064 class = dev->class >> 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001065
1066 switch (dev->hdr_type) { /* header type */
1067 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1068 if (class == PCI_CLASS_BRIDGE_PCI)
1069 goto bad;
1070 pci_read_irq(dev);
1071 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1072 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1073 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
Alan Cox368c73d2006-10-04 00:41:26 +01001074
1075 /*
1076 * Do the ugly legacy mode stuff here rather than broken chip
1077 * quirk code. Legacy mode ATA controllers have fixed
1078 * addresses. These are not always echoed in BAR0-3, and
1079 * BAR0-3 in a few cases contain junk!
1080 */
1081 if (class == PCI_CLASS_STORAGE_IDE) {
1082 u8 progif;
1083 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1084 if ((progif & 1) == 0) {
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001085 region.start = 0x1F0;
1086 region.end = 0x1F7;
1087 res = &dev->resource[0];
1088 res->flags = LEGACY_IO_RESOURCE;
Bjorn Helgaasfb127cb2012-02-23 20:19:04 -07001089 pcibios_bus_to_resource(dev, res, &region);
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001090 region.start = 0x3F6;
1091 region.end = 0x3F6;
1092 res = &dev->resource[1];
1093 res->flags = LEGACY_IO_RESOURCE;
Bjorn Helgaasfb127cb2012-02-23 20:19:04 -07001094 pcibios_bus_to_resource(dev, res, &region);
Alan Cox368c73d2006-10-04 00:41:26 +01001095 }
1096 if ((progif & 4) == 0) {
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001097 region.start = 0x170;
1098 region.end = 0x177;
1099 res = &dev->resource[2];
1100 res->flags = LEGACY_IO_RESOURCE;
Bjorn Helgaasfb127cb2012-02-23 20:19:04 -07001101 pcibios_bus_to_resource(dev, res, &region);
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001102 region.start = 0x376;
1103 region.end = 0x376;
1104 res = &dev->resource[3];
1105 res->flags = LEGACY_IO_RESOURCE;
Bjorn Helgaasfb127cb2012-02-23 20:19:04 -07001106 pcibios_bus_to_resource(dev, res, &region);
Alan Cox368c73d2006-10-04 00:41:26 +01001107 }
1108 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001109 break;
1110
1111 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1112 if (class != PCI_CLASS_BRIDGE_PCI)
1113 goto bad;
1114 /* The PCI-to-PCI bridge spec requires that subtractive
1115 decoding (i.e. transparent) bridge must have programming
1116 interface code of 0x01. */
Kristen Accardi3efd2732005-11-02 16:55:49 -08001117 pci_read_irq(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001118 dev->transparent = ((dev->class & 0xff) == 1);
1119 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
Eric W. Biederman28760482009-09-09 14:09:24 -07001120 set_pcie_hotplug_bridge(dev);
Gabe Blackbc577d22009-10-06 10:45:19 -05001121 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1122 if (pos) {
1123 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1124 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1125 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001126 break;
1127
1128 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1129 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1130 goto bad;
1131 pci_read_irq(dev);
1132 pci_read_bases(dev, 1, 0);
1133 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1134 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1135 break;
1136
1137 default: /* unknown header */
Bjorn Helgaas80ccba12008-06-13 10:52:11 -06001138 dev_err(&dev->dev, "unknown header type %02x, "
1139 "ignoring device\n", dev->hdr_type);
Yu Zhao480b93b2009-03-20 11:25:14 +08001140 return -EIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001141
1142 bad:
Yinghai Lu2dd8ba92012-02-19 14:50:12 -08001143 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header "
1144 "type %02x)\n", dev->class, dev->hdr_type);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001145 dev->class = PCI_CLASS_NOT_DEFINED;
1146 }
1147
1148 /* We found a fine healthy device, go go go... */
1149 return 0;
1150}
1151
Zhao, Yu201de562008-10-13 19:49:55 +08001152static void pci_release_capabilities(struct pci_dev *dev)
1153{
1154 pci_vpd_release(dev);
Yu Zhaod1b054d2009-03-20 11:25:11 +08001155 pci_iov_release(dev);
Yinghai Luf7968412012-02-11 00:18:30 -08001156 pci_free_cap_save_buffers(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001157}
1158
Linus Torvalds1da177e2005-04-16 15:20:36 -07001159/**
1160 * pci_release_dev - free a pci device structure when all users of it are finished.
1161 * @dev: device that's been disconnected
1162 *
1163 * Will be called only by the device core when all users of this pci device are
1164 * done.
1165 */
1166static void pci_release_dev(struct device *dev)
1167{
1168 struct pci_dev *pci_dev;
1169
1170 pci_dev = to_pci_dev(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001171 pci_release_capabilities(pci_dev);
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +10001172 pci_release_of_node(pci_dev);
Sebastian Ott6ae32c52013-06-04 19:18:14 +02001173 pcibios_release_device(pci_dev);
Gu Zheng8b1fce02013-05-25 21:48:31 +08001174 pci_bus_put(pci_dev->bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001175 kfree(pci_dev);
1176}
1177
1178/**
1179 * pci_cfg_space_size - get the configuration space size of the PCI device.
Randy Dunlap8f7020d2005-10-23 11:57:38 -07001180 * @dev: PCI device
Linus Torvalds1da177e2005-04-16 15:20:36 -07001181 *
1182 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1183 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1184 * access it. Maybe we don't have a way to generate extended config space
1185 * accesses, or the device is behind a reverse Express bridge. So we try
1186 * reading the dword at 0x100 which must either be 0 or a valid extended
1187 * capability header.
1188 */
Yinghai Lu70b9f7d2008-04-28 16:27:23 -07001189int pci_cfg_space_size_ext(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001190{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001191 u32 status;
Zhao, Yu557848c2008-10-13 19:18:07 +08001192 int pos = PCI_CFG_SPACE_SIZE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001193
Zhao, Yu557848c2008-10-13 19:18:07 +08001194 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001195 goto fail;
1196 if (status == 0xffffffff)
1197 goto fail;
1198
1199 return PCI_CFG_SPACE_EXP_SIZE;
1200
1201 fail:
1202 return PCI_CFG_SPACE_SIZE;
1203}
1204
Yinghai Lu57741a72008-02-15 01:32:50 -08001205int pci_cfg_space_size(struct pci_dev *dev)
1206{
Yinghai Lu70b9f7d2008-04-28 16:27:23 -07001207 int pos;
1208 u32 status;
Yinghai Ludfadd9ed2009-03-08 21:35:37 -07001209 u16 class;
1210
1211 class = dev->class >> 8;
1212 if (class == PCI_CLASS_BRIDGE_HOST)
1213 return pci_cfg_space_size_ext(dev);
Yinghai Lu70b9f7d2008-04-28 16:27:23 -07001214
Jiang Liu59875ae2012-07-24 17:20:06 +08001215 if (!pci_is_pcie(dev)) {
Yinghai Lu70b9f7d2008-04-28 16:27:23 -07001216 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1217 if (!pos)
1218 goto fail;
1219
1220 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1221 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1222 goto fail;
1223 }
1224
1225 return pci_cfg_space_size_ext(dev);
1226
1227 fail:
1228 return PCI_CFG_SPACE_SIZE;
Yinghai Lu57741a72008-02-15 01:32:50 -08001229}
1230
Gu Zheng3c6e6ae2013-05-25 21:48:30 +08001231struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
Michael Ellerman65891212007-04-05 17:19:08 +10001232{
1233 struct pci_dev *dev;
1234
1235 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1236 if (!dev)
1237 return NULL;
1238
Michael Ellerman65891212007-04-05 17:19:08 +10001239 INIT_LIST_HEAD(&dev->bus_list);
Brian King88e7b162013-04-08 03:05:07 +00001240 dev->dev.type = &pci_dev_type;
Gu Zheng3c6e6ae2013-05-25 21:48:30 +08001241 dev->bus = pci_bus_get(bus);
Michael Ellerman65891212007-04-05 17:19:08 +10001242
1243 return dev;
1244}
Gu Zheng3c6e6ae2013-05-25 21:48:30 +08001245EXPORT_SYMBOL(pci_alloc_dev);
1246
1247struct pci_dev *alloc_pci_dev(void)
1248{
1249 return pci_alloc_dev(NULL);
1250}
Michael Ellerman65891212007-04-05 17:19:08 +10001251EXPORT_SYMBOL(alloc_pci_dev);
1252
Yinghai Luefdc87d2012-01-27 10:55:10 -08001253bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1254 int crs_timeout)
1255{
1256 int delay = 1;
1257
1258 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1259 return false;
1260
1261 /* some broken boards return 0 or ~0 if a slot is empty: */
1262 if (*l == 0xffffffff || *l == 0x00000000 ||
1263 *l == 0x0000ffff || *l == 0xffff0000)
1264 return false;
1265
1266 /* Configuration request Retry Status */
1267 while (*l == 0xffff0001) {
1268 if (!crs_timeout)
1269 return false;
1270
1271 msleep(delay);
1272 delay *= 2;
1273 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1274 return false;
1275 /* Card hasn't responded in 60 seconds? Must be stuck. */
1276 if (delay > crs_timeout) {
1277 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
1278 "responding\n", pci_domain_nr(bus),
1279 bus->number, PCI_SLOT(devfn),
1280 PCI_FUNC(devfn));
1281 return false;
1282 }
1283 }
1284
1285 return true;
1286}
1287EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1288
Linus Torvalds1da177e2005-04-16 15:20:36 -07001289/*
1290 * Read the config data for a PCI device, sanity-check it
1291 * and fill in the dev structure...
1292 */
Adrian Bunk7f7b5de2008-04-18 13:53:55 -07001293static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001294{
1295 struct pci_dev *dev;
1296 u32 l;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001297
Yinghai Luefdc87d2012-01-27 10:55:10 -08001298 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001299 return NULL;
1300
Gu Zheng8b1fce02013-05-25 21:48:31 +08001301 dev = pci_alloc_dev(bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001302 if (!dev)
1303 return NULL;
1304
Linus Torvalds1da177e2005-04-16 15:20:36 -07001305 dev->devfn = devfn;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001306 dev->vendor = l & 0xffff;
1307 dev->device = (l >> 16) & 0xffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001308
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +10001309 pci_set_of_node(dev);
1310
Yu Zhao480b93b2009-03-20 11:25:14 +08001311 if (pci_setup_device(dev)) {
Gu Zheng8b1fce02013-05-25 21:48:31 +08001312 pci_bus_put(dev->bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001313 kfree(dev);
1314 return NULL;
1315 }
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001316
1317 return dev;
1318}
1319
Zhao, Yu201de562008-10-13 19:49:55 +08001320static void pci_init_capabilities(struct pci_dev *dev)
1321{
1322 /* MSI/MSI-X list */
1323 pci_msi_init_pci_dev(dev);
1324
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01001325 /* Buffers for saving PCIe and PCI-X capabilities */
1326 pci_allocate_cap_save_buffers(dev);
1327
Zhao, Yu201de562008-10-13 19:49:55 +08001328 /* Power Management */
1329 pci_pm_init(dev);
1330
1331 /* Vital Product Data */
1332 pci_vpd_pci22_init(dev);
Yu Zhao58c3a722008-10-14 14:02:53 +08001333
1334 /* Alternative Routing-ID Forwarding */
Yijing Wang31ab2472013-01-15 11:12:17 +08001335 pci_configure_ari(dev);
Yu Zhaod1b054d2009-03-20 11:25:11 +08001336
1337 /* Single Root I/O Virtualization */
1338 pci_iov_init(dev);
Allen Kayae21ee62009-10-07 10:27:17 -07001339
1340 /* Enable ACS P2P upstream forwarding */
Chris Wright5d990b62009-12-04 12:15:21 -08001341 pci_enable_acs(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001342}
1343
Sam Ravnborg96bde062007-03-26 21:53:30 -08001344void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001345{
Yinghai Lu4f535092013-01-21 13:20:52 -08001346 int ret;
1347
Linus Torvalds1da177e2005-04-16 15:20:36 -07001348 device_initialize(&dev->dev);
1349 dev->dev.release = pci_release_dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001350
Yinghai Lu7629d192013-01-21 13:20:44 -08001351 set_dev_node(&dev->dev, pcibus_to_node(bus));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001352 dev->dev.dma_mask = &dev->dma_mask;
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001353 dev->dev.dma_parms = &dev->dma_parms;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001354 dev->dev.coherent_dma_mask = 0xffffffffull;
1355
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001356 pci_set_dma_max_seg_size(dev, 65536);
FUJITA Tomonori59fc67d2008-02-04 22:28:14 -08001357 pci_set_dma_seg_boundary(dev, 0xffffffff);
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001358
Linus Torvalds1da177e2005-04-16 15:20:36 -07001359 /* Fix up broken headers */
1360 pci_fixup_device(pci_fixup_header, dev);
1361
Yinghai Lu2069ecf2012-02-15 21:40:31 -08001362 /* moved out from quirk header fixup code */
1363 pci_reassigndev_resource_alignment(dev);
1364
Rafael J. Wysocki4b77b0a2009-09-09 23:49:59 +02001365 /* Clear the state_saved flag. */
1366 dev->state_saved = false;
1367
Zhao, Yu201de562008-10-13 19:49:55 +08001368 /* Initialize various capabilities */
1369 pci_init_capabilities(dev);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001370
Linus Torvalds1da177e2005-04-16 15:20:36 -07001371 /*
1372 * Add the device to our list of discovered devices
1373 * and the bus list for fixup functions, etc.
1374 */
Zhang Yanmind71374d2006-06-02 12:35:43 +08001375 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001376 list_add_tail(&dev->bus_list, &bus->devices);
Zhang Yanmind71374d2006-06-02 12:35:43 +08001377 up_write(&pci_bus_sem);
Yinghai Lu4f535092013-01-21 13:20:52 -08001378
Yinghai Lu4f535092013-01-21 13:20:52 -08001379 ret = pcibios_add_device(dev);
1380 WARN_ON(ret < 0);
1381
1382 /* Notifier could use PCI capabilities */
1383 dev->match_driver = false;
1384 ret = device_add(&dev->dev);
1385 WARN_ON(ret < 0);
1386
1387 pci_proc_attach_device(dev);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001388}
1389
Sam Ravnborg451124a2008-02-02 22:33:43 +01001390struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001391{
1392 struct pci_dev *dev;
1393
Trent Piepho90bdb312009-03-20 14:56:00 -06001394 dev = pci_get_slot(bus, devfn);
1395 if (dev) {
1396 pci_dev_put(dev);
1397 return dev;
1398 }
1399
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001400 dev = pci_scan_device(bus, devfn);
1401 if (!dev)
1402 return NULL;
1403
1404 pci_device_add(dev, bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001405
1406 return dev;
1407}
Adrian Bunkb73e9682007-11-21 15:07:11 -08001408EXPORT_SYMBOL(pci_scan_single_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001409
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001410static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001411{
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001412 int pos;
1413 u16 cap = 0;
1414 unsigned next_fn;
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07001415
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001416 if (pci_ari_enabled(bus)) {
1417 if (!dev)
1418 return 0;
1419 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1420 if (!pos)
1421 return 0;
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07001422
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001423 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1424 next_fn = PCI_ARI_CAP_NFN(cap);
1425 if (next_fn <= fn)
1426 return 0; /* protect against malformed list */
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001427
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001428 return next_fn;
1429 }
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001430
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001431 /* dev may be NULL for non-contiguous multifunction devices */
1432 if (!dev || dev->multifunction)
1433 return (fn + 1) % 8;
1434
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001435 return 0;
1436}
1437
1438static int only_one_child(struct pci_bus *bus)
1439{
1440 struct pci_dev *parent = bus->self;
Bjorn Helgaas284f5f92012-04-30 15:21:02 -06001441
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001442 if (!parent || !pci_is_pcie(parent))
1443 return 0;
Yijing Wang62f87c02012-07-24 17:20:03 +08001444 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
Bjorn Helgaas284f5f92012-04-30 15:21:02 -06001445 return 1;
Yijing Wang62f87c02012-07-24 17:20:03 +08001446 if (pci_pcie_type(parent) == PCI_EXP_TYPE_DOWNSTREAM &&
Bjorn Helgaas284f5f92012-04-30 15:21:02 -06001447 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001448 return 1;
1449 return 0;
1450}
1451
Linus Torvalds1da177e2005-04-16 15:20:36 -07001452/**
1453 * pci_scan_slot - scan a PCI slot on a bus for devices.
1454 * @bus: PCI bus to scan
1455 * @devfn: slot number to scan (must have zero function.)
1456 *
1457 * Scan a PCI slot on the specified PCI bus for devices, adding
1458 * discovered devices to the @bus->devices list. New devices
Greg Kroah-Hartman8a1bc902008-02-14 14:56:56 -08001459 * will not have is_added set.
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001460 *
1461 * Returns the number of new devices found.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001462 */
Sam Ravnborg96bde062007-03-26 21:53:30 -08001463int pci_scan_slot(struct pci_bus *bus, int devfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001464{
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001465 unsigned fn, nr = 0;
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001466 struct pci_dev *dev;
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001467
1468 if (only_one_child(bus) && (devfn > 0))
1469 return 0; /* Already scanned the entire slot */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001470
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001471 dev = pci_scan_single_device(bus, devfn);
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07001472 if (!dev)
1473 return 0;
1474 if (!dev->is_added)
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001475 nr++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001476
Yijing Wangb1bd58e2013-01-25 09:12:31 -07001477 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001478 dev = pci_scan_single_device(bus, devfn + fn);
1479 if (dev) {
1480 if (!dev->is_added)
1481 nr++;
1482 dev->multifunction = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001483 }
1484 }
Shaohua Li7d715a62008-02-25 09:46:41 +08001485
Shaohua Li149e1632008-07-23 10:32:31 +08001486 /* only one slot has pcie device */
1487 if (bus->self && nr)
Shaohua Li7d715a62008-02-25 09:46:41 +08001488 pcie_aspm_init_link_state(bus->self);
1489
Linus Torvalds1da177e2005-04-16 15:20:36 -07001490 return nr;
1491}
1492
Jon Masonb03e7492011-07-20 15:20:54 -05001493static int pcie_find_smpss(struct pci_dev *dev, void *data)
1494{
1495 u8 *smpss = data;
1496
1497 if (!pci_is_pcie(dev))
1498 return 0;
1499
Yijing Wangd4aa68f2013-08-22 11:24:47 +08001500 /*
1501 * We don't have a way to change MPS settings on devices that have
1502 * drivers attached. A hot-added device might support only the minimum
1503 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1504 * where devices may be hot-added, we limit the fabric MPS to 128 so
1505 * hot-added devices will work correctly.
1506 *
1507 * However, if we hot-add a device to a slot directly below a Root
1508 * Port, it's impossible for there to be other existing devices below
1509 * the port. We don't limit the MPS in this case because we can
1510 * reconfigure MPS on both the Root Port and the hot-added device,
1511 * and there are no other devices involved.
1512 *
1513 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
Jon Masonb03e7492011-07-20 15:20:54 -05001514 */
Yijing Wangd4aa68f2013-08-22 11:24:47 +08001515 if (dev->is_hotplug_bridge &&
1516 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
Jon Masonb03e7492011-07-20 15:20:54 -05001517 *smpss = 0;
1518
1519 if (*smpss > dev->pcie_mpss)
1520 *smpss = dev->pcie_mpss;
1521
1522 return 0;
1523}
1524
1525static void pcie_write_mps(struct pci_dev *dev, int mps)
1526{
Jon Mason62f392e2011-10-14 14:56:14 -05001527 int rc;
Jon Masonb03e7492011-07-20 15:20:54 -05001528
1529 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
Jon Mason62f392e2011-10-14 14:56:14 -05001530 mps = 128 << dev->pcie_mpss;
Jon Masonb03e7492011-07-20 15:20:54 -05001531
Yijing Wang62f87c02012-07-24 17:20:03 +08001532 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1533 dev->bus->self)
Jon Mason62f392e2011-10-14 14:56:14 -05001534 /* For "Performance", the assumption is made that
Jon Masonb03e7492011-07-20 15:20:54 -05001535 * downstream communication will never be larger than
1536 * the MRRS. So, the MPS only needs to be configured
1537 * for the upstream communication. This being the case,
1538 * walk from the top down and set the MPS of the child
1539 * to that of the parent bus.
Jon Mason62f392e2011-10-14 14:56:14 -05001540 *
1541 * Configure the device MPS with the smaller of the
1542 * device MPSS or the bridge MPS (which is assumed to be
1543 * properly configured at this point to the largest
1544 * allowable MPS based on its parent bus).
Jon Masonb03e7492011-07-20 15:20:54 -05001545 */
Jon Mason62f392e2011-10-14 14:56:14 -05001546 mps = min(mps, pcie_get_mps(dev->bus->self));
Jon Masonb03e7492011-07-20 15:20:54 -05001547 }
1548
1549 rc = pcie_set_mps(dev, mps);
1550 if (rc)
1551 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1552}
1553
Jon Mason62f392e2011-10-14 14:56:14 -05001554static void pcie_write_mrrs(struct pci_dev *dev)
Jon Masonb03e7492011-07-20 15:20:54 -05001555{
Jon Mason62f392e2011-10-14 14:56:14 -05001556 int rc, mrrs;
Jon Masonb03e7492011-07-20 15:20:54 -05001557
Jon Masoned2888e2011-09-08 16:41:18 -05001558 /* In the "safe" case, do not configure the MRRS. There appear to be
1559 * issues with setting MRRS to 0 on a number of devices.
1560 */
Jon Masoned2888e2011-09-08 16:41:18 -05001561 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1562 return;
Jon Masonb03e7492011-07-20 15:20:54 -05001563
Jon Masoned2888e2011-09-08 16:41:18 -05001564 /* For Max performance, the MRRS must be set to the largest supported
1565 * value. However, it cannot be configured larger than the MPS the
Jon Mason62f392e2011-10-14 14:56:14 -05001566 * device or the bus can support. This should already be properly
1567 * configured by a prior call to pcie_write_mps.
Jon Masoned2888e2011-09-08 16:41:18 -05001568 */
Jon Mason62f392e2011-10-14 14:56:14 -05001569 mrrs = pcie_get_mps(dev);
Jon Masonb03e7492011-07-20 15:20:54 -05001570
1571 /* MRRS is a R/W register. Invalid values can be written, but a
Jon Masoned2888e2011-09-08 16:41:18 -05001572 * subsequent read will verify if the value is acceptable or not.
Jon Masonb03e7492011-07-20 15:20:54 -05001573 * If the MRRS value provided is not acceptable (e.g., too large),
1574 * shrink the value until it is acceptable to the HW.
1575 */
1576 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1577 rc = pcie_set_readrq(dev, mrrs);
Jon Mason62f392e2011-10-14 14:56:14 -05001578 if (!rc)
1579 break;
Jon Masonb03e7492011-07-20 15:20:54 -05001580
Jon Mason62f392e2011-10-14 14:56:14 -05001581 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
Jon Masonb03e7492011-07-20 15:20:54 -05001582 mrrs /= 2;
1583 }
Jon Mason62f392e2011-10-14 14:56:14 -05001584
1585 if (mrrs < 128)
1586 dev_err(&dev->dev, "MRRS was unable to be configured with a "
1587 "safe value. If problems are experienced, try running "
1588 "with pci=pcie_bus_safe.\n");
Jon Masonb03e7492011-07-20 15:20:54 -05001589}
1590
Yijing Wang5895af72013-08-26 16:33:06 +08001591static void pcie_bus_detect_mps(struct pci_dev *dev)
1592{
1593 struct pci_dev *bridge = dev->bus->self;
1594 int mps, p_mps;
1595
1596 if (!bridge)
1597 return;
1598
1599 mps = pcie_get_mps(dev);
1600 p_mps = pcie_get_mps(bridge);
1601
1602 if (mps != p_mps)
1603 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1604 mps, pci_name(bridge), p_mps);
1605}
1606
Jon Masonb03e7492011-07-20 15:20:54 -05001607static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1608{
Jon Masona513a992011-10-14 14:56:16 -05001609 int mps, orig_mps;
Jon Masonb03e7492011-07-20 15:20:54 -05001610
1611 if (!pci_is_pcie(dev))
1612 return 0;
1613
Yijing Wang5895af72013-08-26 16:33:06 +08001614 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1615 pcie_bus_detect_mps(dev);
1616 return 0;
1617 }
1618
Jon Masona513a992011-10-14 14:56:16 -05001619 mps = 128 << *(u8 *)data;
1620 orig_mps = pcie_get_mps(dev);
Jon Masonb03e7492011-07-20 15:20:54 -05001621
1622 pcie_write_mps(dev, mps);
Jon Mason62f392e2011-10-14 14:56:14 -05001623 pcie_write_mrrs(dev);
Jon Masonb03e7492011-07-20 15:20:54 -05001624
Bjorn Helgaas2c25e342013-08-22 11:24:43 +08001625 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), "
Jon Masona513a992011-10-14 14:56:16 -05001626 "Max Read Rq %4d\n", pcie_get_mps(dev), 128 << dev->pcie_mpss,
1627 orig_mps, pcie_get_readrq(dev));
Jon Masonb03e7492011-07-20 15:20:54 -05001628
1629 return 0;
1630}
1631
Jon Masona513a992011-10-14 14:56:16 -05001632/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
Jon Masonb03e7492011-07-20 15:20:54 -05001633 * parents then children fashion. If this changes, then this code will not
1634 * work as designed.
1635 */
Bjorn Helgaasa58674f2013-08-22 11:24:44 +08001636void pcie_bus_configure_settings(struct pci_bus *bus)
Jon Masonb03e7492011-07-20 15:20:54 -05001637{
Jon Mason5f39e672011-10-03 09:50:20 -05001638 u8 smpss;
Jon Masonb03e7492011-07-20 15:20:54 -05001639
Bjorn Helgaasa58674f2013-08-22 11:24:44 +08001640 if (!bus->self)
1641 return;
1642
Jon Masonb03e7492011-07-20 15:20:54 -05001643 if (!pci_is_pcie(bus->self))
1644 return;
1645
Jon Mason5f39e672011-10-03 09:50:20 -05001646 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
Jon Mason33154722013-08-26 16:33:05 +08001647 * to be aware of the MPS of the destination. To work around this,
Jon Mason5f39e672011-10-03 09:50:20 -05001648 * simply force the MPS of the entire system to the smallest possible.
1649 */
1650 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1651 smpss = 0;
1652
Jon Masonb03e7492011-07-20 15:20:54 -05001653 if (pcie_bus_config == PCIE_BUS_SAFE) {
Bjorn Helgaasa58674f2013-08-22 11:24:44 +08001654 smpss = bus->self->pcie_mpss;
Jon Mason5f39e672011-10-03 09:50:20 -05001655
Jon Masonb03e7492011-07-20 15:20:54 -05001656 pcie_find_smpss(bus->self, &smpss);
1657 pci_walk_bus(bus, pcie_find_smpss, &smpss);
1658 }
1659
1660 pcie_bus_configure_set(bus->self, &smpss);
1661 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
1662}
Jon Masondebc3b72011-08-02 00:01:18 -05001663EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
Jon Masonb03e7492011-07-20 15:20:54 -05001664
Bill Pemberton15856ad2012-11-21 15:35:00 -05001665unsigned int pci_scan_child_bus(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001666{
Yinghai Lub918c622012-05-17 18:51:11 -07001667 unsigned int devfn, pass, max = bus->busn_res.start;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001668 struct pci_dev *dev;
1669
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001670 dev_dbg(&bus->dev, "scanning bus\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001671
1672 /* Go find them, Rover! */
1673 for (devfn = 0; devfn < 0x100; devfn += 8)
1674 pci_scan_slot(bus, devfn);
1675
Yu Zhaoa28724b2009-03-20 11:25:13 +08001676 /* Reserve buses for SR-IOV capability. */
1677 max += pci_iov_bus_range(bus);
1678
Linus Torvalds1da177e2005-04-16 15:20:36 -07001679 /*
1680 * After performing arch-dependent fixup of the bus, look behind
1681 * all PCI-to-PCI bridges on this bus.
1682 */
Alex Chiang74710de2009-03-20 14:56:10 -06001683 if (!bus->is_added) {
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001684 dev_dbg(&bus->dev, "fixups for bus\n");
Alex Chiang74710de2009-03-20 14:56:10 -06001685 pcibios_fixup_bus(bus);
Jiang Liu981cf9e2013-04-12 05:44:16 +00001686 bus->is_added = 1;
Alex Chiang74710de2009-03-20 14:56:10 -06001687 }
1688
Linus Torvalds1da177e2005-04-16 15:20:36 -07001689 for (pass=0; pass < 2; pass++)
1690 list_for_each_entry(dev, &bus->devices, bus_list) {
1691 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1692 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1693 max = pci_scan_bridge(bus, dev, max, pass);
1694 }
1695
1696 /*
1697 * We've scanned the bus and so we know all about what's on
1698 * the other side of any bridges that may be on this bus plus
1699 * any devices.
1700 *
1701 * Return how far we've got finding sub-buses.
1702 */
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001703 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001704 return max;
1705}
1706
Rafael J. Wysocki6c0cc952013-01-09 22:33:37 +01001707/**
1708 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
1709 * @bridge: Host bridge to set up.
1710 *
1711 * Default empty implementation. Replace with an architecture-specific setup
1712 * routine, if necessary.
1713 */
1714int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
1715{
1716 return 0;
1717}
1718
Jiang Liu10a95742013-04-12 05:44:20 +00001719void __weak pcibios_add_bus(struct pci_bus *bus)
1720{
1721}
1722
1723void __weak pcibios_remove_bus(struct pci_bus *bus)
1724{
1725}
1726
Bjorn Helgaas166c6372011-10-28 16:25:45 -06001727struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1728 struct pci_ops *ops, void *sysdata, struct list_head *resources)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001729{
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07001730 int error;
Bjorn Helgaas5a21d702012-02-23 20:18:59 -07001731 struct pci_host_bridge *bridge;
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001732 struct pci_bus *b, *b2;
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07001733 struct pci_host_bridge_window *window, *n;
Bjorn Helgaasa9d9f522011-10-28 16:25:40 -06001734 struct resource *res;
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07001735 resource_size_t offset;
1736 char bus_addr[64];
1737 char *fmt;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001738
Bjorn Helgaas5a21d702012-02-23 20:18:59 -07001739 b = pci_alloc_bus();
1740 if (!b)
Yinghai Lu7b543662012-04-02 18:31:53 -07001741 return NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001742
1743 b->sysdata = sysdata;
1744 b->ops = ops;
Yinghai Lu4f535092013-01-21 13:20:52 -08001745 b->number = b->busn_res.start = bus;
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001746 b2 = pci_find_bus(pci_domain_nr(b), bus);
1747 if (b2) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001748 /* If we already got to this bus through a different bridge, ignore it */
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001749 dev_dbg(&b2->dev, "bus already known\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001750 goto err_out;
1751 }
Zhang Yanmind71374d2006-06-02 12:35:43 +08001752
Yinghai Lu7b543662012-04-02 18:31:53 -07001753 bridge = pci_alloc_host_bridge(b);
1754 if (!bridge)
1755 goto err_out;
1756
1757 bridge->dev.parent = parent;
Jiang Liu70efde22013-06-07 16:16:51 -06001758 bridge->dev.release = pci_release_host_bridge_dev;
Yinghai Lu7b543662012-04-02 18:31:53 -07001759 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
Rafael J. Wysocki6c0cc952013-01-09 22:33:37 +01001760 error = pcibios_root_bridge_prepare(bridge);
Jiang Liu343df772013-06-07 01:10:08 +08001761 if (error) {
1762 kfree(bridge);
1763 goto err_out;
1764 }
Rafael J. Wysocki6c0cc952013-01-09 22:33:37 +01001765
Yinghai Lu7b543662012-04-02 18:31:53 -07001766 error = device_register(&bridge->dev);
Jiang Liu343df772013-06-07 01:10:08 +08001767 if (error) {
1768 put_device(&bridge->dev);
1769 goto err_out;
1770 }
Yinghai Lu7b543662012-04-02 18:31:53 -07001771 b->bridge = get_device(&bridge->dev);
Rafael J. Wysockia1e4d722010-02-08 19:16:33 +01001772 device_enable_async_suspend(b->bridge);
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +10001773 pci_set_bus_of_node(b);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001774
Yinghai Lu0d358f22008-02-19 03:20:41 -08001775 if (!parent)
1776 set_dev_node(b->bridge, pcibus_to_node(b));
1777
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -04001778 b->dev.class = &pcibus_class;
1779 b->dev.parent = b->bridge;
Kay Sievers1a927132008-10-30 02:17:49 +01001780 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -04001781 error = device_register(&b->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001782 if (error)
1783 goto class_dev_reg_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001784
Jiang Liu10a95742013-04-12 05:44:20 +00001785 pcibios_add_bus(b);
1786
Linus Torvalds1da177e2005-04-16 15:20:36 -07001787 /* Create legacy_io and legacy_mem files for this bus */
1788 pci_create_legacy_files(b);
1789
Bjorn Helgaasa9d9f522011-10-28 16:25:40 -06001790 if (parent)
1791 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
1792 else
1793 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
1794
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07001795 /* Add initial resources to the bus */
1796 list_for_each_entry_safe(window, n, resources, list) {
1797 list_move_tail(&window->list, &bridge->windows);
1798 res = window->res;
1799 offset = window->offset;
Yinghai Luf848ffb2012-05-17 18:51:12 -07001800 if (res->flags & IORESOURCE_BUS)
1801 pci_bus_insert_busn_res(b, bus, res->end);
1802 else
1803 pci_bus_add_resource(b, res, 0);
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07001804 if (offset) {
1805 if (resource_type(res) == IORESOURCE_IO)
1806 fmt = " (bus address [%#06llx-%#06llx])";
1807 else
1808 fmt = " (bus address [%#010llx-%#010llx])";
1809 snprintf(bus_addr, sizeof(bus_addr), fmt,
1810 (unsigned long long) (res->start - offset),
1811 (unsigned long long) (res->end - offset));
1812 } else
1813 bus_addr[0] = '\0';
1814 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
Bjorn Helgaasa9d9f522011-10-28 16:25:40 -06001815 }
1816
Bjorn Helgaasa5390aa2012-02-23 20:18:59 -07001817 down_write(&pci_bus_sem);
1818 list_add_tail(&b->node, &pci_root_buses);
1819 up_write(&pci_bus_sem);
1820
Linus Torvalds1da177e2005-04-16 15:20:36 -07001821 return b;
1822
Linus Torvalds1da177e2005-04-16 15:20:36 -07001823class_dev_reg_err:
Yinghai Lu7b543662012-04-02 18:31:53 -07001824 put_device(&bridge->dev);
1825 device_unregister(&bridge->dev);
Yinghai Lu7b543662012-04-02 18:31:53 -07001826err_out:
1827 kfree(b);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001828 return NULL;
1829}
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001830
Yinghai Lu98a35832012-05-18 11:35:50 -06001831int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
1832{
1833 struct resource *res = &b->busn_res;
1834 struct resource *parent_res, *conflict;
1835
1836 res->start = bus;
1837 res->end = bus_max;
1838 res->flags = IORESOURCE_BUS;
1839
1840 if (!pci_is_root_bus(b))
1841 parent_res = &b->parent->busn_res;
1842 else {
1843 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
1844 res->flags |= IORESOURCE_PCI_FIXED;
1845 }
1846
1847 conflict = insert_resource_conflict(parent_res, res);
1848
1849 if (conflict)
1850 dev_printk(KERN_DEBUG, &b->dev,
1851 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
1852 res, pci_is_root_bus(b) ? "domain " : "",
1853 parent_res, conflict->name, conflict);
Yinghai Lu98a35832012-05-18 11:35:50 -06001854
1855 return conflict == NULL;
1856}
1857
1858int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
1859{
1860 struct resource *res = &b->busn_res;
1861 struct resource old_res = *res;
1862 resource_size_t size;
1863 int ret;
1864
1865 if (res->start > bus_max)
1866 return -EINVAL;
1867
1868 size = bus_max - res->start + 1;
1869 ret = adjust_resource(res, res->start, size);
1870 dev_printk(KERN_DEBUG, &b->dev,
1871 "busn_res: %pR end %s updated to %02x\n",
1872 &old_res, ret ? "can not be" : "is", bus_max);
1873
1874 if (!ret && !res->parent)
1875 pci_bus_insert_busn_res(b, res->start, res->end);
1876
1877 return ret;
1878}
1879
1880void pci_bus_release_busn_res(struct pci_bus *b)
1881{
1882 struct resource *res = &b->busn_res;
1883 int ret;
1884
1885 if (!res->flags || !res->parent)
1886 return;
1887
1888 ret = release_resource(res);
1889 dev_printk(KERN_DEBUG, &b->dev,
1890 "busn_res: %pR %s released\n",
1891 res, ret ? "can not be" : "is");
1892}
1893
Bill Pemberton15856ad2012-11-21 15:35:00 -05001894struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
Bjorn Helgaasa2ebb822011-10-28 16:25:50 -06001895 struct pci_ops *ops, void *sysdata, struct list_head *resources)
1896{
Yinghai Lu4d99f522012-05-17 18:51:12 -07001897 struct pci_host_bridge_window *window;
1898 bool found = false;
Bjorn Helgaasa2ebb822011-10-28 16:25:50 -06001899 struct pci_bus *b;
Yinghai Lu4d99f522012-05-17 18:51:12 -07001900 int max;
1901
1902 list_for_each_entry(window, resources, list)
1903 if (window->res->flags & IORESOURCE_BUS) {
1904 found = true;
1905 break;
1906 }
Bjorn Helgaasa2ebb822011-10-28 16:25:50 -06001907
1908 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
1909 if (!b)
1910 return NULL;
1911
Yinghai Lu4d99f522012-05-17 18:51:12 -07001912 if (!found) {
1913 dev_info(&b->dev,
1914 "No busn resource found for root bus, will use [bus %02x-ff]\n",
1915 bus);
1916 pci_bus_insert_busn_res(b, bus, 255);
1917 }
1918
1919 max = pci_scan_child_bus(b);
1920
1921 if (!found)
1922 pci_bus_update_busn_res_end(b, max);
1923
Bjorn Helgaasa2ebb822011-10-28 16:25:50 -06001924 pci_bus_add_devices(b);
1925 return b;
1926}
1927EXPORT_SYMBOL(pci_scan_root_bus);
1928
Bjorn Helgaas7e00fe22011-10-28 16:26:05 -06001929/* Deprecated; use pci_scan_root_bus() instead */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001930struct pci_bus *pci_scan_bus_parented(struct device *parent,
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001931 int bus, struct pci_ops *ops, void *sysdata)
1932{
Bjorn Helgaas1e39ae92011-10-28 16:26:00 -06001933 LIST_HEAD(resources);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001934 struct pci_bus *b;
1935
Bjorn Helgaas1e39ae92011-10-28 16:26:00 -06001936 pci_add_resource(&resources, &ioport_resource);
1937 pci_add_resource(&resources, &iomem_resource);
Yinghai Lu857c3b62012-05-17 18:51:12 -07001938 pci_add_resource(&resources, &busn_resource);
Bjorn Helgaas1e39ae92011-10-28 16:26:00 -06001939 b = pci_create_root_bus(parent, bus, ops, sysdata, &resources);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001940 if (b)
Yinghai Lu857c3b62012-05-17 18:51:12 -07001941 pci_scan_child_bus(b);
Bjorn Helgaas1e39ae92011-10-28 16:26:00 -06001942 else
1943 pci_free_resource_list(&resources);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001944 return b;
1945}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001946EXPORT_SYMBOL(pci_scan_bus_parented);
1947
Bill Pemberton15856ad2012-11-21 15:35:00 -05001948struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
Bjorn Helgaasde4b2f72011-10-28 16:25:55 -06001949 void *sysdata)
1950{
1951 LIST_HEAD(resources);
1952 struct pci_bus *b;
1953
1954 pci_add_resource(&resources, &ioport_resource);
1955 pci_add_resource(&resources, &iomem_resource);
Yinghai Lu857c3b62012-05-17 18:51:12 -07001956 pci_add_resource(&resources, &busn_resource);
Bjorn Helgaasde4b2f72011-10-28 16:25:55 -06001957 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
1958 if (b) {
Yinghai Lu857c3b62012-05-17 18:51:12 -07001959 pci_scan_child_bus(b);
Bjorn Helgaasde4b2f72011-10-28 16:25:55 -06001960 pci_bus_add_devices(b);
1961 } else {
1962 pci_free_resource_list(&resources);
1963 }
1964 return b;
1965}
1966EXPORT_SYMBOL(pci_scan_bus);
1967
Alex Chiang3ed4fd92009-03-20 14:56:25 -06001968/**
Yinghai Lu2f320522012-01-21 02:08:22 -08001969 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
1970 * @bridge: PCI bridge for the bus to scan
1971 *
1972 * Scan a PCI bus and child buses for new devices, add them,
1973 * and enable them, resizing bridge mmio/io resource if necessary
1974 * and possible. The caller must ensure the child devices are already
1975 * removed for resizing to occur.
1976 *
1977 * Returns the max number of subordinate bus discovered.
1978 */
1979unsigned int __ref pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
1980{
1981 unsigned int max;
1982 struct pci_bus *bus = bridge->subordinate;
1983
1984 max = pci_scan_child_bus(bus);
1985
1986 pci_assign_unassigned_bridge_resources(bridge);
1987
1988 pci_bus_add_devices(bus);
1989
1990 return max;
1991}
1992
Yinghai Lua5213a32012-10-30 14:31:21 -06001993/**
1994 * pci_rescan_bus - scan a PCI bus for devices.
1995 * @bus: PCI bus to scan
1996 *
1997 * Scan a PCI bus and child buses for new devices, adds them,
1998 * and enables them.
1999 *
2000 * Returns the max number of subordinate bus discovered.
2001 */
2002unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
2003{
2004 unsigned int max;
2005
2006 max = pci_scan_child_bus(bus);
2007 pci_assign_unassigned_bus_resources(bus);
2008 pci_bus_add_devices(bus);
2009
2010 return max;
2011}
2012EXPORT_SYMBOL_GPL(pci_rescan_bus);
2013
Linus Torvalds1da177e2005-04-16 15:20:36 -07002014EXPORT_SYMBOL(pci_add_new_bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002015EXPORT_SYMBOL(pci_scan_slot);
2016EXPORT_SYMBOL(pci_scan_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002017EXPORT_SYMBOL_GPL(pci_scan_child_bus);
Matt Domsch6b4b78f2006-09-29 15:23:23 -05002018
Greg Kroah-Hartman99178b02008-08-26 11:00:57 -05002019static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
Matt Domsch6b4b78f2006-09-29 15:23:23 -05002020{
Greg Kroah-Hartman99178b02008-08-26 11:00:57 -05002021 const struct pci_dev *a = to_pci_dev(d_a);
2022 const struct pci_dev *b = to_pci_dev(d_b);
2023
Matt Domsch6b4b78f2006-09-29 15:23:23 -05002024 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2025 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2026
2027 if (a->bus->number < b->bus->number) return -1;
2028 else if (a->bus->number > b->bus->number) return 1;
2029
2030 if (a->devfn < b->devfn) return -1;
2031 else if (a->devfn > b->devfn) return 1;
2032
2033 return 0;
2034}
2035
Greg Kroah-Hartman5ff580c2008-02-14 14:56:56 -08002036void __init pci_sort_breadthfirst(void)
Matt Domsch6b4b78f2006-09-29 15:23:23 -05002037{
Greg Kroah-Hartman99178b02008-08-26 11:00:57 -05002038 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
Matt Domsch6b4b78f2006-09-29 15:23:23 -05002039}