Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 1 | /* |
Paul Walmsley | a64bb9c | 2010-12-21 21:05:14 -0700 | [diff] [blame^] | 2 | * OMAP2/3/4 powerdomain control |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 3 | * |
Paul Walmsley | 55ed969 | 2010-01-26 20:12:59 -0700 | [diff] [blame] | 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. |
Paul Walmsley | 6e01478 | 2010-12-21 20:01:20 -0700 | [diff] [blame] | 5 | * Copyright (C) 2007-2010 Nokia Corporation |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 6 | * |
| 7 | * Written by Paul Walmsley |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
Paul Walmsley | 6e01478 | 2010-12-21 20:01:20 -0700 | [diff] [blame] | 12 | * |
| 13 | * XXX This should be moved to the mach-omap2/ directory at the earliest |
| 14 | * opportunity. |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 15 | */ |
| 16 | |
Paul Walmsley | 6e01478 | 2010-12-21 20:01:20 -0700 | [diff] [blame] | 17 | #ifndef ASM_ARM_PLAT_OMAP_INCLUDE_PLAT_POWERDOMAIN |
| 18 | #define ASM_ARM_PLAT_OMAP_INCLUDE_PLAT_POWERDOMAIN |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 19 | |
| 20 | #include <linux/types.h> |
| 21 | #include <linux/list.h> |
| 22 | |
| 23 | #include <asm/atomic.h> |
| 24 | |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 25 | #include <plat/cpu.h> |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 26 | |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 27 | /* Powerdomain basic power states */ |
| 28 | #define PWRDM_POWER_OFF 0x0 |
| 29 | #define PWRDM_POWER_RET 0x1 |
| 30 | #define PWRDM_POWER_INACTIVE 0x2 |
| 31 | #define PWRDM_POWER_ON 0x3 |
| 32 | |
Paul Walmsley | 2354eb5 | 2009-12-08 16:33:12 -0700 | [diff] [blame] | 33 | #define PWRDM_MAX_PWRSTS 4 |
| 34 | |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 35 | /* Powerdomain allowable state bitfields */ |
Rajendra Nayak | d3353e1 | 2010-05-18 20:24:01 -0600 | [diff] [blame] | 36 | #define PWRSTS_ON (1 << PWRDM_POWER_ON) |
Rajendra Nayak | bb722f3 | 2010-09-27 14:02:56 -0600 | [diff] [blame] | 37 | #define PWRSTS_OFF (1 << PWRDM_POWER_OFF) |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 38 | #define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ |
| 39 | (1 << PWRDM_POWER_ON)) |
| 40 | |
| 41 | #define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \ |
| 42 | (1 << PWRDM_POWER_RET)) |
| 43 | |
Abhijit Pagare | f37c6df | 2010-01-26 20:12:52 -0700 | [diff] [blame] | 44 | #define PWRSTS_RET_ON ((1 << PWRDM_POWER_RET) | \ |
| 45 | (1 << PWRDM_POWER_ON)) |
| 46 | |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 47 | #define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON)) |
| 48 | |
| 49 | |
Paul Walmsley | 0b7cbfb | 2008-06-25 18:09:37 -0600 | [diff] [blame] | 50 | /* Powerdomain flags */ |
| 51 | #define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */ |
Thara Gopinath | 3863c74 | 2009-12-08 16:33:15 -0700 | [diff] [blame] | 52 | #define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits |
| 53 | * in MEM bank 1 position. This is |
| 54 | * true for OMAP3430 |
| 55 | */ |
Rajendra Nayak | 90dbc7b | 2010-05-18 20:24:03 -0600 | [diff] [blame] | 56 | #define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /* |
| 57 | * support to transition from a |
| 58 | * sleep state to a lower sleep |
| 59 | * state without waking up the |
| 60 | * powerdomain |
| 61 | */ |
Paul Walmsley | 0b7cbfb | 2008-06-25 18:09:37 -0600 | [diff] [blame] | 62 | |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 63 | /* |
Abhijit Pagare | 38900c2 | 2010-01-26 20:12:52 -0700 | [diff] [blame] | 64 | * Number of memory banks that are power-controllable. On OMAP4430, the |
| 65 | * maximum is 5. |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 66 | */ |
Abhijit Pagare | 38900c2 | 2010-01-26 20:12:52 -0700 | [diff] [blame] | 67 | #define PWRDM_MAX_MEM_BANKS 5 |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 68 | |
Paul Walmsley | 8420bb1 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 69 | /* |
| 70 | * Maximum number of clockdomains that can be associated with a powerdomain. |
Abhijit Pagare | 38900c2 | 2010-01-26 20:12:52 -0700 | [diff] [blame] | 71 | * CORE powerdomain on OMAP4 is the worst case |
Paul Walmsley | 8420bb1 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 72 | */ |
Abhijit Pagare | 38900c2 | 2010-01-26 20:12:52 -0700 | [diff] [blame] | 73 | #define PWRDM_MAX_CLKDMS 9 |
Paul Walmsley | 8420bb1 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 74 | |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 75 | /* XXX A completely arbitrary number. What is reasonable here? */ |
| 76 | #define PWRDM_TRANSITION_BAILOUT 100000 |
| 77 | |
Paul Walmsley | 8420bb1 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 78 | struct clockdomain; |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 79 | struct powerdomain; |
| 80 | |
Paul Walmsley | f0271d6 | 2010-01-26 20:13:02 -0700 | [diff] [blame] | 81 | /** |
| 82 | * struct powerdomain - OMAP powerdomain |
| 83 | * @name: Powerdomain name |
| 84 | * @omap_chip: represents the OMAP chip types containing this pwrdm |
| 85 | * @prcm_offs: the address offset from CM_BASE/PRM_BASE |
Paul Walmsley | a64bb9c | 2010-12-21 21:05:14 -0700 | [diff] [blame^] | 86 | * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs |
Paul Walmsley | f0271d6 | 2010-01-26 20:13:02 -0700 | [diff] [blame] | 87 | * @pwrsts: Possible powerdomain power states |
| 88 | * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION |
| 89 | * @flags: Powerdomain flags |
| 90 | * @banks: Number of software-controllable memory banks in this powerdomain |
| 91 | * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION |
| 92 | * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON |
| 93 | * @pwrdm_clkdms: Clockdomains in this powerdomain |
| 94 | * @node: list_head linking all powerdomains |
| 95 | * @state: |
| 96 | * @state_counter: |
| 97 | * @timer: |
| 98 | * @state_timer: |
Paul Walmsley | a64bb9c | 2010-12-21 21:05:14 -0700 | [diff] [blame^] | 99 | * |
| 100 | * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h. |
Paul Walmsley | f0271d6 | 2010-01-26 20:13:02 -0700 | [diff] [blame] | 101 | */ |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 102 | struct powerdomain { |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 103 | const char *name; |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 104 | const struct omap_chip_id omap_chip; |
Paul Walmsley | e0594b4 | 2010-01-26 20:13:01 -0700 | [diff] [blame] | 105 | const s16 prcm_offs; |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 106 | const u8 pwrsts; |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 107 | const u8 pwrsts_logic_ret; |
Paul Walmsley | 0b7cbfb | 2008-06-25 18:09:37 -0600 | [diff] [blame] | 108 | const u8 flags; |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 109 | const u8 banks; |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 110 | const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS]; |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 111 | const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS]; |
Paul Walmsley | a64bb9c | 2010-12-21 21:05:14 -0700 | [diff] [blame^] | 112 | const u8 prcm_partition; |
Paul Walmsley | 8420bb1 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 113 | struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS]; |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 114 | struct list_head node; |
Peter 'p2' De Schrijver | ba20bb1 | 2008-10-15 17:48:43 +0300 | [diff] [blame] | 115 | int state; |
Paul Walmsley | 2354eb5 | 2009-12-08 16:33:12 -0700 | [diff] [blame] | 116 | unsigned state_counter[PWRDM_MAX_PWRSTS]; |
Thara Gopinath | cde08f8 | 2010-02-24 12:05:50 -0700 | [diff] [blame] | 117 | unsigned ret_logic_off_counter; |
| 118 | unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; |
Peter 'p2' De Schrijver | 331b93f | 2008-10-15 18:13:48 +0300 | [diff] [blame] | 119 | |
| 120 | #ifdef CONFIG_PM_DEBUG |
| 121 | s64 timer; |
Paul Walmsley | 2354eb5 | 2009-12-08 16:33:12 -0700 | [diff] [blame] | 122 | s64 state_timer[PWRDM_MAX_PWRSTS]; |
Peter 'p2' De Schrijver | 331b93f | 2008-10-15 18:13:48 +0300 | [diff] [blame] | 123 | #endif |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 124 | }; |
| 125 | |
Rajendra Nayak | 3b1e8b2 | 2010-12-21 20:01:18 -0700 | [diff] [blame] | 126 | /** |
| 127 | * struct pwrdm_ops - Arch specfic function implementations |
| 128 | * @pwrdm_set_next_pwrst: Set the target power state for a pd |
| 129 | * @pwrdm_read_next_pwrst: Read the target power state set for a pd |
| 130 | * @pwrdm_read_pwrst: Read the current power state of a pd |
| 131 | * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd |
| 132 | * @pwrdm_set_logic_retst: Set the logic state in RET for a pd |
| 133 | * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd |
| 134 | * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd |
| 135 | * @pwrdm_read_logic_pwrst: Read the current logic state of a pd |
| 136 | * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd |
| 137 | * @pwrdm_read_logic_retst: Read the logic state in RET for a pd |
| 138 | * @pwrdm_read_mem_pwrst: Read the current memory state of a pd |
| 139 | * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd |
| 140 | * @pwrdm_read_mem_retst: Read the memory state in RET for a pd |
| 141 | * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd |
| 142 | * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd |
| 143 | * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd |
| 144 | * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep |
| 145 | * @pwrdm_wait_transition: Wait for a pd state transition to complete |
| 146 | */ |
| 147 | struct pwrdm_ops { |
| 148 | int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst); |
| 149 | int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm); |
| 150 | int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm); |
| 151 | int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm); |
| 152 | int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst); |
| 153 | int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); |
| 154 | int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); |
| 155 | int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm); |
| 156 | int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm); |
| 157 | int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm); |
| 158 | int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); |
| 159 | int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); |
| 160 | int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank); |
| 161 | int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm); |
| 162 | int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm); |
| 163 | int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm); |
| 164 | int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm); |
| 165 | int (*pwrdm_wait_transition)(struct powerdomain *pwrdm); |
| 166 | }; |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 167 | |
Rajendra Nayak | 74bea6b | 2010-12-21 20:01:17 -0700 | [diff] [blame] | 168 | void pwrdm_fw_init(void); |
Rajendra Nayak | 3b1e8b2 | 2010-12-21 20:01:18 -0700 | [diff] [blame] | 169 | void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs); |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 170 | |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 171 | struct powerdomain *pwrdm_lookup(const char *name); |
| 172 | |
Peter 'p2' De Schrijver | a23456e | 2008-10-15 18:13:47 +0300 | [diff] [blame] | 173 | int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), |
| 174 | void *user); |
Artem Bityutskiy | ee894b1 | 2009-10-01 10:01:55 +0300 | [diff] [blame] | 175 | int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user), |
| 176 | void *user); |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 177 | |
Paul Walmsley | 8420bb1 | 2008-08-19 11:08:44 +0300 | [diff] [blame] | 178 | int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); |
| 179 | int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); |
| 180 | int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, |
| 181 | int (*fn)(struct powerdomain *pwrdm, |
| 182 | struct clockdomain *clkdm)); |
| 183 | |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 184 | int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); |
| 185 | |
| 186 | int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); |
| 187 | int pwrdm_read_next_pwrst(struct powerdomain *pwrdm); |
Paul Walmsley | fecb494 | 2009-01-27 19:12:50 -0700 | [diff] [blame] | 188 | int pwrdm_read_pwrst(struct powerdomain *pwrdm); |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 189 | int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm); |
| 190 | int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm); |
| 191 | |
| 192 | int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst); |
| 193 | int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); |
| 194 | int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); |
| 195 | |
| 196 | int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm); |
| 197 | int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm); |
Thara Gopinath | 1e3d0d2 | 2010-02-24 12:05:49 -0700 | [diff] [blame] | 198 | int pwrdm_read_logic_retst(struct powerdomain *pwrdm); |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 199 | int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank); |
| 200 | int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank); |
Thara Gopinath | 1e3d0d2 | 2010-02-24 12:05:49 -0700 | [diff] [blame] | 201 | int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank); |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 202 | |
Paul Walmsley | 0b7cbfb | 2008-06-25 18:09:37 -0600 | [diff] [blame] | 203 | int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm); |
| 204 | int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm); |
| 205 | bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm); |
| 206 | |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 207 | int pwrdm_wait_transition(struct powerdomain *pwrdm); |
| 208 | |
Peter 'p2' De Schrijver | ba20bb1 | 2008-10-15 17:48:43 +0300 | [diff] [blame] | 209 | int pwrdm_state_switch(struct powerdomain *pwrdm); |
| 210 | int pwrdm_clkdm_state_switch(struct clockdomain *clkdm); |
| 211 | int pwrdm_pre_transition(void); |
| 212 | int pwrdm_post_transition(void); |
Manjunath Kondaiah G | 04aeae7 | 2010-10-08 09:58:35 -0700 | [diff] [blame] | 213 | int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm); |
Peter 'p2' De Schrijver | ba20bb1 | 2008-10-15 17:48:43 +0300 | [diff] [blame] | 214 | |
Paul Walmsley | 6e01478 | 2010-12-21 20:01:20 -0700 | [diff] [blame] | 215 | extern void omap2xxx_powerdomains_init(void); |
| 216 | extern void omap3xxx_powerdomains_init(void); |
| 217 | extern void omap44xx_powerdomains_init(void); |
| 218 | |
Paul Walmsley | ad67ef6 | 2008-08-19 11:08:40 +0300 | [diff] [blame] | 219 | #endif |