blob: 5b2c88ca6edbee20f094cf6204f98fe49f6b6389 [file] [log] [blame]
Eric Anholt7d573822009-01-02 13:33:00 -08001/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29#include <linux/i2c.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090030#include <linux/slab.h>
Eric Anholt7d573822009-01-02 13:33:00 -080031#include <linux/delay.h>
32#include "drmP.h"
33#include "drm.h"
34#include "drm_crtc.h"
Keith Packardaa93d632009-05-05 09:52:46 -070035#include "drm_edid.h"
Eric Anholt7d573822009-01-02 13:33:00 -080036#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
39
Daniel Vetterafba0182012-06-12 16:36:45 +020040static void
41assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
42{
43 struct drm_device *dev = intel_hdmi->base.base.dev;
44 struct drm_i915_private *dev_priv = dev->dev_private;
45 uint32_t enabled_bits;
46
47 enabled_bits = IS_HASWELL(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
48
49 WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits,
50 "HDMI port enabled, expecting disabled\n");
51}
52
Eugeni Dodonovf5bbfca2012-05-09 15:37:30 -030053struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
Chris Wilsonea5b2132010-08-04 13:50:23 +010054{
Chris Wilson4ef69c72010-09-09 15:14:28 +010055 return container_of(encoder, struct intel_hdmi, base.base);
Chris Wilsonea5b2132010-08-04 13:50:23 +010056}
57
Chris Wilsondf0e9242010-09-09 16:20:55 +010058static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
59{
60 return container_of(intel_attached_encoder(connector),
61 struct intel_hdmi, base);
62}
63
Jesse Barnes45187ac2011-08-03 09:22:55 -070064void intel_dip_infoframe_csum(struct dip_infoframe *frame)
David Härdeman3c17fe42010-09-24 21:44:32 +020065{
Jesse Barnes45187ac2011-08-03 09:22:55 -070066 uint8_t *data = (uint8_t *)frame;
David Härdeman3c17fe42010-09-24 21:44:32 +020067 uint8_t sum = 0;
68 unsigned i;
69
Jesse Barnes45187ac2011-08-03 09:22:55 -070070 frame->checksum = 0;
71 frame->ecc = 0;
David Härdeman3c17fe42010-09-24 21:44:32 +020072
Jesse Barnes64a8fc02011-09-22 11:16:00 +053073 for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
David Härdeman3c17fe42010-09-24 21:44:32 +020074 sum += data[i];
75
Jesse Barnes45187ac2011-08-03 09:22:55 -070076 frame->checksum = 0x100 - sum;
David Härdeman3c17fe42010-09-24 21:44:32 +020077}
78
Daniel Vetterbc2481f2012-05-08 15:18:32 +020079static u32 g4x_infoframe_index(struct dip_infoframe *frame)
David Härdeman3c17fe42010-09-24 21:44:32 +020080{
Jesse Barnes45187ac2011-08-03 09:22:55 -070081 switch (frame->type) {
82 case DIP_TYPE_AVI:
Paulo Zanonied517fb2012-05-14 17:12:50 -030083 return VIDEO_DIP_SELECT_AVI;
Jesse Barnes45187ac2011-08-03 09:22:55 -070084 case DIP_TYPE_SPD:
Paulo Zanonied517fb2012-05-14 17:12:50 -030085 return VIDEO_DIP_SELECT_SPD;
Jesse Barnes45187ac2011-08-03 09:22:55 -070086 default:
87 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
Paulo Zanonied517fb2012-05-14 17:12:50 -030088 return 0;
Jesse Barnes45187ac2011-08-03 09:22:55 -070089 }
Jesse Barnes45187ac2011-08-03 09:22:55 -070090}
91
Daniel Vetterbc2481f2012-05-08 15:18:32 +020092static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
Jesse Barnes45187ac2011-08-03 09:22:55 -070093{
Jesse Barnes45187ac2011-08-03 09:22:55 -070094 switch (frame->type) {
95 case DIP_TYPE_AVI:
Paulo Zanonied517fb2012-05-14 17:12:50 -030096 return VIDEO_DIP_ENABLE_AVI;
Jesse Barnes45187ac2011-08-03 09:22:55 -070097 case DIP_TYPE_SPD:
Paulo Zanonied517fb2012-05-14 17:12:50 -030098 return VIDEO_DIP_ENABLE_SPD;
Paulo Zanonifa193ff2012-05-04 17:18:20 -030099 default:
100 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
Paulo Zanonied517fb2012-05-14 17:12:50 -0300101 return 0;
Paulo Zanonifa193ff2012-05-04 17:18:20 -0300102 }
Paulo Zanonifa193ff2012-05-04 17:18:20 -0300103}
104
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300105static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
106{
107 switch (frame->type) {
108 case DIP_TYPE_AVI:
109 return VIDEO_DIP_ENABLE_AVI_HSW;
110 case DIP_TYPE_SPD:
111 return VIDEO_DIP_ENABLE_SPD_HSW;
112 default:
113 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
114 return 0;
115 }
116}
117
118static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe)
119{
120 switch (frame->type) {
121 case DIP_TYPE_AVI:
122 return HSW_TVIDEO_DIP_AVI_DATA(pipe);
123 case DIP_TYPE_SPD:
124 return HSW_TVIDEO_DIP_SPD_DATA(pipe);
125 default:
126 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
127 return 0;
128 }
129}
130
Daniel Vettera3da1df2012-05-08 15:19:06 +0200131static void g4x_write_infoframe(struct drm_encoder *encoder,
132 struct dip_infoframe *frame)
Jesse Barnes45187ac2011-08-03 09:22:55 -0700133{
134 uint32_t *data = (uint32_t *)frame;
David Härdeman3c17fe42010-09-24 21:44:32 +0200135 struct drm_device *dev = encoder->dev;
136 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300137 u32 val = I915_READ(VIDEO_DIP_CTL);
Jesse Barnes45187ac2011-08-03 09:22:55 -0700138 unsigned i, len = DIP_HEADER_SIZE + frame->len;
David Härdeman3c17fe42010-09-24 21:44:32 +0200139
Paulo Zanoni822974a2012-05-28 16:42:51 -0300140 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
141
Paulo Zanoni1d4f85a2012-05-04 17:18:18 -0300142 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
Daniel Vetterbc2481f2012-05-08 15:18:32 +0200143 val |= g4x_infoframe_index(frame);
Jesse Barnes45187ac2011-08-03 09:22:55 -0700144
Daniel Vetterbc2481f2012-05-08 15:18:32 +0200145 val &= ~g4x_infoframe_enable(frame);
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300146
147 I915_WRITE(VIDEO_DIP_CTL, val);
Jesse Barnes45187ac2011-08-03 09:22:55 -0700148
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300149 mmiowb();
Jesse Barnes45187ac2011-08-03 09:22:55 -0700150 for (i = 0; i < len; i += 4) {
David Härdeman3c17fe42010-09-24 21:44:32 +0200151 I915_WRITE(VIDEO_DIP_DATA, *data);
152 data++;
153 }
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300154 mmiowb();
David Härdeman3c17fe42010-09-24 21:44:32 +0200155
Daniel Vetterbc2481f2012-05-08 15:18:32 +0200156 val |= g4x_infoframe_enable(frame);
Paulo Zanoni60c5ea22012-05-04 17:18:22 -0300157 val &= ~VIDEO_DIP_FREQ_MASK;
Daniel Vetter4b24c932012-05-08 14:41:00 +0200158 val |= VIDEO_DIP_FREQ_VSYNC;
Jesse Barnes45187ac2011-08-03 09:22:55 -0700159
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300160 I915_WRITE(VIDEO_DIP_CTL, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300161 POSTING_READ(VIDEO_DIP_CTL);
David Härdeman3c17fe42010-09-24 21:44:32 +0200162}
163
Paulo Zanonifdf12502012-05-04 17:18:24 -0300164static void ibx_write_infoframe(struct drm_encoder *encoder,
165 struct dip_infoframe *frame)
166{
167 uint32_t *data = (uint32_t *)frame;
168 struct drm_device *dev = encoder->dev;
169 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonied517fb2012-05-14 17:12:50 -0300170 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
Paulo Zanonifdf12502012-05-04 17:18:24 -0300171 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
172 unsigned i, len = DIP_HEADER_SIZE + frame->len;
173 u32 val = I915_READ(reg);
174
Paulo Zanoni822974a2012-05-28 16:42:51 -0300175 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
176
Paulo Zanonifdf12502012-05-04 17:18:24 -0300177 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
Daniel Vetterbc2481f2012-05-08 15:18:32 +0200178 val |= g4x_infoframe_index(frame);
Paulo Zanonifdf12502012-05-04 17:18:24 -0300179
Daniel Vetterbc2481f2012-05-08 15:18:32 +0200180 val &= ~g4x_infoframe_enable(frame);
Paulo Zanonifdf12502012-05-04 17:18:24 -0300181
182 I915_WRITE(reg, val);
183
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300184 mmiowb();
Paulo Zanonifdf12502012-05-04 17:18:24 -0300185 for (i = 0; i < len; i += 4) {
186 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
187 data++;
188 }
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300189 mmiowb();
Paulo Zanonifdf12502012-05-04 17:18:24 -0300190
Daniel Vetterbc2481f2012-05-08 15:18:32 +0200191 val |= g4x_infoframe_enable(frame);
Paulo Zanonifdf12502012-05-04 17:18:24 -0300192 val &= ~VIDEO_DIP_FREQ_MASK;
Daniel Vetter4b24c932012-05-08 14:41:00 +0200193 val |= VIDEO_DIP_FREQ_VSYNC;
Paulo Zanonifdf12502012-05-04 17:18:24 -0300194
195 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300196 POSTING_READ(reg);
Paulo Zanonifdf12502012-05-04 17:18:24 -0300197}
198
199static void cpt_write_infoframe(struct drm_encoder *encoder,
200 struct dip_infoframe *frame)
Jesse Barnes45187ac2011-08-03 09:22:55 -0700201{
202 uint32_t *data = (uint32_t *)frame;
203 struct drm_device *dev = encoder->dev;
204 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonied517fb2012-05-14 17:12:50 -0300205 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
Jesse Barnes45187ac2011-08-03 09:22:55 -0700206 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
207 unsigned i, len = DIP_HEADER_SIZE + frame->len;
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300208 u32 val = I915_READ(reg);
Jesse Barnes45187ac2011-08-03 09:22:55 -0700209
Paulo Zanoni822974a2012-05-28 16:42:51 -0300210 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
211
Jesse Barnes64a8fc02011-09-22 11:16:00 +0530212 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
Daniel Vetterbc2481f2012-05-08 15:18:32 +0200213 val |= g4x_infoframe_index(frame);
Jesse Barnes45187ac2011-08-03 09:22:55 -0700214
Paulo Zanoniecb97852012-05-04 17:18:21 -0300215 /* The DIP control register spec says that we need to update the AVI
216 * infoframe without clearing its enable bit */
Paulo Zanoni822974a2012-05-28 16:42:51 -0300217 if (frame->type != DIP_TYPE_AVI)
Daniel Vetterbc2481f2012-05-08 15:18:32 +0200218 val &= ~g4x_infoframe_enable(frame);
Paulo Zanoniecb97852012-05-04 17:18:21 -0300219
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300220 I915_WRITE(reg, val);
Jesse Barnes45187ac2011-08-03 09:22:55 -0700221
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300222 mmiowb();
Jesse Barnes45187ac2011-08-03 09:22:55 -0700223 for (i = 0; i < len; i += 4) {
224 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
225 data++;
226 }
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300227 mmiowb();
Jesse Barnes45187ac2011-08-03 09:22:55 -0700228
Daniel Vetterbc2481f2012-05-08 15:18:32 +0200229 val |= g4x_infoframe_enable(frame);
Paulo Zanoni60c5ea22012-05-04 17:18:22 -0300230 val &= ~VIDEO_DIP_FREQ_MASK;
Daniel Vetter4b24c932012-05-08 14:41:00 +0200231 val |= VIDEO_DIP_FREQ_VSYNC;
Jesse Barnes45187ac2011-08-03 09:22:55 -0700232
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300233 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300234 POSTING_READ(reg);
Jesse Barnes45187ac2011-08-03 09:22:55 -0700235}
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700236
237static void vlv_write_infoframe(struct drm_encoder *encoder,
238 struct dip_infoframe *frame)
239{
240 uint32_t *data = (uint32_t *)frame;
241 struct drm_device *dev = encoder->dev;
242 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonied517fb2012-05-14 17:12:50 -0300243 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700244 int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
245 unsigned i, len = DIP_HEADER_SIZE + frame->len;
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300246 u32 val = I915_READ(reg);
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700247
Paulo Zanoni822974a2012-05-28 16:42:51 -0300248 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
249
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700250 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
Daniel Vetterbc2481f2012-05-08 15:18:32 +0200251 val |= g4x_infoframe_index(frame);
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700252
Daniel Vetterbc2481f2012-05-08 15:18:32 +0200253 val &= ~g4x_infoframe_enable(frame);
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300254
255 I915_WRITE(reg, val);
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700256
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300257 mmiowb();
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700258 for (i = 0; i < len; i += 4) {
259 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
260 data++;
261 }
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300262 mmiowb();
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700263
Daniel Vetterbc2481f2012-05-08 15:18:32 +0200264 val |= g4x_infoframe_enable(frame);
Paulo Zanoni60c5ea22012-05-04 17:18:22 -0300265 val &= ~VIDEO_DIP_FREQ_MASK;
Daniel Vetter4b24c932012-05-08 14:41:00 +0200266 val |= VIDEO_DIP_FREQ_VSYNC;
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700267
Paulo Zanoni22509ec2012-05-04 17:18:17 -0300268 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300269 POSTING_READ(reg);
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700270}
271
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -0300272static void hsw_write_infoframe(struct drm_encoder *encoder,
Paulo Zanonied517fb2012-05-14 17:12:50 -0300273 struct dip_infoframe *frame)
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -0300274{
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300275 uint32_t *data = (uint32_t *)frame;
276 struct drm_device *dev = encoder->dev;
277 struct drm_i915_private *dev_priv = dev->dev_private;
278 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
279 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
280 u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe);
281 unsigned int i, len = DIP_HEADER_SIZE + frame->len;
282 u32 val = I915_READ(ctl_reg);
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -0300283
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300284 if (data_reg == 0)
285 return;
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -0300286
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300287 val &= ~hsw_infoframe_enable(frame);
288 I915_WRITE(ctl_reg, val);
289
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300290 mmiowb();
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300291 for (i = 0; i < len; i += 4) {
292 I915_WRITE(data_reg + i, *data);
293 data++;
294 }
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300295 mmiowb();
Paulo Zanoni2da8af52012-05-14 17:12:51 -0300296
297 val |= hsw_infoframe_enable(frame);
298 I915_WRITE(ctl_reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300299 POSTING_READ(ctl_reg);
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -0300300}
301
Jesse Barnes45187ac2011-08-03 09:22:55 -0700302static void intel_set_infoframe(struct drm_encoder *encoder,
303 struct dip_infoframe *frame)
304{
305 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
306
Jesse Barnes45187ac2011-08-03 09:22:55 -0700307 intel_dip_infoframe_csum(frame);
308 intel_hdmi->write_infoframe(encoder, frame);
309}
310
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300311static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
Paulo Zanonic846b612012-04-13 16:31:41 -0300312 struct drm_display_mode *adjusted_mode)
Jesse Barnesb055c8f2011-07-08 11:31:57 -0700313{
314 struct dip_infoframe avi_if = {
315 .type = DIP_TYPE_AVI,
316 .ver = DIP_VERSION_AVI,
317 .len = DIP_LEN_AVI,
318 };
Jesse Barnesb055c8f2011-07-08 11:31:57 -0700319
Paulo Zanonic846b612012-04-13 16:31:41 -0300320 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
321 avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
322
Jesse Barnes45187ac2011-08-03 09:22:55 -0700323 intel_set_infoframe(encoder, &avi_if);
Jesse Barnesb055c8f2011-07-08 11:31:57 -0700324}
325
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300326static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
Jesse Barnesc0864cb2011-08-03 09:22:56 -0700327{
328 struct dip_infoframe spd_if;
329
330 memset(&spd_if, 0, sizeof(spd_if));
331 spd_if.type = DIP_TYPE_SPD;
332 spd_if.ver = DIP_VERSION_SPD;
333 spd_if.len = DIP_LEN_SPD;
334 strcpy(spd_if.body.spd.vn, "Intel");
335 strcpy(spd_if.body.spd.pd, "Integrated gfx");
336 spd_if.body.spd.sdi = DIP_SPD_PC;
337
338 intel_set_infoframe(encoder, &spd_if);
339}
340
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300341static void g4x_set_infoframes(struct drm_encoder *encoder,
342 struct drm_display_mode *adjusted_mode)
343{
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300344 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
345 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
346 u32 reg = VIDEO_DIP_CTL;
347 u32 val = I915_READ(reg);
Paulo Zanoni72b78c92012-05-28 16:42:54 -0300348 u32 port;
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300349
Daniel Vetterafba0182012-06-12 16:36:45 +0200350 assert_hdmi_port_disabled(intel_hdmi);
351
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300352 /* If the registers were not initialized yet, they might be zeroes,
353 * which means we're selecting the AVI DIP and we're setting its
354 * frequency to once. This seems to really confuse the HW and make
355 * things stop working (the register spec says the AVI always needs to
356 * be sent every VSync). So here we avoid writing to the register more
357 * than we need and also explicitly select the AVI DIP and explicitly
358 * set its frequency to every VSync. Avoiding to write it twice seems to
359 * be enough to solve the problem, but being defensive shouldn't hurt us
360 * either. */
361 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
362
363 if (!intel_hdmi->has_hdmi_sink) {
364 if (!(val & VIDEO_DIP_ENABLE))
365 return;
366 val &= ~VIDEO_DIP_ENABLE;
367 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300368 POSTING_READ(reg);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300369 return;
370 }
371
Paulo Zanonif278d972012-05-28 16:42:50 -0300372 switch (intel_hdmi->sdvox_reg) {
373 case SDVOB:
Paulo Zanoni72b78c92012-05-28 16:42:54 -0300374 port = VIDEO_DIP_PORT_B;
Paulo Zanonif278d972012-05-28 16:42:50 -0300375 break;
376 case SDVOC:
Paulo Zanoni72b78c92012-05-28 16:42:54 -0300377 port = VIDEO_DIP_PORT_C;
Paulo Zanonif278d972012-05-28 16:42:50 -0300378 break;
379 default:
380 return;
381 }
382
Paulo Zanoni72b78c92012-05-28 16:42:54 -0300383 if (port != (val & VIDEO_DIP_PORT_MASK)) {
384 if (val & VIDEO_DIP_ENABLE) {
385 val &= ~VIDEO_DIP_ENABLE;
386 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300387 POSTING_READ(reg);
Paulo Zanoni72b78c92012-05-28 16:42:54 -0300388 }
389 val &= ~VIDEO_DIP_PORT_MASK;
390 val |= port;
391 }
392
Paulo Zanoni822974a2012-05-28 16:42:51 -0300393 val |= VIDEO_DIP_ENABLE;
Paulo Zanoni0dd87d22012-05-28 16:42:53 -0300394 val &= ~VIDEO_DIP_ENABLE_VENDOR;
Paulo Zanoni822974a2012-05-28 16:42:51 -0300395
Paulo Zanonif278d972012-05-28 16:42:50 -0300396 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300397 POSTING_READ(reg);
Paulo Zanonif278d972012-05-28 16:42:50 -0300398
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300399 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
400 intel_hdmi_set_spd_infoframe(encoder);
401}
402
403static void ibx_set_infoframes(struct drm_encoder *encoder,
404 struct drm_display_mode *adjusted_mode)
405{
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300406 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
407 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
408 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
409 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
410 u32 val = I915_READ(reg);
Paulo Zanoni72b78c92012-05-28 16:42:54 -0300411 u32 port;
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300412
Daniel Vetterafba0182012-06-12 16:36:45 +0200413 assert_hdmi_port_disabled(intel_hdmi);
414
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300415 /* See the big comment in g4x_set_infoframes() */
416 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
417
418 if (!intel_hdmi->has_hdmi_sink) {
419 if (!(val & VIDEO_DIP_ENABLE))
420 return;
421 val &= ~VIDEO_DIP_ENABLE;
422 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300423 POSTING_READ(reg);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300424 return;
425 }
426
Paulo Zanonif278d972012-05-28 16:42:50 -0300427 switch (intel_hdmi->sdvox_reg) {
428 case HDMIB:
Paulo Zanoni72b78c92012-05-28 16:42:54 -0300429 port = VIDEO_DIP_PORT_B;
Paulo Zanonif278d972012-05-28 16:42:50 -0300430 break;
431 case HDMIC:
Paulo Zanoni72b78c92012-05-28 16:42:54 -0300432 port = VIDEO_DIP_PORT_C;
Paulo Zanonif278d972012-05-28 16:42:50 -0300433 break;
434 case HDMID:
Paulo Zanoni72b78c92012-05-28 16:42:54 -0300435 port = VIDEO_DIP_PORT_D;
Paulo Zanonif278d972012-05-28 16:42:50 -0300436 break;
437 default:
438 return;
439 }
440
Paulo Zanoni72b78c92012-05-28 16:42:54 -0300441 if (port != (val & VIDEO_DIP_PORT_MASK)) {
442 if (val & VIDEO_DIP_ENABLE) {
443 val &= ~VIDEO_DIP_ENABLE;
444 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300445 POSTING_READ(reg);
Paulo Zanoni72b78c92012-05-28 16:42:54 -0300446 }
447 val &= ~VIDEO_DIP_PORT_MASK;
448 val |= port;
449 }
450
Paulo Zanoni822974a2012-05-28 16:42:51 -0300451 val |= VIDEO_DIP_ENABLE;
Paulo Zanoni0dd87d22012-05-28 16:42:53 -0300452 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
453 VIDEO_DIP_ENABLE_GCP);
Paulo Zanoni822974a2012-05-28 16:42:51 -0300454
Paulo Zanonif278d972012-05-28 16:42:50 -0300455 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300456 POSTING_READ(reg);
Paulo Zanonif278d972012-05-28 16:42:50 -0300457
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300458 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
459 intel_hdmi_set_spd_infoframe(encoder);
460}
461
462static void cpt_set_infoframes(struct drm_encoder *encoder,
463 struct drm_display_mode *adjusted_mode)
464{
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300465 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
466 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
467 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
468 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
469 u32 val = I915_READ(reg);
470
Daniel Vetterafba0182012-06-12 16:36:45 +0200471 assert_hdmi_port_disabled(intel_hdmi);
472
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300473 /* See the big comment in g4x_set_infoframes() */
474 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
475
476 if (!intel_hdmi->has_hdmi_sink) {
477 if (!(val & VIDEO_DIP_ENABLE))
478 return;
479 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
480 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300481 POSTING_READ(reg);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300482 return;
483 }
484
Paulo Zanoni822974a2012-05-28 16:42:51 -0300485 /* Set both together, unset both together: see the spec. */
486 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
Paulo Zanoni0dd87d22012-05-28 16:42:53 -0300487 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
488 VIDEO_DIP_ENABLE_GCP);
Paulo Zanoni822974a2012-05-28 16:42:51 -0300489
490 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300491 POSTING_READ(reg);
Paulo Zanoni822974a2012-05-28 16:42:51 -0300492
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300493 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
494 intel_hdmi_set_spd_infoframe(encoder);
495}
496
497static void vlv_set_infoframes(struct drm_encoder *encoder,
498 struct drm_display_mode *adjusted_mode)
499{
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300500 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
501 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
502 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
503 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
504 u32 val = I915_READ(reg);
505
Daniel Vetterafba0182012-06-12 16:36:45 +0200506 assert_hdmi_port_disabled(intel_hdmi);
507
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300508 /* See the big comment in g4x_set_infoframes() */
509 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
510
511 if (!intel_hdmi->has_hdmi_sink) {
512 if (!(val & VIDEO_DIP_ENABLE))
513 return;
514 val &= ~VIDEO_DIP_ENABLE;
515 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300516 POSTING_READ(reg);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300517 return;
518 }
519
Paulo Zanoni822974a2012-05-28 16:42:51 -0300520 val |= VIDEO_DIP_ENABLE;
Paulo Zanoni0dd87d22012-05-28 16:42:53 -0300521 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
522 VIDEO_DIP_ENABLE_GCP);
Paulo Zanoni822974a2012-05-28 16:42:51 -0300523
524 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300525 POSTING_READ(reg);
Paulo Zanoni822974a2012-05-28 16:42:51 -0300526
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300527 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
528 intel_hdmi_set_spd_infoframe(encoder);
529}
530
531static void hsw_set_infoframes(struct drm_encoder *encoder,
532 struct drm_display_mode *adjusted_mode)
533{
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300534 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
535 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
536 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
537 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
Paulo Zanoni0dd87d22012-05-28 16:42:53 -0300538 u32 val = I915_READ(reg);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300539
Daniel Vetterafba0182012-06-12 16:36:45 +0200540 assert_hdmi_port_disabled(intel_hdmi);
541
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300542 if (!intel_hdmi->has_hdmi_sink) {
543 I915_WRITE(reg, 0);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300544 POSTING_READ(reg);
Paulo Zanoni0c14c7f2012-05-28 16:42:49 -0300545 return;
546 }
547
Paulo Zanoni0dd87d22012-05-28 16:42:53 -0300548 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
549 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
550
551 I915_WRITE(reg, val);
Paulo Zanoni9d9740f2012-05-28 16:43:00 -0300552 POSTING_READ(reg);
Paulo Zanoni0dd87d22012-05-28 16:42:53 -0300553
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300554 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
555 intel_hdmi_set_spd_infoframe(encoder);
556}
557
Eric Anholt7d573822009-01-02 13:33:00 -0800558static void intel_hdmi_mode_set(struct drm_encoder *encoder,
559 struct drm_display_mode *mode,
560 struct drm_display_mode *adjusted_mode)
561{
562 struct drm_device *dev = encoder->dev;
563 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonied517fb2012-05-14 17:12:50 -0300564 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
Chris Wilsonea5b2132010-08-04 13:50:23 +0100565 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
Eric Anholt7d573822009-01-02 13:33:00 -0800566 u32 sdvox;
567
Paulo Zanonib659c3d2012-05-28 16:42:56 -0300568 sdvox = SDVO_ENCODING_HDMI;
Jesse Barnes5d4fac92011-06-24 12:19:19 -0700569 if (!HAS_PCH_SPLIT(dev))
570 sdvox |= intel_hdmi->color_range;
Adam Jacksonb599c0b2010-07-16 14:46:31 -0400571 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
572 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
573 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
574 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
Eric Anholt7d573822009-01-02 13:33:00 -0800575
Jesse Barnes020f6702011-06-24 12:19:25 -0700576 if (intel_crtc->bpp > 24)
577 sdvox |= COLOR_FORMAT_12bpc;
578 else
579 sdvox |= COLOR_FORMAT_8bpc;
580
Zhenyu Wang2e3d6002010-09-10 10:39:40 +0800581 /* Required on CPT */
582 if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
583 sdvox |= HDMI_MODE_SELECT;
584
David Härdeman3c17fe42010-09-24 21:44:32 +0200585 if (intel_hdmi->has_audio) {
Wu Fengguange0dac652011-09-05 14:25:34 +0800586 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
587 pipe_name(intel_crtc->pipe));
Eric Anholt7d573822009-01-02 13:33:00 -0800588 sdvox |= SDVO_AUDIO_ENABLE;
David Härdeman3c17fe42010-09-24 21:44:32 +0200589 sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
Wu Fengguange0dac652011-09-05 14:25:34 +0800590 intel_write_eld(encoder, adjusted_mode);
David Härdeman3c17fe42010-09-24 21:44:32 +0200591 }
Eric Anholt7d573822009-01-02 13:33:00 -0800592
Jesse Barnes75770562011-10-12 09:01:58 -0700593 if (HAS_PCH_CPT(dev))
594 sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
Daniel Vetter7a87c282012-06-05 11:03:39 +0200595 else if (intel_crtc->pipe == PIPE_B)
Jesse Barnes75770562011-10-12 09:01:58 -0700596 sdvox |= SDVO_PIPE_B_SELECT;
Eric Anholt7d573822009-01-02 13:33:00 -0800597
Chris Wilsonea5b2132010-08-04 13:50:23 +0100598 I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
599 POSTING_READ(intel_hdmi->sdvox_reg);
David Härdeman3c17fe42010-09-24 21:44:32 +0200600
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300601 intel_hdmi->set_infoframes(encoder, adjusted_mode);
Eric Anholt7d573822009-01-02 13:33:00 -0800602}
603
604static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
605{
606 struct drm_device *dev = encoder->dev;
607 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonea5b2132010-08-04 13:50:23 +0100608 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
Eric Anholt7d573822009-01-02 13:33:00 -0800609 u32 temp;
Wu Fengguang2deed762011-12-09 20:42:20 +0800610 u32 enable_bits = SDVO_ENABLE;
611
612 if (intel_hdmi->has_audio)
613 enable_bits |= SDVO_AUDIO_ENABLE;
Eric Anholt7d573822009-01-02 13:33:00 -0800614
Chris Wilsonea5b2132010-08-04 13:50:23 +0100615 temp = I915_READ(intel_hdmi->sdvox_reg);
Zhenyu Wangd8a2d0e2009-11-02 07:52:30 +0000616
Daniel Vetter7a87c282012-06-05 11:03:39 +0200617 /* HW workaround for IBX, we need to move the port to transcoder A
618 * before disabling it. */
619 if (HAS_PCH_IBX(dev)) {
620 struct drm_crtc *crtc = encoder->crtc;
621 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
622
623 if (mode != DRM_MODE_DPMS_ON) {
624 if (temp & SDVO_PIPE_B_SELECT) {
625 temp &= ~SDVO_PIPE_B_SELECT;
626 I915_WRITE(intel_hdmi->sdvox_reg, temp);
627 POSTING_READ(intel_hdmi->sdvox_reg);
628
629 /* Again we need to write this twice. */
630 I915_WRITE(intel_hdmi->sdvox_reg, temp);
631 POSTING_READ(intel_hdmi->sdvox_reg);
632
633 /* Transcoder selection bits only update
634 * effectively on vblank. */
635 if (crtc)
636 intel_wait_for_vblank(dev, pipe);
637 else
638 msleep(50);
639 }
640 } else {
641 /* Restore the transcoder select bit. */
642 if (pipe == PIPE_B)
643 enable_bits |= SDVO_PIPE_B_SELECT;
644 }
645 }
646
Zhenyu Wangd8a2d0e2009-11-02 07:52:30 +0000647 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
648 * we do this anyway which shows more stable in testing.
649 */
Eric Anholtc619eed2010-01-28 16:45:52 -0800650 if (HAS_PCH_SPLIT(dev)) {
Chris Wilsonea5b2132010-08-04 13:50:23 +0100651 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
652 POSTING_READ(intel_hdmi->sdvox_reg);
Eric Anholt7d573822009-01-02 13:33:00 -0800653 }
Zhenyu Wangd8a2d0e2009-11-02 07:52:30 +0000654
655 if (mode != DRM_MODE_DPMS_ON) {
Wu Fengguang2deed762011-12-09 20:42:20 +0800656 temp &= ~enable_bits;
Zhenyu Wangd8a2d0e2009-11-02 07:52:30 +0000657 } else {
Wu Fengguang2deed762011-12-09 20:42:20 +0800658 temp |= enable_bits;
Zhenyu Wangd8a2d0e2009-11-02 07:52:30 +0000659 }
660
Chris Wilsonea5b2132010-08-04 13:50:23 +0100661 I915_WRITE(intel_hdmi->sdvox_reg, temp);
662 POSTING_READ(intel_hdmi->sdvox_reg);
Zhenyu Wangd8a2d0e2009-11-02 07:52:30 +0000663
664 /* HW workaround, need to write this twice for issue that may result
665 * in first write getting masked.
666 */
Eric Anholtc619eed2010-01-28 16:45:52 -0800667 if (HAS_PCH_SPLIT(dev)) {
Chris Wilsonea5b2132010-08-04 13:50:23 +0100668 I915_WRITE(intel_hdmi->sdvox_reg, temp);
669 POSTING_READ(intel_hdmi->sdvox_reg);
Zhenyu Wangd8a2d0e2009-11-02 07:52:30 +0000670 }
Eric Anholt7d573822009-01-02 13:33:00 -0800671}
672
Eric Anholt7d573822009-01-02 13:33:00 -0800673static int intel_hdmi_mode_valid(struct drm_connector *connector,
674 struct drm_display_mode *mode)
675{
676 if (mode->clock > 165000)
677 return MODE_CLOCK_HIGH;
678 if (mode->clock < 20000)
Nicolas Kaiser5cbba412011-05-30 12:48:26 +0200679 return MODE_CLOCK_LOW;
Eric Anholt7d573822009-01-02 13:33:00 -0800680
681 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
682 return MODE_NO_DBLESCAN;
683
684 return MODE_OK;
685}
686
687static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
688 struct drm_display_mode *mode,
689 struct drm_display_mode *adjusted_mode)
690{
691 return true;
692}
693
Chris Wilson8ec22b22012-05-11 18:01:34 +0100694static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi)
695{
696 struct drm_device *dev = intel_hdmi->base.base.dev;
697 struct drm_i915_private *dev_priv = dev->dev_private;
698 uint32_t bit;
699
700 switch (intel_hdmi->sdvox_reg) {
Chris Wilsoneeafaac2012-05-25 10:23:37 +0100701 case SDVOB:
Chris Wilson8ec22b22012-05-11 18:01:34 +0100702 bit = HDMIB_HOTPLUG_LIVE_STATUS;
703 break;
Chris Wilsoneeafaac2012-05-25 10:23:37 +0100704 case SDVOC:
Chris Wilson8ec22b22012-05-11 18:01:34 +0100705 bit = HDMIC_HOTPLUG_LIVE_STATUS;
706 break;
Chris Wilson8ec22b22012-05-11 18:01:34 +0100707 default:
708 bit = 0;
709 break;
710 }
711
712 return I915_READ(PORT_HOTPLUG_STAT) & bit;
713}
714
Keith Packardaa93d632009-05-05 09:52:46 -0700715static enum drm_connector_status
Chris Wilson930a9e22010-09-14 11:07:23 +0100716intel_hdmi_detect(struct drm_connector *connector, bool force)
Ma Ling9dff6af2009-04-02 13:13:26 +0800717{
Chris Wilsondf0e9242010-09-09 16:20:55 +0100718 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
Chris Wilsonf899fc62010-07-20 15:44:45 -0700719 struct drm_i915_private *dev_priv = connector->dev->dev_private;
720 struct edid *edid;
Keith Packardaa93d632009-05-05 09:52:46 -0700721 enum drm_connector_status status = connector_status_disconnected;
Ma Ling9dff6af2009-04-02 13:13:26 +0800722
Chris Wilson8ec22b22012-05-11 18:01:34 +0100723 if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi))
724 return status;
725
Chris Wilsonea5b2132010-08-04 13:50:23 +0100726 intel_hdmi->has_hdmi_sink = false;
Zhenyu Wang2e3d6002010-09-10 10:39:40 +0800727 intel_hdmi->has_audio = false;
Chris Wilsonf899fc62010-07-20 15:44:45 -0700728 edid = drm_get_edid(connector,
Daniel Kurtz3bd7d902012-03-28 02:36:14 +0800729 intel_gmbus_get_adapter(dev_priv,
730 intel_hdmi->ddc_bus));
ling.ma@intel.com2ded9e22009-07-16 17:23:09 +0800731
Keith Packardaa93d632009-05-05 09:52:46 -0700732 if (edid) {
Eric Anholtbe9f1c42009-06-21 22:14:55 -0700733 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
Keith Packardaa93d632009-05-05 09:52:46 -0700734 status = connector_status_connected;
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +0800735 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
736 intel_hdmi->has_hdmi_sink =
737 drm_detect_hdmi_monitor(edid);
Zhenyu Wang2e3d6002010-09-10 10:39:40 +0800738 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
Keith Packardaa93d632009-05-05 09:52:46 -0700739 }
Zhenyu Wang674e2d02010-03-29 15:57:42 +0800740 connector->display_info.raw_edid = NULL;
Keith Packardaa93d632009-05-05 09:52:46 -0700741 kfree(edid);
Ma Ling9dff6af2009-04-02 13:13:26 +0800742 }
ling.ma@intel.com2ded9e22009-07-16 17:23:09 +0800743
Chris Wilson55b7d6e82010-09-19 09:29:33 +0100744 if (status == connector_status_connected) {
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +0800745 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
746 intel_hdmi->has_audio =
747 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
Chris Wilson55b7d6e82010-09-19 09:29:33 +0100748 }
749
Keith Packardaa93d632009-05-05 09:52:46 -0700750 return status;
Ma Ling9dff6af2009-04-02 13:13:26 +0800751}
752
Eric Anholt7d573822009-01-02 13:33:00 -0800753static int intel_hdmi_get_modes(struct drm_connector *connector)
754{
Chris Wilsondf0e9242010-09-09 16:20:55 +0100755 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
Chris Wilsonf899fc62010-07-20 15:44:45 -0700756 struct drm_i915_private *dev_priv = connector->dev->dev_private;
Eric Anholt7d573822009-01-02 13:33:00 -0800757
758 /* We should parse the EDID data and find out if it's an HDMI sink so
759 * we can send audio to it.
760 */
761
Chris Wilsonf899fc62010-07-20 15:44:45 -0700762 return intel_ddc_get_modes(connector,
Daniel Kurtz3bd7d902012-03-28 02:36:14 +0800763 intel_gmbus_get_adapter(dev_priv,
764 intel_hdmi->ddc_bus));
Eric Anholt7d573822009-01-02 13:33:00 -0800765}
766
Chris Wilson1aad7ac2011-02-09 18:46:58 +0000767static bool
768intel_hdmi_detect_audio(struct drm_connector *connector)
769{
770 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
771 struct drm_i915_private *dev_priv = connector->dev->dev_private;
772 struct edid *edid;
773 bool has_audio = false;
774
775 edid = drm_get_edid(connector,
Daniel Kurtz3bd7d902012-03-28 02:36:14 +0800776 intel_gmbus_get_adapter(dev_priv,
777 intel_hdmi->ddc_bus));
Chris Wilson1aad7ac2011-02-09 18:46:58 +0000778 if (edid) {
779 if (edid->input & DRM_EDID_INPUT_DIGITAL)
780 has_audio = drm_detect_monitor_audio(edid);
781
782 connector->display_info.raw_edid = NULL;
783 kfree(edid);
784 }
785
786 return has_audio;
787}
788
Chris Wilson55b7d6e82010-09-19 09:29:33 +0100789static int
790intel_hdmi_set_property(struct drm_connector *connector,
Paulo Zanonied517fb2012-05-14 17:12:50 -0300791 struct drm_property *property,
792 uint64_t val)
Chris Wilson55b7d6e82010-09-19 09:29:33 +0100793{
794 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
Chris Wilsone953fd72011-02-21 22:23:52 +0000795 struct drm_i915_private *dev_priv = connector->dev->dev_private;
Chris Wilson55b7d6e82010-09-19 09:29:33 +0100796 int ret;
797
798 ret = drm_connector_property_set_value(connector, property, val);
799 if (ret)
800 return ret;
801
Chris Wilson3f43c482011-05-12 22:17:24 +0100802 if (property == dev_priv->force_audio_property) {
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +0800803 enum hdmi_force_audio i = val;
Chris Wilson1aad7ac2011-02-09 18:46:58 +0000804 bool has_audio;
805
806 if (i == intel_hdmi->force_audio)
Chris Wilson55b7d6e82010-09-19 09:29:33 +0100807 return 0;
808
Chris Wilson1aad7ac2011-02-09 18:46:58 +0000809 intel_hdmi->force_audio = i;
Chris Wilson55b7d6e82010-09-19 09:29:33 +0100810
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +0800811 if (i == HDMI_AUDIO_AUTO)
Chris Wilson1aad7ac2011-02-09 18:46:58 +0000812 has_audio = intel_hdmi_detect_audio(connector);
813 else
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +0800814 has_audio = (i == HDMI_AUDIO_ON);
Chris Wilson1aad7ac2011-02-09 18:46:58 +0000815
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +0800816 if (i == HDMI_AUDIO_OFF_DVI)
817 intel_hdmi->has_hdmi_sink = 0;
Chris Wilson55b7d6e82010-09-19 09:29:33 +0100818
Chris Wilson1aad7ac2011-02-09 18:46:58 +0000819 intel_hdmi->has_audio = has_audio;
Chris Wilson55b7d6e82010-09-19 09:29:33 +0100820 goto done;
821 }
822
Chris Wilsone953fd72011-02-21 22:23:52 +0000823 if (property == dev_priv->broadcast_rgb_property) {
824 if (val == !!intel_hdmi->color_range)
825 return 0;
826
827 intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
828 goto done;
829 }
830
Chris Wilson55b7d6e82010-09-19 09:29:33 +0100831 return -EINVAL;
832
833done:
834 if (intel_hdmi->base.base.crtc) {
835 struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
836 drm_crtc_helper_set_mode(crtc, &crtc->mode,
837 crtc->x, crtc->y,
838 crtc->fb);
839 }
840
841 return 0;
842}
843
Eric Anholt7d573822009-01-02 13:33:00 -0800844static void intel_hdmi_destroy(struct drm_connector *connector)
845{
Eric Anholt7d573822009-01-02 13:33:00 -0800846 drm_sysfs_connector_remove(connector);
847 drm_connector_cleanup(connector);
Zhenyu Wang674e2d02010-03-29 15:57:42 +0800848 kfree(connector);
Eric Anholt7d573822009-01-02 13:33:00 -0800849}
850
Eugeni Dodonov72662e12012-05-09 15:37:31 -0300851static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = {
852 .dpms = intel_ddi_dpms,
853 .mode_fixup = intel_hdmi_mode_fixup,
854 .prepare = intel_encoder_prepare,
855 .mode_set = intel_ddi_mode_set,
856 .commit = intel_encoder_commit,
857};
858
Eric Anholt7d573822009-01-02 13:33:00 -0800859static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
860 .dpms = intel_hdmi_dpms,
861 .mode_fixup = intel_hdmi_mode_fixup,
862 .prepare = intel_encoder_prepare,
863 .mode_set = intel_hdmi_mode_set,
864 .commit = intel_encoder_commit,
865};
866
867static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
Keith Packardc9fb15f2009-05-30 20:42:28 -0700868 .dpms = drm_helper_connector_dpms,
Eric Anholt7d573822009-01-02 13:33:00 -0800869 .detect = intel_hdmi_detect,
870 .fill_modes = drm_helper_probe_single_connector_modes,
Chris Wilson55b7d6e82010-09-19 09:29:33 +0100871 .set_property = intel_hdmi_set_property,
Eric Anholt7d573822009-01-02 13:33:00 -0800872 .destroy = intel_hdmi_destroy,
873};
874
875static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
876 .get_modes = intel_hdmi_get_modes,
877 .mode_valid = intel_hdmi_mode_valid,
Chris Wilsondf0e9242010-09-09 16:20:55 +0100878 .best_encoder = intel_best_encoder,
Eric Anholt7d573822009-01-02 13:33:00 -0800879};
880
Eric Anholt7d573822009-01-02 13:33:00 -0800881static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
Chris Wilsonea5b2132010-08-04 13:50:23 +0100882 .destroy = intel_encoder_destroy,
Eric Anholt7d573822009-01-02 13:33:00 -0800883};
884
Chris Wilson55b7d6e82010-09-19 09:29:33 +0100885static void
886intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
887{
Chris Wilson3f43c482011-05-12 22:17:24 +0100888 intel_attach_force_audio_property(connector);
Chris Wilsone953fd72011-02-21 22:23:52 +0000889 intel_attach_broadcast_rgb_property(connector);
Chris Wilson55b7d6e82010-09-19 09:29:33 +0100890}
891
Eric Anholt7d573822009-01-02 13:33:00 -0800892void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
893{
894 struct drm_i915_private *dev_priv = dev->dev_private;
895 struct drm_connector *connector;
Eric Anholt21d40d32010-03-25 11:11:14 -0700896 struct intel_encoder *intel_encoder;
Zhenyu Wang674e2d02010-03-29 15:57:42 +0800897 struct intel_connector *intel_connector;
Chris Wilsonea5b2132010-08-04 13:50:23 +0100898 struct intel_hdmi *intel_hdmi;
Eric Anholt7d573822009-01-02 13:33:00 -0800899
Chris Wilsonea5b2132010-08-04 13:50:23 +0100900 intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
901 if (!intel_hdmi)
Eric Anholt7d573822009-01-02 13:33:00 -0800902 return;
Zhenyu Wang674e2d02010-03-29 15:57:42 +0800903
904 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
905 if (!intel_connector) {
Chris Wilsonea5b2132010-08-04 13:50:23 +0100906 kfree(intel_hdmi);
Zhenyu Wang674e2d02010-03-29 15:57:42 +0800907 return;
908 }
909
Chris Wilsonea5b2132010-08-04 13:50:23 +0100910 intel_encoder = &intel_hdmi->base;
Chris Wilson373a3cf2010-09-15 12:03:59 +0100911 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
912 DRM_MODE_ENCODER_TMDS);
913
Zhenyu Wang674e2d02010-03-29 15:57:42 +0800914 connector = &intel_connector->base;
Eric Anholt7d573822009-01-02 13:33:00 -0800915 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
Adam Jackson8d911042009-09-23 15:08:29 -0400916 DRM_MODE_CONNECTOR_HDMIA);
Eric Anholt7d573822009-01-02 13:33:00 -0800917 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
918
Eric Anholt21d40d32010-03-25 11:11:14 -0700919 intel_encoder->type = INTEL_OUTPUT_HDMI;
Eric Anholt7d573822009-01-02 13:33:00 -0800920
Dave Airlieeb1f8e42010-05-07 06:42:51 +0000921 connector->polled = DRM_CONNECTOR_POLL_HPD;
Peter Rossc3febcc2012-01-28 14:49:26 +0100922 connector->interlace_allowed = 1;
Eric Anholt7d573822009-01-02 13:33:00 -0800923 connector->doublescan_allowed = 0;
Jesse Barnes27f82272011-09-02 12:54:37 -0700924 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
Eric Anholt7d573822009-01-02 13:33:00 -0800925
926 /* Set up the DDC bus. */
Ma Lingf8aed702009-08-24 13:50:24 +0800927 if (sdvox_reg == SDVOB) {
Eric Anholt21d40d32010-03-25 11:11:14 -0700928 intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
Chris Wilsonf899fc62010-07-20 15:44:45 -0700929 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
Jesse Barnesb01f2c32009-12-11 11:07:17 -0800930 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
Ma Lingf8aed702009-08-24 13:50:24 +0800931 } else if (sdvox_reg == SDVOC) {
Eric Anholt21d40d32010-03-25 11:11:14 -0700932 intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
Chris Wilsonf899fc62010-07-20 15:44:45 -0700933 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
Jesse Barnesb01f2c32009-12-11 11:07:17 -0800934 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
Ma Lingf8aed702009-08-24 13:50:24 +0800935 } else if (sdvox_reg == HDMIB) {
Eric Anholt21d40d32010-03-25 11:11:14 -0700936 intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
Chris Wilsonf899fc62010-07-20 15:44:45 -0700937 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
Jesse Barnesb01f2c32009-12-11 11:07:17 -0800938 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
Ma Lingf8aed702009-08-24 13:50:24 +0800939 } else if (sdvox_reg == HDMIC) {
Eric Anholt21d40d32010-03-25 11:11:14 -0700940 intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
Chris Wilsonf899fc62010-07-20 15:44:45 -0700941 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
Jesse Barnesb01f2c32009-12-11 11:07:17 -0800942 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
Ma Lingf8aed702009-08-24 13:50:24 +0800943 } else if (sdvox_reg == HDMID) {
Eric Anholt21d40d32010-03-25 11:11:14 -0700944 intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
Chris Wilsonf899fc62010-07-20 15:44:45 -0700945 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
Jesse Barnesb01f2c32009-12-11 11:07:17 -0800946 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
Eugeni Dodonov7ceae0a2012-05-09 15:37:28 -0300947 } else if (sdvox_reg == DDI_BUF_CTL(PORT_B)) {
948 DRM_DEBUG_DRIVER("LPT: detected output on DDI B\n");
949 intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
950 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
951 intel_hdmi->ddi_port = PORT_B;
952 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
953 } else if (sdvox_reg == DDI_BUF_CTL(PORT_C)) {
954 DRM_DEBUG_DRIVER("LPT: detected output on DDI C\n");
955 intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
956 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
957 intel_hdmi->ddi_port = PORT_C;
958 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
959 } else if (sdvox_reg == DDI_BUF_CTL(PORT_D)) {
960 DRM_DEBUG_DRIVER("LPT: detected output on DDI D\n");
961 intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
962 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
963 intel_hdmi->ddi_port = PORT_D;
964 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
Eugeni Dodonov6e4c1672012-05-09 15:37:13 -0300965 } else {
966 /* If we got an unknown sdvox_reg, things are pretty much broken
967 * in a way that we should let the kernel know about it */
968 BUG();
Ma Lingf8aed702009-08-24 13:50:24 +0800969 }
Eric Anholt7d573822009-01-02 13:33:00 -0800970
Chris Wilsonea5b2132010-08-04 13:50:23 +0100971 intel_hdmi->sdvox_reg = sdvox_reg;
Eric Anholt7d573822009-01-02 13:33:00 -0800972
Jesse Barnes64a8fc02011-09-22 11:16:00 +0530973 if (!HAS_PCH_SPLIT(dev)) {
Daniel Vettera3da1df2012-05-08 15:19:06 +0200974 intel_hdmi->write_infoframe = g4x_write_infoframe;
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300975 intel_hdmi->set_infoframes = g4x_set_infoframes;
Shobhit Kumar90b107c2012-03-28 13:39:32 -0700976 } else if (IS_VALLEYVIEW(dev)) {
977 intel_hdmi->write_infoframe = vlv_write_infoframe;
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300978 intel_hdmi->set_infoframes = vlv_set_infoframes;
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -0300979 } else if (IS_HASWELL(dev)) {
Eugeni Dodonov8c5f5f72012-05-10 10:18:02 -0300980 intel_hdmi->write_infoframe = hsw_write_infoframe;
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300981 intel_hdmi->set_infoframes = hsw_set_infoframes;
Paulo Zanonifdf12502012-05-04 17:18:24 -0300982 } else if (HAS_PCH_IBX(dev)) {
983 intel_hdmi->write_infoframe = ibx_write_infoframe;
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300984 intel_hdmi->set_infoframes = ibx_set_infoframes;
Paulo Zanonifdf12502012-05-04 17:18:24 -0300985 } else {
986 intel_hdmi->write_infoframe = cpt_write_infoframe;
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300987 intel_hdmi->set_infoframes = cpt_set_infoframes;
Jesse Barnes64a8fc02011-09-22 11:16:00 +0530988 }
Jesse Barnes45187ac2011-08-03 09:22:55 -0700989
Eugeni Dodonov72662e12012-05-09 15:37:31 -0300990 if (IS_HASWELL(dev))
991 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs_hsw);
992 else
993 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
Eric Anholt7d573822009-01-02 13:33:00 -0800994
Chris Wilson55b7d6e82010-09-19 09:29:33 +0100995 intel_hdmi_add_properties(intel_hdmi, connector);
996
Chris Wilsondf0e9242010-09-09 16:20:55 +0100997 intel_connector_attach_encoder(intel_connector, intel_encoder);
Eric Anholt7d573822009-01-02 13:33:00 -0800998 drm_sysfs_connector_add(connector);
999
1000 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1001 * 0xd. Failure to do so will result in spurious interrupts being
1002 * generated on the port when a cable is not attached.
1003 */
1004 if (IS_G4X(dev) && !IS_GM45(dev)) {
1005 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1006 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1007 }
Eric Anholt7d573822009-01-02 13:33:00 -08001008}