Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 1 | /* |
| 2 | * OMAP4 SMP source file. It contains platform specific fucntions |
| 3 | * needed for the linux smp kernel. |
| 4 | * |
| 5 | * Copyright (C) 2009 Texas Instruments, Inc. |
| 6 | * |
| 7 | * Author: |
| 8 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
| 9 | * |
| 10 | * Platform file needed for the OMAP4 SMP. This file is based on arm |
| 11 | * realview smp platform. |
| 12 | * * Copyright (c) 2002 ARM Limited. |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License version 2 as |
| 16 | * published by the Free Software Foundation. |
| 17 | */ |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/device.h> |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 20 | #include <linux/smp.h> |
| 21 | #include <linux/io.h> |
| 22 | |
Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 23 | #include <asm/cacheflush.h> |
Russell King | 0f7b332 | 2011-04-03 13:01:30 +0100 | [diff] [blame] | 24 | #include <asm/hardware/gic.h> |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 25 | #include <asm/smp_scu.h> |
Tony Lindgren | ee0839c | 2012-02-24 10:34:35 -0800 | [diff] [blame] | 26 | |
Tony Lindgren | c1db9d7 | 2012-09-20 11:41:14 -0700 | [diff] [blame] | 27 | #include "omap-secure.h" |
Tony Lindgren | 732231a | 2012-09-20 11:41:16 -0700 | [diff] [blame] | 28 | #include "omap-wakeupgen.h" |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 29 | #include <asm/cputype.h> |
Tony Lindgren | 4e65331 | 2011-11-10 22:45:17 +0100 | [diff] [blame] | 30 | |
Tony Lindgren | dbc0416 | 2012-08-31 10:59:07 -0700 | [diff] [blame] | 31 | #include "soc.h" |
Tony Lindgren | ee0839c | 2012-02-24 10:34:35 -0800 | [diff] [blame] | 32 | #include "iomap.h" |
Tony Lindgren | 4e65331 | 2011-11-10 22:45:17 +0100 | [diff] [blame] | 33 | #include "common.h" |
Santosh Shilimkar | e97ca47 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 34 | #include "clockdomain.h" |
| 35 | |
Santosh Shilimkar | 283f708 | 2012-03-19 19:29:41 +0530 | [diff] [blame] | 36 | #define CPU_MASK 0xff0ffff0 |
| 37 | #define CPU_CORTEX_A9 0x410FC090 |
| 38 | #define CPU_CORTEX_A15 0x410FC0F0 |
| 39 | |
| 40 | #define OMAP5_CORE_COUNT 0x2 |
| 41 | |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 42 | /* SCU base address */ |
Tony Lindgren | e4e7a13 | 2009-10-19 15:25:26 -0700 | [diff] [blame] | 43 | static void __iomem *scu_base; |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 44 | |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 45 | static DEFINE_SPINLOCK(boot_lock); |
| 46 | |
Santosh Shilimkar | 02afe8a | 2011-03-03 18:03:25 +0530 | [diff] [blame] | 47 | void __iomem *omap4_get_scu_base(void) |
| 48 | { |
| 49 | return scu_base; |
| 50 | } |
| 51 | |
Marc Zyngier | 0691532 | 2011-09-08 13:15:22 +0100 | [diff] [blame] | 52 | static void __cpuinit omap4_secondary_init(unsigned int cpu) |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 53 | { |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 54 | /* |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 55 | * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device. |
| 56 | * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA |
| 57 | * init and for CPU1, a secure PPA API provided. CPU0 must be ON |
| 58 | * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+. |
| 59 | * OMAP443X GP devices- SMP bit isn't accessible. |
| 60 | * OMAP446X GP devices - SMP bit access is enabled on both CPUs. |
| 61 | */ |
| 62 | if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) |
| 63 | omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX, |
| 64 | 4, 0, 0, 0, 0, 0); |
| 65 | |
| 66 | /* |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 67 | * If any interrupts are already enabled for the primary |
| 68 | * core (e.g. timer irq), then they will not have been enabled |
| 69 | * for us: do so |
| 70 | */ |
Russell King | 3848953 | 2010-12-04 16:01:03 +0000 | [diff] [blame] | 71 | gic_secondary_init(0); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 72 | |
| 73 | /* |
| 74 | * Synchronise with the boot thread. |
| 75 | */ |
| 76 | spin_lock(&boot_lock); |
| 77 | spin_unlock(&boot_lock); |
| 78 | } |
| 79 | |
Marc Zyngier | 0691532 | 2011-09-08 13:15:22 +0100 | [diff] [blame] | 80 | static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *idle) |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 81 | { |
Santosh Shilimkar | e97ca47 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 82 | static struct clockdomain *cpu1_clkdm; |
| 83 | static bool booted; |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 84 | void __iomem *base = omap_get_wakeupgen_base(); |
| 85 | |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 86 | /* |
| 87 | * Set synchronisation state between this boot processor |
| 88 | * and the secondary one |
| 89 | */ |
| 90 | spin_lock(&boot_lock); |
| 91 | |
| 92 | /* |
Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 93 | * Update the AuxCoreBoot0 with boot state for secondary core. |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 94 | * omap_secondary_startup() routine will hold the secondary core till |
| 95 | * the AuxCoreBoot1 register is updated with cpu state |
| 96 | * A barrier is added to ensure that write buffer is drained |
| 97 | */ |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 98 | if (omap_secure_apis_support()) |
| 99 | omap_modify_auxcoreboot0(0x200, 0xfffffdff); |
| 100 | else |
| 101 | __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0); |
| 102 | |
Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 103 | flush_cache_all(); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 104 | smp_wmb(); |
Santosh Shilimkar | e97ca47 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 105 | |
| 106 | if (!cpu1_clkdm) |
| 107 | cpu1_clkdm = clkdm_lookup("mpu1_clkdm"); |
| 108 | |
| 109 | /* |
| 110 | * The SGI(Software Generated Interrupts) are not wakeup capable |
| 111 | * from low power states. This is known limitation on OMAP4 and |
| 112 | * needs to be worked around by using software forced clockdomain |
| 113 | * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to |
| 114 | * software force wakeup. The clockdomain is then put back to |
| 115 | * hardware supervised mode. |
| 116 | * More details can be found in OMAP4430 TRM - Version J |
| 117 | * Section : |
| 118 | * 4.3.4.2 Power States of CPU0 and CPU1 |
| 119 | */ |
| 120 | if (booted) { |
| 121 | clkdm_wakeup(cpu1_clkdm); |
| 122 | clkdm_allow_idle(cpu1_clkdm); |
| 123 | } else { |
| 124 | dsb_sev(); |
| 125 | booted = true; |
| 126 | } |
| 127 | |
Russell King | 79d15ce | 2012-06-11 20:24:07 +0100 | [diff] [blame] | 128 | gic_raise_softirq(cpumask_of(cpu), 0); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 129 | |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 130 | /* |
| 131 | * Now the secondary core is starting up let it run its |
| 132 | * calibrations, then wait for it to finish |
| 133 | */ |
| 134 | spin_unlock(&boot_lock); |
| 135 | |
| 136 | return 0; |
| 137 | } |
| 138 | |
| 139 | static void __init wakeup_secondary(void) |
| 140 | { |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 141 | void __iomem *base = omap_get_wakeupgen_base(); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 142 | /* |
| 143 | * Write the address of secondary startup routine into the |
Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 144 | * AuxCoreBoot1 where ROM code will jump and start executing |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 145 | * on secondary core once out of WFE |
| 146 | * A barrier is added to ensure that write buffer is drained |
| 147 | */ |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 148 | if (omap_secure_apis_support()) |
| 149 | omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup)); |
| 150 | else |
| 151 | __raw_writel(virt_to_phys(omap5_secondary_startup), |
| 152 | base + OMAP_AUX_CORE_BOOT_1); |
| 153 | |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 154 | smp_wmb(); |
| 155 | |
| 156 | /* |
| 157 | * Send a 'sev' to wake the secondary core from WFE. |
Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 158 | * Drain the outstanding writes to memory |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 159 | */ |
Tony Lindgren | a4192d3 | 2010-08-16 09:21:20 +0300 | [diff] [blame] | 160 | dsb_sev(); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 161 | mb(); |
| 162 | } |
| 163 | |
| 164 | /* |
| 165 | * Initialise the CPU possible map early - this describes the CPUs |
| 166 | * which may be present or become present in the system. |
| 167 | */ |
Marc Zyngier | 0691532 | 2011-09-08 13:15:22 +0100 | [diff] [blame] | 168 | static void __init omap4_smp_init_cpus(void) |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 169 | { |
Santosh Shilimkar | 283f708 | 2012-03-19 19:29:41 +0530 | [diff] [blame] | 170 | unsigned int i = 0, ncores = 1, cpu_id; |
Tony Lindgren | e4e7a13 | 2009-10-19 15:25:26 -0700 | [diff] [blame] | 171 | |
Santosh Shilimkar | 283f708 | 2012-03-19 19:29:41 +0530 | [diff] [blame] | 172 | /* Use ARM cpuid check here, as SoC detection will not work so early */ |
| 173 | cpu_id = read_cpuid(CPUID_ID) & CPU_MASK; |
| 174 | if (cpu_id == CPU_CORTEX_A9) { |
| 175 | /* |
| 176 | * Currently we can't call ioremap here because |
| 177 | * SoC detection won't work until after init_early. |
| 178 | */ |
| 179 | scu_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE); |
| 180 | BUG_ON(!scu_base); |
| 181 | ncores = scu_get_core_count(scu_base); |
| 182 | } else if (cpu_id == CPU_CORTEX_A15) { |
| 183 | ncores = OMAP5_CORE_COUNT; |
| 184 | } |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 185 | |
| 186 | /* sanity check */ |
Russell King | a06f916 | 2011-10-20 22:04:18 +0100 | [diff] [blame] | 187 | if (ncores > nr_cpu_ids) { |
| 188 | pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", |
| 189 | ncores, nr_cpu_ids); |
| 190 | ncores = nr_cpu_ids; |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 191 | } |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 192 | |
Russell King | bbc3d14 | 2010-12-03 10:42:58 +0000 | [diff] [blame] | 193 | for (i = 0; i < ncores; i++) |
| 194 | set_cpu_possible(i, true); |
Russell King | 0f7b332 | 2011-04-03 13:01:30 +0100 | [diff] [blame] | 195 | |
| 196 | set_smp_cross_call(gic_raise_softirq); |
Russell King | bbc3d14 | 2010-12-03 10:42:58 +0000 | [diff] [blame] | 197 | } |
| 198 | |
Marc Zyngier | 0691532 | 2011-09-08 13:15:22 +0100 | [diff] [blame] | 199 | static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) |
Russell King | bbc3d14 | 2010-12-03 10:42:58 +0000 | [diff] [blame] | 200 | { |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 201 | |
Russell King | 05c74a6 | 2010-12-03 11:09:48 +0000 | [diff] [blame] | 202 | /* |
| 203 | * Initialise the SCU and wake up the secondary core using |
| 204 | * wakeup_secondary(). |
| 205 | */ |
Santosh Shilimkar | 283f708 | 2012-03-19 19:29:41 +0530 | [diff] [blame] | 206 | if (scu_base) |
| 207 | scu_enable(scu_base); |
Russell King | 05c74a6 | 2010-12-03 11:09:48 +0000 | [diff] [blame] | 208 | wakeup_secondary(); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 209 | } |
Marc Zyngier | 0691532 | 2011-09-08 13:15:22 +0100 | [diff] [blame] | 210 | |
| 211 | struct smp_operations omap4_smp_ops __initdata = { |
| 212 | .smp_init_cpus = omap4_smp_init_cpus, |
| 213 | .smp_prepare_cpus = omap4_smp_prepare_cpus, |
| 214 | .smp_secondary_init = omap4_secondary_init, |
| 215 | .smp_boot_secondary = omap4_boot_secondary, |
| 216 | #ifdef CONFIG_HOTPLUG_CPU |
| 217 | .cpu_die = omap4_cpu_die, |
| 218 | #endif |
| 219 | }; |