blob: f6a2eba244e7de2f23eb4574927b028d05f70afe [file] [log] [blame]
Mythri P Kc3198a52011-03-12 12:04:27 +05301/*
2 * hdmi.c
3 *
4 * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#define DSS_SUBSYS_NAME "HDMI"
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/err.h>
27#include <linux/io.h>
28#include <linux/interrupt.h>
29#include <linux/mutex.h>
30#include <linux/delay.h>
31#include <linux/string.h>
Tomi Valkeinen24e62892011-05-23 11:51:18 +030032#include <linux/platform_device.h>
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +030033#include <linux/pm_runtime.h>
34#include <linux/clk.h>
Tomi Valkeinencca35012012-04-26 14:48:32 +030035#include <linux/gpio.h>
Tomi Valkeinen17486942012-08-15 15:55:04 +030036#include <linux/regulator/consumer.h>
Tomi Valkeinena0b38cc2011-05-11 14:05:07 +030037#include <video/omapdss.h>
Mythri P Kc3198a52011-03-12 12:04:27 +053038
Mythri P K94c52982011-09-08 19:06:21 +053039#include "ti_hdmi.h"
Mythri P Kc3198a52011-03-12 12:04:27 +053040#include "dss.h"
Ricardo Neriad44cc32011-05-18 22:31:56 -050041#include "dss_features.h"
Mythri P Kc3198a52011-03-12 12:04:27 +053042
Mythri P K95a8aeb2011-09-08 19:06:18 +053043#define HDMI_CORE_SYS 0x400
44#define HDMI_CORE_AV 0x900
Mythri P K95a8aeb2011-09-08 19:06:18 +053045#define HDMI_PHY 0x300
46
Mythri P K7c1f1ec2011-09-08 19:06:22 +053047/* HDMI EDID Length move this */
48#define HDMI_EDID_MAX_LENGTH 256
49#define EDID_TIMING_DESCRIPTOR_SIZE 0x12
50#define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
51#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
52#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
53#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
54
Mythri P Kc3198a52011-03-12 12:04:27 +053055static struct {
56 struct mutex lock;
Mythri P Kc3198a52011-03-12 12:04:27 +053057 struct platform_device *pdev;
Ricardo Neri66a06b02012-11-06 00:19:14 -060058
Mythri P K95a8aeb2011-09-08 19:06:18 +053059 struct hdmi_ip_data ip_data;
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +030060
61 struct clk *sys_clk;
Tomi Valkeinen17486942012-08-15 15:55:04 +030062 struct regulator *vdda_hdmi_dac_reg;
Tomi Valkeinencca35012012-04-26 14:48:32 +030063
Tomi Valkeinen0b450c32013-05-24 13:20:17 +030064 bool core_enabled;
65
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +030066 struct omap_dss_device output;
Mythri P Kc3198a52011-03-12 12:04:27 +053067} hdmi;
68
69/*
70 * Logic for the below structure :
71 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
72 * There is a correspondence between CEA/VESA timing and code, please
73 * refer to section 6.3 in HDMI 1.3 specification for timing code.
74 *
75 * In the below structure, cea_vesa_timings corresponds to all OMAP4
76 * supported CEA and VESA timing values.code_cea corresponds to the CEA
77 * code, It is used to get the timing from cea_vesa_timing array.Similarly
78 * with code_vesa. Code_index is used for back mapping, that is once EDID
79 * is read from the TV, EDID is parsed to find the timing values and then
80 * map it to corresponding CEA or VESA index.
81 */
82
Mythri P K46095b22012-01-06 17:52:09 +053083static const struct hdmi_config cea_timings[] = {
Archit Tanejacc937e52012-06-24 13:08:10 +053084 {
85 { 640, 480, 25200, 96, 16, 48, 2, 10, 33,
86 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
87 false, },
88 { 1, HDMI_HDMI },
89 },
90 {
91 { 720, 480, 27027, 62, 16, 60, 6, 9, 30,
92 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
93 false, },
94 { 2, HDMI_HDMI },
95 },
96 {
97 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
98 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
99 false, },
100 { 4, HDMI_HDMI },
101 },
102 {
103 { 1920, 540, 74250, 44, 88, 148, 5, 2, 15,
104 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
105 true, },
106 { 5, HDMI_HDMI },
107 },
108 {
109 { 1440, 240, 27027, 124, 38, 114, 3, 4, 15,
110 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
111 true, },
112 { 6, HDMI_HDMI },
113 },
114 {
115 { 1920, 1080, 148500, 44, 88, 148, 5, 4, 36,
116 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
117 false, },
118 { 16, HDMI_HDMI },
119 },
120 {
121 { 720, 576, 27000, 64, 12, 68, 5, 5, 39,
122 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
123 false, },
124 { 17, HDMI_HDMI },
125 },
126 {
127 { 1280, 720, 74250, 40, 440, 220, 5, 5, 20,
128 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
129 false, },
130 { 19, HDMI_HDMI },
131 },
132 {
133 { 1920, 540, 74250, 44, 528, 148, 5, 2, 15,
134 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
135 true, },
136 { 20, HDMI_HDMI },
137 },
138 {
139 { 1440, 288, 27000, 126, 24, 138, 3, 2, 19,
140 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
141 true, },
142 { 21, HDMI_HDMI },
143 },
144 {
145 { 1440, 576, 54000, 128, 24, 136, 5, 5, 39,
146 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
147 false, },
148 { 29, HDMI_HDMI },
149 },
150 {
151 { 1920, 1080, 148500, 44, 528, 148, 5, 4, 36,
152 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
153 false, },
154 { 31, HDMI_HDMI },
155 },
156 {
157 { 1920, 1080, 74250, 44, 638, 148, 5, 4, 36,
158 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
159 false, },
160 { 32, HDMI_HDMI },
161 },
162 {
163 { 2880, 480, 108108, 248, 64, 240, 6, 9, 30,
164 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
165 false, },
166 { 35, HDMI_HDMI },
167 },
168 {
169 { 2880, 576, 108000, 256, 48, 272, 5, 5, 39,
170 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
171 false, },
172 { 37, HDMI_HDMI },
173 },
Mythri P K46095b22012-01-06 17:52:09 +0530174};
Archit Tanejacc937e52012-06-24 13:08:10 +0530175
Mythri P K46095b22012-01-06 17:52:09 +0530176static const struct hdmi_config vesa_timings[] = {
Mythri P Ka05ce782012-01-06 17:52:08 +0530177/* VESA From Here */
Archit Tanejacc937e52012-06-24 13:08:10 +0530178 {
179 { 640, 480, 25175, 96, 16, 48, 2, 11, 31,
180 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
181 false, },
182 { 4, HDMI_DVI },
183 },
184 {
185 { 800, 600, 40000, 128, 40, 88, 4, 1, 23,
186 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
187 false, },
188 { 9, HDMI_DVI },
189 },
190 {
191 { 848, 480, 33750, 112, 16, 112, 8, 6, 23,
192 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
193 false, },
194 { 0xE, HDMI_DVI },
195 },
196 {
197 { 1280, 768, 79500, 128, 64, 192, 7, 3, 20,
198 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
199 false, },
200 { 0x17, HDMI_DVI },
201 },
202 {
203 { 1280, 800, 83500, 128, 72, 200, 6, 3, 22,
204 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
205 false, },
206 { 0x1C, HDMI_DVI },
207 },
208 {
209 { 1360, 768, 85500, 112, 64, 256, 6, 3, 18,
210 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
211 false, },
212 { 0x27, HDMI_DVI },
213 },
214 {
215 { 1280, 960, 108000, 112, 96, 312, 3, 1, 36,
216 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
217 false, },
218 { 0x20, HDMI_DVI },
219 },
220 {
221 { 1280, 1024, 108000, 112, 48, 248, 3, 1, 38,
222 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
223 false, },
224 { 0x23, HDMI_DVI },
225 },
226 {
227 { 1024, 768, 65000, 136, 24, 160, 6, 3, 29,
228 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
229 false, },
230 { 0x10, HDMI_DVI },
231 },
232 {
233 { 1400, 1050, 121750, 144, 88, 232, 4, 3, 32,
234 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
235 false, },
236 { 0x2A, HDMI_DVI },
237 },
238 {
239 { 1440, 900, 106500, 152, 80, 232, 6, 3, 25,
240 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
241 false, },
242 { 0x2F, HDMI_DVI },
243 },
244 {
245 { 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30,
246 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
247 false, },
248 { 0x3A, HDMI_DVI },
249 },
250 {
251 { 1366, 768, 85500, 143, 70, 213, 3, 3, 24,
252 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
253 false, },
254 { 0x51, HDMI_DVI },
255 },
256 {
257 { 1920, 1080, 148500, 44, 148, 80, 5, 4, 36,
258 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
259 false, },
260 { 0x52, HDMI_DVI },
261 },
262 {
263 { 1280, 768, 68250, 32, 48, 80, 7, 3, 12,
264 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
265 false, },
266 { 0x16, HDMI_DVI },
267 },
268 {
269 { 1400, 1050, 101000, 32, 48, 80, 4, 3, 23,
270 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
271 false, },
272 { 0x29, HDMI_DVI },
273 },
274 {
275 { 1680, 1050, 119000, 32, 48, 80, 6, 3, 21,
276 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
277 false, },
278 { 0x39, HDMI_DVI },
279 },
280 {
281 { 1280, 800, 79500, 32, 48, 80, 6, 3, 14,
282 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
283 false, },
284 { 0x1B, HDMI_DVI },
285 },
286 {
287 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
288 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
289 false, },
290 { 0x55, HDMI_DVI },
291 },
Tomi Valkeinen7a7ce2c2012-10-24 11:55:39 +0300292 {
293 { 1920, 1200, 154000, 32, 48, 80, 6, 3, 26,
294 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
295 false, },
296 { 0x44, HDMI_DVI },
297 },
Mythri P Kc3198a52011-03-12 12:04:27 +0530298};
299
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +0300300static int hdmi_runtime_get(void)
301{
302 int r;
303
304 DSSDBG("hdmi_runtime_get\n");
305
306 r = pm_runtime_get_sync(&hdmi.pdev->dev);
307 WARN_ON(r < 0);
Archit Tanejaa247ce782012-02-10 11:45:52 +0530308 if (r < 0)
Tomi Valkeinen852f0832012-02-17 17:58:04 +0200309 return r;
Archit Tanejaa247ce782012-02-10 11:45:52 +0530310
311 return 0;
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +0300312}
313
314static void hdmi_runtime_put(void)
315{
316 int r;
317
318 DSSDBG("hdmi_runtime_put\n");
319
Tomi Valkeinen0eaf9f52012-01-23 13:23:08 +0200320 r = pm_runtime_put_sync(&hdmi.pdev->dev);
Tomi Valkeinen5be3aeb2012-06-27 16:37:18 +0300321 WARN_ON(r < 0 && r != -ENOSYS);
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +0300322}
323
Tomi Valkeinene25001d2013-05-10 15:20:52 +0300324static int hdmi_init_regulator(void)
325{
326 struct regulator *reg;
327
328 if (hdmi.vdda_hdmi_dac_reg != NULL)
329 return 0;
330
331 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda_hdmi_dac");
332
333 /* DT HACK: try VDAC to make omapdss work for o4 sdp/panda */
334 if (IS_ERR(reg))
335 reg = devm_regulator_get(&hdmi.pdev->dev, "VDAC");
336
337 if (IS_ERR(reg)) {
338 DSSERR("can't get VDDA_HDMI_DAC regulator\n");
339 return PTR_ERR(reg);
340 }
341
342 hdmi.vdda_hdmi_dac_reg = reg;
343
344 return 0;
345}
346
Mythri P K46095b22012-01-06 17:52:09 +0530347static const struct hdmi_config *hdmi_find_timing(
348 const struct hdmi_config *timings_arr,
349 int len)
Mythri P Kc3198a52011-03-12 12:04:27 +0530350{
Mythri P K46095b22012-01-06 17:52:09 +0530351 int i;
Mythri P Kc3198a52011-03-12 12:04:27 +0530352
Mythri P K46095b22012-01-06 17:52:09 +0530353 for (i = 0; i < len; i++) {
Mythri P K9e4ed602012-01-06 17:52:10 +0530354 if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code)
Mythri P K46095b22012-01-06 17:52:09 +0530355 return &timings_arr[i];
Mythri P Kc3198a52011-03-12 12:04:27 +0530356 }
Mythri P K46095b22012-01-06 17:52:09 +0530357 return NULL;
358}
359
360static const struct hdmi_config *hdmi_get_timings(void)
361{
362 const struct hdmi_config *arr;
363 int len;
364
Mythri P K9e4ed602012-01-06 17:52:10 +0530365 if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) {
Mythri P K46095b22012-01-06 17:52:09 +0530366 arr = vesa_timings;
367 len = ARRAY_SIZE(vesa_timings);
368 } else {
369 arr = cea_timings;
370 len = ARRAY_SIZE(cea_timings);
371 }
372
373 return hdmi_find_timing(arr, len);
374}
375
376static bool hdmi_timings_compare(struct omap_video_timings *timing1,
Archit Tanejacc937e52012-06-24 13:08:10 +0530377 const struct omap_video_timings *timing2)
Mythri P K46095b22012-01-06 17:52:09 +0530378{
379 int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
380
Tomi Valkeinenf236b892012-10-24 11:55:54 +0300381 if ((DIV_ROUND_CLOSEST(timing2->pixel_clock, 1000) ==
382 DIV_ROUND_CLOSEST(timing1->pixel_clock, 1000)) &&
Mythri P K46095b22012-01-06 17:52:09 +0530383 (timing2->x_res == timing1->x_res) &&
384 (timing2->y_res == timing1->y_res)) {
385
386 timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp;
387 timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp;
388 timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
389 timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
390
391 DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
392 "timing2_hsync = %d timing2_vsync = %d\n",
393 timing1_hsync, timing1_vsync,
394 timing2_hsync, timing2_vsync);
395
396 if ((timing1_hsync == timing2_hsync) &&
397 (timing1_vsync == timing2_vsync)) {
398 return true;
399 }
400 }
401 return false;
Mythri P Kc3198a52011-03-12 12:04:27 +0530402}
403
404static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
405{
Mythri P K46095b22012-01-06 17:52:09 +0530406 int i;
Mythri P Kc3198a52011-03-12 12:04:27 +0530407 struct hdmi_cm cm = {-1};
408 DSSDBG("hdmi_get_code\n");
409
Mythri P K46095b22012-01-06 17:52:09 +0530410 for (i = 0; i < ARRAY_SIZE(cea_timings); i++) {
411 if (hdmi_timings_compare(timing, &cea_timings[i].timings)) {
412 cm = cea_timings[i].cm;
413 goto end;
414 }
415 }
416 for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) {
417 if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) {
418 cm = vesa_timings[i].cm;
419 goto end;
Mythri P Kc3198a52011-03-12 12:04:27 +0530420 }
421 }
422
Mythri P K46095b22012-01-06 17:52:09 +0530423end: return cm;
Mythri P Kc3198a52011-03-12 12:04:27 +0530424
Mythri P Kc3198a52011-03-12 12:04:27 +0530425}
426
Tomi Valkeinenbb426fc92012-10-19 17:42:10 +0300427static int hdmi_power_on_core(struct omap_dss_device *dssdev)
Mythri P Kc3198a52011-03-12 12:04:27 +0530428{
Mythri P K46095b22012-01-06 17:52:09 +0530429 int r;
Mythri P Kc3198a52011-03-12 12:04:27 +0530430
Tomi Valkeinen17486942012-08-15 15:55:04 +0300431 r = regulator_enable(hdmi.vdda_hdmi_dac_reg);
432 if (r)
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300433 return r;
Tomi Valkeinen17486942012-08-15 15:55:04 +0300434
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +0300435 r = hdmi_runtime_get();
436 if (r)
Tomi Valkeinencca35012012-04-26 14:48:32 +0300437 goto err_runtime_get;
Mythri P Kc3198a52011-03-12 12:04:27 +0530438
Tomi Valkeinenbb426fc92012-10-19 17:42:10 +0300439 /* Make selection of HDMI in DSS */
440 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
441
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300442 hdmi.core_enabled = true;
443
Tomi Valkeinenbb426fc92012-10-19 17:42:10 +0300444 return 0;
445
446err_runtime_get:
447 regulator_disable(hdmi.vdda_hdmi_dac_reg);
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300448
Tomi Valkeinenbb426fc92012-10-19 17:42:10 +0300449 return r;
450}
451
452static void hdmi_power_off_core(struct omap_dss_device *dssdev)
453{
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300454 hdmi.core_enabled = false;
455
Tomi Valkeinenbb426fc92012-10-19 17:42:10 +0300456 hdmi_runtime_put();
457 regulator_disable(hdmi.vdda_hdmi_dac_reg);
Tomi Valkeinenbb426fc92012-10-19 17:42:10 +0300458}
459
460static int hdmi_power_on_full(struct omap_dss_device *dssdev)
461{
462 int r;
463 struct omap_video_timings *p;
Tomi Valkeinen7ae9a712013-05-10 15:27:07 +0300464 struct omap_overlay_manager *mgr = hdmi.output.manager;
Tomi Valkeinenbb426fc92012-10-19 17:42:10 +0300465 unsigned long phy;
466
467 r = hdmi_power_on_core(dssdev);
468 if (r)
469 return r;
470
Archit Tanejacea87b92012-09-07 17:56:20 +0530471 dss_mgr_disable(mgr);
Mythri P Kc3198a52011-03-12 12:04:27 +0530472
Archit Taneja78493982012-08-08 16:50:42 +0530473 p = &hdmi.ip_data.cfg.timings;
Mythri P Kc3198a52011-03-12 12:04:27 +0530474
Archit Taneja78493982012-08-08 16:50:42 +0530475 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
Mythri P Kc3198a52011-03-12 12:04:27 +0530476
Mythri P Kc3198a52011-03-12 12:04:27 +0530477 phy = p->pixel_clock;
478
Archit Tanejac1577c12013-10-08 12:55:26 +0530479 hdmi_pll_compute(&hdmi.ip_data.pll, clk_get_rate(hdmi.sys_clk), phy);
Mythri P Kc3198a52011-03-12 12:04:27 +0530480
Archit Tanejaf382d9e2013-08-06 14:56:55 +0530481 hdmi_wp_video_stop(&hdmi.ip_data.wp);
Mythri P Kc3198a52011-03-12 12:04:27 +0530482
Mythri P K95a8aeb2011-09-08 19:06:18 +0530483 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
Archit Tanejac1577c12013-10-08 12:55:26 +0530484 r = hdmi_pll_enable(&hdmi.ip_data.pll, &hdmi.ip_data.wp);
Mythri P Kc3198a52011-03-12 12:04:27 +0530485 if (r) {
486 DSSDBG("Failed to lock PLL\n");
Tomi Valkeinencca35012012-04-26 14:48:32 +0300487 goto err_pll_enable;
Mythri P Kc3198a52011-03-12 12:04:27 +0530488 }
489
Mythri P K60634a22011-09-08 19:06:26 +0530490 r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data);
Mythri P Kc3198a52011-03-12 12:04:27 +0530491 if (r) {
492 DSSDBG("Failed to start PHY\n");
Ricardo Nerid3b4aa52012-07-30 19:12:02 -0500493 goto err_phy_enable;
Mythri P Kc3198a52011-03-12 12:04:27 +0530494 }
495
Mythri P K60634a22011-09-08 19:06:26 +0530496 hdmi.ip_data.ops->video_configure(&hdmi.ip_data);
Mythri P Kc3198a52011-03-12 12:04:27 +0530497
Mythri P Kc3198a52011-03-12 12:04:27 +0530498 /* bypass TV gamma table */
499 dispc_enable_gamma_table(0);
500
501 /* tv size */
Archit Tanejacea87b92012-09-07 17:56:20 +0530502 dss_mgr_set_timings(mgr, p);
Mythri P Kc3198a52011-03-12 12:04:27 +0530503
Archit Tanejaf382d9e2013-08-06 14:56:55 +0530504 r = hdmi_wp_video_start(&hdmi.ip_data.wp);
Ricardo Neric0456be2012-04-27 13:48:45 -0500505 if (r)
506 goto err_vid_enable;
Mythri P Kc3198a52011-03-12 12:04:27 +0530507
Archit Tanejacea87b92012-09-07 17:56:20 +0530508 r = dss_mgr_enable(mgr);
Tomi Valkeinen33ca2372011-11-21 13:42:58 +0200509 if (r)
510 goto err_mgr_enable;
Tomi Valkeinen3870c902011-08-31 14:47:11 +0300511
Mythri P Kc3198a52011-03-12 12:04:27 +0530512 return 0;
Tomi Valkeinen33ca2372011-11-21 13:42:58 +0200513
514err_mgr_enable:
Archit Tanejaf382d9e2013-08-06 14:56:55 +0530515 hdmi_wp_video_stop(&hdmi.ip_data.wp);
Ricardo Neric0456be2012-04-27 13:48:45 -0500516err_vid_enable:
Tomi Valkeinen33ca2372011-11-21 13:42:58 +0200517 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
Ricardo Nerid3b4aa52012-07-30 19:12:02 -0500518err_phy_enable:
Archit Tanejac1577c12013-10-08 12:55:26 +0530519 hdmi_pll_disable(&hdmi.ip_data.pll, &hdmi.ip_data.wp);
Tomi Valkeinencca35012012-04-26 14:48:32 +0300520err_pll_enable:
Tomi Valkeinenbb426fc92012-10-19 17:42:10 +0300521 hdmi_power_off_core(dssdev);
Mythri P Kc3198a52011-03-12 12:04:27 +0530522 return -EIO;
523}
524
Tomi Valkeinenbb426fc92012-10-19 17:42:10 +0300525static void hdmi_power_off_full(struct omap_dss_device *dssdev)
Mythri P Kc3198a52011-03-12 12:04:27 +0530526{
Tomi Valkeinen7ae9a712013-05-10 15:27:07 +0300527 struct omap_overlay_manager *mgr = hdmi.output.manager;
Archit Tanejacea87b92012-09-07 17:56:20 +0530528
529 dss_mgr_disable(mgr);
Mythri P Kc3198a52011-03-12 12:04:27 +0530530
Archit Tanejaf382d9e2013-08-06 14:56:55 +0530531 hdmi_wp_video_stop(&hdmi.ip_data.wp);
Mythri P K60634a22011-09-08 19:06:26 +0530532 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
Archit Tanejac1577c12013-10-08 12:55:26 +0530533 hdmi_pll_disable(&hdmi.ip_data.pll, &hdmi.ip_data.wp);
Tomi Valkeinencca35012012-04-26 14:48:32 +0300534
Tomi Valkeinenbb426fc92012-10-19 17:42:10 +0300535 hdmi_power_off_core(dssdev);
Mythri P Kc3198a52011-03-12 12:04:27 +0530536}
537
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300538static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
Mythri P Kc3198a52011-03-12 12:04:27 +0530539 struct omap_video_timings *timings)
540{
541 struct hdmi_cm cm;
542
543 cm = hdmi_get_code(timings);
544 if (cm.code == -1) {
Mythri P Kc3198a52011-03-12 12:04:27 +0530545 return -EINVAL;
546 }
547
548 return 0;
549
550}
551
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300552static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
Archit Taneja78493982012-08-08 16:50:42 +0530553 struct omap_video_timings *timings)
Mythri P Kc3198a52011-03-12 12:04:27 +0530554{
555 struct hdmi_cm cm;
Archit Taneja78493982012-08-08 16:50:42 +0530556 const struct hdmi_config *t;
Mythri P Kc3198a52011-03-12 12:04:27 +0530557
Archit Tanejaed1aa902012-08-15 00:40:31 +0530558 mutex_lock(&hdmi.lock);
559
Archit Taneja78493982012-08-08 16:50:42 +0530560 cm = hdmi_get_code(timings);
561 hdmi.ip_data.cfg.cm = cm;
562
563 t = hdmi_get_timings();
Tomi Valkeinendb680c62013-08-27 14:11:48 +0300564 if (t != NULL) {
Archit Taneja78493982012-08-08 16:50:42 +0530565 hdmi.ip_data.cfg = *t;
Tomi Valkeinenfa70dc52011-08-22 14:57:33 +0300566
Tomi Valkeinendb680c62013-08-27 14:11:48 +0300567 dispc_set_tv_pclk(t->timings.pixel_clock * 1000);
568 }
Tomi Valkeinen5391e872013-05-16 10:44:13 +0300569
Archit Tanejaed1aa902012-08-15 00:40:31 +0530570 mutex_unlock(&hdmi.lock);
Mythri P Kc3198a52011-03-12 12:04:27 +0530571}
572
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300573static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300574 struct omap_video_timings *timings)
575{
576 const struct hdmi_config *cfg;
577
578 cfg = hdmi_get_timings();
579 if (cfg == NULL)
580 cfg = &vesa_timings[0];
581
582 memcpy(timings, &cfg->timings, sizeof(cfg->timings));
583}
584
Tomi Valkeinene40402c2012-03-02 18:01:07 +0200585static void hdmi_dump_regs(struct seq_file *s)
Mythri P K162874d2011-09-22 13:37:45 +0530586{
587 mutex_lock(&hdmi.lock);
588
Wei Yongjunf8fb7d72012-10-21 20:54:26 +0800589 if (hdmi_runtime_get()) {
590 mutex_unlock(&hdmi.lock);
Mythri P K162874d2011-09-22 13:37:45 +0530591 return;
Wei Yongjunf8fb7d72012-10-21 20:54:26 +0800592 }
Mythri P K162874d2011-09-22 13:37:45 +0530593
Archit Tanejaf382d9e2013-08-06 14:56:55 +0530594 hdmi_wp_dump(&hdmi.ip_data.wp, s);
Archit Tanejac1577c12013-10-08 12:55:26 +0530595 hdmi_pll_dump(&hdmi.ip_data.pll, s);
Mythri P K162874d2011-09-22 13:37:45 +0530596 hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s);
597 hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s);
598
599 hdmi_runtime_put();
600 mutex_unlock(&hdmi.lock);
601}
602
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300603static int read_edid(u8 *buf, int len)
Tomi Valkeinen47024562011-08-25 17:12:56 +0300604{
605 int r;
606
607 mutex_lock(&hdmi.lock);
608
609 r = hdmi_runtime_get();
610 BUG_ON(r);
611
612 r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len);
613
614 hdmi_runtime_put();
615 mutex_unlock(&hdmi.lock);
616
617 return r;
618}
619
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300620static int hdmi_display_enable(struct omap_dss_device *dssdev)
Mythri P Kc3198a52011-03-12 12:04:27 +0530621{
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +0300622 struct omap_dss_device *out = &hdmi.output;
Mythri P Kc3198a52011-03-12 12:04:27 +0530623 int r = 0;
624
625 DSSDBG("ENTER hdmi_display_enable\n");
626
627 mutex_lock(&hdmi.lock);
628
Archit Tanejacea87b92012-09-07 17:56:20 +0530629 if (out == NULL || out->manager == NULL) {
630 DSSERR("failed to enable display: no output/manager\n");
Tomi Valkeinen05e1d602011-06-23 16:38:21 +0300631 r = -ENODEV;
632 goto err0;
633 }
634
Tomi Valkeinenbb426fc92012-10-19 17:42:10 +0300635 r = hdmi_power_on_full(dssdev);
Mythri P Kc3198a52011-03-12 12:04:27 +0530636 if (r) {
637 DSSERR("failed to power on device\n");
Tomi Valkeinend3923932013-04-25 13:12:07 +0300638 goto err0;
Mythri P Kc3198a52011-03-12 12:04:27 +0530639 }
640
641 mutex_unlock(&hdmi.lock);
642 return 0;
643
Mythri P Kc3198a52011-03-12 12:04:27 +0530644err0:
645 mutex_unlock(&hdmi.lock);
646 return r;
647}
648
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300649static void hdmi_display_disable(struct omap_dss_device *dssdev)
Mythri P Kc3198a52011-03-12 12:04:27 +0530650{
651 DSSDBG("Enter hdmi_display_disable\n");
652
653 mutex_lock(&hdmi.lock);
654
Tomi Valkeinenbb426fc92012-10-19 17:42:10 +0300655 hdmi_power_off_full(dssdev);
Mythri P Kc3198a52011-03-12 12:04:27 +0530656
Mythri P Kc3198a52011-03-12 12:04:27 +0530657 mutex_unlock(&hdmi.lock);
658}
659
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300660static int hdmi_core_enable(struct omap_dss_device *dssdev)
Tomi Valkeinen44898232012-10-19 17:42:27 +0300661{
662 int r = 0;
663
664 DSSDBG("ENTER omapdss_hdmi_core_enable\n");
665
666 mutex_lock(&hdmi.lock);
667
Tomi Valkeinen44898232012-10-19 17:42:27 +0300668 r = hdmi_power_on_core(dssdev);
669 if (r) {
670 DSSERR("failed to power on device\n");
671 goto err0;
672 }
673
674 mutex_unlock(&hdmi.lock);
675 return 0;
676
677err0:
678 mutex_unlock(&hdmi.lock);
679 return r;
680}
681
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300682static void hdmi_core_disable(struct omap_dss_device *dssdev)
Tomi Valkeinen44898232012-10-19 17:42:27 +0300683{
684 DSSDBG("Enter omapdss_hdmi_core_disable\n");
685
686 mutex_lock(&hdmi.lock);
687
688 hdmi_power_off_core(dssdev);
689
690 mutex_unlock(&hdmi.lock);
691}
692
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +0300693static int hdmi_get_clocks(struct platform_device *pdev)
694{
695 struct clk *clk;
696
Archit Tanejab2c9c8e2013-04-08 11:55:00 +0300697 clk = devm_clk_get(&pdev->dev, "sys_clk");
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +0300698 if (IS_ERR(clk)) {
699 DSSERR("can't get sys_clk\n");
700 return PTR_ERR(clk);
701 }
702
703 hdmi.sys_clk = clk;
704
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +0300705 return 0;
706}
707
Ricardo Neri35547622012-03-20 21:02:01 -0600708#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
709int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts)
710{
711 u32 deep_color;
Ricardo Neri25a65352012-03-23 15:49:02 -0600712 bool deep_color_correct = false;
Ricardo Neri35547622012-03-20 21:02:01 -0600713 u32 pclk = hdmi.ip_data.cfg.timings.pixel_clock;
714
715 if (n == NULL || cts == NULL)
716 return -EINVAL;
717
718 /* TODO: When implemented, query deep color mode here. */
719 deep_color = 100;
720
Ricardo Neri25a65352012-03-23 15:49:02 -0600721 /*
722 * When using deep color, the default N value (as in the HDMI
723 * specification) yields to an non-integer CTS. Hence, we
724 * modify it while keeping the restrictions described in
725 * section 7.2.1 of the HDMI 1.4a specification.
726 */
Ricardo Neri35547622012-03-20 21:02:01 -0600727 switch (sample_freq) {
728 case 32000:
Ricardo Neri25a65352012-03-23 15:49:02 -0600729 case 48000:
730 case 96000:
731 case 192000:
732 if (deep_color == 125)
733 if (pclk == 27027 || pclk == 74250)
734 deep_color_correct = true;
735 if (deep_color == 150)
736 if (pclk == 27027)
737 deep_color_correct = true;
Ricardo Neri35547622012-03-20 21:02:01 -0600738 break;
739 case 44100:
Ricardo Neri25a65352012-03-23 15:49:02 -0600740 case 88200:
741 case 176400:
742 if (deep_color == 125)
743 if (pclk == 27027)
744 deep_color_correct = true;
Ricardo Neri35547622012-03-20 21:02:01 -0600745 break;
746 default:
Ricardo Neri35547622012-03-20 21:02:01 -0600747 return -EINVAL;
748 }
749
Ricardo Neri25a65352012-03-23 15:49:02 -0600750 if (deep_color_correct) {
751 switch (sample_freq) {
752 case 32000:
753 *n = 8192;
754 break;
755 case 44100:
756 *n = 12544;
757 break;
758 case 48000:
759 *n = 8192;
760 break;
761 case 88200:
762 *n = 25088;
763 break;
764 case 96000:
765 *n = 16384;
766 break;
767 case 176400:
768 *n = 50176;
769 break;
770 case 192000:
771 *n = 32768;
772 break;
773 default:
774 return -EINVAL;
775 }
776 } else {
777 switch (sample_freq) {
778 case 32000:
779 *n = 4096;
780 break;
781 case 44100:
782 *n = 6272;
783 break;
784 case 48000:
785 *n = 6144;
786 break;
787 case 88200:
788 *n = 12544;
789 break;
790 case 96000:
791 *n = 12288;
792 break;
793 case 176400:
794 *n = 25088;
795 break;
796 case 192000:
797 *n = 24576;
798 break;
799 default:
800 return -EINVAL;
801 }
802 }
Ricardo Neri35547622012-03-20 21:02:01 -0600803 /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
804 *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10);
805
806 return 0;
807}
Ricardo Nerif3a974912012-05-09 21:09:50 -0500808
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300809static bool hdmi_mode_has_audio(void)
Ricardo Nerif3a974912012-05-09 21:09:50 -0500810{
811 if (hdmi.ip_data.cfg.cm.mode == HDMI_HDMI)
812 return true;
813 else
814 return false;
815}
816
Ricardo Neri35547622012-03-20 21:02:01 -0600817#endif
818
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300819static int hdmi_connect(struct omap_dss_device *dssdev,
820 struct omap_dss_device *dst)
821{
822 struct omap_overlay_manager *mgr;
823 int r;
824
825 dss_init_hdmi_ip_ops(&hdmi.ip_data, omapdss_get_version());
826
827 r = hdmi_init_regulator();
828 if (r)
829 return r;
830
831 mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
832 if (!mgr)
833 return -ENODEV;
834
835 r = dss_mgr_connect(mgr, dssdev);
836 if (r)
837 return r;
838
839 r = omapdss_output_set_device(dssdev, dst);
840 if (r) {
841 DSSERR("failed to connect output to new device: %s\n",
842 dst->name);
843 dss_mgr_disconnect(mgr, dssdev);
844 return r;
845 }
846
847 return 0;
848}
849
850static void hdmi_disconnect(struct omap_dss_device *dssdev,
851 struct omap_dss_device *dst)
852{
Tomi Valkeinen9560dc102013-07-24 13:06:54 +0300853 WARN_ON(dst != dssdev->dst);
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300854
Tomi Valkeinen9560dc102013-07-24 13:06:54 +0300855 if (dst != dssdev->dst)
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300856 return;
857
858 omapdss_output_unset_device(dssdev);
859
860 if (dssdev->manager)
861 dss_mgr_disconnect(dssdev->manager, dssdev);
862}
863
864static int hdmi_read_edid(struct omap_dss_device *dssdev,
865 u8 *edid, int len)
866{
867 bool need_enable;
868 int r;
869
870 need_enable = hdmi.core_enabled == false;
871
872 if (need_enable) {
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300873 r = hdmi_core_enable(dssdev);
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300874 if (r)
875 return r;
876 }
877
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300878 r = read_edid(edid, len);
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300879
880 if (need_enable)
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300881 hdmi_core_disable(dssdev);
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300882
883 return r;
884}
885
886#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300887static int hdmi_audio_enable(struct omap_dss_device *dssdev)
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300888{
889 int r;
890
891 mutex_lock(&hdmi.lock);
892
893 if (!hdmi_mode_has_audio()) {
894 r = -EPERM;
895 goto err;
896 }
897
Archit Tanejaf382d9e2013-08-06 14:56:55 +0530898 r = hdmi_wp_audio_enable(&hdmi.ip_data.wp, true);
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300899 if (r)
900 goto err;
901
902 mutex_unlock(&hdmi.lock);
903 return 0;
904
905err:
906 mutex_unlock(&hdmi.lock);
907 return r;
908}
909
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300910static void hdmi_audio_disable(struct omap_dss_device *dssdev)
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300911{
Archit Tanejaf382d9e2013-08-06 14:56:55 +0530912 hdmi_wp_audio_enable(&hdmi.ip_data.wp, false);
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300913}
914
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300915static int hdmi_audio_start(struct omap_dss_device *dssdev)
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300916{
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300917 return hdmi.ip_data.ops->audio_start(&hdmi.ip_data);
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300918}
919
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300920static void hdmi_audio_stop(struct omap_dss_device *dssdev)
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300921{
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300922 hdmi.ip_data.ops->audio_stop(&hdmi.ip_data);
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300923}
924
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300925static bool hdmi_audio_supported(struct omap_dss_device *dssdev)
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300926{
927 bool r;
928
929 mutex_lock(&hdmi.lock);
930
931 r = hdmi_mode_has_audio();
932
933 mutex_unlock(&hdmi.lock);
934 return r;
935}
936
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300937static int hdmi_audio_config(struct omap_dss_device *dssdev,
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300938 struct omap_dss_audio *audio)
939{
940 int r;
941
942 mutex_lock(&hdmi.lock);
943
944 if (!hdmi_mode_has_audio()) {
945 r = -EPERM;
946 goto err;
947 }
948
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300949 r = hdmi.ip_data.ops->audio_config(&hdmi.ip_data, audio);
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300950 if (r)
951 goto err;
952
953 mutex_unlock(&hdmi.lock);
954 return 0;
955
956err:
957 mutex_unlock(&hdmi.lock);
958 return r;
959}
960#else
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300961static int hdmi_audio_enable(struct omap_dss_device *dssdev)
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300962{
963 return -EPERM;
964}
965
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300966static void hdmi_audio_disable(struct omap_dss_device *dssdev)
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300967{
968}
969
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300970static int hdmi_audio_start(struct omap_dss_device *dssdev)
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300971{
972 return -EPERM;
973}
974
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300975static void hdmi_audio_stop(struct omap_dss_device *dssdev)
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300976{
977}
978
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300979static bool hdmi_audio_supported(struct omap_dss_device *dssdev)
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300980{
981 return false;
982}
983
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300984static int hdmi_audio_config(struct omap_dss_device *dssdev,
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300985 struct omap_dss_audio *audio)
986{
987 return -EPERM;
988}
989#endif
990
991static const struct omapdss_hdmi_ops hdmi_ops = {
992 .connect = hdmi_connect,
993 .disconnect = hdmi_disconnect,
994
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300995 .enable = hdmi_display_enable,
996 .disable = hdmi_display_disable,
Tomi Valkeinen0b450c32013-05-24 13:20:17 +0300997
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +0300998 .check_timings = hdmi_display_check_timing,
999 .set_timings = hdmi_display_set_timing,
1000 .get_timings = hdmi_display_get_timings,
Tomi Valkeinen0b450c32013-05-24 13:20:17 +03001001
1002 .read_edid = hdmi_read_edid,
1003
Tomi Valkeinen164ebdd2013-05-15 10:48:45 +03001004 .audio_enable = hdmi_audio_enable,
1005 .audio_disable = hdmi_audio_disable,
1006 .audio_start = hdmi_audio_start,
1007 .audio_stop = hdmi_audio_stop,
1008 .audio_supported = hdmi_audio_supported,
1009 .audio_config = hdmi_audio_config,
Tomi Valkeinen0b450c32013-05-24 13:20:17 +03001010};
1011
Tomi Valkeinen17ae4e82013-04-26 14:48:43 +03001012static void hdmi_init_output(struct platform_device *pdev)
Archit Taneja81b87f52012-09-26 16:30:49 +05301013{
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +03001014 struct omap_dss_device *out = &hdmi.output;
Archit Taneja81b87f52012-09-26 16:30:49 +05301015
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +03001016 out->dev = &pdev->dev;
Archit Taneja81b87f52012-09-26 16:30:49 +05301017 out->id = OMAP_DSS_OUTPUT_HDMI;
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +03001018 out->output_type = OMAP_DISPLAY_TYPE_HDMI;
Tomi Valkeinen7286a082013-02-18 13:06:01 +02001019 out->name = "hdmi.0";
Tomi Valkeinen2eea5ae2013-02-13 11:23:54 +02001020 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
Tomi Valkeinen0b450c32013-05-24 13:20:17 +03001021 out->ops.hdmi = &hdmi_ops;
Tomi Valkeinenb7328e12013-05-03 11:42:18 +03001022 out->owner = THIS_MODULE;
Archit Taneja81b87f52012-09-26 16:30:49 +05301023
Tomi Valkeinen5d47dbc2013-04-24 13:32:51 +03001024 omapdss_register_output(out);
Archit Taneja81b87f52012-09-26 16:30:49 +05301025}
1026
1027static void __exit hdmi_uninit_output(struct platform_device *pdev)
1028{
Tomi Valkeinen1f68d9c2013-04-19 15:09:34 +03001029 struct omap_dss_device *out = &hdmi.output;
Archit Taneja81b87f52012-09-26 16:30:49 +05301030
Tomi Valkeinen5d47dbc2013-04-24 13:32:51 +03001031 omapdss_unregister_output(out);
Archit Taneja81b87f52012-09-26 16:30:49 +05301032}
1033
Mythri P Kc3198a52011-03-12 12:04:27 +05301034/* HDMI HW IP initialisation */
Tomi Valkeinen17ae4e82013-04-26 14:48:43 +03001035static int omapdss_hdmihw_probe(struct platform_device *pdev)
Mythri P Kc3198a52011-03-12 12:04:27 +05301036{
Tomi Valkeinen38f3daf2012-05-02 14:55:12 +03001037 int r;
Mythri P Kc3198a52011-03-12 12:04:27 +05301038
Mythri P Kc3198a52011-03-12 12:04:27 +05301039 hdmi.pdev = pdev;
1040
1041 mutex_init(&hdmi.lock);
Ricardo Neri66a06b02012-11-06 00:19:14 -06001042 mutex_init(&hdmi.ip_data.lock);
Mythri P Kc3198a52011-03-12 12:04:27 +05301043
Archit Tanejaf382d9e2013-08-06 14:56:55 +05301044 r = hdmi_wp_init(pdev, &hdmi.ip_data.wp);
1045 if (r)
1046 return r;
Mythri P Kc3198a52011-03-12 12:04:27 +05301047
Archit Tanejac1577c12013-10-08 12:55:26 +05301048 r = hdmi_pll_init(pdev, &hdmi.ip_data.pll);
1049 if (r)
1050 return r;
1051
Tomi Valkeinenddb1d5c2013-06-06 13:08:35 +03001052 hdmi.ip_data.irq = platform_get_irq(pdev, 0);
1053 if (hdmi.ip_data.irq < 0) {
1054 DSSERR("platform_get_irq failed\n");
1055 return -ENODEV;
1056 }
1057
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001058 r = hdmi_get_clocks(pdev);
1059 if (r) {
Ricardo Neri47e443b2012-11-06 00:19:12 -06001060 DSSERR("can't get clocks\n");
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001061 return r;
1062 }
1063
1064 pm_runtime_enable(&pdev->dev);
1065
Mythri P K95a8aeb2011-09-08 19:06:18 +05301066 hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS;
1067 hdmi.ip_data.core_av_offset = HDMI_CORE_AV;
Mythri P K95a8aeb2011-09-08 19:06:18 +05301068 hdmi.ip_data.phy_offset = HDMI_PHY;
Archit Taneja78493982012-08-08 16:50:42 +05301069
Tomi Valkeinen002d3682013-02-13 12:17:43 +02001070 hdmi_init_output(pdev);
1071
Tomi Valkeinene40402c2012-03-02 18:01:07 +02001072 dss_debugfs_create_file("hdmi", hdmi_dump_regs);
1073
Tomi Valkeinencca35012012-04-26 14:48:32 +03001074 return 0;
1075}
1076
Tomi Valkeinen6e7e8f02012-02-17 17:41:13 +02001077static int __exit omapdss_hdmihw_remove(struct platform_device *pdev)
Mythri P Kc3198a52011-03-12 12:04:27 +05301078{
Archit Taneja81b87f52012-09-26 16:30:49 +05301079 hdmi_uninit_output(pdev);
1080
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001081 pm_runtime_disable(&pdev->dev);
1082
Mythri P Kc3198a52011-03-12 12:04:27 +05301083 return 0;
1084}
1085
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001086static int hdmi_runtime_suspend(struct device *dev)
1087{
Rajendra Nayakf11766d2012-06-27 14:21:26 +05301088 clk_disable_unprepare(hdmi.sys_clk);
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001089
1090 dispc_runtime_put();
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001091
1092 return 0;
1093}
1094
1095static int hdmi_runtime_resume(struct device *dev)
1096{
1097 int r;
1098
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001099 r = dispc_runtime_get();
1100 if (r < 0)
Tomi Valkeinen852f0832012-02-17 17:58:04 +02001101 return r;
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001102
Rajendra Nayakf11766d2012-06-27 14:21:26 +05301103 clk_prepare_enable(hdmi.sys_clk);
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001104
1105 return 0;
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001106}
1107
1108static const struct dev_pm_ops hdmi_pm_ops = {
1109 .runtime_suspend = hdmi_runtime_suspend,
1110 .runtime_resume = hdmi_runtime_resume,
1111};
1112
Mythri P Kc3198a52011-03-12 12:04:27 +05301113static struct platform_driver omapdss_hdmihw_driver = {
Tomi Valkeinen17ae4e82013-04-26 14:48:43 +03001114 .probe = omapdss_hdmihw_probe,
Tomi Valkeinen6e7e8f02012-02-17 17:41:13 +02001115 .remove = __exit_p(omapdss_hdmihw_remove),
Mythri P Kc3198a52011-03-12 12:04:27 +05301116 .driver = {
1117 .name = "omapdss_hdmi",
1118 .owner = THIS_MODULE,
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001119 .pm = &hdmi_pm_ops,
Mythri P Kc3198a52011-03-12 12:04:27 +05301120 },
1121};
1122
Tomi Valkeinen6e7e8f02012-02-17 17:41:13 +02001123int __init hdmi_init_platform_driver(void)
Mythri P Kc3198a52011-03-12 12:04:27 +05301124{
Tomi Valkeinen17ae4e82013-04-26 14:48:43 +03001125 return platform_driver_register(&omapdss_hdmihw_driver);
Mythri P Kc3198a52011-03-12 12:04:27 +05301126}
1127
Tomi Valkeinen6e7e8f02012-02-17 17:41:13 +02001128void __exit hdmi_uninit_platform_driver(void)
Mythri P Kc3198a52011-03-12 12:04:27 +05301129{
Tomi Valkeinen04c742c2012-02-23 15:32:37 +02001130 platform_driver_unregister(&omapdss_hdmihw_driver);
Mythri P Kc3198a52011-03-12 12:04:27 +05301131}