blob: 3b6056ae457a30b765a1093928c56039fcc900e1 [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
Jiri Pirko22a67762017-02-03 10:29:07 +01003 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
Jiri Pirko1d20d232016-10-27 15:12:59 +020040#include <linux/pci.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020041#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010052#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020053#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020054#include <linux/dcbnl.h>
Ido Schimmel99724c12016-07-04 08:23:14 +020055#include <linux/inetdevice.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020056#include <net/switchdev.h>
Yotam Gigi763b4b72016-07-21 12:03:17 +020057#include <net/pkt_cls.h>
58#include <net/tc_act/tc_mirred.h>
Jiri Pirkoe7322632016-09-01 10:37:43 +020059#include <net/netevent.h>
Yotam Gigi98d0f7b2017-01-23 11:07:11 +010060#include <net/tc_act/tc_sample.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020061
62#include "spectrum.h"
Jiri Pirko1d20d232016-10-27 15:12:59 +020063#include "pci.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020064#include "core.h"
65#include "reg.h"
66#include "port.h"
67#include "trap.h"
68#include "txheader.h"
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +010069#include "spectrum_cnt.h"
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +020070#include "spectrum_dpipe.h"
Yotam Gigie5e5c882017-05-23 21:56:27 +020071#include "../mlxfw/mlxfw.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020072
Yotam Gigi6b742192017-05-23 21:56:29 +020073#define MLXSW_FWREV_MAJOR 13
74#define MLXSW_FWREV_MINOR 1420
75#define MLXSW_FWREV_SUBMINOR 122
76
77static const struct mlxsw_fw_rev mlxsw_sp_supported_fw_rev = {
78 .major = MLXSW_FWREV_MAJOR,
79 .minor = MLXSW_FWREV_MINOR,
80 .subminor = MLXSW_FWREV_SUBMINOR
81};
82
83#define MLXSW_SP_FW_FILENAME \
84 "mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \
85 "." __stringify(MLXSW_FWREV_MINOR) \
86 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2"
87
Jiri Pirko56ade8f2015-10-16 14:01:37 +020088static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
89static const char mlxsw_sp_driver_version[] = "1.0";
90
91/* tx_hdr_version
92 * Tx header version.
93 * Must be set to 1.
94 */
95MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
96
97/* tx_hdr_ctl
98 * Packet control type.
99 * 0 - Ethernet control (e.g. EMADs, LACP)
100 * 1 - Ethernet data
101 */
102MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
103
104/* tx_hdr_proto
105 * Packet protocol type. Must be set to 1 (Ethernet).
106 */
107MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
108
109/* tx_hdr_rx_is_router
110 * Packet is sent from the router. Valid for data packets only.
111 */
112MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
113
114/* tx_hdr_fid_valid
115 * Indicates if the 'fid' field is valid and should be used for
116 * forwarding lookup. Valid for data packets only.
117 */
118MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
119
120/* tx_hdr_swid
121 * Switch partition ID. Must be set to 0.
122 */
123MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
124
125/* tx_hdr_control_tclass
126 * Indicates if the packet should use the control TClass and not one
127 * of the data TClasses.
128 */
129MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
130
131/* tx_hdr_etclass
132 * Egress TClass to be used on the egress device on the egress port.
133 */
134MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
135
136/* tx_hdr_port_mid
137 * Destination local port for unicast packets.
138 * Destination multicast ID for multicast packets.
139 *
140 * Control packets are directed to a specific egress port, while data
141 * packets are transmitted through the CPU port (0) into the switch partition,
142 * where forwarding rules are applied.
143 */
144MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
145
146/* tx_hdr_fid
147 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
148 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
149 * Valid for data packets only.
150 */
151MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
152
153/* tx_hdr_type
154 * 0 - Data packets
155 * 6 - Control packets
156 */
157MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
158
Yotam Gigie5e5c882017-05-23 21:56:27 +0200159struct mlxsw_sp_mlxfw_dev {
160 struct mlxfw_dev mlxfw_dev;
161 struct mlxsw_sp *mlxsw_sp;
162};
163
164static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
165 u16 component_index, u32 *p_max_size,
166 u8 *p_align_bits, u16 *p_max_write_size)
167{
168 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
169 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
170 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
171 char mcqi_pl[MLXSW_REG_MCQI_LEN];
172 int err;
173
174 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
175 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
176 if (err)
177 return err;
178 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
179 p_max_write_size);
180
181 *p_align_bits = max_t(u8, *p_align_bits, 2);
182 *p_max_write_size = min_t(u16, *p_max_write_size,
183 MLXSW_REG_MCDA_MAX_DATA_LEN);
184 return 0;
185}
186
187static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
188{
189 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
190 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
191 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
192 char mcc_pl[MLXSW_REG_MCC_LEN];
193 u8 control_state;
194 int err;
195
196 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
197 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
198 if (err)
199 return err;
200
201 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
202 if (control_state != MLXFW_FSM_STATE_IDLE)
203 return -EBUSY;
204
205 mlxsw_reg_mcc_pack(mcc_pl,
206 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
207 0, *fwhandle, 0);
208 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
209}
210
211static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
212 u32 fwhandle, u16 component_index,
213 u32 component_size)
214{
215 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
216 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
217 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
218 char mcc_pl[MLXSW_REG_MCC_LEN];
219
220 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
221 component_index, fwhandle, component_size);
222 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
223}
224
225static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
226 u32 fwhandle, u8 *data, u16 size,
227 u32 offset)
228{
229 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
230 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
231 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
232 char mcda_pl[MLXSW_REG_MCDA_LEN];
233
234 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
235 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
236}
237
238static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
239 u32 fwhandle, u16 component_index)
240{
241 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
242 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
243 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
244 char mcc_pl[MLXSW_REG_MCC_LEN];
245
246 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
247 component_index, fwhandle, 0);
248 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
249}
250
251static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
252{
253 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
254 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
255 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
256 char mcc_pl[MLXSW_REG_MCC_LEN];
257
258 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
259 fwhandle, 0);
260 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
261}
262
263static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
264 enum mlxfw_fsm_state *fsm_state,
265 enum mlxfw_fsm_state_err *fsm_state_err)
266{
267 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
268 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
269 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
270 char mcc_pl[MLXSW_REG_MCC_LEN];
271 u8 control_state;
272 u8 error_code;
273 int err;
274
275 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
276 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
277 if (err)
278 return err;
279
280 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
281 *fsm_state = control_state;
282 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
283 MLXFW_FSM_STATE_ERR_MAX);
284 return 0;
285}
286
287static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
288{
289 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
290 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
291 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
292 char mcc_pl[MLXSW_REG_MCC_LEN];
293
294 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
295 fwhandle, 0);
296 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
297}
298
299static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
300{
301 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
302 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
303 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
304 char mcc_pl[MLXSW_REG_MCC_LEN];
305
306 mlxsw_reg_mcc_pack(mcc_pl,
307 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
308 fwhandle, 0);
309 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
310}
311
312static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
313 .component_query = mlxsw_sp_component_query,
314 .fsm_lock = mlxsw_sp_fsm_lock,
315 .fsm_component_update = mlxsw_sp_fsm_component_update,
316 .fsm_block_download = mlxsw_sp_fsm_block_download,
317 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
318 .fsm_activate = mlxsw_sp_fsm_activate,
319 .fsm_query_state = mlxsw_sp_fsm_query_state,
320 .fsm_cancel = mlxsw_sp_fsm_cancel,
321 .fsm_release = mlxsw_sp_fsm_release
322};
323
Yotam Gigi6b742192017-05-23 21:56:29 +0200324static bool mlxsw_sp_fw_rev_ge(const struct mlxsw_fw_rev *a,
325 const struct mlxsw_fw_rev *b)
326{
327 if (a->major != b->major)
328 return a->major > b->major;
329 if (a->minor != b->minor)
330 return a->minor > b->minor;
331 return a->subminor >= b->subminor;
332}
333
334static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
335{
336 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
337 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
338 .mlxfw_dev = {
339 .ops = &mlxsw_sp_mlxfw_dev_ops,
340 .psid = mlxsw_sp->bus_info->psid,
341 .psid_size = strlen(mlxsw_sp->bus_info->psid),
342 },
343 .mlxsw_sp = mlxsw_sp
344 };
345 const struct firmware *firmware;
346 int err;
347
348 if (mlxsw_sp_fw_rev_ge(rev, &mlxsw_sp_supported_fw_rev))
349 return 0;
350
351 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d out of data\n",
352 rev->major, rev->minor, rev->subminor);
353 dev_info(mlxsw_sp->bus_info->dev, "Upgrading firmware using file %s\n",
354 MLXSW_SP_FW_FILENAME);
355
356 err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME,
357 mlxsw_sp->bus_info->dev);
358 if (err) {
359 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
360 MLXSW_SP_FW_FILENAME);
361 return err;
362 }
363
364 err = mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
365 release_firmware(firmware);
366 return err;
367}
368
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100369int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
370 unsigned int counter_index, u64 *packets,
371 u64 *bytes)
372{
373 char mgpc_pl[MLXSW_REG_MGPC_LEN];
374 int err;
375
376 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
377 MLXSW_REG_MGPC_COUNTER_SET_TYPE_PACKETS_BYTES);
378 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
379 if (err)
380 return err;
381 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
382 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
383 return 0;
384}
385
386static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
387 unsigned int counter_index)
388{
389 char mgpc_pl[MLXSW_REG_MGPC_LEN];
390
391 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
392 MLXSW_REG_MGPC_COUNTER_SET_TYPE_PACKETS_BYTES);
393 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
394}
395
396int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
397 unsigned int *p_counter_index)
398{
399 int err;
400
401 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
402 p_counter_index);
403 if (err)
404 return err;
405 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
406 if (err)
407 goto err_counter_clear;
408 return 0;
409
410err_counter_clear:
411 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
412 *p_counter_index);
413 return err;
414}
415
416void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
417 unsigned int counter_index)
418{
419 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
420 counter_index);
421}
422
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200423static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
424 const struct mlxsw_tx_info *tx_info)
425{
426 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
427
428 memset(txhdr, 0, MLXSW_TXHDR_LEN);
429
430 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
431 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
432 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
433 mlxsw_tx_hdr_swid_set(txhdr, 0);
434 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
435 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
436 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
437}
438
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200439int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
440 u8 state)
441{
442 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
443 enum mlxsw_reg_spms_state spms_state;
444 char *spms_pl;
445 int err;
446
447 switch (state) {
448 case BR_STATE_FORWARDING:
449 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
450 break;
451 case BR_STATE_LEARNING:
452 spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
453 break;
454 case BR_STATE_LISTENING: /* fall-through */
455 case BR_STATE_DISABLED: /* fall-through */
456 case BR_STATE_BLOCKING:
457 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
458 break;
459 default:
460 BUG();
461 }
462
463 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
464 if (!spms_pl)
465 return -ENOMEM;
466 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
467 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
468
469 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
470 kfree(spms_pl);
471 return err;
472}
473
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200474static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
475{
Elad Raz5b090742016-10-28 21:35:46 +0200476 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200477 int err;
478
479 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
480 if (err)
481 return err;
482 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
483 return 0;
484}
485
Yotam Gigi763b4b72016-07-21 12:03:17 +0200486static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
487{
Yotam Gigi763b4b72016-07-21 12:03:17 +0200488 int i;
489
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200490 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
Yotam Gigi763b4b72016-07-21 12:03:17 +0200491 return -EIO;
492
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200493 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
494 MAX_SPAN);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200495 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
496 sizeof(struct mlxsw_sp_span_entry),
497 GFP_KERNEL);
498 if (!mlxsw_sp->span.entries)
499 return -ENOMEM;
500
501 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
502 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
503
504 return 0;
505}
506
507static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
508{
509 int i;
510
511 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
512 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
513
514 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
515 }
516 kfree(mlxsw_sp->span.entries);
517}
518
519static struct mlxsw_sp_span_entry *
520mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
521{
522 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
523 struct mlxsw_sp_span_entry *span_entry;
524 char mpat_pl[MLXSW_REG_MPAT_LEN];
525 u8 local_port = port->local_port;
526 int index;
527 int i;
528 int err;
529
530 /* find a free entry to use */
531 index = -1;
532 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
533 if (!mlxsw_sp->span.entries[i].used) {
534 index = i;
535 span_entry = &mlxsw_sp->span.entries[i];
536 break;
537 }
538 }
539 if (index < 0)
540 return NULL;
541
542 /* create a new port analayzer entry for local_port */
543 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
544 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
545 if (err)
546 return NULL;
547
548 span_entry->used = true;
549 span_entry->id = index;
Yotam Gigi2d644d42016-11-11 16:34:25 +0100550 span_entry->ref_count = 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200551 span_entry->local_port = local_port;
552 return span_entry;
553}
554
555static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
556 struct mlxsw_sp_span_entry *span_entry)
557{
558 u8 local_port = span_entry->local_port;
559 char mpat_pl[MLXSW_REG_MPAT_LEN];
560 int pa_id = span_entry->id;
561
562 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
563 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
564 span_entry->used = false;
565}
566
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200567static struct mlxsw_sp_span_entry *
568mlxsw_sp_span_entry_find(struct mlxsw_sp_port *port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200569{
570 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
571 int i;
572
573 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
574 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
575
576 if (curr->used && curr->local_port == port->local_port)
577 return curr;
578 }
579 return NULL;
580}
581
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200582static struct mlxsw_sp_span_entry
583*mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200584{
585 struct mlxsw_sp_span_entry *span_entry;
586
587 span_entry = mlxsw_sp_span_entry_find(port);
588 if (span_entry) {
Yotam Gigi2d644d42016-11-11 16:34:25 +0100589 /* Already exists, just take a reference */
Yotam Gigi763b4b72016-07-21 12:03:17 +0200590 span_entry->ref_count++;
591 return span_entry;
592 }
593
594 return mlxsw_sp_span_entry_create(port);
595}
596
597static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
598 struct mlxsw_sp_span_entry *span_entry)
599{
Yotam Gigi2d644d42016-11-11 16:34:25 +0100600 WARN_ON(!span_entry->ref_count);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200601 if (--span_entry->ref_count == 0)
602 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
603 return 0;
604}
605
606static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
607{
608 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
609 struct mlxsw_sp_span_inspected_port *p;
610 int i;
611
612 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
613 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
614
615 list_for_each_entry(p, &curr->bound_ports_list, list)
616 if (p->local_port == port->local_port &&
617 p->type == MLXSW_SP_SPAN_EGRESS)
618 return true;
619 }
620
621 return false;
622}
623
Ido Schimmel18281f22017-03-24 08:02:51 +0100624static int mlxsw_sp_span_mtu_to_buffsize(const struct mlxsw_sp *mlxsw_sp,
625 int mtu)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200626{
Ido Schimmel18281f22017-03-24 08:02:51 +0100627 return mlxsw_sp_bytes_cells(mlxsw_sp, mtu * 5 / 2) + 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200628}
629
630static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
631{
632 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
633 char sbib_pl[MLXSW_REG_SBIB_LEN];
634 int err;
635
636 /* If port is egress mirrored, the shared buffer size should be
637 * updated according to the mtu value
638 */
639 if (mlxsw_sp_span_is_egress_mirror(port)) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100640 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp, mtu);
641
642 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200643 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
644 if (err) {
645 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
646 return err;
647 }
648 }
649
650 return 0;
651}
652
653static struct mlxsw_sp_span_inspected_port *
654mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
655 struct mlxsw_sp_span_entry *span_entry)
656{
657 struct mlxsw_sp_span_inspected_port *p;
658
659 list_for_each_entry(p, &span_entry->bound_ports_list, list)
660 if (port->local_port == p->local_port)
661 return p;
662 return NULL;
663}
664
665static int
666mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
667 struct mlxsw_sp_span_entry *span_entry,
668 enum mlxsw_sp_span_type type)
669{
670 struct mlxsw_sp_span_inspected_port *inspected_port;
671 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
672 char mpar_pl[MLXSW_REG_MPAR_LEN];
673 char sbib_pl[MLXSW_REG_SBIB_LEN];
674 int pa_id = span_entry->id;
675 int err;
676
677 /* if it is an egress SPAN, bind a shared buffer to it */
678 if (type == MLXSW_SP_SPAN_EGRESS) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100679 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp,
680 port->dev->mtu);
681
682 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200683 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
684 if (err) {
685 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
686 return err;
687 }
688 }
689
690 /* bind the port to the SPAN entry */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200691 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
692 (enum mlxsw_reg_mpar_i_e) type, true, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200693 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
694 if (err)
695 goto err_mpar_reg_write;
696
697 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
698 if (!inspected_port) {
699 err = -ENOMEM;
700 goto err_inspected_port_alloc;
701 }
702 inspected_port->local_port = port->local_port;
703 inspected_port->type = type;
704 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
705
706 return 0;
707
708err_mpar_reg_write:
709err_inspected_port_alloc:
710 if (type == MLXSW_SP_SPAN_EGRESS) {
711 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
712 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
713 }
714 return err;
715}
716
717static void
718mlxsw_sp_span_inspected_port_unbind(struct mlxsw_sp_port *port,
719 struct mlxsw_sp_span_entry *span_entry,
720 enum mlxsw_sp_span_type type)
721{
722 struct mlxsw_sp_span_inspected_port *inspected_port;
723 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
724 char mpar_pl[MLXSW_REG_MPAR_LEN];
725 char sbib_pl[MLXSW_REG_SBIB_LEN];
726 int pa_id = span_entry->id;
727
728 inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
729 if (!inspected_port)
730 return;
731
732 /* remove the inspected port */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200733 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
734 (enum mlxsw_reg_mpar_i_e) type, false, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200735 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
736
737 /* remove the SBIB buffer if it was egress SPAN */
738 if (type == MLXSW_SP_SPAN_EGRESS) {
739 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
740 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
741 }
742
743 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
744
745 list_del(&inspected_port->list);
746 kfree(inspected_port);
747}
748
749static int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
750 struct mlxsw_sp_port *to,
751 enum mlxsw_sp_span_type type)
752{
753 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
754 struct mlxsw_sp_span_entry *span_entry;
755 int err;
756
757 span_entry = mlxsw_sp_span_entry_get(to);
758 if (!span_entry)
759 return -ENOENT;
760
761 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
762 span_entry->id);
763
764 err = mlxsw_sp_span_inspected_port_bind(from, span_entry, type);
765 if (err)
766 goto err_port_bind;
767
768 return 0;
769
770err_port_bind:
771 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
772 return err;
773}
774
775static void mlxsw_sp_span_mirror_remove(struct mlxsw_sp_port *from,
776 struct mlxsw_sp_port *to,
777 enum mlxsw_sp_span_type type)
778{
779 struct mlxsw_sp_span_entry *span_entry;
780
781 span_entry = mlxsw_sp_span_entry_find(to);
782 if (!span_entry) {
783 netdev_err(from->dev, "no span entry found\n");
784 return;
785 }
786
787 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
788 span_entry->id);
789 mlxsw_sp_span_inspected_port_unbind(from, span_entry, type);
790}
791
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100792static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
793 bool enable, u32 rate)
794{
795 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
796 char mpsc_pl[MLXSW_REG_MPSC_LEN];
797
798 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
799 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
800}
801
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200802static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
803 bool is_up)
804{
805 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
806 char paos_pl[MLXSW_REG_PAOS_LEN];
807
808 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
809 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
810 MLXSW_PORT_ADMIN_STATUS_DOWN);
811 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
812}
813
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200814static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
815 unsigned char *addr)
816{
817 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
818 char ppad_pl[MLXSW_REG_PPAD_LEN];
819
820 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
821 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
822 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
823}
824
825static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
826{
827 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
828 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
829
830 ether_addr_copy(addr, mlxsw_sp->base_mac);
831 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
832 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
833}
834
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200835static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
836{
837 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
838 char pmtu_pl[MLXSW_REG_PMTU_LEN];
839 int max_mtu;
840 int err;
841
842 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
843 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
844 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
845 if (err)
846 return err;
847 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
848
849 if (mtu > max_mtu)
850 return -EINVAL;
851
852 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
853 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
854}
855
Ido Schimmelbe945352016-06-09 09:51:39 +0200856static int __mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, u8 local_port,
857 u8 swid)
858{
859 char pspa_pl[MLXSW_REG_PSPA_LEN];
860
861 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
862 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
863}
864
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200865static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
866{
867 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200868
Ido Schimmelbe945352016-06-09 09:51:39 +0200869 return __mlxsw_sp_port_swid_set(mlxsw_sp, mlxsw_sp_port->local_port,
870 swid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200871}
872
873static int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
874 bool enable)
875{
876 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
877 char svpe_pl[MLXSW_REG_SVPE_LEN];
878
879 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
880 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
881}
882
883int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
884 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
885 u16 vid)
886{
887 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
888 char svfa_pl[MLXSW_REG_SVFA_LEN];
889
890 mlxsw_reg_svfa_pack(svfa_pl, mlxsw_sp_port->local_port, mt, valid,
891 fid, vid);
892 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
893}
894
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200895int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
896 bool learn_enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200897{
898 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
899 char *spvmlr_pl;
900 int err;
901
902 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
903 if (!spvmlr_pl)
904 return -ENOMEM;
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200905 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
906 learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200907 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
908 kfree(spvmlr_pl);
909 return err;
910}
911
Ido Schimmelb02eae92017-05-16 19:38:34 +0200912static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
913 u16 vid)
914{
915 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
916 char spvid_pl[MLXSW_REG_SPVID_LEN];
917
918 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
919 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
920}
921
922static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
923 bool allow)
924{
925 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
926 char spaft_pl[MLXSW_REG_SPAFT_LEN];
927
928 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
929 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
930}
931
932int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
933{
934 int err;
935
936 if (!vid) {
937 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
938 if (err)
939 return err;
940 } else {
941 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
942 if (err)
943 return err;
944 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
945 if (err)
946 goto err_port_allow_untagged_set;
947 }
948
949 mlxsw_sp_port->pvid = vid;
950 return 0;
951
952err_port_allow_untagged_set:
953 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
954 return err;
955}
956
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200957static int
958mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
959{
960 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
961 char sspr_pl[MLXSW_REG_SSPR_LEN];
962
963 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
964 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
965}
966
Ido Schimmeld664b412016-06-09 09:51:40 +0200967static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
968 u8 local_port, u8 *p_module,
969 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200970{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200971 char pmlp_pl[MLXSW_REG_PMLP_LEN];
972 int err;
973
Ido Schimmel558c2d52016-02-26 17:32:29 +0100974 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200975 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
976 if (err)
977 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100978 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
979 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200980 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200981 return 0;
982}
983
Ido Schimmel18f1e702016-02-26 17:32:31 +0100984static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
985 u8 module, u8 width, u8 lane)
986{
987 char pmlp_pl[MLXSW_REG_PMLP_LEN];
988 int i;
989
990 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
991 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
992 for (i = 0; i < width; i++) {
993 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
994 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
995 }
996
997 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
998}
999
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01001000static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
1001{
1002 char pmlp_pl[MLXSW_REG_PMLP_LEN];
1003
1004 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
1005 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
1006 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
1007}
1008
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001009static int mlxsw_sp_port_open(struct net_device *dev)
1010{
1011 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1012 int err;
1013
1014 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1015 if (err)
1016 return err;
1017 netif_start_queue(dev);
1018 return 0;
1019}
1020
1021static int mlxsw_sp_port_stop(struct net_device *dev)
1022{
1023 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1024
1025 netif_stop_queue(dev);
1026 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1027}
1028
1029static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
1030 struct net_device *dev)
1031{
1032 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1033 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1034 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
1035 const struct mlxsw_tx_info tx_info = {
1036 .local_port = mlxsw_sp_port->local_port,
1037 .is_emad = false,
1038 };
1039 u64 len;
1040 int err;
1041
Jiri Pirko307c2432016-04-08 19:11:22 +02001042 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001043 return NETDEV_TX_BUSY;
1044
1045 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
1046 struct sk_buff *skb_orig = skb;
1047
1048 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
1049 if (!skb) {
1050 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1051 dev_kfree_skb_any(skb_orig);
1052 return NETDEV_TX_OK;
1053 }
Arkadi Sharshevsky36bf38d2017-01-12 09:10:37 +01001054 dev_consume_skb_any(skb_orig);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001055 }
1056
1057 if (eth_skb_pad(skb)) {
1058 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1059 return NETDEV_TX_OK;
1060 }
1061
1062 mlxsw_sp_txhdr_construct(skb, &tx_info);
Nogah Frankel63dcdd32016-06-17 15:09:05 +02001063 /* TX header is consumed by HW on the way so we shouldn't count its
1064 * bytes as being sent.
1065 */
1066 len = skb->len - MLXSW_TXHDR_LEN;
1067
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001068 /* Due to a race we might fail here because of a full queue. In that
1069 * unlikely case we simply drop the packet.
1070 */
Jiri Pirko307c2432016-04-08 19:11:22 +02001071 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001072
1073 if (!err) {
1074 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
1075 u64_stats_update_begin(&pcpu_stats->syncp);
1076 pcpu_stats->tx_packets++;
1077 pcpu_stats->tx_bytes += len;
1078 u64_stats_update_end(&pcpu_stats->syncp);
1079 } else {
1080 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1081 dev_kfree_skb_any(skb);
1082 }
1083 return NETDEV_TX_OK;
1084}
1085
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001086static void mlxsw_sp_set_rx_mode(struct net_device *dev)
1087{
1088}
1089
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001090static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
1091{
1092 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1093 struct sockaddr *addr = p;
1094 int err;
1095
1096 if (!is_valid_ether_addr(addr->sa_data))
1097 return -EADDRNOTAVAIL;
1098
1099 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
1100 if (err)
1101 return err;
1102 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1103 return 0;
1104}
1105
Ido Schimmel18281f22017-03-24 08:02:51 +01001106static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
1107 int mtu)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001108{
Ido Schimmel18281f22017-03-24 08:02:51 +01001109 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001110}
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001111
Ido Schimmelf417f042017-03-24 08:02:50 +01001112#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
Ido Schimmel18281f22017-03-24 08:02:51 +01001113
1114static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1115 u16 delay)
Ido Schimmelf417f042017-03-24 08:02:50 +01001116{
Ido Schimmel18281f22017-03-24 08:02:51 +01001117 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
1118 BITS_PER_BYTE));
1119 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
1120 mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001121}
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001122
Ido Schimmel18281f22017-03-24 08:02:51 +01001123/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
Ido Schimmelf417f042017-03-24 08:02:50 +01001124 * Assumes 100m cable and maximum MTU.
1125 */
Ido Schimmel18281f22017-03-24 08:02:51 +01001126#define MLXSW_SP_PAUSE_DELAY 58752
1127
1128static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1129 u16 delay, bool pfc, bool pause)
Ido Schimmelf417f042017-03-24 08:02:50 +01001130{
1131 if (pfc)
Ido Schimmel18281f22017-03-24 08:02:51 +01001132 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
Ido Schimmelf417f042017-03-24 08:02:50 +01001133 else if (pause)
Ido Schimmel18281f22017-03-24 08:02:51 +01001134 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001135 else
Ido Schimmelf417f042017-03-24 08:02:50 +01001136 return 0;
1137}
1138
1139static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
1140 bool lossy)
1141{
1142 if (lossy)
1143 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
1144 else
1145 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
1146 thres);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001147}
1148
1149int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001150 u8 *prio_tc, bool pause_en,
1151 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +02001152{
1153 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001154 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
1155 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001156 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001157 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001158
1159 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
1160 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1161 if (err)
1162 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001163
1164 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1165 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001166 bool pfc = false;
Ido Schimmelf417f042017-03-24 08:02:50 +01001167 bool lossy;
1168 u16 thres;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001169
1170 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
1171 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001172 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001173 configure = true;
1174 break;
1175 }
1176 }
1177
1178 if (!configure)
1179 continue;
Ido Schimmelf417f042017-03-24 08:02:50 +01001180
1181 lossy = !(pfc || pause_en);
Ido Schimmel18281f22017-03-24 08:02:51 +01001182 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
1183 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
1184 pause_en);
Ido Schimmelf417f042017-03-24 08:02:50 +01001185 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001186 }
1187
Ido Schimmelff6551e2016-04-06 17:10:03 +02001188 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1189}
1190
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001191static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001192 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001193{
1194 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
1195 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001196 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001197 u8 *prio_tc;
1198
1199 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001200 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001201
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001202 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001203 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001204}
1205
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001206static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
1207{
1208 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001209 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001210 int err;
1211
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001212 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001213 if (err)
1214 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001215 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
1216 if (err)
1217 goto err_span_port_mtu_update;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001218 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
1219 if (err)
1220 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001221 dev->mtu = mtu;
1222 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001223
1224err_port_mtu_set:
Yotam Gigi763b4b72016-07-21 12:03:17 +02001225 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
1226err_span_port_mtu_update:
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001227 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +02001228 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001229}
1230
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001231static int
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001232mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
1233 struct rtnl_link_stats64 *stats)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001234{
1235 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1236 struct mlxsw_sp_port_pcpu_stats *p;
1237 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
1238 u32 tx_dropped = 0;
1239 unsigned int start;
1240 int i;
1241
1242 for_each_possible_cpu(i) {
1243 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
1244 do {
1245 start = u64_stats_fetch_begin_irq(&p->syncp);
1246 rx_packets = p->rx_packets;
1247 rx_bytes = p->rx_bytes;
1248 tx_packets = p->tx_packets;
1249 tx_bytes = p->tx_bytes;
1250 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
1251
1252 stats->rx_packets += rx_packets;
1253 stats->rx_bytes += rx_bytes;
1254 stats->tx_packets += tx_packets;
1255 stats->tx_bytes += tx_bytes;
1256 /* tx_dropped is u32, updated without syncp protection. */
1257 tx_dropped += p->tx_dropped;
1258 }
1259 stats->tx_dropped = tx_dropped;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001260 return 0;
1261}
1262
Or Gerlitz3df5b3c2016-11-22 23:09:54 +02001263static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001264{
1265 switch (attr_id) {
1266 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1267 return true;
1268 }
1269
1270 return false;
1271}
1272
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001273static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1274 void *sp)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001275{
1276 switch (attr_id) {
1277 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1278 return mlxsw_sp_port_get_sw_stats64(dev, sp);
1279 }
1280
1281 return -EINVAL;
1282}
1283
1284static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1285 int prio, char *ppcnt_pl)
1286{
1287 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1288 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1289
1290 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1291 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1292}
1293
1294static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1295 struct rtnl_link_stats64 *stats)
1296{
1297 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1298 int err;
1299
1300 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1301 0, ppcnt_pl);
1302 if (err)
1303 goto out;
1304
1305 stats->tx_packets =
1306 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1307 stats->rx_packets =
1308 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1309 stats->tx_bytes =
1310 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1311 stats->rx_bytes =
1312 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1313 stats->multicast =
1314 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1315
1316 stats->rx_crc_errors =
1317 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1318 stats->rx_frame_errors =
1319 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1320
1321 stats->rx_length_errors = (
1322 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1323 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1324 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1325
1326 stats->rx_errors = (stats->rx_crc_errors +
1327 stats->rx_frame_errors + stats->rx_length_errors);
1328
1329out:
1330 return err;
1331}
1332
1333static void update_stats_cache(struct work_struct *work)
1334{
1335 struct mlxsw_sp_port *mlxsw_sp_port =
1336 container_of(work, struct mlxsw_sp_port,
1337 hw_stats.update_dw.work);
1338
1339 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1340 goto out;
1341
1342 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
1343 mlxsw_sp_port->hw_stats.cache);
1344
1345out:
1346 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw,
1347 MLXSW_HW_STATS_UPDATE_TIME);
1348}
1349
1350/* Return the stats from a cache that is updated periodically,
1351 * as this function might get called in an atomic context.
1352 */
stephen hemmingerbc1f4472017-01-06 19:12:52 -08001353static void
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001354mlxsw_sp_port_get_stats64(struct net_device *dev,
1355 struct rtnl_link_stats64 *stats)
1356{
1357 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1358
1359 memcpy(stats, mlxsw_sp_port->hw_stats.cache, sizeof(*stats));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001360}
1361
Jiri Pirko93cd0812017-04-18 16:55:35 +02001362static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1363 u16 vid_begin, u16 vid_end,
1364 bool is_member, bool untagged)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001365{
1366 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1367 char *spvm_pl;
1368 int err;
1369
1370 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1371 if (!spvm_pl)
1372 return -ENOMEM;
1373
1374 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1375 vid_end, is_member, untagged);
1376 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1377 kfree(spvm_pl);
1378 return err;
1379}
1380
Jiri Pirko93cd0812017-04-18 16:55:35 +02001381int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1382 u16 vid_end, bool is_member, bool untagged)
1383{
1384 u16 vid, vid_e;
1385 int err;
1386
1387 for (vid = vid_begin; vid <= vid_end;
1388 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1389 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1390 vid_end);
1391
1392 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1393 is_member, untagged);
1394 if (err)
1395 return err;
1396 }
1397
1398 return 0;
1399}
1400
Ido Schimmel4aafc362017-05-26 08:37:25 +02001401int mlxsw_sp_port_vp_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001402{
1403 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001404 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1405 struct mlxsw_sp_fid *fid;
1406 u16 vid;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001407 int err;
1408
Ido Schimmelc57529e2017-05-26 08:37:31 +02001409 list_for_each_entry(mlxsw_sp_port_vlan, &mlxsw_sp_port->vlans_list,
1410 list) {
1411 fid = mlxsw_sp_port_vlan->fid;
1412
1413 if (!fid || fid->fid >= MLXSW_SP_VFID_BASE)
1414 continue;
1415
1416 vid = mlxsw_sp_port_vlan->vid;
1417 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true,
1418 fid->fid, vid);
1419 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001420 goto err_port_vid_to_fid_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001421 }
1422
1423 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001424 if (err)
1425 goto err_port_vp_mode_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001426
1427 return 0;
1428
Ido Schimmelc57529e2017-05-26 08:37:31 +02001429err_port_vp_mode_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001430err_port_vid_to_fid_set:
Ido Schimmelc57529e2017-05-26 08:37:31 +02001431 list_for_each_entry_continue_reverse(mlxsw_sp_port_vlan,
1432 &mlxsw_sp_port->vlans_list, list) {
1433 fid = mlxsw_sp_port_vlan->fid;
1434
1435 if (!fid || fid->fid >= MLXSW_SP_VFID_BASE)
1436 continue;
1437
1438 vid = mlxsw_sp_port_vlan->vid;
1439 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, fid->fid,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001440 vid);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001441 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001442 return err;
1443}
1444
Ido Schimmel4aafc362017-05-26 08:37:25 +02001445int mlxsw_sp_port_vlan_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001446{
1447 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001448 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001449 int err;
1450
1451 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
1452 if (err)
1453 return err;
1454
Ido Schimmelc57529e2017-05-26 08:37:31 +02001455 list_for_each_entry_reverse(mlxsw_sp_port_vlan,
1456 &mlxsw_sp_port->vlans_list, list) {
1457 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1458 u16 vid = mlxsw_sp_port_vlan->vid;
1459
1460 if (!fid || fid->fid >= MLXSW_SP_VFID_BASE)
1461 continue;
1462
1463 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, fid->fid,
1464 vid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001465 }
1466
1467 return 0;
1468}
1469
Ido Schimmelc57529e2017-05-26 08:37:31 +02001470static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001471{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001472 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001473
Ido Schimmelc57529e2017-05-26 08:37:31 +02001474 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1475 &mlxsw_sp_port->vlans_list, list)
1476 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001477}
1478
Ido Schimmel31a08a52017-05-26 08:37:26 +02001479static struct mlxsw_sp_port_vlan *
1480mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1481{
1482 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001483 bool untagged = vid == 1;
1484 int err;
1485
1486 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1487 if (err)
1488 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001489
1490 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001491 if (!mlxsw_sp_port_vlan) {
1492 err = -ENOMEM;
1493 goto err_port_vlan_alloc;
1494 }
Ido Schimmel31a08a52017-05-26 08:37:26 +02001495
1496 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1497 mlxsw_sp_port_vlan->vid = vid;
1498 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1499
1500 return mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001501
1502err_port_vlan_alloc:
1503 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1504 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001505}
1506
1507static void
1508mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1509{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001510 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1511 u16 vid = mlxsw_sp_port_vlan->vid;
Ido Schimmel7cbecf22017-05-26 08:37:28 +02001512
Ido Schimmel31a08a52017-05-26 08:37:26 +02001513 list_del(&mlxsw_sp_port_vlan->list);
1514 kfree(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001515 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1516}
1517
1518struct mlxsw_sp_port_vlan *
1519mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1520{
1521 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1522
1523 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1524 if (mlxsw_sp_port_vlan)
1525 return mlxsw_sp_port_vlan;
1526
1527 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1528}
1529
1530void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1531{
1532 if (mlxsw_sp_port_vlan->bridge_port)
1533 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
1534 else if (mlxsw_sp_port_vlan->fid)
1535 mlxsw_sp_port_vlan->fid->leave(mlxsw_sp_port_vlan);
1536
1537 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001538}
1539
Ido Schimmel05978482016-08-17 16:39:30 +02001540static int mlxsw_sp_port_add_vid(struct net_device *dev,
1541 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001542{
1543 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001544
1545 /* VLAN 0 is added to HW filter when device goes up, but it is
1546 * reserved in our case, so simply return.
1547 */
1548 if (!vid)
1549 return 0;
1550
Ido Schimmelc57529e2017-05-26 08:37:31 +02001551 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001552}
1553
Ido Schimmel32d863f2016-07-02 11:00:10 +02001554static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1555 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001556{
1557 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001558 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001559
1560 /* VLAN 0 is removed from HW filter when device goes down, but
1561 * it is reserved in our case, so simply return.
1562 */
1563 if (!vid)
1564 return 0;
1565
Ido Schimmel31a08a52017-05-26 08:37:26 +02001566 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001567 if (!mlxsw_sp_port_vlan)
Ido Schimmel31a08a52017-05-26 08:37:26 +02001568 return 0;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001569 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001570
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001571 return 0;
1572}
1573
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001574static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1575 size_t len)
1576{
1577 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmeld664b412016-06-09 09:51:40 +02001578 u8 module = mlxsw_sp_port->mapping.module;
1579 u8 width = mlxsw_sp_port->mapping.width;
1580 u8 lane = mlxsw_sp_port->mapping.lane;
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001581 int err;
1582
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001583 if (!mlxsw_sp_port->split)
1584 err = snprintf(name, len, "p%d", module + 1);
1585 else
1586 err = snprintf(name, len, "p%ds%d", module + 1,
1587 lane / width);
1588
1589 if (err >= len)
1590 return -EINVAL;
1591
1592 return 0;
1593}
1594
Yotam Gigi763b4b72016-07-21 12:03:17 +02001595static struct mlxsw_sp_port_mall_tc_entry *
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001596mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1597 unsigned long cookie) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001598 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1599
1600 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1601 if (mall_tc_entry->cookie == cookie)
1602 return mall_tc_entry;
1603
1604 return NULL;
1605}
1606
1607static int
1608mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001609 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001610 const struct tc_action *a,
1611 bool ingress)
1612{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001613 struct net *net = dev_net(mlxsw_sp_port->dev);
1614 enum mlxsw_sp_span_type span_type;
1615 struct mlxsw_sp_port *to_port;
1616 struct net_device *to_dev;
1617 int ifindex;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001618
1619 ifindex = tcf_mirred_ifindex(a);
1620 to_dev = __dev_get_by_index(net, ifindex);
1621 if (!to_dev) {
1622 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1623 return -EINVAL;
1624 }
1625
1626 if (!mlxsw_sp_port_dev_check(to_dev)) {
1627 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
Yotam Gigie915ac62017-01-09 11:25:48 +01001628 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001629 }
1630 to_port = netdev_priv(to_dev);
1631
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001632 mirror->to_local_port = to_port->local_port;
1633 mirror->ingress = ingress;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001634 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001635 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type);
1636}
Yotam Gigi763b4b72016-07-21 12:03:17 +02001637
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001638static void
1639mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1640 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1641{
1642 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1643 enum mlxsw_sp_span_type span_type;
1644 struct mlxsw_sp_port *to_port;
1645
1646 to_port = mlxsw_sp->ports[mirror->to_local_port];
1647 span_type = mirror->ingress ?
1648 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1649 mlxsw_sp_span_mirror_remove(mlxsw_sp_port, to_port, span_type);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001650}
1651
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001652static int
1653mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1654 struct tc_cls_matchall_offload *cls,
1655 const struct tc_action *a,
1656 bool ingress)
1657{
1658 int err;
1659
1660 if (!mlxsw_sp_port->sample)
1661 return -EOPNOTSUPP;
1662 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1663 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1664 return -EEXIST;
1665 }
1666 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1667 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1668 return -EOPNOTSUPP;
1669 }
1670
1671 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1672 tcf_sample_psample_group(a));
1673 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1674 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1675 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1676
1677 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1678 if (err)
1679 goto err_port_sample_set;
1680 return 0;
1681
1682err_port_sample_set:
1683 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1684 return err;
1685}
1686
1687static void
1688mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1689{
1690 if (!mlxsw_sp_port->sample)
1691 return;
1692
1693 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1694 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1695}
1696
Yotam Gigi763b4b72016-07-21 12:03:17 +02001697static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1698 __be16 protocol,
1699 struct tc_cls_matchall_offload *cls,
1700 bool ingress)
1701{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001702 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001703 const struct tc_action *a;
WANG Cong22dc13c2016-08-13 22:35:00 -07001704 LIST_HEAD(actions);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001705 int err;
1706
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001707 if (!tc_single_action(cls->exts)) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001708 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
Yotam Gigie915ac62017-01-09 11:25:48 +01001709 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001710 }
1711
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001712 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1713 if (!mall_tc_entry)
1714 return -ENOMEM;
1715 mall_tc_entry->cookie = cls->cookie;
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001716
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001717 tcf_exts_to_list(cls->exts, &actions);
1718 a = list_first_entry(&actions, struct tc_action, list);
1719
1720 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1721 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1722
1723 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1724 mirror = &mall_tc_entry->mirror;
1725 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1726 mirror, a, ingress);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001727 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1728 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
1729 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, cls,
1730 a, ingress);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001731 } else {
1732 err = -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001733 }
1734
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001735 if (err)
1736 goto err_add_action;
1737
1738 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001739 return 0;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001740
1741err_add_action:
1742 kfree(mall_tc_entry);
1743 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001744}
1745
1746static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1747 struct tc_cls_matchall_offload *cls)
1748{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001749 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001750
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001751 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
1752 cls->cookie);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001753 if (!mall_tc_entry) {
1754 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1755 return;
1756 }
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001757 list_del(&mall_tc_entry->list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001758
1759 switch (mall_tc_entry->type) {
1760 case MLXSW_SP_PORT_MALL_MIRROR:
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001761 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1762 &mall_tc_entry->mirror);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001763 break;
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001764 case MLXSW_SP_PORT_MALL_SAMPLE:
1765 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1766 break;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001767 default:
1768 WARN_ON(1);
1769 }
1770
Yotam Gigi763b4b72016-07-21 12:03:17 +02001771 kfree(mall_tc_entry);
1772}
1773
1774static int mlxsw_sp_setup_tc(struct net_device *dev, u32 handle,
1775 __be16 proto, struct tc_to_netdev *tc)
1776{
1777 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1778 bool ingress = TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS);
1779
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +01001780 switch (tc->type) {
1781 case TC_SETUP_MATCHALL:
Yotam Gigi763b4b72016-07-21 12:03:17 +02001782 switch (tc->cls_mall->command) {
1783 case TC_CLSMATCHALL_REPLACE:
1784 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port,
1785 proto,
1786 tc->cls_mall,
1787 ingress);
1788 case TC_CLSMATCHALL_DESTROY:
1789 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port,
1790 tc->cls_mall);
1791 return 0;
1792 default:
Or Gerlitzabbdf4b2017-03-17 09:38:01 +01001793 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001794 }
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +01001795 case TC_SETUP_CLSFLOWER:
1796 switch (tc->cls_flower->command) {
1797 case TC_CLSFLOWER_REPLACE:
1798 return mlxsw_sp_flower_replace(mlxsw_sp_port, ingress,
1799 proto, tc->cls_flower);
1800 case TC_CLSFLOWER_DESTROY:
1801 mlxsw_sp_flower_destroy(mlxsw_sp_port, ingress,
1802 tc->cls_flower);
1803 return 0;
Arkadi Sharshevsky7c1b8eb2017-03-11 09:42:59 +01001804 case TC_CLSFLOWER_STATS:
1805 return mlxsw_sp_flower_stats(mlxsw_sp_port, ingress,
1806 tc->cls_flower);
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +01001807 default:
1808 return -EOPNOTSUPP;
1809 }
Yotam Gigi763b4b72016-07-21 12:03:17 +02001810 }
1811
Yotam Gigie915ac62017-01-09 11:25:48 +01001812 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001813}
1814
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001815static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1816 .ndo_open = mlxsw_sp_port_open,
1817 .ndo_stop = mlxsw_sp_port_stop,
1818 .ndo_start_xmit = mlxsw_sp_port_xmit,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001819 .ndo_setup_tc = mlxsw_sp_setup_tc,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001820 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001821 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1822 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1823 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001824 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1825 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001826 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1827 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
1828 .ndo_fdb_add = switchdev_port_fdb_add,
1829 .ndo_fdb_del = switchdev_port_fdb_del,
1830 .ndo_fdb_dump = switchdev_port_fdb_dump,
1831 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
1832 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
1833 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001834 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001835};
1836
1837static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1838 struct ethtool_drvinfo *drvinfo)
1839{
1840 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1841 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1842
1843 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1844 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1845 sizeof(drvinfo->version));
1846 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1847 "%d.%d.%d",
1848 mlxsw_sp->bus_info->fw_rev.major,
1849 mlxsw_sp->bus_info->fw_rev.minor,
1850 mlxsw_sp->bus_info->fw_rev.subminor);
1851 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1852 sizeof(drvinfo->bus_info));
1853}
1854
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001855static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1856 struct ethtool_pauseparam *pause)
1857{
1858 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1859
1860 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1861 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1862}
1863
1864static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1865 struct ethtool_pauseparam *pause)
1866{
1867 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1868
1869 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1870 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1871 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1872
1873 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1874 pfcc_pl);
1875}
1876
1877static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1878 struct ethtool_pauseparam *pause)
1879{
1880 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1881 bool pause_en = pause->tx_pause || pause->rx_pause;
1882 int err;
1883
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001884 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1885 netdev_err(dev, "PFC already enabled on port\n");
1886 return -EINVAL;
1887 }
1888
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001889 if (pause->autoneg) {
1890 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1891 return -EINVAL;
1892 }
1893
1894 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1895 if (err) {
1896 netdev_err(dev, "Failed to configure port's headroom\n");
1897 return err;
1898 }
1899
1900 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1901 if (err) {
1902 netdev_err(dev, "Failed to set PAUSE parameters\n");
1903 goto err_port_pause_configure;
1904 }
1905
1906 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1907 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1908
1909 return 0;
1910
1911err_port_pause_configure:
1912 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1913 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1914 return err;
1915}
1916
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001917struct mlxsw_sp_port_hw_stats {
1918 char str[ETH_GSTRING_LEN];
Jiri Pirko412791d2016-10-21 16:07:19 +02001919 u64 (*getter)(const char *payload);
Ido Schimmel18281f22017-03-24 08:02:51 +01001920 bool cells_bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001921};
1922
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001923static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001924 {
1925 .str = "a_frames_transmitted_ok",
1926 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1927 },
1928 {
1929 .str = "a_frames_received_ok",
1930 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1931 },
1932 {
1933 .str = "a_frame_check_sequence_errors",
1934 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1935 },
1936 {
1937 .str = "a_alignment_errors",
1938 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1939 },
1940 {
1941 .str = "a_octets_transmitted_ok",
1942 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1943 },
1944 {
1945 .str = "a_octets_received_ok",
1946 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1947 },
1948 {
1949 .str = "a_multicast_frames_xmitted_ok",
1950 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1951 },
1952 {
1953 .str = "a_broadcast_frames_xmitted_ok",
1954 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1955 },
1956 {
1957 .str = "a_multicast_frames_received_ok",
1958 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1959 },
1960 {
1961 .str = "a_broadcast_frames_received_ok",
1962 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1963 },
1964 {
1965 .str = "a_in_range_length_errors",
1966 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1967 },
1968 {
1969 .str = "a_out_of_range_length_field",
1970 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1971 },
1972 {
1973 .str = "a_frame_too_long_errors",
1974 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1975 },
1976 {
1977 .str = "a_symbol_error_during_carrier",
1978 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1979 },
1980 {
1981 .str = "a_mac_control_frames_transmitted",
1982 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1983 },
1984 {
1985 .str = "a_mac_control_frames_received",
1986 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1987 },
1988 {
1989 .str = "a_unsupported_opcodes_received",
1990 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1991 },
1992 {
1993 .str = "a_pause_mac_ctrl_frames_received",
1994 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1995 },
1996 {
1997 .str = "a_pause_mac_ctrl_frames_xmitted",
1998 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1999 },
2000};
2001
2002#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
2003
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002004static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
2005 {
2006 .str = "rx_octets_prio",
2007 .getter = mlxsw_reg_ppcnt_rx_octets_get,
2008 },
2009 {
2010 .str = "rx_frames_prio",
2011 .getter = mlxsw_reg_ppcnt_rx_frames_get,
2012 },
2013 {
2014 .str = "tx_octets_prio",
2015 .getter = mlxsw_reg_ppcnt_tx_octets_get,
2016 },
2017 {
2018 .str = "tx_frames_prio",
2019 .getter = mlxsw_reg_ppcnt_tx_frames_get,
2020 },
2021 {
2022 .str = "rx_pause_prio",
2023 .getter = mlxsw_reg_ppcnt_rx_pause_get,
2024 },
2025 {
2026 .str = "rx_pause_duration_prio",
2027 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
2028 },
2029 {
2030 .str = "tx_pause_prio",
2031 .getter = mlxsw_reg_ppcnt_tx_pause_get,
2032 },
2033 {
2034 .str = "tx_pause_duration_prio",
2035 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
2036 },
2037};
2038
2039#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
2040
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002041static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
2042 {
2043 .str = "tc_transmit_queue_tc",
Ido Schimmel18281f22017-03-24 08:02:51 +01002044 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
2045 .cells_bytes = true,
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002046 },
2047 {
2048 .str = "tc_no_buffer_discard_uc_tc",
2049 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
2050 },
2051};
2052
2053#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
2054
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002055#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002056 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
2057 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002058 IEEE_8021QAZ_MAX_TCS)
2059
2060static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
2061{
2062 int i;
2063
2064 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
2065 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2066 mlxsw_sp_port_hw_prio_stats[i].str, prio);
2067 *p += ETH_GSTRING_LEN;
2068 }
2069}
2070
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002071static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
2072{
2073 int i;
2074
2075 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
2076 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2077 mlxsw_sp_port_hw_tc_stats[i].str, tc);
2078 *p += ETH_GSTRING_LEN;
2079 }
2080}
2081
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002082static void mlxsw_sp_port_get_strings(struct net_device *dev,
2083 u32 stringset, u8 *data)
2084{
2085 u8 *p = data;
2086 int i;
2087
2088 switch (stringset) {
2089 case ETH_SS_STATS:
2090 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2091 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2092 ETH_GSTRING_LEN);
2093 p += ETH_GSTRING_LEN;
2094 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002095
2096 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2097 mlxsw_sp_port_get_prio_strings(&p, i);
2098
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002099 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2100 mlxsw_sp_port_get_tc_strings(&p, i);
2101
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002102 break;
2103 }
2104}
2105
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002106static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2107 enum ethtool_phys_id_state state)
2108{
2109 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2110 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2111 char mlcr_pl[MLXSW_REG_MLCR_LEN];
2112 bool active;
2113
2114 switch (state) {
2115 case ETHTOOL_ID_ACTIVE:
2116 active = true;
2117 break;
2118 case ETHTOOL_ID_INACTIVE:
2119 active = false;
2120 break;
2121 default:
2122 return -EOPNOTSUPP;
2123 }
2124
2125 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2126 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2127}
2128
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002129static int
2130mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2131 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2132{
2133 switch (grp) {
2134 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2135 *p_hw_stats = mlxsw_sp_port_hw_stats;
2136 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2137 break;
2138 case MLXSW_REG_PPCNT_PRIO_CNT:
2139 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2140 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2141 break;
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002142 case MLXSW_REG_PPCNT_TC_CNT:
2143 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2144 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2145 break;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002146 default:
2147 WARN_ON(1);
Yotam Gigie915ac62017-01-09 11:25:48 +01002148 return -EOPNOTSUPP;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002149 }
2150 return 0;
2151}
2152
2153static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2154 enum mlxsw_reg_ppcnt_grp grp, int prio,
2155 u64 *data, int data_index)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002156{
Ido Schimmel18281f22017-03-24 08:02:51 +01002157 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2158 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002159 struct mlxsw_sp_port_hw_stats *hw_stats;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002160 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002161 int i, len;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002162 int err;
2163
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002164 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2165 if (err)
2166 return;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002167 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002168 for (i = 0; i < len; i++) {
Colin Ian Kingfaac0ff2016-09-23 12:02:45 +01002169 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002170 if (!hw_stats[i].cells_bytes)
2171 continue;
2172 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2173 data[data_index + i]);
2174 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002175}
2176
2177static void mlxsw_sp_port_get_stats(struct net_device *dev,
2178 struct ethtool_stats *stats, u64 *data)
2179{
2180 int i, data_index = 0;
2181
2182 /* IEEE 802.3 Counters */
2183 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2184 data, data_index);
2185 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2186
2187 /* Per-Priority Counters */
2188 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2189 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2190 data, data_index);
2191 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2192 }
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002193
2194 /* Per-TC Counters */
2195 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2196 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2197 data, data_index);
2198 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2199 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002200}
2201
2202static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2203{
2204 switch (sset) {
2205 case ETH_SS_STATS:
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002206 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002207 default:
2208 return -EOPNOTSUPP;
2209 }
2210}
2211
2212struct mlxsw_sp_port_link_mode {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002213 enum ethtool_link_mode_bit_indices mask_ethtool;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002214 u32 mask;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002215 u32 speed;
2216};
2217
2218static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2219 {
2220 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002221 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2222 .speed = SPEED_100,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002223 },
2224 {
2225 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2226 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002227 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2228 .speed = SPEED_1000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002229 },
2230 {
2231 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002232 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2233 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002234 },
2235 {
2236 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2237 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002238 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2239 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002240 },
2241 {
2242 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2243 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2244 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2245 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002246 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2247 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002248 },
2249 {
2250 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002251 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2252 .speed = SPEED_20000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002253 },
2254 {
2255 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002256 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2257 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002258 },
2259 {
2260 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002261 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2262 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002263 },
2264 {
2265 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002266 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2267 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002268 },
2269 {
2270 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002271 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2272 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002273 },
2274 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002275 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2276 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2277 .speed = SPEED_25000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002278 },
2279 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002280 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2281 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2282 .speed = SPEED_25000,
2283 },
2284 {
2285 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2286 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2287 .speed = SPEED_25000,
2288 },
2289 {
2290 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2291 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2292 .speed = SPEED_25000,
2293 },
2294 {
2295 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2296 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2297 .speed = SPEED_50000,
2298 },
2299 {
2300 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2301 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2302 .speed = SPEED_50000,
2303 },
2304 {
2305 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2306 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2307 .speed = SPEED_50000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002308 },
2309 {
2310 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002311 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2312 .speed = SPEED_56000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002313 },
2314 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002315 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2316 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2317 .speed = SPEED_56000,
2318 },
2319 {
2320 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2321 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2322 .speed = SPEED_56000,
2323 },
2324 {
2325 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2326 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2327 .speed = SPEED_56000,
2328 },
2329 {
2330 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2331 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2332 .speed = SPEED_100000,
2333 },
2334 {
2335 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2336 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2337 .speed = SPEED_100000,
2338 },
2339 {
2340 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2341 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2342 .speed = SPEED_100000,
2343 },
2344 {
2345 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2346 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2347 .speed = SPEED_100000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002348 },
2349};
2350
2351#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2352
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002353static void
2354mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2355 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002356{
2357 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2358 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2359 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2360 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2361 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2362 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002363 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002364
2365 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2366 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2367 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2368 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2369 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002370 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002371}
2372
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002373static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002374{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002375 int i;
2376
2377 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2378 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002379 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2380 mode);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002381 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002382}
2383
2384static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002385 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002386{
2387 u32 speed = SPEED_UNKNOWN;
2388 u8 duplex = DUPLEX_UNKNOWN;
2389 int i;
2390
2391 if (!carrier_ok)
2392 goto out;
2393
2394 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2395 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2396 speed = mlxsw_sp_port_link_mode[i].speed;
2397 duplex = DUPLEX_FULL;
2398 break;
2399 }
2400 }
2401out:
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002402 cmd->base.speed = speed;
2403 cmd->base.duplex = duplex;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002404}
2405
2406static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2407{
2408 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2409 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2410 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2411 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2412 return PORT_FIBRE;
2413
2414 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2415 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2416 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2417 return PORT_DA;
2418
2419 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2420 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2421 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2422 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2423 return PORT_NONE;
2424
2425 return PORT_OTHER;
2426}
2427
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002428static u32
2429mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002430{
2431 u32 ptys_proto = 0;
2432 int i;
2433
2434 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002435 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2436 cmd->link_modes.advertising))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002437 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2438 }
2439 return ptys_proto;
2440}
2441
2442static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2443{
2444 u32 ptys_proto = 0;
2445 int i;
2446
2447 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2448 if (speed == mlxsw_sp_port_link_mode[i].speed)
2449 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2450 }
2451 return ptys_proto;
2452}
2453
Ido Schimmel18f1e702016-02-26 17:32:31 +01002454static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2455{
2456 u32 ptys_proto = 0;
2457 int i;
2458
2459 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2460 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2461 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2462 }
2463 return ptys_proto;
2464}
2465
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002466static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2467 struct ethtool_link_ksettings *cmd)
2468{
2469 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2470 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2471 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2472
2473 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2474 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2475}
2476
2477static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2478 struct ethtool_link_ksettings *cmd)
2479{
2480 if (!autoneg)
2481 return;
2482
2483 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2484 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2485}
2486
2487static void
2488mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2489 struct ethtool_link_ksettings *cmd)
2490{
2491 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2492 return;
2493
2494 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2495 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2496}
2497
2498static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2499 struct ethtool_link_ksettings *cmd)
2500{
2501 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2502 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2503 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2504 char ptys_pl[MLXSW_REG_PTYS_LEN];
2505 u8 autoneg_status;
2506 bool autoneg;
2507 int err;
2508
2509 autoneg = mlxsw_sp_port->link.autoneg;
Elad Raz401c8b42016-10-28 21:35:52 +02002510 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002511 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2512 if (err)
2513 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002514 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2515 &eth_proto_oper);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002516
2517 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2518
2519 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2520
2521 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2522 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2523 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2524
2525 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2526 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2527 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2528 cmd);
2529
2530 return 0;
2531}
2532
2533static int
2534mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2535 const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002536{
2537 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2538 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2539 char ptys_pl[MLXSW_REG_PTYS_LEN];
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002540 u32 eth_proto_cap, eth_proto_new;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002541 bool autoneg;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002542 int err;
2543
Elad Raz401c8b42016-10-28 21:35:52 +02002544 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002545 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002546 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002547 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002548 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002549
2550 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2551 eth_proto_new = autoneg ?
2552 mlxsw_sp_to_ptys_advert_link(cmd) :
2553 mlxsw_sp_to_ptys_speed(cmd->base.speed);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002554
2555 eth_proto_new = eth_proto_new & eth_proto_cap;
2556 if (!eth_proto_new) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002557 netdev_err(dev, "No supported speed requested\n");
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002558 return -EINVAL;
2559 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002560
Elad Raz401c8b42016-10-28 21:35:52 +02002561 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2562 eth_proto_new);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002563 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002564 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002565 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002566
Ido Schimmel6277d462016-07-15 11:14:58 +02002567 if (!netif_running(dev))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002568 return 0;
2569
Ido Schimmel0c83f882016-09-12 13:26:23 +02002570 mlxsw_sp_port->link.autoneg = autoneg;
2571
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002572 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2573 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002574
2575 return 0;
2576}
2577
2578static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2579 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2580 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002581 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2582 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002583 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002584 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002585 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2586 .get_sset_count = mlxsw_sp_port_get_sset_count,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002587 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2588 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002589};
2590
Ido Schimmel18f1e702016-02-26 17:32:31 +01002591static int
2592mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2593{
2594 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2595 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2596 char ptys_pl[MLXSW_REG_PTYS_LEN];
2597 u32 eth_proto_admin;
2598
2599 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
Elad Raz401c8b42016-10-28 21:35:52 +02002600 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2601 eth_proto_admin);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002602 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2603}
2604
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002605int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2606 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2607 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02002608{
2609 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2610 char qeec_pl[MLXSW_REG_QEEC_LEN];
2611
2612 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2613 next_index);
2614 mlxsw_reg_qeec_de_set(qeec_pl, true);
2615 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2616 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2617 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2618}
2619
Ido Schimmelcc7cf512016-04-06 17:10:11 +02002620int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2621 enum mlxsw_reg_qeec_hr hr, u8 index,
2622 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02002623{
2624 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2625 char qeec_pl[MLXSW_REG_QEEC_LEN];
2626
2627 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2628 next_index);
2629 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2630 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2631 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2632}
2633
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002634int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2635 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02002636{
2637 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2638 char qtct_pl[MLXSW_REG_QTCT_LEN];
2639
2640 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2641 tclass);
2642 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2643}
2644
2645static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2646{
2647 int err, i;
2648
2649 /* Setup the elements hierarcy, so that each TC is linked to
2650 * one subgroup, which are all member in the same group.
2651 */
2652 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2653 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2654 0);
2655 if (err)
2656 return err;
2657 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2658 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2659 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2660 0, false, 0);
2661 if (err)
2662 return err;
2663 }
2664 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2665 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2666 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2667 false, 0);
2668 if (err)
2669 return err;
2670 }
2671
2672 /* Make sure the max shaper is disabled in all hierarcies that
2673 * support it.
2674 */
2675 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2676 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2677 MLXSW_REG_QEEC_MAS_DIS);
2678 if (err)
2679 return err;
2680 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2681 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2682 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2683 i, 0,
2684 MLXSW_REG_QEEC_MAS_DIS);
2685 if (err)
2686 return err;
2687 }
2688 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2689 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2690 MLXSW_REG_QEEC_HIERARCY_TC,
2691 i, i,
2692 MLXSW_REG_QEEC_MAS_DIS);
2693 if (err)
2694 return err;
2695 }
2696
2697 /* Map all priorities to traffic class 0. */
2698 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2699 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2700 if (err)
2701 return err;
2702 }
2703
2704 return 0;
2705}
2706
Jiri Pirko67963a32016-10-28 21:35:55 +02002707static int __mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2708 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002709{
Ido Schimmelc57529e2017-05-26 08:37:31 +02002710 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002711 struct mlxsw_sp_port *mlxsw_sp_port;
2712 struct net_device *dev;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002713 int err;
2714
2715 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
2716 if (!dev)
2717 return -ENOMEM;
Jiri Pirkof20a91f2016-10-27 15:13:00 +02002718 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002719 mlxsw_sp_port = netdev_priv(dev);
2720 mlxsw_sp_port->dev = dev;
2721 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2722 mlxsw_sp_port->local_port = local_port;
Ido Schimmelc57529e2017-05-26 08:37:31 +02002723 mlxsw_sp_port->pvid = 1;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002724 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02002725 mlxsw_sp_port->mapping.module = module;
2726 mlxsw_sp_port->mapping.width = width;
2727 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002728 mlxsw_sp_port->link.autoneg = 1;
Ido Schimmel31a08a52017-05-26 08:37:26 +02002729 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02002730 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002731
2732 mlxsw_sp_port->pcpu_stats =
2733 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2734 if (!mlxsw_sp_port->pcpu_stats) {
2735 err = -ENOMEM;
2736 goto err_alloc_stats;
2737 }
2738
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002739 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2740 GFP_KERNEL);
2741 if (!mlxsw_sp_port->sample) {
2742 err = -ENOMEM;
2743 goto err_alloc_sample;
2744 }
2745
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002746 mlxsw_sp_port->hw_stats.cache =
2747 kzalloc(sizeof(*mlxsw_sp_port->hw_stats.cache), GFP_KERNEL);
2748
2749 if (!mlxsw_sp_port->hw_stats.cache) {
2750 err = -ENOMEM;
2751 goto err_alloc_hw_stats;
2752 }
2753 INIT_DELAYED_WORK(&mlxsw_sp_port->hw_stats.update_dw,
2754 &update_stats_cache);
2755
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002756 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2757 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2758
Ido Schimmel3247ff22016-09-08 08:16:02 +02002759 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2760 if (err) {
2761 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2762 mlxsw_sp_port->local_port);
2763 goto err_port_swid_set;
2764 }
2765
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002766 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2767 if (err) {
2768 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2769 mlxsw_sp_port->local_port);
2770 goto err_dev_addr_init;
2771 }
2772
2773 netif_carrier_off(dev);
2774
2775 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
Yotam Gigi763b4b72016-07-21 12:03:17 +02002776 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2777 dev->hw_features |= NETIF_F_HW_TC;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002778
Jarod Wilsond894be52016-10-20 13:55:16 -04002779 dev->min_mtu = 0;
2780 dev->max_mtu = ETH_MAX_MTU;
2781
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002782 /* Each packet needs to have a Tx header (metadata) on top all other
2783 * headers.
2784 */
Yotam Gigifeb7d382016-10-04 09:46:04 +02002785 dev->needed_headroom = MLXSW_TXHDR_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002786
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002787 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2788 if (err) {
2789 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2790 mlxsw_sp_port->local_port);
2791 goto err_port_system_port_mapping_set;
2792 }
2793
Ido Schimmel18f1e702016-02-26 17:32:31 +01002794 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2795 if (err) {
2796 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2797 mlxsw_sp_port->local_port);
2798 goto err_port_speed_by_width_set;
2799 }
2800
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002801 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2802 if (err) {
2803 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2804 mlxsw_sp_port->local_port);
2805 goto err_port_mtu_set;
2806 }
2807
2808 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2809 if (err)
2810 goto err_port_admin_status_set;
2811
2812 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2813 if (err) {
2814 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2815 mlxsw_sp_port->local_port);
2816 goto err_port_buffers_init;
2817 }
2818
Ido Schimmel90183b92016-04-06 17:10:08 +02002819 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2820 if (err) {
2821 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2822 mlxsw_sp_port->local_port);
2823 goto err_port_ets_init;
2824 }
2825
Ido Schimmelf00817d2016-04-06 17:10:09 +02002826 /* ETS and buffers must be initialized before DCB. */
2827 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2828 if (err) {
2829 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2830 mlxsw_sp_port->local_port);
2831 goto err_port_dcb_init;
2832 }
2833
Ido Schimmel45a4a162017-05-16 19:38:35 +02002834 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
2835 if (err) {
2836 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set non-virtual mode\n",
2837 mlxsw_sp_port->local_port);
2838 goto err_port_vp_mode_set;
2839 }
2840
Ido Schimmelc57529e2017-05-26 08:37:31 +02002841 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
2842 if (IS_ERR(mlxsw_sp_port_vlan)) {
2843 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
Ido Schimmel05978482016-08-17 16:39:30 +02002844 mlxsw_sp_port->local_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002845 goto err_port_vlan_get;
Ido Schimmel05978482016-08-17 16:39:30 +02002846 }
2847
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002848 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
Ido Schimmel2f258442016-08-17 16:39:31 +02002849 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002850 err = register_netdev(dev);
2851 if (err) {
2852 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
2853 mlxsw_sp_port->local_port);
2854 goto err_register_netdev;
2855 }
2856
Elad Razd808c7e2016-10-28 21:35:57 +02002857 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
2858 mlxsw_sp_port, dev, mlxsw_sp_port->split,
2859 module);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002860 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002861 return 0;
2862
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002863err_register_netdev:
Ido Schimmel2f258442016-08-17 16:39:31 +02002864 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002865 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002866 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
2867err_port_vlan_get:
Ido Schimmel45a4a162017-05-16 19:38:35 +02002868err_port_vp_mode_set:
Ido Schimmel4de34eb2016-08-04 17:36:22 +03002869 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002870err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02002871err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002872err_port_buffers_init:
2873err_port_admin_status_set:
2874err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01002875err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002876err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002877err_dev_addr_init:
Ido Schimmel3247ff22016-09-08 08:16:02 +02002878 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2879err_port_swid_set:
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002880 kfree(mlxsw_sp_port->hw_stats.cache);
2881err_alloc_hw_stats:
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002882 kfree(mlxsw_sp_port->sample);
2883err_alloc_sample:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002884 free_percpu(mlxsw_sp_port->pcpu_stats);
2885err_alloc_stats:
2886 free_netdev(dev);
2887 return err;
2888}
2889
Jiri Pirko67963a32016-10-28 21:35:55 +02002890static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2891 bool split, u8 module, u8 width, u8 lane)
2892{
2893 int err;
2894
2895 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2896 if (err) {
2897 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2898 local_port);
2899 return err;
2900 }
Ido Schimmel9a60c902016-12-16 19:29:03 +01002901 err = __mlxsw_sp_port_create(mlxsw_sp, local_port, split,
Jiri Pirko67963a32016-10-28 21:35:55 +02002902 module, width, lane);
2903 if (err)
2904 goto err_port_create;
2905 return 0;
2906
2907err_port_create:
2908 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2909 return err;
2910}
2911
2912static void __mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002913{
2914 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2915
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002916 cancel_delayed_work_sync(&mlxsw_sp_port->hw_stats.update_dw);
Jiri Pirko67963a32016-10-28 21:35:55 +02002917 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002918 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmel2f258442016-08-17 16:39:31 +02002919 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002920 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002921 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002922 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01002923 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2924 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002925 kfree(mlxsw_sp_port->hw_stats.cache);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002926 kfree(mlxsw_sp_port->sample);
Yotam Gigi136f1442017-01-09 11:25:47 +01002927 free_percpu(mlxsw_sp_port->pcpu_stats);
Ido Schimmel31a08a52017-05-26 08:37:26 +02002928 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002929 free_netdev(mlxsw_sp_port->dev);
2930}
2931
Jiri Pirko67963a32016-10-28 21:35:55 +02002932static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2933{
2934 __mlxsw_sp_port_remove(mlxsw_sp, local_port);
2935 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2936}
2937
Jiri Pirkof83e2102016-10-28 21:35:49 +02002938static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2939{
2940 return mlxsw_sp->ports[local_port] != NULL;
2941}
2942
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002943static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
2944{
2945 int i;
2946
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002947 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002948 if (mlxsw_sp_port_created(mlxsw_sp, i))
2949 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002950 kfree(mlxsw_sp->port_to_module);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002951 kfree(mlxsw_sp->ports);
2952}
2953
2954static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
2955{
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002956 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
Ido Schimmeld664b412016-06-09 09:51:40 +02002957 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002958 size_t alloc_size;
2959 int i;
2960 int err;
2961
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002962 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002963 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
2964 if (!mlxsw_sp->ports)
2965 return -ENOMEM;
2966
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002967 mlxsw_sp->port_to_module = kcalloc(max_ports, sizeof(u8), GFP_KERNEL);
2968 if (!mlxsw_sp->port_to_module) {
2969 err = -ENOMEM;
2970 goto err_port_to_module_alloc;
2971 }
2972
2973 for (i = 1; i < max_ports; i++) {
Ido Schimmel558c2d52016-02-26 17:32:29 +01002974 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02002975 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01002976 if (err)
2977 goto err_port_module_info_get;
2978 if (!width)
2979 continue;
2980 mlxsw_sp->port_to_module[i] = module;
Jiri Pirko67963a32016-10-28 21:35:55 +02002981 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
2982 module, width, lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002983 if (err)
2984 goto err_port_create;
2985 }
2986 return 0;
2987
2988err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01002989err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002990 for (i--; i >= 1; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002991 if (mlxsw_sp_port_created(mlxsw_sp, i))
2992 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002993 kfree(mlxsw_sp->port_to_module);
2994err_port_to_module_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002995 kfree(mlxsw_sp->ports);
2996 return err;
2997}
2998
Ido Schimmel18f1e702016-02-26 17:32:31 +01002999static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3000{
3001 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3002
3003 return local_port - offset;
3004}
3005
Ido Schimmelbe945352016-06-09 09:51:39 +02003006static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3007 u8 module, unsigned int count)
3008{
3009 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3010 int err, i;
3011
3012 for (i = 0; i < count; i++) {
3013 err = mlxsw_sp_port_module_map(mlxsw_sp, base_port + i, module,
3014 width, i * width);
3015 if (err)
3016 goto err_port_module_map;
3017 }
3018
3019 for (i = 0; i < count; i++) {
3020 err = __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i, 0);
3021 if (err)
3022 goto err_port_swid_set;
3023 }
3024
3025 for (i = 0; i < count; i++) {
3026 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02003027 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02003028 if (err)
3029 goto err_port_create;
3030 }
3031
3032 return 0;
3033
3034err_port_create:
3035 for (i--; i >= 0; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003036 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3037 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmelbe945352016-06-09 09:51:39 +02003038 i = count;
3039err_port_swid_set:
3040 for (i--; i >= 0; i--)
3041 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i,
3042 MLXSW_PORT_SWID_DISABLED_PORT);
3043 i = count;
3044err_port_module_map:
3045 for (i--; i >= 0; i--)
3046 mlxsw_sp_port_module_unmap(mlxsw_sp, base_port + i);
3047 return err;
3048}
3049
3050static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3051 u8 base_port, unsigned int count)
3052{
3053 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3054 int i;
3055
3056 /* Split by four means we need to re-create two ports, otherwise
3057 * only one.
3058 */
3059 count = count / 2;
3060
3061 for (i = 0; i < count; i++) {
3062 local_port = base_port + i * 2;
3063 module = mlxsw_sp->port_to_module[local_port];
3064
3065 mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
3066 0);
3067 }
3068
3069 for (i = 0; i < count; i++)
3070 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i * 2, 0);
3071
3072 for (i = 0; i < count; i++) {
3073 local_port = base_port + i * 2;
3074 module = mlxsw_sp->port_to_module[local_port];
3075
3076 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003077 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02003078 }
3079}
3080
Jiri Pirkob2f10572016-04-08 19:11:23 +02003081static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3082 unsigned int count)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003083{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003084 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003085 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003086 u8 module, cur_width, base_port;
3087 int i;
3088 int err;
3089
3090 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3091 if (!mlxsw_sp_port) {
3092 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3093 local_port);
3094 return -EINVAL;
3095 }
3096
Ido Schimmeld664b412016-06-09 09:51:40 +02003097 module = mlxsw_sp_port->mapping.module;
3098 cur_width = mlxsw_sp_port->mapping.width;
3099
Ido Schimmel18f1e702016-02-26 17:32:31 +01003100 if (count != 2 && count != 4) {
3101 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3102 return -EINVAL;
3103 }
3104
Ido Schimmel18f1e702016-02-26 17:32:31 +01003105 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3106 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3107 return -EINVAL;
3108 }
3109
3110 /* Make sure we have enough slave (even) ports for the split. */
3111 if (count == 2) {
3112 base_port = local_port;
3113 if (mlxsw_sp->ports[base_port + 1]) {
3114 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3115 return -EINVAL;
3116 }
3117 } else {
3118 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3119 if (mlxsw_sp->ports[base_port + 1] ||
3120 mlxsw_sp->ports[base_port + 3]) {
3121 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3122 return -EINVAL;
3123 }
3124 }
3125
3126 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003127 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3128 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003129
Ido Schimmelbe945352016-06-09 09:51:39 +02003130 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3131 if (err) {
3132 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3133 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003134 }
3135
3136 return 0;
3137
Ido Schimmelbe945352016-06-09 09:51:39 +02003138err_port_split_create:
3139 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003140 return err;
3141}
3142
Jiri Pirkob2f10572016-04-08 19:11:23 +02003143static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003144{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003145 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003146 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02003147 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003148 unsigned int count;
3149 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003150
3151 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3152 if (!mlxsw_sp_port) {
3153 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3154 local_port);
3155 return -EINVAL;
3156 }
3157
3158 if (!mlxsw_sp_port->split) {
3159 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
3160 return -EINVAL;
3161 }
3162
Ido Schimmeld664b412016-06-09 09:51:40 +02003163 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003164 count = cur_width == 1 ? 4 : 2;
3165
3166 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3167
3168 /* Determine which ports to remove. */
3169 if (count == 2 && local_port >= base_port + 2)
3170 base_port = base_port + 2;
3171
3172 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003173 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3174 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003175
Ido Schimmelbe945352016-06-09 09:51:39 +02003176 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003177
3178 return 0;
3179}
3180
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003181static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3182 char *pude_pl, void *priv)
3183{
3184 struct mlxsw_sp *mlxsw_sp = priv;
3185 struct mlxsw_sp_port *mlxsw_sp_port;
3186 enum mlxsw_reg_pude_oper_status status;
3187 u8 local_port;
3188
3189 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3190 mlxsw_sp_port = mlxsw_sp->ports[local_port];
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003191 if (!mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003192 return;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003193
3194 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3195 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3196 netdev_info(mlxsw_sp_port->dev, "link up\n");
3197 netif_carrier_on(mlxsw_sp_port->dev);
3198 } else {
3199 netdev_info(mlxsw_sp_port->dev, "link down\n");
3200 netif_carrier_off(mlxsw_sp_port->dev);
3201 }
3202}
3203
Nogah Frankel14eeda92016-11-25 10:33:32 +01003204static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3205 u8 local_port, void *priv)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003206{
3207 struct mlxsw_sp *mlxsw_sp = priv;
3208 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3209 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3210
3211 if (unlikely(!mlxsw_sp_port)) {
3212 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3213 local_port);
3214 return;
3215 }
3216
3217 skb->dev = mlxsw_sp_port->dev;
3218
3219 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3220 u64_stats_update_begin(&pcpu_stats->syncp);
3221 pcpu_stats->rx_packets++;
3222 pcpu_stats->rx_bytes += skb->len;
3223 u64_stats_update_end(&pcpu_stats->syncp);
3224
3225 skb->protocol = eth_type_trans(skb, skb->dev);
3226 netif_receive_skb(skb);
3227}
3228
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003229static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3230 void *priv)
3231{
3232 skb->offload_fwd_mark = 1;
Nogah Frankel14eeda92016-11-25 10:33:32 +01003233 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003234}
3235
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003236static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3237 void *priv)
3238{
3239 struct mlxsw_sp *mlxsw_sp = priv;
3240 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3241 struct psample_group *psample_group;
3242 u32 size;
3243
3244 if (unlikely(!mlxsw_sp_port)) {
3245 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3246 local_port);
3247 goto out;
3248 }
3249 if (unlikely(!mlxsw_sp_port->sample)) {
3250 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3251 local_port);
3252 goto out;
3253 }
3254
3255 size = mlxsw_sp_port->sample->truncate ?
3256 mlxsw_sp_port->sample->trunc_size : skb->len;
3257
3258 rcu_read_lock();
3259 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3260 if (!psample_group)
3261 goto out_unlock;
3262 psample_sample_packet(psample_group, skb, size,
3263 mlxsw_sp_port->dev->ifindex, 0,
3264 mlxsw_sp_port->sample->rate);
3265out_unlock:
3266 rcu_read_unlock();
3267out:
3268 consume_skb(skb);
3269}
3270
Nogah Frankel117b0da2016-11-25 10:33:44 +01003271#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel0fb78a42016-11-25 10:33:39 +01003272 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003273 _is_ctrl, SP_##_trap_group, DISCARD)
Ido Schimmel93393b32016-08-25 18:42:38 +02003274
Nogah Frankel117b0da2016-11-25 10:33:44 +01003275#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel14eeda92016-11-25 10:33:32 +01003276 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003277 _is_ctrl, SP_##_trap_group, DISCARD)
3278
3279#define MLXSW_SP_EVENTL(_func, _trap_id) \
3280 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
Nogah Frankel14eeda92016-11-25 10:33:32 +01003281
Nogah Frankel45449132016-11-25 10:33:35 +01003282static const struct mlxsw_listener mlxsw_sp_listener[] = {
3283 /* Events */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003284 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
Nogah Frankelee4a60d2016-11-25 10:33:29 +01003285 /* L2 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003286 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3287 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3288 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3289 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3290 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3291 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3292 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3293 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3294 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3295 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3296 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
Jiri Pirko9d41acc2017-04-18 16:55:38 +02003297 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
Ido Schimmel93393b32016-08-25 18:42:38 +02003298 /* L3 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003299 MLXSW_SP_RXL_NO_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3300 MLXSW_SP_RXL_NO_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3301 MLXSW_SP_RXL_NO_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3302 MLXSW_SP_RXL_MARK(OSPF, TRAP_TO_CPU, OSPF, false),
3303 MLXSW_SP_RXL_NO_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
3304 MLXSW_SP_RXL_NO_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
3305 MLXSW_SP_RXL_NO_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, ARP_MISS, false),
3306 MLXSW_SP_RXL_NO_MARK(BGP_IPV4, TRAP_TO_CPU, BGP_IPV4, false),
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003307 /* PKT Sample trap */
3308 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
3309 false, SP_IP2ME, DISCARD)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003310};
3311
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003312static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3313{
3314 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3315 enum mlxsw_reg_qpcr_ir_units ir_units;
3316 int max_cpu_policers;
3317 bool is_bytes;
3318 u8 burst_size;
3319 u32 rate;
3320 int i, err;
3321
3322 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3323 return -EIO;
3324
3325 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3326
3327 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3328 for (i = 0; i < max_cpu_policers; i++) {
3329 is_bytes = false;
3330 switch (i) {
3331 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3332 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3333 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3334 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3335 rate = 128;
3336 burst_size = 7;
3337 break;
3338 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3339 rate = 16 * 1024;
3340 burst_size = 10;
3341 break;
3342 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4:
3343 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3344 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3345 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS:
3346 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3347 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3348 rate = 1024;
3349 burst_size = 7;
3350 break;
3351 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3352 is_bytes = true;
3353 rate = 4 * 1024;
3354 burst_size = 4;
3355 break;
3356 default:
3357 continue;
3358 }
3359
3360 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3361 burst_size);
3362 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3363 if (err)
3364 return err;
3365 }
3366
3367 return 0;
3368}
3369
Nogah Frankel579c82e2016-11-25 10:33:42 +01003370static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003371{
3372 char htgt_pl[MLXSW_REG_HTGT_LEN];
Nogah Frankel117b0da2016-11-25 10:33:44 +01003373 enum mlxsw_reg_htgt_trap_group i;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003374 int max_cpu_policers;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003375 int max_trap_groups;
3376 u8 priority, tc;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003377 u16 policer_id;
Nogah Frankel117b0da2016-11-25 10:33:44 +01003378 int err;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003379
3380 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3381 return -EIO;
3382
3383 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003384 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003385
3386 for (i = 0; i < max_trap_groups; i++) {
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003387 policer_id = i;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003388 switch (i) {
Nogah Frankel117b0da2016-11-25 10:33:44 +01003389 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3390 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3391 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3392 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3393 priority = 5;
3394 tc = 5;
3395 break;
3396 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4:
3397 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3398 priority = 4;
3399 tc = 4;
3400 break;
3401 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3402 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3403 priority = 3;
3404 tc = 3;
3405 break;
3406 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3407 priority = 2;
3408 tc = 2;
3409 break;
3410 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS:
3411 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3412 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3413 priority = 1;
3414 tc = 1;
3415 break;
3416 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
Nogah Frankel579c82e2016-11-25 10:33:42 +01003417 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3418 tc = MLXSW_REG_HTGT_DEFAULT_TC;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003419 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003420 break;
3421 default:
3422 continue;
3423 }
Nogah Frankel117b0da2016-11-25 10:33:44 +01003424
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003425 if (max_cpu_policers <= policer_id &&
3426 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3427 return -EIO;
3428
3429 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003430 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3431 if (err)
3432 return err;
3433 }
3434
3435 return 0;
3436}
3437
3438static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3439{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003440 int i;
3441 int err;
3442
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003443 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3444 if (err)
3445 return err;
3446
Nogah Frankel579c82e2016-11-25 10:33:42 +01003447 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003448 if (err)
3449 return err;
3450
Nogah Frankel45449132016-11-25 10:33:35 +01003451 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003452 err = mlxsw_core_trap_register(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003453 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003454 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003455 if (err)
Nogah Frankel45449132016-11-25 10:33:35 +01003456 goto err_listener_register;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003457
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003458 }
3459 return 0;
3460
Nogah Frankel45449132016-11-25 10:33:35 +01003461err_listener_register:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003462 for (i--; i >= 0; i--) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003463 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003464 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003465 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003466 }
3467 return err;
3468}
3469
3470static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3471{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003472 int i;
3473
Nogah Frankel45449132016-11-25 10:33:35 +01003474 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003475 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003476 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003477 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003478 }
3479}
3480
3481static int __mlxsw_sp_flood_init(struct mlxsw_core *mlxsw_core,
3482 enum mlxsw_reg_sfgc_type type,
3483 enum mlxsw_reg_sfgc_bridge_type bridge_type)
3484{
3485 enum mlxsw_flood_table_type table_type;
3486 enum mlxsw_sp_flood_table flood_table;
3487 char sfgc_pl[MLXSW_REG_SFGC_LEN];
3488
Ido Schimmel19ae6122015-12-15 16:03:39 +01003489 if (bridge_type == MLXSW_REG_SFGC_BRIDGE_TYPE_VFID)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003490 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID;
Ido Schimmel19ae6122015-12-15 16:03:39 +01003491 else
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003492 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
Ido Schimmel19ae6122015-12-15 16:03:39 +01003493
Nogah Frankel71c365b2017-02-09 14:54:46 +01003494 switch (type) {
3495 case MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST:
Ido Schimmel19ae6122015-12-15 16:03:39 +01003496 flood_table = MLXSW_SP_FLOOD_TABLE_UC;
Nogah Frankel71c365b2017-02-09 14:54:46 +01003497 break;
3498 case MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4:
Nogah Frankel71c365b2017-02-09 14:54:46 +01003499 flood_table = MLXSW_SP_FLOOD_TABLE_MC;
3500 break;
3501 default:
3502 flood_table = MLXSW_SP_FLOOD_TABLE_BC;
3503 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003504
3505 mlxsw_reg_sfgc_pack(sfgc_pl, type, bridge_type, table_type,
3506 flood_table);
3507 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(sfgc), sfgc_pl);
3508}
3509
3510static int mlxsw_sp_flood_init(struct mlxsw_sp *mlxsw_sp)
3511{
3512 int type, err;
3513
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003514 for (type = 0; type < MLXSW_REG_SFGC_TYPE_MAX; type++) {
3515 if (type == MLXSW_REG_SFGC_TYPE_RESERVED)
3516 continue;
3517
3518 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
3519 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID);
3520 if (err)
3521 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003522
3523 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
3524 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID);
3525 if (err)
3526 return err;
3527 }
3528
3529 return 0;
3530}
3531
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003532static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3533{
3534 char slcr_pl[MLXSW_REG_SLCR_LEN];
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003535 int err;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003536
3537 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3538 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3539 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3540 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3541 MLXSW_REG_SLCR_LAG_HASH_SIP |
3542 MLXSW_REG_SLCR_LAG_HASH_DIP |
3543 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3544 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3545 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003546 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3547 if (err)
3548 return err;
3549
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003550 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3551 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003552 return -EIO;
3553
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003554 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003555 sizeof(struct mlxsw_sp_upper),
3556 GFP_KERNEL);
3557 if (!mlxsw_sp->lags)
3558 return -ENOMEM;
3559
3560 return 0;
3561}
3562
3563static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3564{
3565 kfree(mlxsw_sp->lags);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003566}
3567
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003568static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3569{
3570 char htgt_pl[MLXSW_REG_HTGT_LEN];
3571
Nogah Frankel579c82e2016-11-25 10:33:42 +01003572 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3573 MLXSW_REG_HTGT_INVALID_POLICER,
3574 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3575 MLXSW_REG_HTGT_DEFAULT_TC);
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003576 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3577}
3578
Jiri Pirko202d6f42017-04-18 16:55:33 +02003579static int mlxsw_sp_dummy_fid_init(struct mlxsw_sp *mlxsw_sp)
3580{
Ido Schimmelc57529e2017-05-26 08:37:31 +02003581 return mlxsw_sp_fid_op(mlxsw_sp, MLXSW_SP_DUMMY_FID, true);
Jiri Pirko202d6f42017-04-18 16:55:33 +02003582}
3583
3584static void mlxsw_sp_dummy_fid_fini(struct mlxsw_sp *mlxsw_sp)
3585{
Ido Schimmelc57529e2017-05-26 08:37:31 +02003586 mlxsw_sp_fid_op(mlxsw_sp, MLXSW_SP_DUMMY_FID, false);
Jiri Pirko202d6f42017-04-18 16:55:33 +02003587}
3588
Jiri Pirkob2f10572016-04-08 19:11:23 +02003589static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003590 const struct mlxsw_bus_info *mlxsw_bus_info)
3591{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003592 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003593 int err;
3594
3595 mlxsw_sp->core = mlxsw_core;
3596 mlxsw_sp->bus_info = mlxsw_bus_info;
Ido Schimmel14d39462016-06-20 23:04:15 +02003597 INIT_LIST_HEAD(&mlxsw_sp->fids);
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003598 INIT_LIST_HEAD(&mlxsw_sp->vfids.list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003599
Yotam Gigi6b742192017-05-23 21:56:29 +02003600 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3601 if (err) {
3602 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3603 return err;
3604 }
3605
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003606 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3607 if (err) {
3608 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3609 return err;
3610 }
3611
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003612 err = mlxsw_sp_traps_init(mlxsw_sp);
3613 if (err) {
Nogah Frankel45449132016-11-25 10:33:35 +01003614 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3615 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003616 }
3617
3618 err = mlxsw_sp_flood_init(mlxsw_sp);
3619 if (err) {
3620 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize flood tables\n");
3621 goto err_flood_init;
3622 }
3623
3624 err = mlxsw_sp_buffers_init(mlxsw_sp);
3625 if (err) {
3626 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3627 goto err_buffers_init;
3628 }
3629
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003630 err = mlxsw_sp_lag_init(mlxsw_sp);
3631 if (err) {
3632 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3633 goto err_lag_init;
3634 }
3635
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003636 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3637 if (err) {
3638 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3639 goto err_switchdev_init;
3640 }
3641
Ido Schimmel464dce12016-07-02 11:00:15 +02003642 err = mlxsw_sp_router_init(mlxsw_sp);
3643 if (err) {
3644 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3645 goto err_router_init;
3646 }
3647
Yotam Gigi763b4b72016-07-21 12:03:17 +02003648 err = mlxsw_sp_span_init(mlxsw_sp);
3649 if (err) {
3650 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3651 goto err_span_init;
3652 }
3653
Jiri Pirko22a67762017-02-03 10:29:07 +01003654 err = mlxsw_sp_acl_init(mlxsw_sp);
3655 if (err) {
3656 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3657 goto err_acl_init;
3658 }
3659
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +01003660 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3661 if (err) {
3662 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3663 goto err_counter_pool_init;
3664 }
3665
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003666 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3667 if (err) {
3668 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3669 goto err_dpipe_init;
3670 }
3671
Jiri Pirko202d6f42017-04-18 16:55:33 +02003672 err = mlxsw_sp_dummy_fid_init(mlxsw_sp);
3673 if (err) {
3674 dev_err(mlxsw_sp->bus_info->dev, "Failed to init dummy FID\n");
3675 goto err_dummy_fid_init;
3676 }
3677
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003678 err = mlxsw_sp_ports_create(mlxsw_sp);
3679 if (err) {
3680 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3681 goto err_ports_create;
3682 }
3683
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003684 return 0;
3685
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003686err_ports_create:
Jiri Pirko202d6f42017-04-18 16:55:33 +02003687 mlxsw_sp_dummy_fid_fini(mlxsw_sp);
3688err_dummy_fid_init:
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003689 mlxsw_sp_dpipe_fini(mlxsw_sp);
3690err_dpipe_init:
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +01003691 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3692err_counter_pool_init:
Jiri Pirko22a67762017-02-03 10:29:07 +01003693 mlxsw_sp_acl_fini(mlxsw_sp);
3694err_acl_init:
Yotam Gigi763b4b72016-07-21 12:03:17 +02003695 mlxsw_sp_span_fini(mlxsw_sp);
3696err_span_init:
Ido Schimmel464dce12016-07-02 11:00:15 +02003697 mlxsw_sp_router_fini(mlxsw_sp);
3698err_router_init:
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003699 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003700err_switchdev_init:
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003701 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003702err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02003703 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003704err_buffers_init:
3705err_flood_init:
3706 mlxsw_sp_traps_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003707 return err;
3708}
3709
Jiri Pirkob2f10572016-04-08 19:11:23 +02003710static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003711{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003712 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003713
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003714 mlxsw_sp_ports_remove(mlxsw_sp);
Jiri Pirko202d6f42017-04-18 16:55:33 +02003715 mlxsw_sp_dummy_fid_fini(mlxsw_sp);
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003716 mlxsw_sp_dpipe_fini(mlxsw_sp);
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +01003717 mlxsw_sp_counter_pool_fini(mlxsw_sp);
Jiri Pirko22a67762017-02-03 10:29:07 +01003718 mlxsw_sp_acl_fini(mlxsw_sp);
Yotam Gigi763b4b72016-07-21 12:03:17 +02003719 mlxsw_sp_span_fini(mlxsw_sp);
Ido Schimmel464dce12016-07-02 11:00:15 +02003720 mlxsw_sp_router_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003721 mlxsw_sp_switchdev_fini(mlxsw_sp);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003722 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02003723 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003724 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003725 WARN_ON(!list_empty(&mlxsw_sp->vfids.list));
Ido Schimmel14d39462016-06-20 23:04:15 +02003726 WARN_ON(!list_empty(&mlxsw_sp->fids));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003727}
3728
3729static struct mlxsw_config_profile mlxsw_sp_config_profile = {
3730 .used_max_vepa_channels = 1,
3731 .max_vepa_channels = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003732 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01003733 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003734 .used_max_pgt = 1,
3735 .max_pgt = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003736 .used_flood_tables = 1,
3737 .used_flood_mode = 1,
3738 .flood_mode = 3,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003739 .max_fid_offset_flood_tables = 3,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003740 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003741 .max_fid_flood_tables = 3,
Ido Schimmel19ae6122015-12-15 16:03:39 +01003742 .fid_flood_table_size = MLXSW_SP_VFID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003743 .used_max_ib_mc = 1,
3744 .max_ib_mc = 0,
3745 .used_max_pkey = 1,
3746 .max_pkey = 0,
Nogah Frankel403547d2016-09-20 11:16:52 +02003747 .used_kvd_split_data = 1,
3748 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
3749 .kvd_hash_single_parts = 2,
3750 .kvd_hash_double_parts = 1,
Jiri Pirkoc6022422016-07-05 11:27:46 +02003751 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003752 .swid_config = {
3753 {
3754 .used_type = 1,
3755 .type = MLXSW_PORT_SWID_TYPE_ETH,
3756 }
3757 },
Nogah Frankel57d316b2016-07-21 12:03:09 +02003758 .resource_query_enable = 1,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003759};
3760
3761static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko1d20d232016-10-27 15:12:59 +02003762 .kind = mlxsw_sp_driver_name,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003763 .priv_size = sizeof(struct mlxsw_sp),
3764 .init = mlxsw_sp_init,
3765 .fini = mlxsw_sp_fini,
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003766 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003767 .port_split = mlxsw_sp_port_split,
3768 .port_unsplit = mlxsw_sp_port_unsplit,
3769 .sb_pool_get = mlxsw_sp_sb_pool_get,
3770 .sb_pool_set = mlxsw_sp_sb_pool_set,
3771 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3772 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3773 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3774 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3775 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3776 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3777 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3778 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3779 .txhdr_construct = mlxsw_sp_txhdr_construct,
3780 .txhdr_len = MLXSW_TXHDR_LEN,
3781 .profile = &mlxsw_sp_config_profile,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003782};
3783
Jiri Pirko22a67762017-02-03 10:29:07 +01003784bool mlxsw_sp_port_dev_check(const struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003785{
3786 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
3787}
3788
Jiri Pirko1182e532017-03-06 21:25:20 +01003789static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
David Aherndd823642016-10-17 19:15:49 -07003790{
Jiri Pirko1182e532017-03-06 21:25:20 +01003791 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
David Aherndd823642016-10-17 19:15:49 -07003792 int ret = 0;
3793
3794 if (mlxsw_sp_port_dev_check(lower_dev)) {
Jiri Pirko1182e532017-03-06 21:25:20 +01003795 *p_mlxsw_sp_port = netdev_priv(lower_dev);
David Aherndd823642016-10-17 19:15:49 -07003796 ret = 1;
3797 }
3798
3799 return ret;
3800}
3801
Ido Schimmelc57529e2017-05-26 08:37:31 +02003802struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003803{
Jiri Pirko1182e532017-03-06 21:25:20 +01003804 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003805
3806 if (mlxsw_sp_port_dev_check(dev))
3807 return netdev_priv(dev);
3808
Jiri Pirko1182e532017-03-06 21:25:20 +01003809 mlxsw_sp_port = NULL;
3810 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07003811
Jiri Pirko1182e532017-03-06 21:25:20 +01003812 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003813}
3814
Ido Schimmel4724ba562017-03-10 08:53:39 +01003815struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003816{
3817 struct mlxsw_sp_port *mlxsw_sp_port;
3818
3819 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
3820 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
3821}
3822
3823static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
3824{
Jiri Pirko1182e532017-03-06 21:25:20 +01003825 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003826
3827 if (mlxsw_sp_port_dev_check(dev))
3828 return netdev_priv(dev);
3829
Jiri Pirko1182e532017-03-06 21:25:20 +01003830 mlxsw_sp_port = NULL;
3831 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
3832 &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07003833
Jiri Pirko1182e532017-03-06 21:25:20 +01003834 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003835}
3836
3837struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
3838{
3839 struct mlxsw_sp_port *mlxsw_sp_port;
3840
3841 rcu_read_lock();
3842 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
3843 if (mlxsw_sp_port)
3844 dev_hold(mlxsw_sp_port->dev);
3845 rcu_read_unlock();
3846 return mlxsw_sp_port;
3847}
3848
3849void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
3850{
3851 dev_put(mlxsw_sp_port->dev);
3852}
3853
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003854static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003855{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003856 char sldr_pl[MLXSW_REG_SLDR_LEN];
3857
3858 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
3859 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3860}
3861
3862static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
3863{
3864 char sldr_pl[MLXSW_REG_SLDR_LEN];
3865
3866 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
3867 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3868}
3869
3870static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
3871 u16 lag_id, u8 port_index)
3872{
3873 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3874 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3875
3876 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
3877 lag_id, port_index);
3878 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3879}
3880
3881static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
3882 u16 lag_id)
3883{
3884 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3885 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3886
3887 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
3888 lag_id);
3889 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3890}
3891
3892static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
3893 u16 lag_id)
3894{
3895 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3896 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3897
3898 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
3899 lag_id);
3900 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3901}
3902
3903static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
3904 u16 lag_id)
3905{
3906 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3907 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3908
3909 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
3910 lag_id);
3911 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3912}
3913
3914static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
3915 struct net_device *lag_dev,
3916 u16 *p_lag_id)
3917{
3918 struct mlxsw_sp_upper *lag;
3919 int free_lag_id = -1;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003920 u64 max_lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003921 int i;
3922
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003923 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
3924 for (i = 0; i < max_lag; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003925 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
3926 if (lag->ref_count) {
3927 if (lag->dev == lag_dev) {
3928 *p_lag_id = i;
3929 return 0;
3930 }
3931 } else if (free_lag_id < 0) {
3932 free_lag_id = i;
3933 }
3934 }
3935 if (free_lag_id < 0)
3936 return -EBUSY;
3937 *p_lag_id = free_lag_id;
3938 return 0;
3939}
3940
3941static bool
3942mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
3943 struct net_device *lag_dev,
3944 struct netdev_lag_upper_info *lag_upper_info)
3945{
3946 u16 lag_id;
3947
3948 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
3949 return false;
3950 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
3951 return false;
3952 return true;
3953}
3954
3955static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
3956 u16 lag_id, u8 *p_port_index)
3957{
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003958 u64 max_lag_members;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003959 int i;
3960
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003961 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
3962 MAX_LAG_MEMBERS);
3963 for (i = 0; i < max_lag_members; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003964 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
3965 *p_port_index = i;
3966 return 0;
3967 }
3968 }
3969 return -EBUSY;
3970}
3971
3972static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
3973 struct net_device *lag_dev)
3974{
3975 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelc57529e2017-05-26 08:37:31 +02003976 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003977 struct mlxsw_sp_upper *lag;
3978 u16 lag_id;
3979 u8 port_index;
3980 int err;
3981
3982 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
3983 if (err)
3984 return err;
3985 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
3986 if (!lag->ref_count) {
3987 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
3988 if (err)
3989 return err;
3990 lag->dev = lag_dev;
3991 }
3992
3993 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
3994 if (err)
3995 return err;
3996 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
3997 if (err)
3998 goto err_col_port_add;
3999 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4000 if (err)
4001 goto err_col_port_enable;
4002
4003 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4004 mlxsw_sp_port->local_port);
4005 mlxsw_sp_port->lag_id = lag_id;
4006 mlxsw_sp_port->lagged = 1;
4007 lag->ref_count++;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004008
Ido Schimmelc57529e2017-05-26 08:37:31 +02004009 /* Port is no longer usable as a router interface */
4010 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4011 if (mlxsw_sp_port_vlan->fid)
4012 mlxsw_sp_port_vlan->fid->leave(mlxsw_sp_port_vlan);
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004013
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004014 return 0;
4015
Ido Schimmel51554db2016-05-06 22:18:39 +02004016err_col_port_enable:
4017 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004018err_col_port_add:
4019 if (!lag->ref_count)
4020 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004021 return err;
4022}
4023
Ido Schimmel82e6db02016-06-20 23:04:04 +02004024static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4025 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004026{
4027 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004028 u16 lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel1c800752016-06-20 23:04:20 +02004029 struct mlxsw_sp_upper *lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004030
4031 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004032 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004033 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4034 WARN_ON(lag->ref_count == 0);
4035
Ido Schimmel82e6db02016-06-20 23:04:04 +02004036 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4037 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004038
Ido Schimmelc57529e2017-05-26 08:37:31 +02004039 /* Any VLANs configured on the port are no longer valid */
4040 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01004041
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004042 if (lag->ref_count == 1)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004043 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004044
4045 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4046 mlxsw_sp_port->local_port);
4047 mlxsw_sp_port->lagged = 0;
4048 lag->ref_count--;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004049
Ido Schimmelc57529e2017-05-26 08:37:31 +02004050 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4051 /* Make sure untagged frames are allowed to ingress */
4052 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004053}
4054
Jiri Pirko74581202015-12-03 12:12:30 +01004055static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4056 u16 lag_id)
4057{
4058 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4059 char sldr_pl[MLXSW_REG_SLDR_LEN];
4060
4061 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4062 mlxsw_sp_port->local_port);
4063 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4064}
4065
4066static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4067 u16 lag_id)
4068{
4069 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4070 char sldr_pl[MLXSW_REG_SLDR_LEN];
4071
4072 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4073 mlxsw_sp_port->local_port);
4074 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4075}
4076
4077static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4078 bool lag_tx_enabled)
4079{
4080 if (lag_tx_enabled)
4081 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4082 mlxsw_sp_port->lag_id);
4083 else
4084 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4085 mlxsw_sp_port->lag_id);
4086}
4087
4088static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4089 struct netdev_lag_lower_state_info *info)
4090{
4091 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4092}
4093
Jiri Pirko2b94e582017-04-18 16:55:37 +02004094static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4095 bool enable)
4096{
4097 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4098 enum mlxsw_reg_spms_state spms_state;
4099 char *spms_pl;
4100 u16 vid;
4101 int err;
4102
4103 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4104 MLXSW_REG_SPMS_STATE_DISCARDING;
4105
4106 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4107 if (!spms_pl)
4108 return -ENOMEM;
4109 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4110
4111 for (vid = 0; vid < VLAN_N_VID; vid++)
4112 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4113
4114 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4115 kfree(spms_pl);
4116 return err;
4117}
4118
4119static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4120{
4121 int err;
4122
Ido Schimmel4aafc362017-05-26 08:37:25 +02004123 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004124 if (err)
4125 return err;
Ido Schimmel4aafc362017-05-26 08:37:25 +02004126 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4127 if (err)
4128 goto err_port_stp_set;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004129 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4130 true, false);
4131 if (err)
4132 goto err_port_vlan_set;
4133 return 0;
4134
4135err_port_vlan_set:
4136 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004137err_port_stp_set:
4138 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004139 return err;
4140}
4141
4142static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4143{
4144 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4145 false, false);
4146 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004147 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004148}
4149
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004150static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4151 struct net_device *dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004152 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004153{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004154 struct netdev_notifier_changeupper_info *info;
4155 struct mlxsw_sp_port *mlxsw_sp_port;
4156 struct net_device *upper_dev;
4157 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004158 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004159
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004160 mlxsw_sp_port = netdev_priv(dev);
4161 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4162 info = ptr;
4163
4164 switch (event) {
4165 case NETDEV_PRECHANGEUPPER:
4166 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004167 if (!is_vlan_dev(upper_dev) &&
4168 !netif_is_lag_master(upper_dev) &&
Ido Schimmel7179eb52017-03-16 09:08:18 +01004169 !netif_is_bridge_master(upper_dev) &&
Jiri Pirko2b94e582017-04-18 16:55:37 +02004170 !netif_is_ovs_master(upper_dev))
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004171 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02004172 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004173 break;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004174 if (netif_is_lag_master(upper_dev) &&
4175 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4176 info->upper_info))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004177 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02004178 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
4179 return -EINVAL;
4180 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
4181 !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
4182 return -EINVAL;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004183 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev))
4184 return -EINVAL;
4185 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev))
4186 return -EINVAL;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004187 break;
4188 case NETDEV_CHANGEUPPER:
4189 upper_dev = info->upper_dev;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004190 if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02004191 if (info->linking)
4192 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004193 lower_dev,
Ido Schimmel7117a572016-06-20 23:04:06 +02004194 upper_dev);
4195 else
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004196 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4197 lower_dev,
4198 upper_dev);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004199 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004200 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004201 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4202 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004203 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02004204 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4205 upper_dev);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004206 } else if (netif_is_ovs_master(upper_dev)) {
4207 if (info->linking)
4208 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4209 else
4210 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004211 }
4212 break;
4213 }
4214
Ido Schimmel80bedf12016-06-20 23:03:59 +02004215 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004216}
4217
Jiri Pirko74581202015-12-03 12:12:30 +01004218static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4219 unsigned long event, void *ptr)
4220{
4221 struct netdev_notifier_changelowerstate_info *info;
4222 struct mlxsw_sp_port *mlxsw_sp_port;
4223 int err;
4224
4225 mlxsw_sp_port = netdev_priv(dev);
4226 info = ptr;
4227
4228 switch (event) {
4229 case NETDEV_CHANGELOWERSTATE:
4230 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4231 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4232 info->lower_state_info);
4233 if (err)
4234 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4235 }
4236 break;
4237 }
4238
Ido Schimmel80bedf12016-06-20 23:03:59 +02004239 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004240}
4241
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004242static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4243 struct net_device *port_dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004244 unsigned long event, void *ptr)
4245{
4246 switch (event) {
4247 case NETDEV_PRECHANGEUPPER:
4248 case NETDEV_CHANGEUPPER:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004249 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4250 event, ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004251 case NETDEV_CHANGELOWERSTATE:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004252 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4253 ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004254 }
4255
Ido Schimmel80bedf12016-06-20 23:03:59 +02004256 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004257}
4258
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004259static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4260 unsigned long event, void *ptr)
4261{
4262 struct net_device *dev;
4263 struct list_head *iter;
4264 int ret;
4265
4266 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4267 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004268 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4269 ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004270 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004271 return ret;
4272 }
4273 }
4274
Ido Schimmel80bedf12016-06-20 23:03:59 +02004275 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004276}
4277
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004278static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4279 struct net_device *dev,
4280 unsigned long event, void *ptr,
4281 u16 vid)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004282{
4283 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4284 struct netdev_notifier_changeupper_info *info = ptr;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004285 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004286 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004287
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004288 switch (event) {
4289 case NETDEV_PRECHANGEUPPER:
4290 upper_dev = info->upper_dev;
Ido Schimmelb1e45522017-04-30 19:47:14 +03004291 if (!netif_is_bridge_master(upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004292 return -EINVAL;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004293 break;
4294 case NETDEV_CHANGEUPPER:
4295 upper_dev = info->upper_dev;
Ido Schimmel1f880612017-03-10 08:53:35 +01004296 if (netif_is_bridge_master(upper_dev)) {
4297 if (info->linking)
Ido Schimmelc57529e2017-05-26 08:37:31 +02004298 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4299 vlan_dev,
4300 upper_dev);
Ido Schimmel1f880612017-03-10 08:53:35 +01004301 else
Ido Schimmelc57529e2017-05-26 08:37:31 +02004302 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4303 vlan_dev,
4304 upper_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004305 } else {
Ido Schimmel1f880612017-03-10 08:53:35 +01004306 err = -EINVAL;
4307 WARN_ON(1);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004308 }
Ido Schimmel1f880612017-03-10 08:53:35 +01004309 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004310 }
4311
Ido Schimmel80bedf12016-06-20 23:03:59 +02004312 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004313}
4314
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004315static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4316 struct net_device *lag_dev,
4317 unsigned long event,
4318 void *ptr, u16 vid)
Ido Schimmel272c4472015-12-15 16:03:47 +01004319{
4320 struct net_device *dev;
4321 struct list_head *iter;
4322 int ret;
4323
4324 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4325 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004326 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4327 event, ptr,
4328 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004329 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01004330 return ret;
4331 }
4332 }
4333
Ido Schimmel80bedf12016-06-20 23:03:59 +02004334 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01004335}
4336
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004337static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4338 unsigned long event, void *ptr)
4339{
4340 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4341 u16 vid = vlan_dev_vlan_id(vlan_dev);
4342
Ido Schimmel272c4472015-12-15 16:03:47 +01004343 if (mlxsw_sp_port_dev_check(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004344 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
4345 event, ptr, vid);
Ido Schimmel272c4472015-12-15 16:03:47 +01004346 else if (netif_is_lag_master(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004347 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
4348 real_dev, event,
4349 ptr, vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004350
Ido Schimmel80bedf12016-06-20 23:03:59 +02004351 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004352}
4353
Ido Schimmelb1e45522017-04-30 19:47:14 +03004354static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4355{
4356 struct netdev_notifier_changeupper_info *info = ptr;
4357
4358 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4359 return false;
4360 return netif_is_l3_master(info->upper_dev);
4361}
4362
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004363static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
4364 unsigned long event, void *ptr)
4365{
4366 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004367 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004368
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004369 if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
4370 err = mlxsw_sp_netdevice_router_port_event(dev);
Ido Schimmelb1e45522017-04-30 19:47:14 +03004371 else if (mlxsw_sp_is_vrf_event(event, ptr))
4372 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004373 else if (mlxsw_sp_port_dev_check(dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004374 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004375 else if (netif_is_lag_master(dev))
4376 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
4377 else if (is_vlan_dev(dev))
4378 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004379
Ido Schimmel80bedf12016-06-20 23:03:59 +02004380 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004381}
4382
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004383static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
4384 .notifier_call = mlxsw_sp_netdevice_event,
4385};
4386
Ido Schimmel99724c12016-07-04 08:23:14 +02004387static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4388 .notifier_call = mlxsw_sp_inetaddr_event,
4389 .priority = 10, /* Must be called before FIB notifier block */
4390};
4391
Jiri Pirkoe7322632016-09-01 10:37:43 +02004392static struct notifier_block mlxsw_sp_router_netevent_nb __read_mostly = {
4393 .notifier_call = mlxsw_sp_router_netevent_event,
4394};
4395
Jiri Pirko1d20d232016-10-27 15:12:59 +02004396static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4397 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4398 {0, },
4399};
4400
4401static struct pci_driver mlxsw_sp_pci_driver = {
4402 .name = mlxsw_sp_driver_name,
4403 .id_table = mlxsw_sp_pci_id_table,
4404};
4405
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004406static int __init mlxsw_sp_module_init(void)
4407{
4408 int err;
4409
4410 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004411 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirkoe7322632016-09-01 10:37:43 +02004412 register_netevent_notifier(&mlxsw_sp_router_netevent_nb);
4413
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004414 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4415 if (err)
4416 goto err_core_driver_register;
Jiri Pirko1d20d232016-10-27 15:12:59 +02004417
4418 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4419 if (err)
4420 goto err_pci_driver_register;
4421
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004422 return 0;
4423
Jiri Pirko1d20d232016-10-27 15:12:59 +02004424err_pci_driver_register:
4425 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004426err_core_driver_register:
Jiri Pirkoe7322632016-09-01 10:37:43 +02004427 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
Jiri Pirkode7d6292016-09-01 10:37:42 +02004428 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004429 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4430 return err;
4431}
4432
4433static void __exit mlxsw_sp_module_exit(void)
4434{
Jiri Pirko1d20d232016-10-27 15:12:59 +02004435 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004436 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirkoe7322632016-09-01 10:37:43 +02004437 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004438 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004439 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4440}
4441
4442module_init(mlxsw_sp_module_init);
4443module_exit(mlxsw_sp_module_exit);
4444
4445MODULE_LICENSE("Dual BSD/GPL");
4446MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4447MODULE_DESCRIPTION("Mellanox Spectrum driver");
Jiri Pirko1d20d232016-10-27 15:12:59 +02004448MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
Yotam Gigi6b742192017-05-23 21:56:29 +02004449MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME);