blob: 7098bfd32b1b23ad6cc8dfd18786a874cd67bf9b [file] [log] [blame]
Pan Wenc80dfd92016-11-14 10:49:54 +08001config COMMON_CLK_HI3516CV300
2 tristate "HI3516CV300 Clock Driver"
3 depends on ARCH_HISI || COMPILE_TEST
4 select RESET_HISI
5 default ARCH_HISI
6 help
7 Build the clock driver for hi3516cv300.
8
Jiancheng Xue6c9da382016-04-23 15:40:30 +08009config COMMON_CLK_HI3519
10 tristate "Hi3519 Clock Driver"
11 depends on ARCH_HISI || COMPILE_TEST
12 select RESET_HISI
13 default ARCH_HISI
14 help
15 Build the clock driver for hi3519.
16
Zhangfei Gaod374e6f2016-12-29 10:33:25 +080017config COMMON_CLK_HI3660
18 bool "Hi3660 Clock Driver"
19 depends on ARCH_HISI || COMPILE_TEST
20 default ARCH_HISI
21 help
22 Build the clock driver for hi3660.
23
Jiancheng Xue707d33c2016-10-29 14:13:37 +080024config COMMON_CLK_HI3798CV200
25 tristate "Hi3798CV200 Clock Driver"
26 depends on ARCH_HISI || COMPILE_TEST
27 select RESET_HISI
28 default ARCH_HISI
29 help
30 Build the clock driver for hi3798cv200.
31
Bintian Wang72ea4862015-05-29 10:08:38 +080032config COMMON_CLK_HI6220
33 bool "Hi6220 Clock Driver"
Leo Yan9f42a892015-09-02 10:57:47 +080034 depends on ARCH_HISI || COMPILE_TEST
Bintian Wang72ea4862015-05-29 10:08:38 +080035 default ARCH_HISI
36 help
37 Build the Hisilicon Hi6220 clock driver based on the common clock framework.
Leo Yan9f42a892015-09-02 10:57:47 +080038
Jiancheng Xue25824d52016-04-23 15:40:28 +080039config RESET_HISI
40 bool "HiSilicon Reset Controller Driver"
41 depends on ARCH_HISI || COMPILE_TEST
42 select RESET_CONTROLLER
43 help
44 Build reset controller driver for HiSilicon device chipsets.
45
Leo Yan9f42a892015-09-02 10:57:47 +080046config STUB_CLK_HI6220
47 bool "Hi6220 Stub Clock Driver"
48 depends on COMMON_CLK_HI6220 && MAILBOX
Leo Yan9a881bc2016-08-31 16:50:15 +080049 default ARCH_HISI
Leo Yan9f42a892015-09-02 10:57:47 +080050 help
51 Build the Hisilicon Hi6220 stub clock driver.