Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1 | /* |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2 | * A driver for the ARM PL022 PrimeCell SSP/SPI bus master. |
| 3 | * |
Linus Walleij | aeef991 | 2012-09-26 16:48:36 +0200 | [diff] [blame] | 4 | * Copyright (C) 2008-2012 ST-Ericsson AB |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 5 | * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. |
| 6 | * |
| 7 | * Author: Linus Walleij <linus.walleij@stericsson.com> |
| 8 | * |
| 9 | * Initial version inspired by: |
| 10 | * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c |
| 11 | * Initial adoption to PL022 by: |
| 12 | * Sachin Verma <sachin.verma@st.com> |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License as published by |
| 16 | * the Free Software Foundation; either version 2 of the License, or |
| 17 | * (at your option) any later version. |
| 18 | * |
| 19 | * This program is distributed in the hope that it will be useful, |
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 22 | * GNU General Public License for more details. |
| 23 | */ |
| 24 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 25 | #include <linux/init.h> |
| 26 | #include <linux/module.h> |
| 27 | #include <linux/device.h> |
| 28 | #include <linux/ioport.h> |
| 29 | #include <linux/errno.h> |
| 30 | #include <linux/interrupt.h> |
| 31 | #include <linux/spi/spi.h> |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 32 | #include <linux/delay.h> |
| 33 | #include <linux/clk.h> |
| 34 | #include <linux/err.h> |
| 35 | #include <linux/amba/bus.h> |
| 36 | #include <linux/amba/pl022.h> |
| 37 | #include <linux/io.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 38 | #include <linux/slab.h> |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 39 | #include <linux/dmaengine.h> |
| 40 | #include <linux/dma-mapping.h> |
| 41 | #include <linux/scatterlist.h> |
Rabin Vincent | bcda6ff | 2011-06-16 10:14:40 +0200 | [diff] [blame] | 42 | #include <linux/pm_runtime.h> |
Roland Stigge | f6f46de | 2012-08-22 15:49:17 +0200 | [diff] [blame] | 43 | #include <linux/gpio.h> |
Roland Stigge | 6d3952a | 2012-08-22 15:49:18 +0200 | [diff] [blame] | 44 | #include <linux/of_gpio.h> |
Patrice Chotard | 4f5e1b3 | 2012-09-19 14:23:46 +0200 | [diff] [blame] | 45 | #include <linux/pinctrl/consumer.h> |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 46 | |
| 47 | /* |
| 48 | * This macro is used to define some register default values. |
| 49 | * reg is masked with mask, the OR:ed with an (again masked) |
| 50 | * val shifted sb steps to the left. |
| 51 | */ |
| 52 | #define SSP_WRITE_BITS(reg, val, mask, sb) \ |
| 53 | ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) |
| 54 | |
| 55 | /* |
| 56 | * This macro is also used to define some default values. |
| 57 | * It will just shift val by sb steps to the left and mask |
| 58 | * the result with mask. |
| 59 | */ |
| 60 | #define GEN_MASK_BITS(val, mask, sb) \ |
| 61 | (((val)<<(sb)) & (mask)) |
| 62 | |
| 63 | #define DRIVE_TX 0 |
| 64 | #define DO_NOT_DRIVE_TX 1 |
| 65 | |
| 66 | #define DO_NOT_QUEUE_DMA 0 |
| 67 | #define QUEUE_DMA 1 |
| 68 | |
| 69 | #define RX_TRANSFER 1 |
| 70 | #define TX_TRANSFER 2 |
| 71 | |
| 72 | /* |
| 73 | * Macros to access SSP Registers with their offsets |
| 74 | */ |
| 75 | #define SSP_CR0(r) (r + 0x000) |
| 76 | #define SSP_CR1(r) (r + 0x004) |
| 77 | #define SSP_DR(r) (r + 0x008) |
| 78 | #define SSP_SR(r) (r + 0x00C) |
| 79 | #define SSP_CPSR(r) (r + 0x010) |
| 80 | #define SSP_IMSC(r) (r + 0x014) |
| 81 | #define SSP_RIS(r) (r + 0x018) |
| 82 | #define SSP_MIS(r) (r + 0x01C) |
| 83 | #define SSP_ICR(r) (r + 0x020) |
| 84 | #define SSP_DMACR(r) (r + 0x024) |
| 85 | #define SSP_ITCR(r) (r + 0x080) |
| 86 | #define SSP_ITIP(r) (r + 0x084) |
| 87 | #define SSP_ITOP(r) (r + 0x088) |
| 88 | #define SSP_TDR(r) (r + 0x08C) |
| 89 | |
| 90 | #define SSP_PID0(r) (r + 0xFE0) |
| 91 | #define SSP_PID1(r) (r + 0xFE4) |
| 92 | #define SSP_PID2(r) (r + 0xFE8) |
| 93 | #define SSP_PID3(r) (r + 0xFEC) |
| 94 | |
| 95 | #define SSP_CID0(r) (r + 0xFF0) |
| 96 | #define SSP_CID1(r) (r + 0xFF4) |
| 97 | #define SSP_CID2(r) (r + 0xFF8) |
| 98 | #define SSP_CID3(r) (r + 0xFFC) |
| 99 | |
| 100 | /* |
| 101 | * SSP Control Register 0 - SSP_CR0 |
| 102 | */ |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 103 | #define SSP_CR0_MASK_DSS (0x0FUL << 0) |
| 104 | #define SSP_CR0_MASK_FRF (0x3UL << 4) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 105 | #define SSP_CR0_MASK_SPO (0x1UL << 6) |
| 106 | #define SSP_CR0_MASK_SPH (0x1UL << 7) |
| 107 | #define SSP_CR0_MASK_SCR (0xFFUL << 8) |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 108 | |
| 109 | /* |
| 110 | * The ST version of this block moves som bits |
| 111 | * in SSP_CR0 and extends it to 32 bits |
| 112 | */ |
| 113 | #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0) |
| 114 | #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5) |
| 115 | #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16) |
| 116 | #define SSP_CR0_MASK_FRF_ST (0x3UL << 21) |
| 117 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 118 | /* |
| 119 | * SSP Control Register 0 - SSP_CR1 |
| 120 | */ |
| 121 | #define SSP_CR1_MASK_LBM (0x1UL << 0) |
| 122 | #define SSP_CR1_MASK_SSE (0x1UL << 1) |
| 123 | #define SSP_CR1_MASK_MS (0x1UL << 2) |
| 124 | #define SSP_CR1_MASK_SOD (0x1UL << 3) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 125 | |
| 126 | /* |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 127 | * The ST version of this block adds some bits |
| 128 | * in SSP_CR1 |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 129 | */ |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 130 | #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4) |
| 131 | #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5) |
| 132 | #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6) |
| 133 | #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7) |
| 134 | #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10) |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 135 | /* This one is only in the PL023 variant */ |
| 136 | #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 137 | |
| 138 | /* |
| 139 | * SSP Status Register - SSP_SR |
| 140 | */ |
| 141 | #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */ |
| 142 | #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */ |
| 143 | #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */ |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 144 | #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 145 | #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */ |
| 146 | |
| 147 | /* |
| 148 | * SSP Clock Prescale Register - SSP_CPSR |
| 149 | */ |
| 150 | #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0) |
| 151 | |
| 152 | /* |
| 153 | * SSP Interrupt Mask Set/Clear Register - SSP_IMSC |
| 154 | */ |
| 155 | #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */ |
| 156 | #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */ |
| 157 | #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */ |
| 158 | #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */ |
| 159 | |
| 160 | /* |
| 161 | * SSP Raw Interrupt Status Register - SSP_RIS |
| 162 | */ |
| 163 | /* Receive Overrun Raw Interrupt status */ |
| 164 | #define SSP_RIS_MASK_RORRIS (0x1UL << 0) |
| 165 | /* Receive Timeout Raw Interrupt status */ |
| 166 | #define SSP_RIS_MASK_RTRIS (0x1UL << 1) |
| 167 | /* Receive FIFO Raw Interrupt status */ |
| 168 | #define SSP_RIS_MASK_RXRIS (0x1UL << 2) |
| 169 | /* Transmit FIFO Raw Interrupt status */ |
| 170 | #define SSP_RIS_MASK_TXRIS (0x1UL << 3) |
| 171 | |
| 172 | /* |
| 173 | * SSP Masked Interrupt Status Register - SSP_MIS |
| 174 | */ |
| 175 | /* Receive Overrun Masked Interrupt status */ |
| 176 | #define SSP_MIS_MASK_RORMIS (0x1UL << 0) |
| 177 | /* Receive Timeout Masked Interrupt status */ |
| 178 | #define SSP_MIS_MASK_RTMIS (0x1UL << 1) |
| 179 | /* Receive FIFO Masked Interrupt status */ |
| 180 | #define SSP_MIS_MASK_RXMIS (0x1UL << 2) |
| 181 | /* Transmit FIFO Masked Interrupt status */ |
| 182 | #define SSP_MIS_MASK_TXMIS (0x1UL << 3) |
| 183 | |
| 184 | /* |
| 185 | * SSP Interrupt Clear Register - SSP_ICR |
| 186 | */ |
| 187 | /* Receive Overrun Raw Clear Interrupt bit */ |
| 188 | #define SSP_ICR_MASK_RORIC (0x1UL << 0) |
| 189 | /* Receive Timeout Clear Interrupt bit */ |
| 190 | #define SSP_ICR_MASK_RTIC (0x1UL << 1) |
| 191 | |
| 192 | /* |
| 193 | * SSP DMA Control Register - SSP_DMACR |
| 194 | */ |
| 195 | /* Receive DMA Enable bit */ |
| 196 | #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0) |
| 197 | /* Transmit DMA Enable bit */ |
| 198 | #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1) |
| 199 | |
| 200 | /* |
| 201 | * SSP Integration Test control Register - SSP_ITCR |
| 202 | */ |
| 203 | #define SSP_ITCR_MASK_ITEN (0x1UL << 0) |
| 204 | #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1) |
| 205 | |
| 206 | /* |
| 207 | * SSP Integration Test Input Register - SSP_ITIP |
| 208 | */ |
| 209 | #define ITIP_MASK_SSPRXD (0x1UL << 0) |
| 210 | #define ITIP_MASK_SSPFSSIN (0x1UL << 1) |
| 211 | #define ITIP_MASK_SSPCLKIN (0x1UL << 2) |
| 212 | #define ITIP_MASK_RXDMAC (0x1UL << 3) |
| 213 | #define ITIP_MASK_TXDMAC (0x1UL << 4) |
| 214 | #define ITIP_MASK_SSPTXDIN (0x1UL << 5) |
| 215 | |
| 216 | /* |
| 217 | * SSP Integration Test output Register - SSP_ITOP |
| 218 | */ |
| 219 | #define ITOP_MASK_SSPTXD (0x1UL << 0) |
| 220 | #define ITOP_MASK_SSPFSSOUT (0x1UL << 1) |
| 221 | #define ITOP_MASK_SSPCLKOUT (0x1UL << 2) |
| 222 | #define ITOP_MASK_SSPOEn (0x1UL << 3) |
| 223 | #define ITOP_MASK_SSPCTLOEn (0x1UL << 4) |
| 224 | #define ITOP_MASK_RORINTR (0x1UL << 5) |
| 225 | #define ITOP_MASK_RTINTR (0x1UL << 6) |
| 226 | #define ITOP_MASK_RXINTR (0x1UL << 7) |
| 227 | #define ITOP_MASK_TXINTR (0x1UL << 8) |
| 228 | #define ITOP_MASK_INTR (0x1UL << 9) |
| 229 | #define ITOP_MASK_RXDMABREQ (0x1UL << 10) |
| 230 | #define ITOP_MASK_RXDMASREQ (0x1UL << 11) |
| 231 | #define ITOP_MASK_TXDMABREQ (0x1UL << 12) |
| 232 | #define ITOP_MASK_TXDMASREQ (0x1UL << 13) |
| 233 | |
| 234 | /* |
| 235 | * SSP Test Data Register - SSP_TDR |
| 236 | */ |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 237 | #define TDR_MASK_TESTDATA (0xFFFFFFFF) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 238 | |
| 239 | /* |
| 240 | * Message State |
| 241 | * we use the spi_message.state (void *) pointer to |
| 242 | * hold a single state value, that's why all this |
| 243 | * (void *) casting is done here. |
| 244 | */ |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 245 | #define STATE_START ((void *) 0) |
| 246 | #define STATE_RUNNING ((void *) 1) |
| 247 | #define STATE_DONE ((void *) 2) |
| 248 | #define STATE_ERROR ((void *) -1) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 249 | |
| 250 | /* |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 251 | * SSP State - Whether Enabled or Disabled |
| 252 | */ |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 253 | #define SSP_DISABLED (0) |
| 254 | #define SSP_ENABLED (1) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 255 | |
| 256 | /* |
| 257 | * SSP DMA State - Whether DMA Enabled or Disabled |
| 258 | */ |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 259 | #define SSP_DMA_DISABLED (0) |
| 260 | #define SSP_DMA_ENABLED (1) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 261 | |
| 262 | /* |
| 263 | * SSP Clock Defaults |
| 264 | */ |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 265 | #define SSP_DEFAULT_CLKRATE 0x2 |
| 266 | #define SSP_DEFAULT_PRESCALE 0x40 |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 267 | |
| 268 | /* |
| 269 | * SSP Clock Parameter ranges |
| 270 | */ |
| 271 | #define CPSDVR_MIN 0x02 |
| 272 | #define CPSDVR_MAX 0xFE |
| 273 | #define SCR_MIN 0x00 |
| 274 | #define SCR_MAX 0xFF |
| 275 | |
| 276 | /* |
| 277 | * SSP Interrupt related Macros |
| 278 | */ |
| 279 | #define DEFAULT_SSP_REG_IMSC 0x0UL |
| 280 | #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC |
| 281 | #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC) |
| 282 | |
| 283 | #define CLEAR_ALL_INTERRUPTS 0x3 |
| 284 | |
Magnus Templing | a18c266 | 2011-05-19 18:05:34 +0200 | [diff] [blame] | 285 | #define SPI_POLLING_TIMEOUT 1000 |
| 286 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 287 | /* |
| 288 | * The type of reading going on on this chip |
| 289 | */ |
| 290 | enum ssp_reading { |
| 291 | READING_NULL, |
| 292 | READING_U8, |
| 293 | READING_U16, |
| 294 | READING_U32 |
| 295 | }; |
| 296 | |
| 297 | /** |
| 298 | * The type of writing going on on this chip |
| 299 | */ |
| 300 | enum ssp_writing { |
| 301 | WRITING_NULL, |
| 302 | WRITING_U8, |
| 303 | WRITING_U16, |
| 304 | WRITING_U32 |
| 305 | }; |
| 306 | |
| 307 | /** |
| 308 | * struct vendor_data - vendor-specific config parameters |
| 309 | * for PL022 derivates |
| 310 | * @fifodepth: depth of FIFOs (both) |
| 311 | * @max_bpw: maximum number of bits per word |
| 312 | * @unidir: supports unidirection transfers |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 313 | * @extended_cr: 32 bit wide control register 0 with extra |
| 314 | * features and extra features in CR1 as found in the ST variants |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 315 | * @pl023: supports a subset of the ST extensions called "PL023" |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 316 | */ |
| 317 | struct vendor_data { |
| 318 | int fifodepth; |
| 319 | int max_bpw; |
| 320 | bool unidir; |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 321 | bool extended_cr; |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 322 | bool pl023; |
Philippe Langlais | 06fb01f | 2011-03-23 11:05:16 +0100 | [diff] [blame] | 323 | bool loopback; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 324 | }; |
| 325 | |
| 326 | /** |
| 327 | * struct pl022 - This is the private SSP driver data structure |
| 328 | * @adev: AMBA device model hookup |
Linus Walleij | 12e8b32 | 2011-02-08 13:03:55 +0100 | [diff] [blame] | 329 | * @vendor: vendor data for the IP block |
| 330 | * @phybase: the physical memory where the SSP device resides |
| 331 | * @virtbase: the virtual memory where the SSP is mapped |
| 332 | * @clk: outgoing clock "SPICLK" for the SPI bus |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 333 | * @master: SPI framework hookup |
| 334 | * @master_info: controller-specific data from machine setup |
Chris Blair | 14af60b | 2012-02-02 13:59:34 +0100 | [diff] [blame] | 335 | * @kworker: thread struct for message pump |
| 336 | * @kworker_task: pointer to task for message pump kworker thread |
| 337 | * @pump_messages: work struct for scheduling work to the message pump |
Linus Walleij | 12e8b32 | 2011-02-08 13:03:55 +0100 | [diff] [blame] | 338 | * @queue_lock: spinlock to syncronise access to message queue |
| 339 | * @queue: message queue |
Chris Blair | 14af60b | 2012-02-02 13:59:34 +0100 | [diff] [blame] | 340 | * @busy: message pump is busy |
| 341 | * @running: message pump is running |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 342 | * @pump_transfers: Tasklet used in Interrupt Transfer mode |
| 343 | * @cur_msg: Pointer to current spi_message being processed |
| 344 | * @cur_transfer: Pointer to current spi_transfer |
| 345 | * @cur_chip: pointer to current clients chip(assigned from controller_state) |
Virupax Sadashivpetimath | 8b8d719 | 2011-11-10 12:43:24 +0530 | [diff] [blame] | 346 | * @next_msg_cs_active: the next message in the queue has been examined |
| 347 | * and it was found that it uses the same chip select as the previous |
| 348 | * message, so we left it active after the previous transfer, and it's |
| 349 | * active already. |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 350 | * @tx: current position in TX buffer to be read |
| 351 | * @tx_end: end position in TX buffer to be read |
| 352 | * @rx: current position in RX buffer to be written |
| 353 | * @rx_end: end position in RX buffer to be written |
Linus Walleij | 12e8b32 | 2011-02-08 13:03:55 +0100 | [diff] [blame] | 354 | * @read: the type of read currently going on |
| 355 | * @write: the type of write currently going on |
| 356 | * @exp_fifo_level: expected FIFO level |
| 357 | * @dma_rx_channel: optional channel for RX DMA |
| 358 | * @dma_tx_channel: optional channel for TX DMA |
| 359 | * @sgt_rx: scattertable for the RX transfer |
| 360 | * @sgt_tx: scattertable for the TX transfer |
| 361 | * @dummypage: a dummy page used for driving data on the bus with DMA |
Roland Stigge | f6f46de | 2012-08-22 15:49:17 +0200 | [diff] [blame] | 362 | * @cur_cs: current chip select (gpio) |
| 363 | * @chipselects: list of chipselects (gpios) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 364 | */ |
| 365 | struct pl022 { |
| 366 | struct amba_device *adev; |
| 367 | struct vendor_data *vendor; |
| 368 | resource_size_t phybase; |
| 369 | void __iomem *virtbase; |
| 370 | struct clk *clk; |
| 371 | struct spi_master *master; |
| 372 | struct pl022_ssp_controller *master_info; |
Linus Walleij | ffbbdd21 | 2012-02-22 10:05:38 +0100 | [diff] [blame] | 373 | /* Message per-transfer pump */ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 374 | struct tasklet_struct pump_transfers; |
| 375 | struct spi_message *cur_msg; |
| 376 | struct spi_transfer *cur_transfer; |
| 377 | struct chip_data *cur_chip; |
Virupax Sadashivpetimath | 8b8d719 | 2011-11-10 12:43:24 +0530 | [diff] [blame] | 378 | bool next_msg_cs_active; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 379 | void *tx; |
| 380 | void *tx_end; |
| 381 | void *rx; |
| 382 | void *rx_end; |
| 383 | enum ssp_reading read; |
| 384 | enum ssp_writing write; |
Linus Walleij | fc05475 | 2010-01-22 13:53:30 +0100 | [diff] [blame] | 385 | u32 exp_fifo_level; |
Linus Walleij | 083be3f | 2011-06-16 10:14:28 +0200 | [diff] [blame] | 386 | enum ssp_rx_level_trig rx_lev_trig; |
| 387 | enum ssp_tx_level_trig tx_lev_trig; |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 388 | /* DMA settings */ |
| 389 | #ifdef CONFIG_DMA_ENGINE |
| 390 | struct dma_chan *dma_rx_channel; |
| 391 | struct dma_chan *dma_tx_channel; |
| 392 | struct sg_table sgt_rx; |
| 393 | struct sg_table sgt_tx; |
| 394 | char *dummypage; |
Linus Walleij | ffbbdd21 | 2012-02-22 10:05:38 +0100 | [diff] [blame] | 395 | bool dma_running; |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 396 | #endif |
Roland Stigge | f6f46de | 2012-08-22 15:49:17 +0200 | [diff] [blame] | 397 | int cur_cs; |
| 398 | int *chipselects; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 399 | }; |
| 400 | |
| 401 | /** |
| 402 | * struct chip_data - To maintain runtime state of SSP for each client chip |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 403 | * @cr0: Value of control register CR0 of SSP - on later ST variants this |
| 404 | * register is 32 bits wide rather than just 16 |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 405 | * @cr1: Value of control register CR1 of SSP |
| 406 | * @dmacr: Value of DMA control Register of SSP |
| 407 | * @cpsr: Value of Clock prescale register |
| 408 | * @n_bytes: how many bytes(power of 2) reqd for a given data width of client |
| 409 | * @enable_dma: Whether to enable DMA or not |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 410 | * @read: function ptr to be used to read when doing xfer for this chip |
Linus Walleij | 12e8b32 | 2011-02-08 13:03:55 +0100 | [diff] [blame] | 411 | * @write: function ptr to be used to write when doing xfer for this chip |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 412 | * @cs_control: chip select callback provided by chip |
| 413 | * @xfer_type: polling/interrupt/DMA |
| 414 | * |
| 415 | * Runtime state of the SSP controller, maintained per chip, |
| 416 | * This would be set according to the current message that would be served |
| 417 | */ |
| 418 | struct chip_data { |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 419 | u32 cr0; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 420 | u16 cr1; |
| 421 | u16 dmacr; |
| 422 | u16 cpsr; |
| 423 | u8 n_bytes; |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 424 | bool enable_dma; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 425 | enum ssp_reading read; |
| 426 | enum ssp_writing write; |
| 427 | void (*cs_control) (u32 command); |
| 428 | int xfer_type; |
| 429 | }; |
| 430 | |
| 431 | /** |
| 432 | * null_cs_control - Dummy chip select function |
| 433 | * @command: select/delect the chip |
| 434 | * |
| 435 | * If no chip select function is provided by client this is used as dummy |
| 436 | * chip select |
| 437 | */ |
| 438 | static void null_cs_control(u32 command) |
| 439 | { |
| 440 | pr_debug("pl022: dummy chip select control, CS=0x%x\n", command); |
| 441 | } |
| 442 | |
Roland Stigge | f6f46de | 2012-08-22 15:49:17 +0200 | [diff] [blame] | 443 | static void pl022_cs_control(struct pl022 *pl022, u32 command) |
| 444 | { |
| 445 | if (gpio_is_valid(pl022->cur_cs)) |
| 446 | gpio_set_value(pl022->cur_cs, command); |
| 447 | else |
| 448 | pl022->cur_chip->cs_control(command); |
| 449 | } |
| 450 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 451 | /** |
| 452 | * giveback - current spi_message is over, schedule next message and call |
| 453 | * callback of this message. Assumes that caller already |
| 454 | * set message->status; dma and pio irqs are blocked |
| 455 | * @pl022: SSP driver private data structure |
| 456 | */ |
| 457 | static void giveback(struct pl022 *pl022) |
| 458 | { |
| 459 | struct spi_transfer *last_transfer; |
Virupax Sadashivpetimath | 8b8d719 | 2011-11-10 12:43:24 +0530 | [diff] [blame] | 460 | pl022->next_msg_cs_active = false; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 461 | |
Axel Lin | 23e2c2a | 2014-02-12 22:13:27 +0800 | [diff] [blame] | 462 | last_transfer = list_last_entry(&pl022->cur_msg->transfers, |
| 463 | struct spi_transfer, transfer_list); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 464 | |
| 465 | /* Delay if requested before any change in chip select */ |
| 466 | if (last_transfer->delay_usecs) |
| 467 | /* |
| 468 | * FIXME: This runs in interrupt context. |
| 469 | * Is this really smart? |
| 470 | */ |
| 471 | udelay(last_transfer->delay_usecs); |
| 472 | |
Virupax Sadashivpetimath | 8b8d719 | 2011-11-10 12:43:24 +0530 | [diff] [blame] | 473 | if (!last_transfer->cs_change) { |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 474 | struct spi_message *next_msg; |
| 475 | |
Virupax Sadashivpetimath | 8b8d719 | 2011-11-10 12:43:24 +0530 | [diff] [blame] | 476 | /* |
| 477 | * cs_change was not set. We can keep the chip select |
| 478 | * enabled if there is message in the queue and it is |
| 479 | * for the same spi device. |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 480 | * |
| 481 | * We cannot postpone this until pump_messages, because |
| 482 | * after calling msg->complete (below) the driver that |
| 483 | * sent the current message could be unloaded, which |
| 484 | * could invalidate the cs_control() callback... |
| 485 | */ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 486 | /* get a pointer to the next message, if any */ |
Linus Walleij | ffbbdd21 | 2012-02-22 10:05:38 +0100 | [diff] [blame] | 487 | next_msg = spi_get_next_queued_message(pl022->master); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 488 | |
Virupax Sadashivpetimath | 8b8d719 | 2011-11-10 12:43:24 +0530 | [diff] [blame] | 489 | /* |
| 490 | * see if the next and current messages point |
| 491 | * to the same spi device. |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 492 | */ |
Virupax Sadashivpetimath | 8b8d719 | 2011-11-10 12:43:24 +0530 | [diff] [blame] | 493 | if (next_msg && next_msg->spi != pl022->cur_msg->spi) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 494 | next_msg = NULL; |
Virupax Sadashivpetimath | 8b8d719 | 2011-11-10 12:43:24 +0530 | [diff] [blame] | 495 | if (!next_msg || pl022->cur_msg->state == STATE_ERROR) |
Roland Stigge | f6f46de | 2012-08-22 15:49:17 +0200 | [diff] [blame] | 496 | pl022_cs_control(pl022, SSP_CHIP_DESELECT); |
Virupax Sadashivpetimath | 8b8d719 | 2011-11-10 12:43:24 +0530 | [diff] [blame] | 497 | else |
| 498 | pl022->next_msg_cs_active = true; |
Linus Walleij | ffbbdd21 | 2012-02-22 10:05:38 +0100 | [diff] [blame] | 499 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 500 | } |
Virupax Sadashivpetimath | 8b8d719 | 2011-11-10 12:43:24 +0530 | [diff] [blame] | 501 | |
Virupax Sadashivpetimath | 8b8d719 | 2011-11-10 12:43:24 +0530 | [diff] [blame] | 502 | pl022->cur_msg = NULL; |
| 503 | pl022->cur_transfer = NULL; |
| 504 | pl022->cur_chip = NULL; |
Linus Walleij | ffbbdd21 | 2012-02-22 10:05:38 +0100 | [diff] [blame] | 505 | spi_finalize_current_message(pl022->master); |
Virupax Sadashivpetimath | fd31694 | 2012-06-12 15:10:58 +0200 | [diff] [blame] | 506 | |
| 507 | /* disable the SPI/SSP operation */ |
| 508 | writew((readw(SSP_CR1(pl022->virtbase)) & |
| 509 | (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); |
| 510 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 511 | } |
| 512 | |
| 513 | /** |
| 514 | * flush - flush the FIFO to reach a clean state |
| 515 | * @pl022: SSP driver private data structure |
| 516 | */ |
| 517 | static int flush(struct pl022 *pl022) |
| 518 | { |
| 519 | unsigned long limit = loops_per_jiffy << 1; |
| 520 | |
| 521 | dev_dbg(&pl022->adev->dev, "flush\n"); |
| 522 | do { |
| 523 | while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) |
| 524 | readw(SSP_DR(pl022->virtbase)); |
| 525 | } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); |
Linus Walleij | fc05475 | 2010-01-22 13:53:30 +0100 | [diff] [blame] | 526 | |
| 527 | pl022->exp_fifo_level = 0; |
| 528 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 529 | return limit; |
| 530 | } |
| 531 | |
| 532 | /** |
| 533 | * restore_state - Load configuration of current chip |
| 534 | * @pl022: SSP driver private data structure |
| 535 | */ |
| 536 | static void restore_state(struct pl022 *pl022) |
| 537 | { |
| 538 | struct chip_data *chip = pl022->cur_chip; |
| 539 | |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 540 | if (pl022->vendor->extended_cr) |
| 541 | writel(chip->cr0, SSP_CR0(pl022->virtbase)); |
| 542 | else |
| 543 | writew(chip->cr0, SSP_CR0(pl022->virtbase)); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 544 | writew(chip->cr1, SSP_CR1(pl022->virtbase)); |
| 545 | writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); |
| 546 | writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); |
| 547 | writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); |
| 548 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); |
| 549 | } |
| 550 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 551 | /* |
| 552 | * Default SSP Register Values |
| 553 | */ |
| 554 | #define DEFAULT_SSP_REG_CR0 ( \ |
| 555 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \ |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 556 | GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 557 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ |
Linus Walleij | ee2b805 | 2009-08-15 15:12:05 +0100 | [diff] [blame] | 558 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 559 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ |
| 560 | ) |
| 561 | |
| 562 | /* ST versions have slightly different bit layout */ |
| 563 | #define DEFAULT_SSP_REG_CR0_ST ( \ |
| 564 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ |
| 565 | GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \ |
| 566 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ |
| 567 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ |
| 568 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \ |
| 569 | GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \ |
| 570 | GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 571 | ) |
| 572 | |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 573 | /* The PL023 version is slightly different again */ |
| 574 | #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \ |
| 575 | GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \ |
| 576 | GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \ |
| 577 | GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \ |
| 578 | GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \ |
| 579 | ) |
| 580 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 581 | #define DEFAULT_SSP_REG_CR1 ( \ |
| 582 | GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \ |
| 583 | GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ |
| 584 | GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 585 | GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 586 | ) |
| 587 | |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 588 | /* ST versions extend this register to use all 16 bits */ |
| 589 | #define DEFAULT_SSP_REG_CR1_ST ( \ |
| 590 | DEFAULT_SSP_REG_CR1 | \ |
| 591 | GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ |
| 592 | GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ |
| 593 | GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\ |
| 594 | GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ |
| 595 | GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \ |
| 596 | ) |
| 597 | |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 598 | /* |
| 599 | * The PL023 variant has further differences: no loopback mode, no microwire |
| 600 | * support, and a new clock feedback delay setting. |
| 601 | */ |
| 602 | #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \ |
| 603 | GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \ |
| 604 | GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \ |
| 605 | GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \ |
| 606 | GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \ |
| 607 | GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \ |
| 608 | GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \ |
| 609 | GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \ |
| 610 | GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ |
| 611 | ) |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 612 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 613 | #define DEFAULT_SSP_REG_CPSR ( \ |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 614 | GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 615 | ) |
| 616 | |
| 617 | #define DEFAULT_SSP_REG_DMACR (\ |
| 618 | GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \ |
| 619 | GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \ |
| 620 | ) |
| 621 | |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 622 | /** |
| 623 | * load_ssp_default_config - Load default configuration for SSP |
| 624 | * @pl022: SSP driver private data structure |
| 625 | */ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 626 | static void load_ssp_default_config(struct pl022 *pl022) |
| 627 | { |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 628 | if (pl022->vendor->pl023) { |
| 629 | writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); |
| 630 | writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); |
| 631 | } else if (pl022->vendor->extended_cr) { |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 632 | writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); |
| 633 | writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); |
| 634 | } else { |
| 635 | writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); |
| 636 | writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); |
| 637 | } |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 638 | writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); |
| 639 | writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); |
| 640 | writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); |
| 641 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); |
| 642 | } |
| 643 | |
| 644 | /** |
| 645 | * This will write to TX and read from RX according to the parameters |
| 646 | * set in pl022. |
| 647 | */ |
| 648 | static void readwriter(struct pl022 *pl022) |
| 649 | { |
| 650 | |
| 651 | /* |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 652 | * The FIFO depth is different between primecell variants. |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 653 | * I believe filling in too much in the FIFO might cause |
| 654 | * errons in 8bit wide transfers on ARM variants (just 8 words |
| 655 | * FIFO, means only 8x8 = 64 bits in FIFO) at least. |
| 656 | * |
Linus Walleij | fc05475 | 2010-01-22 13:53:30 +0100 | [diff] [blame] | 657 | * To prevent this issue, the TX FIFO is only filled to the |
| 658 | * unused RX FIFO fill length, regardless of what the TX |
| 659 | * FIFO status flag indicates. |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 660 | */ |
| 661 | dev_dbg(&pl022->adev->dev, |
| 662 | "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", |
| 663 | __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end); |
| 664 | |
| 665 | /* Read as much as you can */ |
| 666 | while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) |
| 667 | && (pl022->rx < pl022->rx_end)) { |
| 668 | switch (pl022->read) { |
| 669 | case READING_NULL: |
| 670 | readw(SSP_DR(pl022->virtbase)); |
| 671 | break; |
| 672 | case READING_U8: |
| 673 | *(u8 *) (pl022->rx) = |
| 674 | readw(SSP_DR(pl022->virtbase)) & 0xFFU; |
| 675 | break; |
| 676 | case READING_U16: |
| 677 | *(u16 *) (pl022->rx) = |
| 678 | (u16) readw(SSP_DR(pl022->virtbase)); |
| 679 | break; |
| 680 | case READING_U32: |
| 681 | *(u32 *) (pl022->rx) = |
| 682 | readl(SSP_DR(pl022->virtbase)); |
| 683 | break; |
| 684 | } |
| 685 | pl022->rx += (pl022->cur_chip->n_bytes); |
Linus Walleij | fc05475 | 2010-01-22 13:53:30 +0100 | [diff] [blame] | 686 | pl022->exp_fifo_level--; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 687 | } |
| 688 | /* |
Linus Walleij | fc05475 | 2010-01-22 13:53:30 +0100 | [diff] [blame] | 689 | * Write as much as possible up to the RX FIFO size |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 690 | */ |
Linus Walleij | fc05475 | 2010-01-22 13:53:30 +0100 | [diff] [blame] | 691 | while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 692 | && (pl022->tx < pl022->tx_end)) { |
| 693 | switch (pl022->write) { |
| 694 | case WRITING_NULL: |
| 695 | writew(0x0, SSP_DR(pl022->virtbase)); |
| 696 | break; |
| 697 | case WRITING_U8: |
| 698 | writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase)); |
| 699 | break; |
| 700 | case WRITING_U16: |
| 701 | writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase)); |
| 702 | break; |
| 703 | case WRITING_U32: |
| 704 | writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase)); |
| 705 | break; |
| 706 | } |
| 707 | pl022->tx += (pl022->cur_chip->n_bytes); |
Linus Walleij | fc05475 | 2010-01-22 13:53:30 +0100 | [diff] [blame] | 708 | pl022->exp_fifo_level++; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 709 | /* |
| 710 | * This inner reader takes care of things appearing in the RX |
| 711 | * FIFO as we're transmitting. This will happen a lot since the |
| 712 | * clock starts running when you put things into the TX FIFO, |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 713 | * and then things are continuously clocked into the RX FIFO. |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 714 | */ |
| 715 | while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) |
| 716 | && (pl022->rx < pl022->rx_end)) { |
| 717 | switch (pl022->read) { |
| 718 | case READING_NULL: |
| 719 | readw(SSP_DR(pl022->virtbase)); |
| 720 | break; |
| 721 | case READING_U8: |
| 722 | *(u8 *) (pl022->rx) = |
| 723 | readw(SSP_DR(pl022->virtbase)) & 0xFFU; |
| 724 | break; |
| 725 | case READING_U16: |
| 726 | *(u16 *) (pl022->rx) = |
| 727 | (u16) readw(SSP_DR(pl022->virtbase)); |
| 728 | break; |
| 729 | case READING_U32: |
| 730 | *(u32 *) (pl022->rx) = |
| 731 | readl(SSP_DR(pl022->virtbase)); |
| 732 | break; |
| 733 | } |
| 734 | pl022->rx += (pl022->cur_chip->n_bytes); |
Linus Walleij | fc05475 | 2010-01-22 13:53:30 +0100 | [diff] [blame] | 735 | pl022->exp_fifo_level--; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 736 | } |
| 737 | } |
| 738 | /* |
| 739 | * When we exit here the TX FIFO should be full and the RX FIFO |
| 740 | * should be empty |
| 741 | */ |
| 742 | } |
| 743 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 744 | /** |
| 745 | * next_transfer - Move to the Next transfer in the current spi message |
| 746 | * @pl022: SSP driver private data structure |
| 747 | * |
| 748 | * This function moves though the linked list of spi transfers in the |
| 749 | * current spi message and returns with the state of current spi |
| 750 | * message i.e whether its last transfer is done(STATE_DONE) or |
| 751 | * Next transfer is ready(STATE_RUNNING) |
| 752 | */ |
| 753 | static void *next_transfer(struct pl022 *pl022) |
| 754 | { |
| 755 | struct spi_message *msg = pl022->cur_msg; |
| 756 | struct spi_transfer *trans = pl022->cur_transfer; |
| 757 | |
| 758 | /* Move to next transfer */ |
| 759 | if (trans->transfer_list.next != &msg->transfers) { |
| 760 | pl022->cur_transfer = |
| 761 | list_entry(trans->transfer_list.next, |
| 762 | struct spi_transfer, transfer_list); |
| 763 | return STATE_RUNNING; |
| 764 | } |
| 765 | return STATE_DONE; |
| 766 | } |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 767 | |
| 768 | /* |
| 769 | * This DMA functionality is only compiled in if we have |
| 770 | * access to the generic DMA devices/DMA engine. |
| 771 | */ |
| 772 | #ifdef CONFIG_DMA_ENGINE |
| 773 | static void unmap_free_dma_scatter(struct pl022 *pl022) |
| 774 | { |
| 775 | /* Unmap and free the SG tables */ |
Linus Walleij | b729889 | 2010-12-22 23:13:07 +0100 | [diff] [blame] | 776 | dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl, |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 777 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
Linus Walleij | b729889 | 2010-12-22 23:13:07 +0100 | [diff] [blame] | 778 | dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl, |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 779 | pl022->sgt_rx.nents, DMA_FROM_DEVICE); |
| 780 | sg_free_table(&pl022->sgt_rx); |
| 781 | sg_free_table(&pl022->sgt_tx); |
| 782 | } |
| 783 | |
| 784 | static void dma_callback(void *data) |
| 785 | { |
| 786 | struct pl022 *pl022 = data; |
| 787 | struct spi_message *msg = pl022->cur_msg; |
| 788 | |
| 789 | BUG_ON(!pl022->sgt_rx.sgl); |
| 790 | |
| 791 | #ifdef VERBOSE_DEBUG |
| 792 | /* |
| 793 | * Optionally dump out buffers to inspect contents, this is |
| 794 | * good if you want to convince yourself that the loopback |
| 795 | * read/write contents are the same, when adopting to a new |
| 796 | * DMA engine. |
| 797 | */ |
| 798 | { |
| 799 | struct scatterlist *sg; |
| 800 | unsigned int i; |
| 801 | |
| 802 | dma_sync_sg_for_cpu(&pl022->adev->dev, |
| 803 | pl022->sgt_rx.sgl, |
| 804 | pl022->sgt_rx.nents, |
| 805 | DMA_FROM_DEVICE); |
| 806 | |
| 807 | for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) { |
| 808 | dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i); |
| 809 | print_hex_dump(KERN_ERR, "SPI RX: ", |
| 810 | DUMP_PREFIX_OFFSET, |
| 811 | 16, |
| 812 | 1, |
| 813 | sg_virt(sg), |
| 814 | sg_dma_len(sg), |
| 815 | 1); |
| 816 | } |
| 817 | for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) { |
| 818 | dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i); |
| 819 | print_hex_dump(KERN_ERR, "SPI TX: ", |
| 820 | DUMP_PREFIX_OFFSET, |
| 821 | 16, |
| 822 | 1, |
| 823 | sg_virt(sg), |
| 824 | sg_dma_len(sg), |
| 825 | 1); |
| 826 | } |
| 827 | } |
| 828 | #endif |
| 829 | |
| 830 | unmap_free_dma_scatter(pl022); |
| 831 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 832 | /* Update total bytes transferred */ |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 833 | msg->actual_length += pl022->cur_transfer->len; |
| 834 | if (pl022->cur_transfer->cs_change) |
Roland Stigge | f6f46de | 2012-08-22 15:49:17 +0200 | [diff] [blame] | 835 | pl022_cs_control(pl022, SSP_CHIP_DESELECT); |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 836 | |
| 837 | /* Move to next transfer */ |
| 838 | msg->state = next_transfer(pl022); |
| 839 | tasklet_schedule(&pl022->pump_transfers); |
| 840 | } |
| 841 | |
| 842 | static void setup_dma_scatter(struct pl022 *pl022, |
| 843 | void *buffer, |
| 844 | unsigned int length, |
| 845 | struct sg_table *sgtab) |
| 846 | { |
| 847 | struct scatterlist *sg; |
| 848 | int bytesleft = length; |
| 849 | void *bufp = buffer; |
| 850 | int mapbytes; |
| 851 | int i; |
| 852 | |
| 853 | if (buffer) { |
| 854 | for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { |
| 855 | /* |
| 856 | * If there are less bytes left than what fits |
| 857 | * in the current page (plus page alignment offset) |
| 858 | * we just feed in this, else we stuff in as much |
| 859 | * as we can. |
| 860 | */ |
| 861 | if (bytesleft < (PAGE_SIZE - offset_in_page(bufp))) |
| 862 | mapbytes = bytesleft; |
| 863 | else |
| 864 | mapbytes = PAGE_SIZE - offset_in_page(bufp); |
| 865 | sg_set_page(sg, virt_to_page(bufp), |
| 866 | mapbytes, offset_in_page(bufp)); |
| 867 | bufp += mapbytes; |
| 868 | bytesleft -= mapbytes; |
| 869 | dev_dbg(&pl022->adev->dev, |
| 870 | "set RX/TX target page @ %p, %d bytes, %d left\n", |
| 871 | bufp, mapbytes, bytesleft); |
| 872 | } |
| 873 | } else { |
| 874 | /* Map the dummy buffer on every page */ |
| 875 | for_each_sg(sgtab->sgl, sg, sgtab->nents, i) { |
| 876 | if (bytesleft < PAGE_SIZE) |
| 877 | mapbytes = bytesleft; |
| 878 | else |
| 879 | mapbytes = PAGE_SIZE; |
| 880 | sg_set_page(sg, virt_to_page(pl022->dummypage), |
| 881 | mapbytes, 0); |
| 882 | bytesleft -= mapbytes; |
| 883 | dev_dbg(&pl022->adev->dev, |
| 884 | "set RX/TX to dummy page %d bytes, %d left\n", |
| 885 | mapbytes, bytesleft); |
| 886 | |
| 887 | } |
| 888 | } |
| 889 | BUG_ON(bytesleft); |
| 890 | } |
| 891 | |
| 892 | /** |
| 893 | * configure_dma - configures the channels for the next transfer |
| 894 | * @pl022: SSP driver's private data structure |
| 895 | */ |
| 896 | static int configure_dma(struct pl022 *pl022) |
| 897 | { |
| 898 | struct dma_slave_config rx_conf = { |
| 899 | .src_addr = SSP_DR(pl022->phybase), |
Vinod Koul | a485df4 | 2011-10-14 10:47:38 +0530 | [diff] [blame] | 900 | .direction = DMA_DEV_TO_MEM, |
Viresh Kumar | 258aea7 | 2012-02-01 16:12:19 +0530 | [diff] [blame] | 901 | .device_fc = false, |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 902 | }; |
| 903 | struct dma_slave_config tx_conf = { |
| 904 | .dst_addr = SSP_DR(pl022->phybase), |
Vinod Koul | a485df4 | 2011-10-14 10:47:38 +0530 | [diff] [blame] | 905 | .direction = DMA_MEM_TO_DEV, |
Viresh Kumar | 258aea7 | 2012-02-01 16:12:19 +0530 | [diff] [blame] | 906 | .device_fc = false, |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 907 | }; |
| 908 | unsigned int pages; |
| 909 | int ret; |
Linus Walleij | 082086f | 2010-12-22 23:13:37 +0100 | [diff] [blame] | 910 | int rx_sglen, tx_sglen; |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 911 | struct dma_chan *rxchan = pl022->dma_rx_channel; |
| 912 | struct dma_chan *txchan = pl022->dma_tx_channel; |
| 913 | struct dma_async_tx_descriptor *rxdesc; |
| 914 | struct dma_async_tx_descriptor *txdesc; |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 915 | |
| 916 | /* Check that the channels are available */ |
| 917 | if (!rxchan || !txchan) |
| 918 | return -ENODEV; |
| 919 | |
Linus Walleij | 083be3f | 2011-06-16 10:14:28 +0200 | [diff] [blame] | 920 | /* |
| 921 | * If supplied, the DMA burstsize should equal the FIFO trigger level. |
| 922 | * Notice that the DMA engine uses one-to-one mapping. Since we can |
| 923 | * not trigger on 2 elements this needs explicit mapping rather than |
| 924 | * calculation. |
| 925 | */ |
| 926 | switch (pl022->rx_lev_trig) { |
| 927 | case SSP_RX_1_OR_MORE_ELEM: |
| 928 | rx_conf.src_maxburst = 1; |
| 929 | break; |
| 930 | case SSP_RX_4_OR_MORE_ELEM: |
| 931 | rx_conf.src_maxburst = 4; |
| 932 | break; |
| 933 | case SSP_RX_8_OR_MORE_ELEM: |
| 934 | rx_conf.src_maxburst = 8; |
| 935 | break; |
| 936 | case SSP_RX_16_OR_MORE_ELEM: |
| 937 | rx_conf.src_maxburst = 16; |
| 938 | break; |
| 939 | case SSP_RX_32_OR_MORE_ELEM: |
| 940 | rx_conf.src_maxburst = 32; |
| 941 | break; |
| 942 | default: |
| 943 | rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; |
| 944 | break; |
| 945 | } |
| 946 | |
| 947 | switch (pl022->tx_lev_trig) { |
| 948 | case SSP_TX_1_OR_MORE_EMPTY_LOC: |
| 949 | tx_conf.dst_maxburst = 1; |
| 950 | break; |
| 951 | case SSP_TX_4_OR_MORE_EMPTY_LOC: |
| 952 | tx_conf.dst_maxburst = 4; |
| 953 | break; |
| 954 | case SSP_TX_8_OR_MORE_EMPTY_LOC: |
| 955 | tx_conf.dst_maxburst = 8; |
| 956 | break; |
| 957 | case SSP_TX_16_OR_MORE_EMPTY_LOC: |
| 958 | tx_conf.dst_maxburst = 16; |
| 959 | break; |
| 960 | case SSP_TX_32_OR_MORE_EMPTY_LOC: |
| 961 | tx_conf.dst_maxburst = 32; |
| 962 | break; |
| 963 | default: |
| 964 | tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; |
| 965 | break; |
| 966 | } |
| 967 | |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 968 | switch (pl022->read) { |
| 969 | case READING_NULL: |
| 970 | /* Use the same as for writing */ |
| 971 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; |
| 972 | break; |
| 973 | case READING_U8: |
| 974 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
| 975 | break; |
| 976 | case READING_U16: |
| 977 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; |
| 978 | break; |
| 979 | case READING_U32: |
| 980 | rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
| 981 | break; |
| 982 | } |
| 983 | |
| 984 | switch (pl022->write) { |
| 985 | case WRITING_NULL: |
| 986 | /* Use the same as for reading */ |
| 987 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; |
| 988 | break; |
| 989 | case WRITING_U8: |
| 990 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
| 991 | break; |
| 992 | case WRITING_U16: |
| 993 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; |
| 994 | break; |
| 995 | case WRITING_U32: |
Joe Perches | bc3f67a | 2010-11-14 19:04:47 -0800 | [diff] [blame] | 996 | tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 997 | break; |
| 998 | } |
| 999 | |
| 1000 | /* SPI pecularity: we need to read and write the same width */ |
| 1001 | if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) |
| 1002 | rx_conf.src_addr_width = tx_conf.dst_addr_width; |
| 1003 | if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) |
| 1004 | tx_conf.dst_addr_width = rx_conf.src_addr_width; |
| 1005 | BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width); |
| 1006 | |
Linus Walleij | ecd442f | 2011-02-08 13:03:12 +0100 | [diff] [blame] | 1007 | dmaengine_slave_config(rxchan, &rx_conf); |
| 1008 | dmaengine_slave_config(txchan, &tx_conf); |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1009 | |
| 1010 | /* Create sglists for the transfers */ |
Viresh Kumar | b181565 | 2011-08-10 17:12:11 +0530 | [diff] [blame] | 1011 | pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE); |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1012 | dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages); |
| 1013 | |
Viresh Kumar | 538a18d | 2011-08-10 14:20:55 +0530 | [diff] [blame] | 1014 | ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC); |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1015 | if (ret) |
| 1016 | goto err_alloc_rx_sg; |
| 1017 | |
Viresh Kumar | 538a18d | 2011-08-10 14:20:55 +0530 | [diff] [blame] | 1018 | ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC); |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1019 | if (ret) |
| 1020 | goto err_alloc_tx_sg; |
| 1021 | |
| 1022 | /* Fill in the scatterlists for the RX+TX buffers */ |
| 1023 | setup_dma_scatter(pl022, pl022->rx, |
| 1024 | pl022->cur_transfer->len, &pl022->sgt_rx); |
| 1025 | setup_dma_scatter(pl022, pl022->tx, |
| 1026 | pl022->cur_transfer->len, &pl022->sgt_tx); |
| 1027 | |
| 1028 | /* Map DMA buffers */ |
Linus Walleij | 082086f | 2010-12-22 23:13:37 +0100 | [diff] [blame] | 1029 | rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl, |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1030 | pl022->sgt_rx.nents, DMA_FROM_DEVICE); |
Linus Walleij | 082086f | 2010-12-22 23:13:37 +0100 | [diff] [blame] | 1031 | if (!rx_sglen) |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1032 | goto err_rx_sgmap; |
| 1033 | |
Linus Walleij | 082086f | 2010-12-22 23:13:37 +0100 | [diff] [blame] | 1034 | tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl, |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1035 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
Linus Walleij | 082086f | 2010-12-22 23:13:37 +0100 | [diff] [blame] | 1036 | if (!tx_sglen) |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1037 | goto err_tx_sgmap; |
| 1038 | |
| 1039 | /* Send both scatterlists */ |
Alexandre Bounine | 1605282 | 2012-03-08 16:11:18 -0500 | [diff] [blame] | 1040 | rxdesc = dmaengine_prep_slave_sg(rxchan, |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1041 | pl022->sgt_rx.sgl, |
Linus Walleij | 082086f | 2010-12-22 23:13:37 +0100 | [diff] [blame] | 1042 | rx_sglen, |
Vinod Koul | a485df4 | 2011-10-14 10:47:38 +0530 | [diff] [blame] | 1043 | DMA_DEV_TO_MEM, |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1044 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 1045 | if (!rxdesc) |
| 1046 | goto err_rxdesc; |
| 1047 | |
Alexandre Bounine | 1605282 | 2012-03-08 16:11:18 -0500 | [diff] [blame] | 1048 | txdesc = dmaengine_prep_slave_sg(txchan, |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1049 | pl022->sgt_tx.sgl, |
Linus Walleij | 082086f | 2010-12-22 23:13:37 +0100 | [diff] [blame] | 1050 | tx_sglen, |
Vinod Koul | a485df4 | 2011-10-14 10:47:38 +0530 | [diff] [blame] | 1051 | DMA_MEM_TO_DEV, |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1052 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 1053 | if (!txdesc) |
| 1054 | goto err_txdesc; |
| 1055 | |
| 1056 | /* Put the callback on the RX transfer only, that should finish last */ |
| 1057 | rxdesc->callback = dma_callback; |
| 1058 | rxdesc->callback_param = pl022; |
| 1059 | |
| 1060 | /* Submit and fire RX and TX with TX last so we're ready to read! */ |
Linus Walleij | ecd442f | 2011-02-08 13:03:12 +0100 | [diff] [blame] | 1061 | dmaengine_submit(rxdesc); |
| 1062 | dmaengine_submit(txdesc); |
| 1063 | dma_async_issue_pending(rxchan); |
| 1064 | dma_async_issue_pending(txchan); |
Linus Walleij | ffbbdd21 | 2012-02-22 10:05:38 +0100 | [diff] [blame] | 1065 | pl022->dma_running = true; |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1066 | |
| 1067 | return 0; |
| 1068 | |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1069 | err_txdesc: |
Linus Walleij | ecd442f | 2011-02-08 13:03:12 +0100 | [diff] [blame] | 1070 | dmaengine_terminate_all(txchan); |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1071 | err_rxdesc: |
Linus Walleij | ecd442f | 2011-02-08 13:03:12 +0100 | [diff] [blame] | 1072 | dmaengine_terminate_all(rxchan); |
Linus Walleij | b729889 | 2010-12-22 23:13:07 +0100 | [diff] [blame] | 1073 | dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl, |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1074 | pl022->sgt_tx.nents, DMA_TO_DEVICE); |
| 1075 | err_tx_sgmap: |
Linus Walleij | b729889 | 2010-12-22 23:13:07 +0100 | [diff] [blame] | 1076 | dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl, |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1077 | pl022->sgt_tx.nents, DMA_FROM_DEVICE); |
| 1078 | err_rx_sgmap: |
| 1079 | sg_free_table(&pl022->sgt_tx); |
| 1080 | err_alloc_tx_sg: |
| 1081 | sg_free_table(&pl022->sgt_rx); |
| 1082 | err_alloc_rx_sg: |
| 1083 | return -ENOMEM; |
| 1084 | } |
| 1085 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 1086 | static int pl022_dma_probe(struct pl022 *pl022) |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1087 | { |
| 1088 | dma_cap_mask_t mask; |
| 1089 | |
| 1090 | /* Try to acquire a generic DMA engine slave channel */ |
| 1091 | dma_cap_zero(mask); |
| 1092 | dma_cap_set(DMA_SLAVE, mask); |
| 1093 | /* |
| 1094 | * We need both RX and TX channels to do DMA, else do none |
| 1095 | * of them. |
| 1096 | */ |
| 1097 | pl022->dma_rx_channel = dma_request_channel(mask, |
| 1098 | pl022->master_info->dma_filter, |
| 1099 | pl022->master_info->dma_rx_param); |
| 1100 | if (!pl022->dma_rx_channel) { |
Viresh Kumar | 43c6401 | 2011-05-16 09:40:10 +0530 | [diff] [blame] | 1101 | dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n"); |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1102 | goto err_no_rxchan; |
| 1103 | } |
| 1104 | |
| 1105 | pl022->dma_tx_channel = dma_request_channel(mask, |
| 1106 | pl022->master_info->dma_filter, |
| 1107 | pl022->master_info->dma_tx_param); |
| 1108 | if (!pl022->dma_tx_channel) { |
Viresh Kumar | 43c6401 | 2011-05-16 09:40:10 +0530 | [diff] [blame] | 1109 | dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n"); |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1110 | goto err_no_txchan; |
| 1111 | } |
| 1112 | |
| 1113 | pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); |
Jingoo Han | 77538f4 | 2014-04-29 17:19:01 +0900 | [diff] [blame] | 1114 | if (!pl022->dummypage) |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1115 | goto err_no_dummypage; |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1116 | |
| 1117 | dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n", |
| 1118 | dma_chan_name(pl022->dma_rx_channel), |
| 1119 | dma_chan_name(pl022->dma_tx_channel)); |
| 1120 | |
| 1121 | return 0; |
| 1122 | |
| 1123 | err_no_dummypage: |
| 1124 | dma_release_channel(pl022->dma_tx_channel); |
| 1125 | err_no_txchan: |
| 1126 | dma_release_channel(pl022->dma_rx_channel); |
| 1127 | pl022->dma_rx_channel = NULL; |
| 1128 | err_no_rxchan: |
Viresh Kumar | 43c6401 | 2011-05-16 09:40:10 +0530 | [diff] [blame] | 1129 | dev_err(&pl022->adev->dev, |
| 1130 | "Failed to work in dma mode, work without dma!\n"); |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1131 | return -ENODEV; |
| 1132 | } |
| 1133 | |
Arnd Bergmann | dc71545 | 2013-01-28 16:24:37 +0000 | [diff] [blame] | 1134 | static int pl022_dma_autoprobe(struct pl022 *pl022) |
| 1135 | { |
| 1136 | struct device *dev = &pl022->adev->dev; |
| 1137 | |
| 1138 | /* automatically configure DMA channels from platform, normally using DT */ |
| 1139 | pl022->dma_rx_channel = dma_request_slave_channel(dev, "rx"); |
| 1140 | if (!pl022->dma_rx_channel) |
| 1141 | goto err_no_rxchan; |
| 1142 | |
| 1143 | pl022->dma_tx_channel = dma_request_slave_channel(dev, "tx"); |
| 1144 | if (!pl022->dma_tx_channel) |
| 1145 | goto err_no_txchan; |
| 1146 | |
| 1147 | pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL); |
| 1148 | if (!pl022->dummypage) |
| 1149 | goto err_no_dummypage; |
| 1150 | |
| 1151 | return 0; |
| 1152 | |
| 1153 | err_no_dummypage: |
| 1154 | dma_release_channel(pl022->dma_tx_channel); |
| 1155 | pl022->dma_tx_channel = NULL; |
| 1156 | err_no_txchan: |
| 1157 | dma_release_channel(pl022->dma_rx_channel); |
| 1158 | pl022->dma_rx_channel = NULL; |
| 1159 | err_no_rxchan: |
| 1160 | return -ENODEV; |
| 1161 | } |
| 1162 | |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1163 | static void terminate_dma(struct pl022 *pl022) |
| 1164 | { |
| 1165 | struct dma_chan *rxchan = pl022->dma_rx_channel; |
| 1166 | struct dma_chan *txchan = pl022->dma_tx_channel; |
| 1167 | |
Linus Walleij | ecd442f | 2011-02-08 13:03:12 +0100 | [diff] [blame] | 1168 | dmaengine_terminate_all(rxchan); |
| 1169 | dmaengine_terminate_all(txchan); |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1170 | unmap_free_dma_scatter(pl022); |
Linus Walleij | ffbbdd21 | 2012-02-22 10:05:38 +0100 | [diff] [blame] | 1171 | pl022->dma_running = false; |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1172 | } |
| 1173 | |
| 1174 | static void pl022_dma_remove(struct pl022 *pl022) |
| 1175 | { |
Linus Walleij | ffbbdd21 | 2012-02-22 10:05:38 +0100 | [diff] [blame] | 1176 | if (pl022->dma_running) |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1177 | terminate_dma(pl022); |
| 1178 | if (pl022->dma_tx_channel) |
| 1179 | dma_release_channel(pl022->dma_tx_channel); |
| 1180 | if (pl022->dma_rx_channel) |
| 1181 | dma_release_channel(pl022->dma_rx_channel); |
| 1182 | kfree(pl022->dummypage); |
| 1183 | } |
| 1184 | |
| 1185 | #else |
| 1186 | static inline int configure_dma(struct pl022 *pl022) |
| 1187 | { |
| 1188 | return -ENODEV; |
| 1189 | } |
| 1190 | |
Arnd Bergmann | dc71545 | 2013-01-28 16:24:37 +0000 | [diff] [blame] | 1191 | static inline int pl022_dma_autoprobe(struct pl022 *pl022) |
| 1192 | { |
| 1193 | return 0; |
| 1194 | } |
| 1195 | |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1196 | static inline int pl022_dma_probe(struct pl022 *pl022) |
| 1197 | { |
| 1198 | return 0; |
| 1199 | } |
| 1200 | |
| 1201 | static inline void pl022_dma_remove(struct pl022 *pl022) |
| 1202 | { |
| 1203 | } |
| 1204 | #endif |
| 1205 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1206 | /** |
| 1207 | * pl022_interrupt_handler - Interrupt handler for SSP controller |
| 1208 | * |
| 1209 | * This function handles interrupts generated for an interrupt based transfer. |
| 1210 | * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the |
| 1211 | * current message's state as STATE_ERROR and schedule the tasklet |
| 1212 | * pump_transfers which will do the postprocessing of the current message by |
| 1213 | * calling giveback(). Otherwise it reads data from RX FIFO till there is no |
| 1214 | * more data, and writes data in TX FIFO till it is not full. If we complete |
| 1215 | * the transfer we move to the next transfer and schedule the tasklet. |
| 1216 | */ |
| 1217 | static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id) |
| 1218 | { |
| 1219 | struct pl022 *pl022 = dev_id; |
| 1220 | struct spi_message *msg = pl022->cur_msg; |
| 1221 | u16 irq_status = 0; |
| 1222 | u16 flag = 0; |
| 1223 | |
| 1224 | if (unlikely(!msg)) { |
| 1225 | dev_err(&pl022->adev->dev, |
| 1226 | "bad message state in interrupt handler"); |
| 1227 | /* Never fail */ |
| 1228 | return IRQ_HANDLED; |
| 1229 | } |
| 1230 | |
| 1231 | /* Read the Interrupt Status Register */ |
| 1232 | irq_status = readw(SSP_MIS(pl022->virtbase)); |
| 1233 | |
| 1234 | if (unlikely(!irq_status)) |
| 1235 | return IRQ_NONE; |
| 1236 | |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1237 | /* |
| 1238 | * This handles the FIFO interrupts, the timeout |
| 1239 | * interrupts are flatly ignored, they cannot be |
| 1240 | * trusted. |
| 1241 | */ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1242 | if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) { |
| 1243 | /* |
| 1244 | * Overrun interrupt - bail out since our Data has been |
| 1245 | * corrupted |
| 1246 | */ |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1247 | dev_err(&pl022->adev->dev, "FIFO overrun\n"); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1248 | if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF) |
| 1249 | dev_err(&pl022->adev->dev, |
| 1250 | "RXFIFO is full\n"); |
| 1251 | if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF) |
| 1252 | dev_err(&pl022->adev->dev, |
| 1253 | "TXFIFO is full\n"); |
| 1254 | |
| 1255 | /* |
| 1256 | * Disable and clear interrupts, disable SSP, |
| 1257 | * mark message with bad status so it can be |
| 1258 | * retried. |
| 1259 | */ |
| 1260 | writew(DISABLE_ALL_INTERRUPTS, |
| 1261 | SSP_IMSC(pl022->virtbase)); |
| 1262 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); |
| 1263 | writew((readw(SSP_CR1(pl022->virtbase)) & |
| 1264 | (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); |
| 1265 | msg->state = STATE_ERROR; |
| 1266 | |
| 1267 | /* Schedule message queue handler */ |
| 1268 | tasklet_schedule(&pl022->pump_transfers); |
| 1269 | return IRQ_HANDLED; |
| 1270 | } |
| 1271 | |
| 1272 | readwriter(pl022); |
| 1273 | |
| 1274 | if ((pl022->tx == pl022->tx_end) && (flag == 0)) { |
| 1275 | flag = 1; |
Chris Blair | 172289d | 2011-06-04 07:57:47 +0100 | [diff] [blame] | 1276 | /* Disable Transmit interrupt, enable receive interrupt */ |
| 1277 | writew((readw(SSP_IMSC(pl022->virtbase)) & |
| 1278 | ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM, |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1279 | SSP_IMSC(pl022->virtbase)); |
| 1280 | } |
| 1281 | |
| 1282 | /* |
| 1283 | * Since all transactions must write as much as shall be read, |
| 1284 | * we can conclude the entire transaction once RX is complete. |
| 1285 | * At this point, all TX will always be finished. |
| 1286 | */ |
| 1287 | if (pl022->rx >= pl022->rx_end) { |
| 1288 | writew(DISABLE_ALL_INTERRUPTS, |
| 1289 | SSP_IMSC(pl022->virtbase)); |
| 1290 | writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); |
| 1291 | if (unlikely(pl022->rx > pl022->rx_end)) { |
| 1292 | dev_warn(&pl022->adev->dev, "read %u surplus " |
| 1293 | "bytes (did you request an odd " |
| 1294 | "number of bytes on a 16bit bus?)\n", |
| 1295 | (u32) (pl022->rx - pl022->rx_end)); |
| 1296 | } |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 1297 | /* Update total bytes transferred */ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1298 | msg->actual_length += pl022->cur_transfer->len; |
| 1299 | if (pl022->cur_transfer->cs_change) |
Roland Stigge | f6f46de | 2012-08-22 15:49:17 +0200 | [diff] [blame] | 1300 | pl022_cs_control(pl022, SSP_CHIP_DESELECT); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1301 | /* Move to next transfer */ |
| 1302 | msg->state = next_transfer(pl022); |
| 1303 | tasklet_schedule(&pl022->pump_transfers); |
| 1304 | return IRQ_HANDLED; |
| 1305 | } |
| 1306 | |
| 1307 | return IRQ_HANDLED; |
| 1308 | } |
| 1309 | |
| 1310 | /** |
| 1311 | * This sets up the pointers to memory for the next message to |
| 1312 | * send out on the SPI bus. |
| 1313 | */ |
| 1314 | static int set_up_next_transfer(struct pl022 *pl022, |
| 1315 | struct spi_transfer *transfer) |
| 1316 | { |
| 1317 | int residue; |
| 1318 | |
| 1319 | /* Sanity check the message for this bus width */ |
| 1320 | residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes; |
| 1321 | if (unlikely(residue != 0)) { |
| 1322 | dev_err(&pl022->adev->dev, |
| 1323 | "message of %u bytes to transmit but the current " |
| 1324 | "chip bus has a data width of %u bytes!\n", |
| 1325 | pl022->cur_transfer->len, |
| 1326 | pl022->cur_chip->n_bytes); |
| 1327 | dev_err(&pl022->adev->dev, "skipping this message\n"); |
| 1328 | return -EIO; |
| 1329 | } |
| 1330 | pl022->tx = (void *)transfer->tx_buf; |
| 1331 | pl022->tx_end = pl022->tx + pl022->cur_transfer->len; |
| 1332 | pl022->rx = (void *)transfer->rx_buf; |
| 1333 | pl022->rx_end = pl022->rx + pl022->cur_transfer->len; |
| 1334 | pl022->write = |
| 1335 | pl022->tx ? pl022->cur_chip->write : WRITING_NULL; |
| 1336 | pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL; |
| 1337 | return 0; |
| 1338 | } |
| 1339 | |
| 1340 | /** |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1341 | * pump_transfers - Tasklet function which schedules next transfer |
| 1342 | * when running in interrupt or DMA transfer mode. |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1343 | * @data: SSP driver private data structure |
| 1344 | * |
| 1345 | */ |
| 1346 | static void pump_transfers(unsigned long data) |
| 1347 | { |
| 1348 | struct pl022 *pl022 = (struct pl022 *) data; |
| 1349 | struct spi_message *message = NULL; |
| 1350 | struct spi_transfer *transfer = NULL; |
| 1351 | struct spi_transfer *previous = NULL; |
| 1352 | |
| 1353 | /* Get current state information */ |
| 1354 | message = pl022->cur_msg; |
| 1355 | transfer = pl022->cur_transfer; |
| 1356 | |
| 1357 | /* Handle for abort */ |
| 1358 | if (message->state == STATE_ERROR) { |
| 1359 | message->status = -EIO; |
| 1360 | giveback(pl022); |
| 1361 | return; |
| 1362 | } |
| 1363 | |
| 1364 | /* Handle end of message */ |
| 1365 | if (message->state == STATE_DONE) { |
| 1366 | message->status = 0; |
| 1367 | giveback(pl022); |
| 1368 | return; |
| 1369 | } |
| 1370 | |
| 1371 | /* Delay if requested at end of transfer before CS change */ |
| 1372 | if (message->state == STATE_RUNNING) { |
| 1373 | previous = list_entry(transfer->transfer_list.prev, |
| 1374 | struct spi_transfer, |
| 1375 | transfer_list); |
| 1376 | if (previous->delay_usecs) |
| 1377 | /* |
| 1378 | * FIXME: This runs in interrupt context. |
| 1379 | * Is this really smart? |
| 1380 | */ |
| 1381 | udelay(previous->delay_usecs); |
| 1382 | |
Virupax Sadashivpetimath | 8b8d719 | 2011-11-10 12:43:24 +0530 | [diff] [blame] | 1383 | /* Reselect chip select only if cs_change was requested */ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1384 | if (previous->cs_change) |
Roland Stigge | f6f46de | 2012-08-22 15:49:17 +0200 | [diff] [blame] | 1385 | pl022_cs_control(pl022, SSP_CHIP_SELECT); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1386 | } else { |
| 1387 | /* STATE_START */ |
| 1388 | message->state = STATE_RUNNING; |
| 1389 | } |
| 1390 | |
| 1391 | if (set_up_next_transfer(pl022, transfer)) { |
| 1392 | message->state = STATE_ERROR; |
| 1393 | message->status = -EIO; |
| 1394 | giveback(pl022); |
| 1395 | return; |
| 1396 | } |
| 1397 | /* Flush the FIFOs and let's go! */ |
| 1398 | flush(pl022); |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1399 | |
| 1400 | if (pl022->cur_chip->enable_dma) { |
| 1401 | if (configure_dma(pl022)) { |
| 1402 | dev_dbg(&pl022->adev->dev, |
| 1403 | "configuration of DMA failed, fall back to interrupt mode\n"); |
| 1404 | goto err_config_dma; |
| 1405 | } |
| 1406 | return; |
| 1407 | } |
| 1408 | |
| 1409 | err_config_dma: |
Chris Blair | 172289d | 2011-06-04 07:57:47 +0100 | [diff] [blame] | 1410 | /* enable all interrupts except RX */ |
| 1411 | writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase)); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1412 | } |
| 1413 | |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1414 | static void do_interrupt_dma_transfer(struct pl022 *pl022) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1415 | { |
Chris Blair | 172289d | 2011-06-04 07:57:47 +0100 | [diff] [blame] | 1416 | /* |
| 1417 | * Default is to enable all interrupts except RX - |
| 1418 | * this will be enabled once TX is complete |
| 1419 | */ |
Mark Brown | d555ea0 | 2014-08-01 17:47:38 +0100 | [diff] [blame] | 1420 | u32 irqflags = (u32)(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1421 | |
Virupax Sadashivpetimath | 8b8d719 | 2011-11-10 12:43:24 +0530 | [diff] [blame] | 1422 | /* Enable target chip, if not already active */ |
| 1423 | if (!pl022->next_msg_cs_active) |
Roland Stigge | f6f46de | 2012-08-22 15:49:17 +0200 | [diff] [blame] | 1424 | pl022_cs_control(pl022, SSP_CHIP_SELECT); |
Virupax Sadashivpetimath | 8b8d719 | 2011-11-10 12:43:24 +0530 | [diff] [blame] | 1425 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1426 | if (set_up_next_transfer(pl022, pl022->cur_transfer)) { |
| 1427 | /* Error path */ |
| 1428 | pl022->cur_msg->state = STATE_ERROR; |
| 1429 | pl022->cur_msg->status = -EIO; |
| 1430 | giveback(pl022); |
| 1431 | return; |
| 1432 | } |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1433 | /* If we're using DMA, set up DMA here */ |
| 1434 | if (pl022->cur_chip->enable_dma) { |
| 1435 | /* Configure DMA transfer */ |
| 1436 | if (configure_dma(pl022)) { |
| 1437 | dev_dbg(&pl022->adev->dev, |
| 1438 | "configuration of DMA failed, fall back to interrupt mode\n"); |
| 1439 | goto err_config_dma; |
| 1440 | } |
| 1441 | /* Disable interrupts in DMA mode, IRQ from DMA controller */ |
| 1442 | irqflags = DISABLE_ALL_INTERRUPTS; |
| 1443 | } |
| 1444 | err_config_dma: |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1445 | /* Enable SSP, turn on interrupts */ |
| 1446 | writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), |
| 1447 | SSP_CR1(pl022->virtbase)); |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1448 | writew(irqflags, SSP_IMSC(pl022->virtbase)); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1449 | } |
| 1450 | |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1451 | static void do_polling_transfer(struct pl022 *pl022) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1452 | { |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1453 | struct spi_message *message = NULL; |
| 1454 | struct spi_transfer *transfer = NULL; |
| 1455 | struct spi_transfer *previous = NULL; |
| 1456 | struct chip_data *chip; |
Magnus Templing | a18c266 | 2011-05-19 18:05:34 +0200 | [diff] [blame] | 1457 | unsigned long time, timeout; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1458 | |
| 1459 | chip = pl022->cur_chip; |
| 1460 | message = pl022->cur_msg; |
| 1461 | |
| 1462 | while (message->state != STATE_DONE) { |
| 1463 | /* Handle for abort */ |
| 1464 | if (message->state == STATE_ERROR) |
| 1465 | break; |
| 1466 | transfer = pl022->cur_transfer; |
| 1467 | |
| 1468 | /* Delay if requested at end of transfer */ |
| 1469 | if (message->state == STATE_RUNNING) { |
| 1470 | previous = |
| 1471 | list_entry(transfer->transfer_list.prev, |
| 1472 | struct spi_transfer, transfer_list); |
| 1473 | if (previous->delay_usecs) |
| 1474 | udelay(previous->delay_usecs); |
| 1475 | if (previous->cs_change) |
Roland Stigge | f6f46de | 2012-08-22 15:49:17 +0200 | [diff] [blame] | 1476 | pl022_cs_control(pl022, SSP_CHIP_SELECT); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1477 | } else { |
| 1478 | /* STATE_START */ |
| 1479 | message->state = STATE_RUNNING; |
Virupax Sadashivpetimath | 8b8d719 | 2011-11-10 12:43:24 +0530 | [diff] [blame] | 1480 | if (!pl022->next_msg_cs_active) |
Roland Stigge | f6f46de | 2012-08-22 15:49:17 +0200 | [diff] [blame] | 1481 | pl022_cs_control(pl022, SSP_CHIP_SELECT); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1482 | } |
| 1483 | |
| 1484 | /* Configuration Changing Per Transfer */ |
| 1485 | if (set_up_next_transfer(pl022, transfer)) { |
| 1486 | /* Error path */ |
| 1487 | message->state = STATE_ERROR; |
| 1488 | break; |
| 1489 | } |
| 1490 | /* Flush FIFOs and enable SSP */ |
| 1491 | flush(pl022); |
| 1492 | writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE), |
| 1493 | SSP_CR1(pl022->virtbase)); |
| 1494 | |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 1495 | dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n"); |
Magnus Templing | a18c266 | 2011-05-19 18:05:34 +0200 | [diff] [blame] | 1496 | |
| 1497 | timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT); |
| 1498 | while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) { |
| 1499 | time = jiffies; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1500 | readwriter(pl022); |
Magnus Templing | a18c266 | 2011-05-19 18:05:34 +0200 | [diff] [blame] | 1501 | if (time_after(time, timeout)) { |
| 1502 | dev_warn(&pl022->adev->dev, |
| 1503 | "%s: timeout!\n", __func__); |
| 1504 | message->state = STATE_ERROR; |
| 1505 | goto out; |
| 1506 | } |
Linus Walleij | 521999b | 2011-05-19 20:01:25 +0200 | [diff] [blame] | 1507 | cpu_relax(); |
Magnus Templing | a18c266 | 2011-05-19 18:05:34 +0200 | [diff] [blame] | 1508 | } |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1509 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 1510 | /* Update total byte transferred */ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1511 | message->actual_length += pl022->cur_transfer->len; |
| 1512 | if (pl022->cur_transfer->cs_change) |
Roland Stigge | f6f46de | 2012-08-22 15:49:17 +0200 | [diff] [blame] | 1513 | pl022_cs_control(pl022, SSP_CHIP_DESELECT); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1514 | /* Move to next transfer */ |
| 1515 | message->state = next_transfer(pl022); |
| 1516 | } |
Magnus Templing | a18c266 | 2011-05-19 18:05:34 +0200 | [diff] [blame] | 1517 | out: |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1518 | /* Handle end of message */ |
| 1519 | if (message->state == STATE_DONE) |
| 1520 | message->status = 0; |
| 1521 | else |
| 1522 | message->status = -EIO; |
| 1523 | |
| 1524 | giveback(pl022); |
| 1525 | return; |
| 1526 | } |
| 1527 | |
Linus Walleij | ffbbdd21 | 2012-02-22 10:05:38 +0100 | [diff] [blame] | 1528 | static int pl022_transfer_one_message(struct spi_master *master, |
| 1529 | struct spi_message *msg) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1530 | { |
Linus Walleij | ffbbdd21 | 2012-02-22 10:05:38 +0100 | [diff] [blame] | 1531 | struct pl022 *pl022 = spi_master_get_devdata(master); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1532 | |
| 1533 | /* Initial message state */ |
Linus Walleij | ffbbdd21 | 2012-02-22 10:05:38 +0100 | [diff] [blame] | 1534 | pl022->cur_msg = msg; |
| 1535 | msg->state = STATE_START; |
| 1536 | |
| 1537 | pl022->cur_transfer = list_entry(msg->transfers.next, |
| 1538 | struct spi_transfer, transfer_list); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1539 | |
| 1540 | /* Setup the SPI using the per chip configuration */ |
Linus Walleij | ffbbdd21 | 2012-02-22 10:05:38 +0100 | [diff] [blame] | 1541 | pl022->cur_chip = spi_get_ctldata(msg->spi); |
Roland Stigge | f6f46de | 2012-08-22 15:49:17 +0200 | [diff] [blame] | 1542 | pl022->cur_cs = pl022->chipselects[msg->spi->chip_select]; |
Chris Blair | d4b6af2 | 2011-11-04 07:43:41 +0000 | [diff] [blame] | 1543 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1544 | restore_state(pl022); |
| 1545 | flush(pl022); |
| 1546 | |
| 1547 | if (pl022->cur_chip->xfer_type == POLLING_TRANSFER) |
| 1548 | do_polling_transfer(pl022); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1549 | else |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1550 | do_interrupt_dma_transfer(pl022); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1551 | |
| 1552 | return 0; |
| 1553 | } |
| 1554 | |
Linus Walleij | ffbbdd21 | 2012-02-22 10:05:38 +0100 | [diff] [blame] | 1555 | static int pl022_unprepare_transfer_hardware(struct spi_master *master) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1556 | { |
Linus Walleij | ffbbdd21 | 2012-02-22 10:05:38 +0100 | [diff] [blame] | 1557 | struct pl022 *pl022 = spi_master_get_devdata(master); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1558 | |
Linus Walleij | ffbbdd21 | 2012-02-22 10:05:38 +0100 | [diff] [blame] | 1559 | /* nothing more to do - disable spi/ssp and power off */ |
| 1560 | writew((readw(SSP_CR1(pl022->virtbase)) & |
| 1561 | (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1562 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1563 | return 0; |
| 1564 | } |
| 1565 | |
| 1566 | static int verify_controller_parameters(struct pl022 *pl022, |
Linus Walleij | f9d629c | 2010-10-01 13:33:13 +0200 | [diff] [blame] | 1567 | struct pl022_config_chip const *chip_info) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1568 | { |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1569 | if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI) |
| 1570 | || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) { |
Linus Walleij | 5a1c98b | 2010-10-01 11:47:32 +0200 | [diff] [blame] | 1571 | dev_err(&pl022->adev->dev, |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1572 | "interface is configured incorrectly\n"); |
| 1573 | return -EINVAL; |
| 1574 | } |
| 1575 | if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) && |
| 1576 | (!pl022->vendor->unidir)) { |
Linus Walleij | 5a1c98b | 2010-10-01 11:47:32 +0200 | [diff] [blame] | 1577 | dev_err(&pl022->adev->dev, |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1578 | "unidirectional mode not supported in this " |
| 1579 | "hardware version\n"); |
| 1580 | return -EINVAL; |
| 1581 | } |
| 1582 | if ((chip_info->hierarchy != SSP_MASTER) |
| 1583 | && (chip_info->hierarchy != SSP_SLAVE)) { |
Linus Walleij | 5a1c98b | 2010-10-01 11:47:32 +0200 | [diff] [blame] | 1584 | dev_err(&pl022->adev->dev, |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1585 | "hierarchy is configured incorrectly\n"); |
| 1586 | return -EINVAL; |
| 1587 | } |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1588 | if ((chip_info->com_mode != INTERRUPT_TRANSFER) |
| 1589 | && (chip_info->com_mode != DMA_TRANSFER) |
| 1590 | && (chip_info->com_mode != POLLING_TRANSFER)) { |
Linus Walleij | 5a1c98b | 2010-10-01 11:47:32 +0200 | [diff] [blame] | 1591 | dev_err(&pl022->adev->dev, |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1592 | "Communication mode is configured incorrectly\n"); |
| 1593 | return -EINVAL; |
| 1594 | } |
Linus Walleij | 78b2b91 | 2011-06-16 10:14:46 +0200 | [diff] [blame] | 1595 | switch (chip_info->rx_lev_trig) { |
| 1596 | case SSP_RX_1_OR_MORE_ELEM: |
| 1597 | case SSP_RX_4_OR_MORE_ELEM: |
| 1598 | case SSP_RX_8_OR_MORE_ELEM: |
| 1599 | /* These are always OK, all variants can handle this */ |
| 1600 | break; |
| 1601 | case SSP_RX_16_OR_MORE_ELEM: |
| 1602 | if (pl022->vendor->fifodepth < 16) { |
| 1603 | dev_err(&pl022->adev->dev, |
| 1604 | "RX FIFO Trigger Level is configured incorrectly\n"); |
| 1605 | return -EINVAL; |
| 1606 | } |
| 1607 | break; |
| 1608 | case SSP_RX_32_OR_MORE_ELEM: |
| 1609 | if (pl022->vendor->fifodepth < 32) { |
| 1610 | dev_err(&pl022->adev->dev, |
| 1611 | "RX FIFO Trigger Level is configured incorrectly\n"); |
| 1612 | return -EINVAL; |
| 1613 | } |
| 1614 | break; |
| 1615 | default: |
Linus Walleij | 5a1c98b | 2010-10-01 11:47:32 +0200 | [diff] [blame] | 1616 | dev_err(&pl022->adev->dev, |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1617 | "RX FIFO Trigger Level is configured incorrectly\n"); |
| 1618 | return -EINVAL; |
| 1619 | } |
Linus Walleij | 78b2b91 | 2011-06-16 10:14:46 +0200 | [diff] [blame] | 1620 | switch (chip_info->tx_lev_trig) { |
| 1621 | case SSP_TX_1_OR_MORE_EMPTY_LOC: |
| 1622 | case SSP_TX_4_OR_MORE_EMPTY_LOC: |
| 1623 | case SSP_TX_8_OR_MORE_EMPTY_LOC: |
| 1624 | /* These are always OK, all variants can handle this */ |
| 1625 | break; |
| 1626 | case SSP_TX_16_OR_MORE_EMPTY_LOC: |
| 1627 | if (pl022->vendor->fifodepth < 16) { |
| 1628 | dev_err(&pl022->adev->dev, |
| 1629 | "TX FIFO Trigger Level is configured incorrectly\n"); |
| 1630 | return -EINVAL; |
| 1631 | } |
| 1632 | break; |
| 1633 | case SSP_TX_32_OR_MORE_EMPTY_LOC: |
| 1634 | if (pl022->vendor->fifodepth < 32) { |
| 1635 | dev_err(&pl022->adev->dev, |
| 1636 | "TX FIFO Trigger Level is configured incorrectly\n"); |
| 1637 | return -EINVAL; |
| 1638 | } |
| 1639 | break; |
| 1640 | default: |
Linus Walleij | 5a1c98b | 2010-10-01 11:47:32 +0200 | [diff] [blame] | 1641 | dev_err(&pl022->adev->dev, |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1642 | "TX FIFO Trigger Level is configured incorrectly\n"); |
| 1643 | return -EINVAL; |
| 1644 | } |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1645 | if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) { |
| 1646 | if ((chip_info->ctrl_len < SSP_BITS_4) |
| 1647 | || (chip_info->ctrl_len > SSP_BITS_32)) { |
Linus Walleij | 5a1c98b | 2010-10-01 11:47:32 +0200 | [diff] [blame] | 1648 | dev_err(&pl022->adev->dev, |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1649 | "CTRL LEN is configured incorrectly\n"); |
| 1650 | return -EINVAL; |
| 1651 | } |
| 1652 | if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO) |
| 1653 | && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) { |
Linus Walleij | 5a1c98b | 2010-10-01 11:47:32 +0200 | [diff] [blame] | 1654 | dev_err(&pl022->adev->dev, |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1655 | "Wait State is configured incorrectly\n"); |
| 1656 | return -EINVAL; |
| 1657 | } |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 1658 | /* Half duplex is only available in the ST Micro version */ |
| 1659 | if (pl022->vendor->extended_cr) { |
| 1660 | if ((chip_info->duplex != |
| 1661 | SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) |
| 1662 | && (chip_info->duplex != |
Julia Lawall | 4a4fd47 | 2010-09-29 17:31:30 +0900 | [diff] [blame] | 1663 | SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) { |
Linus Walleij | 5a1c98b | 2010-10-01 11:47:32 +0200 | [diff] [blame] | 1664 | dev_err(&pl022->adev->dev, |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 1665 | "Microwire duplex mode is configured incorrectly\n"); |
| 1666 | return -EINVAL; |
Julia Lawall | 4a4fd47 | 2010-09-29 17:31:30 +0900 | [diff] [blame] | 1667 | } |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 1668 | } else { |
| 1669 | if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) |
Linus Walleij | 5a1c98b | 2010-10-01 11:47:32 +0200 | [diff] [blame] | 1670 | dev_err(&pl022->adev->dev, |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 1671 | "Microwire half duplex mode requested," |
| 1672 | " but this is only available in the" |
| 1673 | " ST version of PL022\n"); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1674 | return -EINVAL; |
| 1675 | } |
| 1676 | } |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1677 | return 0; |
| 1678 | } |
| 1679 | |
Viresh Kumar | 0379b2a | 2011-08-10 14:20:57 +0530 | [diff] [blame] | 1680 | static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) |
| 1681 | { |
| 1682 | return rate / (cpsdvsr * (1 + scr)); |
| 1683 | } |
| 1684 | |
| 1685 | static int calculate_effective_freq(struct pl022 *pl022, int freq, struct |
| 1686 | ssp_clock_params * clk_freq) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1687 | { |
| 1688 | /* Lets calculate the frequency parameters */ |
Viresh Kumar | 0379b2a | 2011-08-10 14:20:57 +0530 | [diff] [blame] | 1689 | u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN; |
| 1690 | u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0, |
| 1691 | best_scr = 0, tmp, found = 0; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1692 | |
| 1693 | rate = clk_get_rate(pl022->clk); |
| 1694 | /* cpsdvscr = 2 & scr 0 */ |
Viresh Kumar | 0379b2a | 2011-08-10 14:20:57 +0530 | [diff] [blame] | 1695 | max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1696 | /* cpsdvsr = 254 & scr = 255 */ |
Viresh Kumar | 0379b2a | 2011-08-10 14:20:57 +0530 | [diff] [blame] | 1697 | min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1698 | |
Viresh Kumar | ea505bc | 2012-04-19 11:48:15 +0530 | [diff] [blame] | 1699 | if (freq > max_tclk) |
| 1700 | dev_warn(&pl022->adev->dev, |
| 1701 | "Max speed that can be programmed is %d Hz, you requested %d\n", |
| 1702 | max_tclk, freq); |
| 1703 | |
| 1704 | if (freq < min_tclk) { |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1705 | dev_err(&pl022->adev->dev, |
Viresh Kumar | ea505bc | 2012-04-19 11:48:15 +0530 | [diff] [blame] | 1706 | "Requested frequency: %d Hz is less than minimum possible %d Hz\n", |
| 1707 | freq, min_tclk); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1708 | return -EINVAL; |
| 1709 | } |
Viresh Kumar | 0379b2a | 2011-08-10 14:20:57 +0530 | [diff] [blame] | 1710 | |
| 1711 | /* |
| 1712 | * best_freq will give closest possible available rate (<= requested |
| 1713 | * freq) for all values of scr & cpsdvsr. |
| 1714 | */ |
| 1715 | while ((cpsdvsr <= CPSDVR_MAX) && !found) { |
| 1716 | while (scr <= SCR_MAX) { |
| 1717 | tmp = spi_rate(rate, cpsdvsr, scr); |
| 1718 | |
Viresh Kumar | 5eb806a | 2012-04-19 14:44:21 +0530 | [diff] [blame] | 1719 | if (tmp > freq) { |
| 1720 | /* we need lower freq */ |
Viresh Kumar | 0379b2a | 2011-08-10 14:20:57 +0530 | [diff] [blame] | 1721 | scr++; |
Viresh Kumar | 5eb806a | 2012-04-19 14:44:21 +0530 | [diff] [blame] | 1722 | continue; |
| 1723 | } |
| 1724 | |
Viresh Kumar | 0379b2a | 2011-08-10 14:20:57 +0530 | [diff] [blame] | 1725 | /* |
Viresh Kumar | 5eb806a | 2012-04-19 14:44:21 +0530 | [diff] [blame] | 1726 | * If found exact value, mark found and break. |
| 1727 | * If found more closer value, update and break. |
Viresh Kumar | 0379b2a | 2011-08-10 14:20:57 +0530 | [diff] [blame] | 1728 | */ |
Viresh Kumar | 5eb806a | 2012-04-19 14:44:21 +0530 | [diff] [blame] | 1729 | if (tmp > best_freq) { |
Viresh Kumar | 0379b2a | 2011-08-10 14:20:57 +0530 | [diff] [blame] | 1730 | best_freq = tmp; |
| 1731 | best_cpsdvsr = cpsdvsr; |
| 1732 | best_scr = scr; |
| 1733 | |
| 1734 | if (tmp == freq) |
Viresh Kumar | 5eb806a | 2012-04-19 14:44:21 +0530 | [diff] [blame] | 1735 | found = 1; |
Viresh Kumar | 0379b2a | 2011-08-10 14:20:57 +0530 | [diff] [blame] | 1736 | } |
Viresh Kumar | 5eb806a | 2012-04-19 14:44:21 +0530 | [diff] [blame] | 1737 | /* |
| 1738 | * increased scr will give lower rates, which are not |
| 1739 | * required |
| 1740 | */ |
| 1741 | break; |
Viresh Kumar | 0379b2a | 2011-08-10 14:20:57 +0530 | [diff] [blame] | 1742 | } |
| 1743 | cpsdvsr += 2; |
| 1744 | scr = SCR_MIN; |
| 1745 | } |
| 1746 | |
Viresh Kumar | 5eb806a | 2012-04-19 14:44:21 +0530 | [diff] [blame] | 1747 | WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n", |
| 1748 | freq); |
| 1749 | |
Viresh Kumar | 0379b2a | 2011-08-10 14:20:57 +0530 | [diff] [blame] | 1750 | clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF); |
| 1751 | clk_freq->scr = (u8) (best_scr & 0xFF); |
| 1752 | dev_dbg(&pl022->adev->dev, |
| 1753 | "SSP Target Frequency is: %u, Effective Frequency is %u\n", |
| 1754 | freq, best_freq); |
| 1755 | dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n", |
| 1756 | clk_freq->cpsdvsr, clk_freq->scr); |
| 1757 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1758 | return 0; |
| 1759 | } |
| 1760 | |
Linus Walleij | f9d629c | 2010-10-01 13:33:13 +0200 | [diff] [blame] | 1761 | /* |
| 1762 | * A piece of default chip info unless the platform |
| 1763 | * supplies it. |
| 1764 | */ |
| 1765 | static const struct pl022_config_chip pl022_default_chip_info = { |
| 1766 | .com_mode = POLLING_TRANSFER, |
| 1767 | .iface = SSP_INTERFACE_MOTOROLA_SPI, |
| 1768 | .hierarchy = SSP_SLAVE, |
| 1769 | .slave_tx_disable = DO_NOT_DRIVE_TX, |
| 1770 | .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, |
| 1771 | .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, |
| 1772 | .ctrl_len = SSP_BITS_8, |
| 1773 | .wait_state = SSP_MWIRE_WAIT_ZERO, |
| 1774 | .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, |
| 1775 | .cs_control = null_cs_control, |
| 1776 | }; |
| 1777 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1778 | /** |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1779 | * pl022_setup - setup function registered to SPI master framework |
| 1780 | * @spi: spi device which is requesting setup |
| 1781 | * |
| 1782 | * This function is registered to the SPI framework for this SPI master |
| 1783 | * controller. If it is the first time when setup is called by this device, |
| 1784 | * this function will initialize the runtime state for this chip and save |
| 1785 | * the same in the device structure. Else it will update the runtime info |
| 1786 | * with the updated chip info. Nothing is really being written to the |
| 1787 | * controller hardware here, that is not done until the actual transfer |
| 1788 | * commence. |
| 1789 | */ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1790 | static int pl022_setup(struct spi_device *spi) |
| 1791 | { |
Linus Walleij | f9d629c | 2010-10-01 13:33:13 +0200 | [diff] [blame] | 1792 | struct pl022_config_chip const *chip_info; |
Roland Stigge | 6d3952a | 2012-08-22 15:49:18 +0200 | [diff] [blame] | 1793 | struct pl022_config_chip chip_info_dt; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1794 | struct chip_data *chip; |
Jonas Aaberg | c4a4784 | 2011-02-28 16:42:41 +0100 | [diff] [blame] | 1795 | struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0}; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1796 | int status = 0; |
| 1797 | struct pl022 *pl022 = spi_master_get_devdata(spi->master); |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame] | 1798 | unsigned int bits = spi->bits_per_word; |
| 1799 | u32 tmp; |
Roland Stigge | 6d3952a | 2012-08-22 15:49:18 +0200 | [diff] [blame] | 1800 | struct device_node *np = spi->dev.of_node; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1801 | |
| 1802 | if (!spi->max_speed_hz) |
| 1803 | return -EINVAL; |
| 1804 | |
| 1805 | /* Get controller_state if one is supplied */ |
| 1806 | chip = spi_get_ctldata(spi); |
| 1807 | |
| 1808 | if (chip == NULL) { |
| 1809 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
Jingoo Han | 77538f4 | 2014-04-29 17:19:01 +0900 | [diff] [blame] | 1810 | if (!chip) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1811 | return -ENOMEM; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1812 | dev_dbg(&spi->dev, |
| 1813 | "allocated memory for controller's runtime state\n"); |
| 1814 | } |
| 1815 | |
| 1816 | /* Get controller data if one is supplied */ |
| 1817 | chip_info = spi->controller_data; |
| 1818 | |
| 1819 | if (chip_info == NULL) { |
Roland Stigge | 6d3952a | 2012-08-22 15:49:18 +0200 | [diff] [blame] | 1820 | if (np) { |
| 1821 | chip_info_dt = pl022_default_chip_info; |
| 1822 | |
| 1823 | chip_info_dt.hierarchy = SSP_MASTER; |
| 1824 | of_property_read_u32(np, "pl022,interface", |
| 1825 | &chip_info_dt.iface); |
| 1826 | of_property_read_u32(np, "pl022,com-mode", |
| 1827 | &chip_info_dt.com_mode); |
| 1828 | of_property_read_u32(np, "pl022,rx-level-trig", |
| 1829 | &chip_info_dt.rx_lev_trig); |
| 1830 | of_property_read_u32(np, "pl022,tx-level-trig", |
| 1831 | &chip_info_dt.tx_lev_trig); |
| 1832 | of_property_read_u32(np, "pl022,ctrl-len", |
| 1833 | &chip_info_dt.ctrl_len); |
| 1834 | of_property_read_u32(np, "pl022,wait-state", |
| 1835 | &chip_info_dt.wait_state); |
| 1836 | of_property_read_u32(np, "pl022,duplex", |
| 1837 | &chip_info_dt.duplex); |
| 1838 | |
| 1839 | chip_info = &chip_info_dt; |
| 1840 | } else { |
| 1841 | chip_info = &pl022_default_chip_info; |
| 1842 | /* spi_board_info.controller_data not is supplied */ |
| 1843 | dev_dbg(&spi->dev, |
| 1844 | "using default controller_data settings\n"); |
| 1845 | } |
Linus Walleij | f9d629c | 2010-10-01 13:33:13 +0200 | [diff] [blame] | 1846 | } else |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1847 | dev_dbg(&spi->dev, |
| 1848 | "using user supplied controller_data settings\n"); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1849 | |
| 1850 | /* |
| 1851 | * We can override with custom divisors, else we use the board |
| 1852 | * frequency setting |
| 1853 | */ |
| 1854 | if ((0 == chip_info->clk_freq.cpsdvsr) |
| 1855 | && (0 == chip_info->clk_freq.scr)) { |
| 1856 | status = calculate_effective_freq(pl022, |
| 1857 | spi->max_speed_hz, |
Linus Walleij | f9d629c | 2010-10-01 13:33:13 +0200 | [diff] [blame] | 1858 | &clk_freq); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1859 | if (status < 0) |
| 1860 | goto err_config_params; |
| 1861 | } else { |
Linus Walleij | f9d629c | 2010-10-01 13:33:13 +0200 | [diff] [blame] | 1862 | memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq)); |
| 1863 | if ((clk_freq.cpsdvsr % 2) != 0) |
| 1864 | clk_freq.cpsdvsr = |
| 1865 | clk_freq.cpsdvsr - 1; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1866 | } |
Linus Walleij | f9d629c | 2010-10-01 13:33:13 +0200 | [diff] [blame] | 1867 | if ((clk_freq.cpsdvsr < CPSDVR_MIN) |
| 1868 | || (clk_freq.cpsdvsr > CPSDVR_MAX)) { |
Virupax Sadashivpetimath | e3f88ae | 2011-06-13 16:23:46 +0530 | [diff] [blame] | 1869 | status = -EINVAL; |
Linus Walleij | f9d629c | 2010-10-01 13:33:13 +0200 | [diff] [blame] | 1870 | dev_err(&spi->dev, |
| 1871 | "cpsdvsr is configured incorrectly\n"); |
| 1872 | goto err_config_params; |
| 1873 | } |
| 1874 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1875 | status = verify_controller_parameters(pl022, chip_info); |
| 1876 | if (status) { |
| 1877 | dev_err(&spi->dev, "controller data is incorrect"); |
| 1878 | goto err_config_params; |
| 1879 | } |
Linus Walleij | f9d629c | 2010-10-01 13:33:13 +0200 | [diff] [blame] | 1880 | |
Linus Walleij | 083be3f | 2011-06-16 10:14:28 +0200 | [diff] [blame] | 1881 | pl022->rx_lev_trig = chip_info->rx_lev_trig; |
| 1882 | pl022->tx_lev_trig = chip_info->tx_lev_trig; |
| 1883 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1884 | /* Now set controller state based on controller data */ |
| 1885 | chip->xfer_type = chip_info->com_mode; |
Linus Walleij | f9d629c | 2010-10-01 13:33:13 +0200 | [diff] [blame] | 1886 | if (!chip_info->cs_control) { |
| 1887 | chip->cs_control = null_cs_control; |
Roland Stigge | f6f46de | 2012-08-22 15:49:17 +0200 | [diff] [blame] | 1888 | if (!gpio_is_valid(pl022->chipselects[spi->chip_select])) |
| 1889 | dev_warn(&spi->dev, |
| 1890 | "invalid chip select\n"); |
Linus Walleij | f9d629c | 2010-10-01 13:33:13 +0200 | [diff] [blame] | 1891 | } else |
| 1892 | chip->cs_control = chip_info->cs_control; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1893 | |
Vinit Shenoy | eb798c6 | 2012-04-17 12:40:13 +0530 | [diff] [blame] | 1894 | /* Check bits per word with vendor specific range */ |
| 1895 | if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) { |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame] | 1896 | status = -ENOTSUPP; |
Vinit Shenoy | eb798c6 | 2012-04-17 12:40:13 +0530 | [diff] [blame] | 1897 | dev_err(&spi->dev, "illegal data size for this controller!\n"); |
| 1898 | dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n", |
| 1899 | pl022->vendor->max_bpw); |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame] | 1900 | goto err_config_params; |
| 1901 | } else if (bits <= 8) { |
| 1902 | dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n"); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1903 | chip->n_bytes = 1; |
| 1904 | chip->read = READING_U8; |
| 1905 | chip->write = WRITING_U8; |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame] | 1906 | } else if (bits <= 16) { |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1907 | dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n"); |
| 1908 | chip->n_bytes = 2; |
| 1909 | chip->read = READING_U16; |
| 1910 | chip->write = WRITING_U16; |
| 1911 | } else { |
Vinit Shenoy | eb798c6 | 2012-04-17 12:40:13 +0530 | [diff] [blame] | 1912 | dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n"); |
| 1913 | chip->n_bytes = 4; |
| 1914 | chip->read = READING_U32; |
| 1915 | chip->write = WRITING_U32; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1916 | } |
| 1917 | |
| 1918 | /* Now Initialize all register settings required for this chip */ |
| 1919 | chip->cr0 = 0; |
| 1920 | chip->cr1 = 0; |
| 1921 | chip->dmacr = 0; |
| 1922 | chip->cpsr = 0; |
| 1923 | if ((chip_info->com_mode == DMA_TRANSFER) |
| 1924 | && ((pl022->master_info)->enable_dma)) { |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1925 | chip->enable_dma = true; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1926 | dev_dbg(&spi->dev, "DMA mode set in controller state\n"); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1927 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, |
| 1928 | SSP_DMACR_MASK_RXDMAE, 0); |
| 1929 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, |
| 1930 | SSP_DMACR_MASK_TXDMAE, 1); |
| 1931 | } else { |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 1932 | chip->enable_dma = false; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1933 | dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n"); |
| 1934 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, |
| 1935 | SSP_DMACR_MASK_RXDMAE, 0); |
| 1936 | SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, |
| 1937 | SSP_DMACR_MASK_TXDMAE, 1); |
| 1938 | } |
| 1939 | |
Linus Walleij | f9d629c | 2010-10-01 13:33:13 +0200 | [diff] [blame] | 1940 | chip->cpsr = clk_freq.cpsdvsr; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 1941 | |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 1942 | /* Special setup for the ST micro extended control registers */ |
| 1943 | if (pl022->vendor->extended_cr) { |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame] | 1944 | u32 etx; |
| 1945 | |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 1946 | if (pl022->vendor->pl023) { |
| 1947 | /* These bits are only in the PL023 */ |
| 1948 | SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, |
| 1949 | SSP_CR1_MASK_FBCLKDEL_ST, 13); |
| 1950 | } else { |
| 1951 | /* These bits are in the PL022 but not PL023 */ |
| 1952 | SSP_WRITE_BITS(chip->cr0, chip_info->duplex, |
| 1953 | SSP_CR0_MASK_HALFDUP_ST, 5); |
| 1954 | SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, |
| 1955 | SSP_CR0_MASK_CSS_ST, 16); |
| 1956 | SSP_WRITE_BITS(chip->cr0, chip_info->iface, |
| 1957 | SSP_CR0_MASK_FRF_ST, 21); |
| 1958 | SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, |
| 1959 | SSP_CR1_MASK_MWAIT_ST, 6); |
| 1960 | } |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame] | 1961 | SSP_WRITE_BITS(chip->cr0, bits - 1, |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 1962 | SSP_CR0_MASK_DSS_ST, 0); |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame] | 1963 | |
| 1964 | if (spi->mode & SPI_LSB_FIRST) { |
| 1965 | tmp = SSP_RX_LSB; |
| 1966 | etx = SSP_TX_LSB; |
| 1967 | } else { |
| 1968 | tmp = SSP_RX_MSB; |
| 1969 | etx = SSP_TX_MSB; |
| 1970 | } |
| 1971 | SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); |
| 1972 | SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 1973 | SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, |
| 1974 | SSP_CR1_MASK_RXIFLSEL_ST, 7); |
| 1975 | SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, |
| 1976 | SSP_CR1_MASK_TXIFLSEL_ST, 10); |
| 1977 | } else { |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame] | 1978 | SSP_WRITE_BITS(chip->cr0, bits - 1, |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 1979 | SSP_CR0_MASK_DSS, 0); |
| 1980 | SSP_WRITE_BITS(chip->cr0, chip_info->iface, |
| 1981 | SSP_CR0_MASK_FRF, 4); |
| 1982 | } |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame] | 1983 | |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 1984 | /* Stuff that is common for all versions */ |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame] | 1985 | if (spi->mode & SPI_CPOL) |
| 1986 | tmp = SSP_CLK_POL_IDLE_HIGH; |
| 1987 | else |
| 1988 | tmp = SSP_CLK_POL_IDLE_LOW; |
| 1989 | SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6); |
| 1990 | |
| 1991 | if (spi->mode & SPI_CPHA) |
| 1992 | tmp = SSP_CLK_SECOND_EDGE; |
| 1993 | else |
| 1994 | tmp = SSP_CLK_FIRST_EDGE; |
| 1995 | SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7); |
| 1996 | |
Linus Walleij | f9d629c | 2010-10-01 13:33:13 +0200 | [diff] [blame] | 1997 | SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8); |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 1998 | /* Loopback is available on all versions except PL023 */ |
Philippe Langlais | 06fb01f | 2011-03-23 11:05:16 +0100 | [diff] [blame] | 1999 | if (pl022->vendor->loopback) { |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame] | 2000 | if (spi->mode & SPI_LOOP) |
| 2001 | tmp = LOOPBACK_ENABLED; |
| 2002 | else |
| 2003 | tmp = LOOPBACK_DISABLED; |
| 2004 | SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); |
| 2005 | } |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2006 | SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1); |
| 2007 | SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2); |
Viresh Kumar | f1e45f8 | 2011-08-10 14:20:54 +0530 | [diff] [blame] | 2008 | SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, |
| 2009 | 3); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2010 | |
| 2011 | /* Save controller_state */ |
| 2012 | spi_set_ctldata(spi, chip); |
| 2013 | return status; |
| 2014 | err_config_params: |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame] | 2015 | spi_set_ctldata(spi, NULL); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2016 | kfree(chip); |
| 2017 | return status; |
| 2018 | } |
| 2019 | |
| 2020 | /** |
| 2021 | * pl022_cleanup - cleanup function registered to SPI master framework |
| 2022 | * @spi: spi device which is requesting cleanup |
| 2023 | * |
| 2024 | * This function is registered to the SPI framework for this SPI master |
| 2025 | * controller. It will free the runtime state of chip. |
| 2026 | */ |
| 2027 | static void pl022_cleanup(struct spi_device *spi) |
| 2028 | { |
| 2029 | struct chip_data *chip = spi_get_ctldata(spi); |
| 2030 | |
| 2031 | spi_set_ctldata(spi, NULL); |
| 2032 | kfree(chip); |
| 2033 | } |
| 2034 | |
Roland Stigge | 39a6ac1 | 2012-09-18 15:53:53 +0200 | [diff] [blame] | 2035 | static struct pl022_ssp_controller * |
| 2036 | pl022_platform_data_dt_get(struct device *dev) |
| 2037 | { |
| 2038 | struct device_node *np = dev->of_node; |
| 2039 | struct pl022_ssp_controller *pd; |
| 2040 | u32 tmp; |
| 2041 | |
| 2042 | if (!np) { |
| 2043 | dev_err(dev, "no dt node defined\n"); |
| 2044 | return NULL; |
| 2045 | } |
| 2046 | |
| 2047 | pd = devm_kzalloc(dev, sizeof(struct pl022_ssp_controller), GFP_KERNEL); |
Jingoo Han | 77538f4 | 2014-04-29 17:19:01 +0900 | [diff] [blame] | 2048 | if (!pd) |
Roland Stigge | 39a6ac1 | 2012-09-18 15:53:53 +0200 | [diff] [blame] | 2049 | return NULL; |
Roland Stigge | 39a6ac1 | 2012-09-18 15:53:53 +0200 | [diff] [blame] | 2050 | |
| 2051 | pd->bus_id = -1; |
Linus Walleij | dbd897b | 2013-05-23 19:46:40 +0200 | [diff] [blame] | 2052 | pd->enable_dma = 1; |
Roland Stigge | 39a6ac1 | 2012-09-18 15:53:53 +0200 | [diff] [blame] | 2053 | of_property_read_u32(np, "num-cs", &tmp); |
| 2054 | pd->num_chipselect = tmp; |
| 2055 | of_property_read_u32(np, "pl022,autosuspend-delay", |
| 2056 | &pd->autosuspend_delay); |
| 2057 | pd->rt = of_property_read_bool(np, "pl022,rt"); |
| 2058 | |
| 2059 | return pd; |
| 2060 | } |
| 2061 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 2062 | static int pl022_probe(struct amba_device *adev, const struct amba_id *id) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2063 | { |
| 2064 | struct device *dev = &adev->dev; |
Jingoo Han | 8074cf0 | 2013-07-30 16:58:59 +0900 | [diff] [blame] | 2065 | struct pl022_ssp_controller *platform_info = |
| 2066 | dev_get_platdata(&adev->dev); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2067 | struct spi_master *master; |
| 2068 | struct pl022 *pl022 = NULL; /*Data for this driver */ |
Roland Stigge | 6d3952a | 2012-08-22 15:49:18 +0200 | [diff] [blame] | 2069 | struct device_node *np = adev->dev.of_node; |
| 2070 | int status = 0, i, num_cs; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2071 | |
| 2072 | dev_info(&adev->dev, |
| 2073 | "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid); |
Roland Stigge | 39a6ac1 | 2012-09-18 15:53:53 +0200 | [diff] [blame] | 2074 | if (!platform_info && IS_ENABLED(CONFIG_OF)) |
| 2075 | platform_info = pl022_platform_data_dt_get(dev); |
| 2076 | |
| 2077 | if (!platform_info) { |
| 2078 | dev_err(dev, "probe: no platform data defined\n"); |
Linus Walleij | aeef991 | 2012-09-26 16:48:36 +0200 | [diff] [blame] | 2079 | return -ENODEV; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2080 | } |
| 2081 | |
Roland Stigge | 6d3952a | 2012-08-22 15:49:18 +0200 | [diff] [blame] | 2082 | if (platform_info->num_chipselect) { |
| 2083 | num_cs = platform_info->num_chipselect; |
Roland Stigge | 6d3952a | 2012-08-22 15:49:18 +0200 | [diff] [blame] | 2084 | } else { |
Roland Stigge | 39a6ac1 | 2012-09-18 15:53:53 +0200 | [diff] [blame] | 2085 | dev_err(dev, "probe: no chip select defined\n"); |
Linus Walleij | aeef991 | 2012-09-26 16:48:36 +0200 | [diff] [blame] | 2086 | return -ENODEV; |
Roland Stigge | 6d3952a | 2012-08-22 15:49:18 +0200 | [diff] [blame] | 2087 | } |
| 2088 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2089 | /* Allocate master with space for data */ |
Roland Stigge | b4b8482 | 2012-09-03 10:14:29 +0200 | [diff] [blame] | 2090 | master = spi_alloc_master(dev, sizeof(struct pl022)); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2091 | if (master == NULL) { |
| 2092 | dev_err(&adev->dev, "probe - cannot alloc SPI master\n"); |
Linus Walleij | aeef991 | 2012-09-26 16:48:36 +0200 | [diff] [blame] | 2093 | return -ENOMEM; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2094 | } |
| 2095 | |
| 2096 | pl022 = spi_master_get_devdata(master); |
| 2097 | pl022->master = master; |
| 2098 | pl022->master_info = platform_info; |
| 2099 | pl022->adev = adev; |
| 2100 | pl022->vendor = id->data; |
Roland Stigge | b4b8482 | 2012-09-03 10:14:29 +0200 | [diff] [blame] | 2101 | pl022->chipselects = devm_kzalloc(dev, num_cs * sizeof(int), |
| 2102 | GFP_KERNEL); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2103 | |
| 2104 | /* |
| 2105 | * Bus Number Which has been Assigned to this SSP controller |
| 2106 | * on this board |
| 2107 | */ |
| 2108 | master->bus_num = platform_info->bus_id; |
Roland Stigge | 6d3952a | 2012-08-22 15:49:18 +0200 | [diff] [blame] | 2109 | master->num_chipselect = num_cs; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2110 | master->cleanup = pl022_cleanup; |
| 2111 | master->setup = pl022_setup; |
Mark Brown | 29b6e90 | 2013-07-28 15:35:08 +0100 | [diff] [blame] | 2112 | master->auto_runtime_pm = true; |
Linus Walleij | ffbbdd21 | 2012-02-22 10:05:38 +0100 | [diff] [blame] | 2113 | master->transfer_one_message = pl022_transfer_one_message; |
| 2114 | master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware; |
| 2115 | master->rt = platform_info->rt; |
Roland Stigge | 6d3952a | 2012-08-22 15:49:18 +0200 | [diff] [blame] | 2116 | master->dev.of_node = dev->of_node; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2117 | |
Roland Stigge | 6d3952a | 2012-08-22 15:49:18 +0200 | [diff] [blame] | 2118 | if (platform_info->num_chipselect && platform_info->chipselects) { |
| 2119 | for (i = 0; i < num_cs; i++) |
Roland Stigge | f6f46de | 2012-08-22 15:49:17 +0200 | [diff] [blame] | 2120 | pl022->chipselects[i] = platform_info->chipselects[i]; |
Roland Stigge | 6d3952a | 2012-08-22 15:49:18 +0200 | [diff] [blame] | 2121 | } else if (IS_ENABLED(CONFIG_OF)) { |
| 2122 | for (i = 0; i < num_cs; i++) { |
| 2123 | int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); |
| 2124 | |
| 2125 | if (cs_gpio == -EPROBE_DEFER) { |
| 2126 | status = -EPROBE_DEFER; |
| 2127 | goto err_no_gpio; |
| 2128 | } |
| 2129 | |
| 2130 | pl022->chipselects[i] = cs_gpio; |
| 2131 | |
| 2132 | if (gpio_is_valid(cs_gpio)) { |
Linus Walleij | aeef991 | 2012-09-26 16:48:36 +0200 | [diff] [blame] | 2133 | if (devm_gpio_request(dev, cs_gpio, "ssp-pl022")) |
Roland Stigge | 6d3952a | 2012-08-22 15:49:18 +0200 | [diff] [blame] | 2134 | dev_err(&adev->dev, |
| 2135 | "could not request %d gpio\n", |
| 2136 | cs_gpio); |
| 2137 | else if (gpio_direction_output(cs_gpio, 1)) |
| 2138 | dev_err(&adev->dev, |
Roland Stigge | 61e89e6 | 2014-09-09 15:17:50 +0200 | [diff] [blame] | 2139 | "could not set gpio %d as output\n", |
Roland Stigge | 6d3952a | 2012-08-22 15:49:18 +0200 | [diff] [blame] | 2140 | cs_gpio); |
| 2141 | } |
| 2142 | } |
| 2143 | } |
Roland Stigge | f6f46de | 2012-08-22 15:49:17 +0200 | [diff] [blame] | 2144 | |
Kevin Wells | bde435a | 2010-09-16 06:18:50 -0700 | [diff] [blame] | 2145 | /* |
| 2146 | * Supports mode 0-3, loopback, and active low CS. Transfers are |
| 2147 | * always MS bit first on the original pl022. |
| 2148 | */ |
| 2149 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; |
| 2150 | if (pl022->vendor->extended_cr) |
| 2151 | master->mode_bits |= SPI_LSB_FIRST; |
| 2152 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2153 | dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num); |
| 2154 | |
| 2155 | status = amba_request_regions(adev, NULL); |
| 2156 | if (status) |
| 2157 | goto err_no_ioregion; |
| 2158 | |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 2159 | pl022->phybase = adev->res.start; |
Linus Walleij | aeef991 | 2012-09-26 16:48:36 +0200 | [diff] [blame] | 2160 | pl022->virtbase = devm_ioremap(dev, adev->res.start, |
| 2161 | resource_size(&adev->res)); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2162 | if (pl022->virtbase == NULL) { |
| 2163 | status = -ENOMEM; |
| 2164 | goto err_no_ioremap; |
| 2165 | } |
Jingoo Han | 2c06750 | 2013-10-11 18:29:58 +0900 | [diff] [blame] | 2166 | dev_info(&adev->dev, "mapped registers from %pa to %p\n", |
| 2167 | &adev->res.start, pl022->virtbase); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2168 | |
Linus Walleij | aeef991 | 2012-09-26 16:48:36 +0200 | [diff] [blame] | 2169 | pl022->clk = devm_clk_get(&adev->dev, NULL); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2170 | if (IS_ERR(pl022->clk)) { |
| 2171 | status = PTR_ERR(pl022->clk); |
| 2172 | dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n"); |
| 2173 | goto err_no_clk; |
| 2174 | } |
Russell King | 7ff6bcf | 2011-09-22 14:27:11 +0100 | [diff] [blame] | 2175 | |
Ulf Hansson | 6cac167 | 2014-02-04 16:58:50 +0100 | [diff] [blame] | 2176 | status = clk_prepare_enable(pl022->clk); |
Ulf Hansson | 71e63e7 | 2011-11-04 08:10:09 +0100 | [diff] [blame] | 2177 | if (status) { |
| 2178 | dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); |
| 2179 | goto err_no_clk_en; |
| 2180 | } |
| 2181 | |
Linus Walleij | ffbbdd21 | 2012-02-22 10:05:38 +0100 | [diff] [blame] | 2182 | /* Initialize transfer pump */ |
| 2183 | tasklet_init(&pl022->pump_transfers, pump_transfers, |
| 2184 | (unsigned long)pl022); |
| 2185 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2186 | /* Disable SSP */ |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2187 | writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)), |
| 2188 | SSP_CR1(pl022->virtbase)); |
| 2189 | load_ssp_default_config(pl022); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2190 | |
Linus Walleij | aeef991 | 2012-09-26 16:48:36 +0200 | [diff] [blame] | 2191 | status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler, |
| 2192 | 0, "pl022", pl022); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2193 | if (status < 0) { |
| 2194 | dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status); |
| 2195 | goto err_no_irq; |
| 2196 | } |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 2197 | |
Arnd Bergmann | dc71545 | 2013-01-28 16:24:37 +0000 | [diff] [blame] | 2198 | /* Get DMA channels, try autoconfiguration first */ |
| 2199 | status = pl022_dma_autoprobe(pl022); |
| 2200 | |
| 2201 | /* If that failed, use channels from platform_info */ |
| 2202 | if (status == 0) |
| 2203 | platform_info->enable_dma = 1; |
| 2204 | else if (platform_info->enable_dma) { |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 2205 | status = pl022_dma_probe(pl022); |
| 2206 | if (status != 0) |
Viresh Kumar | 43c6401 | 2011-05-16 09:40:10 +0530 | [diff] [blame] | 2207 | platform_info->enable_dma = 0; |
Linus Walleij | b1b6b9a | 2010-09-29 17:31:35 +0900 | [diff] [blame] | 2208 | } |
| 2209 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2210 | /* Register with the SPI framework */ |
| 2211 | amba_set_drvdata(adev, pl022); |
Jingoo Han | 35794a7 | 2013-09-24 13:44:59 +0900 | [diff] [blame] | 2212 | status = devm_spi_register_master(&adev->dev, master); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2213 | if (status != 0) { |
| 2214 | dev_err(&adev->dev, |
| 2215 | "probe - problem registering spi master\n"); |
| 2216 | goto err_spi_register; |
| 2217 | } |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 2218 | dev_dbg(dev, "probe succeeded\n"); |
Russell King | 92b97f0 | 2011-08-14 09:13:48 +0100 | [diff] [blame] | 2219 | |
| 2220 | /* let runtime pm put suspend */ |
Chris Blair | 53e4ace | 2011-11-08 08:54:46 +0000 | [diff] [blame] | 2221 | if (platform_info->autosuspend_delay > 0) { |
| 2222 | dev_info(&adev->dev, |
| 2223 | "will use autosuspend for runtime pm, delay %dms\n", |
| 2224 | platform_info->autosuspend_delay); |
| 2225 | pm_runtime_set_autosuspend_delay(dev, |
| 2226 | platform_info->autosuspend_delay); |
| 2227 | pm_runtime_use_autosuspend(dev); |
Chris Blair | 53e4ace | 2011-11-08 08:54:46 +0000 | [diff] [blame] | 2228 | } |
Ulf Hansson | 0df3499 | 2012-10-17 14:27:08 +0200 | [diff] [blame] | 2229 | pm_runtime_put(dev); |
| 2230 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2231 | return 0; |
| 2232 | |
| 2233 | err_spi_register: |
Viresh Kumar | 3e3ea71 | 2011-08-10 14:20:58 +0530 | [diff] [blame] | 2234 | if (platform_info->enable_dma) |
| 2235 | pl022_dma_remove(pl022); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2236 | err_no_irq: |
Ulf Hansson | 6cac167 | 2014-02-04 16:58:50 +0100 | [diff] [blame] | 2237 | clk_disable_unprepare(pl022->clk); |
Ulf Hansson | 71e63e7 | 2011-11-04 08:10:09 +0100 | [diff] [blame] | 2238 | err_no_clk_en: |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2239 | err_no_clk: |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2240 | err_no_ioremap: |
| 2241 | amba_release_regions(adev); |
| 2242 | err_no_ioregion: |
Roland Stigge | 6d3952a | 2012-08-22 15:49:18 +0200 | [diff] [blame] | 2243 | err_no_gpio: |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2244 | spi_master_put(master); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2245 | return status; |
| 2246 | } |
| 2247 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 2248 | static int |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2249 | pl022_remove(struct amba_device *adev) |
| 2250 | { |
| 2251 | struct pl022 *pl022 = amba_get_drvdata(adev); |
Linus Walleij | 50658b6 | 2011-08-02 11:29:24 +0200 | [diff] [blame] | 2252 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2253 | if (!pl022) |
| 2254 | return 0; |
| 2255 | |
Russell King | 92b97f0 | 2011-08-14 09:13:48 +0100 | [diff] [blame] | 2256 | /* |
| 2257 | * undo pm_runtime_put() in probe. I assume that we're not |
| 2258 | * accessing the primecell here. |
| 2259 | */ |
| 2260 | pm_runtime_get_noresume(&adev->dev); |
| 2261 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2262 | load_ssp_default_config(pl022); |
Viresh Kumar | 3e3ea71 | 2011-08-10 14:20:58 +0530 | [diff] [blame] | 2263 | if (pl022->master_info->enable_dma) |
| 2264 | pl022_dma_remove(pl022); |
| 2265 | |
Ulf Hansson | 6cac167 | 2014-02-04 16:58:50 +0100 | [diff] [blame] | 2266 | clk_disable_unprepare(pl022->clk); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2267 | amba_release_regions(adev); |
| 2268 | tasklet_disable(&pl022->pump_transfers); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2269 | return 0; |
| 2270 | } |
| 2271 | |
Ulf Hansson | 84a5dc4 | 2014-03-01 11:56:07 +0100 | [diff] [blame] | 2272 | #ifdef CONFIG_PM_SLEEP |
Peter Hüwe | 6cfa627 | 2011-09-05 21:07:23 +0100 | [diff] [blame] | 2273 | static int pl022_suspend(struct device *dev) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2274 | { |
Russell King | 92b97f0 | 2011-08-14 09:13:48 +0100 | [diff] [blame] | 2275 | struct pl022 *pl022 = dev_get_drvdata(dev); |
Linus Walleij | ffbbdd21 | 2012-02-22 10:05:38 +0100 | [diff] [blame] | 2276 | int ret; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2277 | |
Linus Walleij | ffbbdd21 | 2012-02-22 10:05:38 +0100 | [diff] [blame] | 2278 | ret = spi_master_suspend(pl022->master); |
| 2279 | if (ret) { |
| 2280 | dev_warn(dev, "cannot suspend master\n"); |
| 2281 | return ret; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2282 | } |
Ulf Hansson | 4964a26 | 2012-10-17 14:27:16 +0200 | [diff] [blame] | 2283 | |
Ulf Hansson | 84a5dc4 | 2014-03-01 11:56:07 +0100 | [diff] [blame] | 2284 | ret = pm_runtime_force_suspend(dev); |
| 2285 | if (ret) { |
| 2286 | spi_master_resume(pl022->master); |
| 2287 | return ret; |
| 2288 | } |
| 2289 | |
| 2290 | pinctrl_pm_select_sleep_state(dev); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2291 | |
Peter Hüwe | 6cfa627 | 2011-09-05 21:07:23 +0100 | [diff] [blame] | 2292 | dev_dbg(dev, "suspended\n"); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2293 | return 0; |
| 2294 | } |
| 2295 | |
Russell King | 92b97f0 | 2011-08-14 09:13:48 +0100 | [diff] [blame] | 2296 | static int pl022_resume(struct device *dev) |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2297 | { |
Russell King | 92b97f0 | 2011-08-14 09:13:48 +0100 | [diff] [blame] | 2298 | struct pl022 *pl022 = dev_get_drvdata(dev); |
Linus Walleij | ffbbdd21 | 2012-02-22 10:05:38 +0100 | [diff] [blame] | 2299 | int ret; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2300 | |
Ulf Hansson | 84a5dc4 | 2014-03-01 11:56:07 +0100 | [diff] [blame] | 2301 | ret = pm_runtime_force_resume(dev); |
| 2302 | if (ret) |
| 2303 | dev_err(dev, "problem resuming\n"); |
Linus Walleij | ada7aec | 2012-09-26 18:06:22 +0200 | [diff] [blame] | 2304 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2305 | /* Start the queue running */ |
Linus Walleij | ffbbdd21 | 2012-02-22 10:05:38 +0100 | [diff] [blame] | 2306 | ret = spi_master_resume(pl022->master); |
| 2307 | if (ret) |
| 2308 | dev_err(dev, "problem starting queue (%d)\n", ret); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2309 | else |
Russell King | 92b97f0 | 2011-08-14 09:13:48 +0100 | [diff] [blame] | 2310 | dev_dbg(dev, "resumed\n"); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2311 | |
Linus Walleij | ffbbdd21 | 2012-02-22 10:05:38 +0100 | [diff] [blame] | 2312 | return ret; |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2313 | } |
Ulf Hansson | 84a5dc4 | 2014-03-01 11:56:07 +0100 | [diff] [blame] | 2314 | #endif |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2315 | |
Ulf Hansson | 736198b | 2014-03-01 11:56:06 +0100 | [diff] [blame] | 2316 | #ifdef CONFIG_PM |
Russell King | 92b97f0 | 2011-08-14 09:13:48 +0100 | [diff] [blame] | 2317 | static int pl022_runtime_suspend(struct device *dev) |
| 2318 | { |
| 2319 | struct pl022 *pl022 = dev_get_drvdata(dev); |
| 2320 | |
Ulf Hansson | 84a5dc4 | 2014-03-01 11:56:07 +0100 | [diff] [blame] | 2321 | clk_disable_unprepare(pl022->clk); |
| 2322 | pinctrl_pm_select_idle_state(dev); |
| 2323 | |
Russell King | 92b97f0 | 2011-08-14 09:13:48 +0100 | [diff] [blame] | 2324 | return 0; |
| 2325 | } |
| 2326 | |
| 2327 | static int pl022_runtime_resume(struct device *dev) |
| 2328 | { |
| 2329 | struct pl022 *pl022 = dev_get_drvdata(dev); |
Patrice Chotard | 4f5e1b3 | 2012-09-19 14:23:46 +0200 | [diff] [blame] | 2330 | |
Ulf Hansson | 84a5dc4 | 2014-03-01 11:56:07 +0100 | [diff] [blame] | 2331 | pinctrl_pm_select_default_state(dev); |
| 2332 | clk_prepare_enable(pl022->clk); |
| 2333 | |
Russell King | 92b97f0 | 2011-08-14 09:13:48 +0100 | [diff] [blame] | 2334 | return 0; |
| 2335 | } |
| 2336 | #endif |
| 2337 | |
| 2338 | static const struct dev_pm_ops pl022_dev_pm_ops = { |
| 2339 | SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume) |
Ulf Hansson | 736198b | 2014-03-01 11:56:06 +0100 | [diff] [blame] | 2340 | SET_PM_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL) |
Russell King | 92b97f0 | 2011-08-14 09:13:48 +0100 | [diff] [blame] | 2341 | }; |
| 2342 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2343 | static struct vendor_data vendor_arm = { |
| 2344 | .fifodepth = 8, |
| 2345 | .max_bpw = 16, |
| 2346 | .unidir = false, |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 2347 | .extended_cr = false, |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 2348 | .pl023 = false, |
Philippe Langlais | 06fb01f | 2011-03-23 11:05:16 +0100 | [diff] [blame] | 2349 | .loopback = true, |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2350 | }; |
| 2351 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2352 | static struct vendor_data vendor_st = { |
| 2353 | .fifodepth = 32, |
| 2354 | .max_bpw = 32, |
| 2355 | .unidir = false, |
Linus Walleij | 556f4ae | 2010-05-05 09:28:15 +0000 | [diff] [blame] | 2356 | .extended_cr = true, |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 2357 | .pl023 = false, |
Philippe Langlais | 06fb01f | 2011-03-23 11:05:16 +0100 | [diff] [blame] | 2358 | .loopback = true, |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 2359 | }; |
| 2360 | |
| 2361 | static struct vendor_data vendor_st_pl023 = { |
| 2362 | .fifodepth = 32, |
| 2363 | .max_bpw = 32, |
| 2364 | .unidir = false, |
| 2365 | .extended_cr = true, |
| 2366 | .pl023 = true, |
Philippe Langlais | 06fb01f | 2011-03-23 11:05:16 +0100 | [diff] [blame] | 2367 | .loopback = false, |
| 2368 | }; |
| 2369 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2370 | static struct amba_id pl022_ids[] = { |
| 2371 | { |
| 2372 | /* |
| 2373 | * ARM PL022 variant, this has a 16bit wide |
| 2374 | * and 8 locations deep TX/RX FIFO |
| 2375 | */ |
| 2376 | .id = 0x00041022, |
| 2377 | .mask = 0x000fffff, |
| 2378 | .data = &vendor_arm, |
| 2379 | }, |
| 2380 | { |
| 2381 | /* |
| 2382 | * ST Micro derivative, this has 32bit wide |
| 2383 | * and 32 locations deep TX/RX FIFO |
| 2384 | */ |
Srinidhi Kasagar | e89e04f | 2009-10-05 06:13:53 +0100 | [diff] [blame] | 2385 | .id = 0x01080022, |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2386 | .mask = 0xffffffff, |
| 2387 | .data = &vendor_st, |
| 2388 | }, |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 2389 | { |
| 2390 | /* |
| 2391 | * ST-Ericsson derivative "PL023" (this is not |
| 2392 | * an official ARM number), this is a PL022 SSP block |
| 2393 | * stripped to SPI mode only, it has 32bit wide |
| 2394 | * and 32 locations deep TX/RX FIFO but no extended |
| 2395 | * CR0/CR1 register |
| 2396 | */ |
Viresh Kumar | f1e45f8 | 2011-08-10 14:20:54 +0530 | [diff] [blame] | 2397 | .id = 0x00080023, |
| 2398 | .mask = 0xffffffff, |
| 2399 | .data = &vendor_st_pl023, |
Linus Walleij | 781c7b1 | 2010-05-07 08:40:53 +0000 | [diff] [blame] | 2400 | }, |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2401 | { 0, 0 }, |
| 2402 | }; |
| 2403 | |
Dave Martin | 7eeac71 | 2011-10-05 15:15:22 +0100 | [diff] [blame] | 2404 | MODULE_DEVICE_TABLE(amba, pl022_ids); |
| 2405 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2406 | static struct amba_driver pl022_driver = { |
| 2407 | .drv = { |
| 2408 | .name = "ssp-pl022", |
Russell King | 92b97f0 | 2011-08-14 09:13:48 +0100 | [diff] [blame] | 2409 | .pm = &pl022_dev_pm_ops, |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2410 | }, |
| 2411 | .id_table = pl022_ids, |
| 2412 | .probe = pl022_probe, |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 2413 | .remove = pl022_remove, |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2414 | }; |
| 2415 | |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2416 | static int __init pl022_init(void) |
| 2417 | { |
| 2418 | return amba_driver_register(&pl022_driver); |
| 2419 | } |
Linus Walleij | 25c8e03 | 2010-09-06 11:02:12 +0200 | [diff] [blame] | 2420 | subsys_initcall(pl022_init); |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2421 | |
| 2422 | static void __exit pl022_exit(void) |
| 2423 | { |
| 2424 | amba_driver_unregister(&pl022_driver); |
| 2425 | } |
Linus Walleij | b43d65f | 2009-06-09 08:11:42 +0100 | [diff] [blame] | 2426 | module_exit(pl022_exit); |
| 2427 | |
| 2428 | MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); |
| 2429 | MODULE_DESCRIPTION("PL022 SSP Controller Driver"); |
| 2430 | MODULE_LICENSE("GPL"); |