Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 1 | /* |
Uwe Zeisberger | f30c226 | 2006-10-03 23:01:26 +0200 | [diff] [blame] | 2 | * linux/arch/arm/mach-omap2/irq.c |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 3 | * |
| 4 | * Interrupt handler for OMAP2 boards. |
| 5 | * |
| 6 | * Copyright (C) 2005 Nokia Corporation |
| 7 | * Author: Paul Mundt <paul.mundt@nokia.com> |
| 8 | * |
| 9 | * This file is subject to the terms and conditions of the GNU General Public |
| 10 | * License. See the file "COPYING" in the main directory of this archive |
| 11 | * for more details. |
| 12 | */ |
| 13 | #include <linux/kernel.h> |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 14 | #include <linux/module.h> |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 15 | #include <linux/init.h> |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 16 | #include <linux/interrupt.h> |
Paul Walmsley | 2e7509e | 2008-10-09 17:51:28 +0300 | [diff] [blame] | 17 | #include <linux/io.h> |
Tony Lindgren | ee0839c | 2012-02-24 10:34:35 -0800 | [diff] [blame] | 18 | |
Marc Zyngier | 2db1499 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 19 | #include <asm/exception.h> |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 20 | #include <asm/mach/irq.h> |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 21 | #include <linux/irqdomain.h> |
| 22 | #include <linux/of.h> |
| 23 | #include <linux/of_address.h> |
R Sricharan | c4082d4 | 2012-06-05 16:31:06 +0530 | [diff] [blame] | 24 | #include <linux/of_irq.h> |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 25 | |
Tony Lindgren | dbc0416 | 2012-08-31 10:59:07 -0700 | [diff] [blame] | 26 | #include "soc.h" |
Paul Walmsley | e2ed89f | 2012-04-13 06:34:26 -0600 | [diff] [blame] | 27 | #include "common.h" |
Felipe Balbi | b65ecd4 | 2014-09-08 17:54:43 -0700 | [diff] [blame] | 28 | #include "../../drivers/irqchip/irqchip.h" |
Paul Walmsley | 2e7509e | 2008-10-09 17:51:28 +0300 | [diff] [blame] | 29 | |
| 30 | /* selected INTC register offsets */ |
| 31 | |
| 32 | #define INTC_REVISION 0x0000 |
| 33 | #define INTC_SYSCONFIG 0x0010 |
| 34 | #define INTC_SYSSTATUS 0x0014 |
Tony Lindgren | 6ccc4c0 | 2008-12-10 17:36:52 -0800 | [diff] [blame] | 35 | #define INTC_SIR 0x0040 |
Paul Walmsley | 2e7509e | 2008-10-09 17:51:28 +0300 | [diff] [blame] | 36 | #define INTC_CONTROL 0x0048 |
Rajendra Nayak | 0addd61 | 2008-09-26 17:48:20 +0530 | [diff] [blame] | 37 | #define INTC_PROTECTION 0x004C |
| 38 | #define INTC_IDLE 0x0050 |
| 39 | #define INTC_THRESHOLD 0x0068 |
| 40 | #define INTC_MIR0 0x0084 |
Paul Walmsley | 2e7509e | 2008-10-09 17:51:28 +0300 | [diff] [blame] | 41 | #define INTC_MIR_CLEAR0 0x0088 |
| 42 | #define INTC_MIR_SET0 0x008c |
| 43 | #define INTC_PENDING_IRQ0 0x0098 |
Felipe Balbi | 1198365 | 2014-09-08 17:54:37 -0700 | [diff] [blame] | 44 | #define INTC_PENDING_IRQ1 0x00b8 |
| 45 | #define INTC_PENDING_IRQ2 0x00d8 |
| 46 | #define INTC_PENDING_IRQ3 0x00f8 |
Felipe Balbi | 33c7c7b | 2014-09-08 17:54:32 -0700 | [diff] [blame] | 47 | #define INTC_ILR0 0x0100 |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 48 | |
Marc Zyngier | 2db1499 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 49 | #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */ |
Felipe Balbi | a88ab43 | 2014-09-08 17:54:35 -0700 | [diff] [blame] | 50 | #define INTCPS_NR_ILR_REGS 128 |
Tony Lindgren | 3003ce3 | 2012-09-04 17:43:29 -0700 | [diff] [blame] | 51 | #define INTCPS_NR_MIR_REGS 3 |
Marc Zyngier | 2db1499 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 52 | |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 53 | /* |
| 54 | * OMAP2 has a number of different interrupt controllers, each interrupt |
| 55 | * controller is identified as its own "bank". Register definitions are |
| 56 | * fairly consistent for each bank, but not all registers are implemented |
| 57 | * for each bank.. when in doubt, consult the TRM. |
| 58 | */ |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 59 | |
Rajendra Nayak | 0addd61 | 2008-09-26 17:48:20 +0530 | [diff] [blame] | 60 | /* Structure to save interrupt controller context */ |
Felipe Balbi | 272a8b0 | 2014-09-08 17:54:38 -0700 | [diff] [blame] | 61 | struct omap_intc_regs { |
Rajendra Nayak | 0addd61 | 2008-09-26 17:48:20 +0530 | [diff] [blame] | 62 | u32 sysconfig; |
| 63 | u32 protection; |
| 64 | u32 idle; |
| 65 | u32 threshold; |
Felipe Balbi | a88ab43 | 2014-09-08 17:54:35 -0700 | [diff] [blame] | 66 | u32 ilr[INTCPS_NR_ILR_REGS]; |
Rajendra Nayak | 0addd61 | 2008-09-26 17:48:20 +0530 | [diff] [blame] | 67 | u32 mir[INTCPS_NR_MIR_REGS]; |
| 68 | }; |
Felipe Balbi | 131b48c | 2014-09-08 17:54:42 -0700 | [diff] [blame] | 69 | static struct omap_intc_regs intc_context; |
| 70 | |
| 71 | static struct irq_domain *domain; |
| 72 | static void __iomem *omap_irq_base; |
Felipe Balbi | 52b1e12 | 2014-09-08 17:54:57 -0700 | [diff] [blame] | 73 | static int omap_nr_pending = 3; |
Felipe Balbi | 131b48c | 2014-09-08 17:54:42 -0700 | [diff] [blame] | 74 | static int omap_nr_irqs = 96; |
Rajendra Nayak | 0addd61 | 2008-09-26 17:48:20 +0530 | [diff] [blame] | 75 | |
Paul Walmsley | 2e7509e | 2008-10-09 17:51:28 +0300 | [diff] [blame] | 76 | /* INTC bank register get/set */ |
Felipe Balbi | 71be00c | 2014-09-08 17:54:32 -0700 | [diff] [blame] | 77 | static void intc_writel(u32 reg, u32 val) |
Paul Walmsley | 2e7509e | 2008-10-09 17:51:28 +0300 | [diff] [blame] | 78 | { |
Felipe Balbi | 71be00c | 2014-09-08 17:54:32 -0700 | [diff] [blame] | 79 | writel_relaxed(val, omap_irq_base + reg); |
Paul Walmsley | 2e7509e | 2008-10-09 17:51:28 +0300 | [diff] [blame] | 80 | } |
| 81 | |
Felipe Balbi | 71be00c | 2014-09-08 17:54:32 -0700 | [diff] [blame] | 82 | static u32 intc_readl(u32 reg) |
Paul Walmsley | 2e7509e | 2008-10-09 17:51:28 +0300 | [diff] [blame] | 83 | { |
Felipe Balbi | 71be00c | 2014-09-08 17:54:32 -0700 | [diff] [blame] | 84 | return readl_relaxed(omap_irq_base + reg); |
Paul Walmsley | 2e7509e | 2008-10-09 17:51:28 +0300 | [diff] [blame] | 85 | } |
| 86 | |
Felipe Balbi | 131b48c | 2014-09-08 17:54:42 -0700 | [diff] [blame] | 87 | void omap_intc_save_context(void) |
| 88 | { |
| 89 | int i; |
| 90 | |
| 91 | intc_context.sysconfig = |
| 92 | intc_readl(INTC_SYSCONFIG); |
| 93 | intc_context.protection = |
| 94 | intc_readl(INTC_PROTECTION); |
| 95 | intc_context.idle = |
| 96 | intc_readl(INTC_IDLE); |
| 97 | intc_context.threshold = |
| 98 | intc_readl(INTC_THRESHOLD); |
| 99 | |
| 100 | for (i = 0; i < omap_nr_irqs; i++) |
| 101 | intc_context.ilr[i] = |
| 102 | intc_readl((INTC_ILR0 + 0x4 * i)); |
| 103 | for (i = 0; i < INTCPS_NR_MIR_REGS; i++) |
| 104 | intc_context.mir[i] = |
| 105 | intc_readl(INTC_MIR0 + (0x20 * i)); |
| 106 | } |
| 107 | |
| 108 | void omap_intc_restore_context(void) |
| 109 | { |
| 110 | int i; |
| 111 | |
| 112 | intc_writel(INTC_SYSCONFIG, intc_context.sysconfig); |
| 113 | intc_writel(INTC_PROTECTION, intc_context.protection); |
| 114 | intc_writel(INTC_IDLE, intc_context.idle); |
| 115 | intc_writel(INTC_THRESHOLD, intc_context.threshold); |
| 116 | |
| 117 | for (i = 0; i < omap_nr_irqs; i++) |
| 118 | intc_writel(INTC_ILR0 + 0x4 * i, |
| 119 | intc_context.ilr[i]); |
| 120 | |
| 121 | for (i = 0; i < INTCPS_NR_MIR_REGS; i++) |
| 122 | intc_writel(INTC_MIR0 + 0x20 * i, |
| 123 | intc_context.mir[i]); |
| 124 | /* MIRs are saved and restore with other PRCM registers */ |
| 125 | } |
| 126 | |
| 127 | void omap3_intc_prepare_idle(void) |
| 128 | { |
| 129 | /* |
| 130 | * Disable autoidle as it can stall interrupt controller, |
| 131 | * cf. errata ID i540 for 3430 (all revisions up to 3.1.x) |
| 132 | */ |
| 133 | intc_writel(INTC_SYSCONFIG, 0); |
| 134 | } |
| 135 | |
| 136 | void omap3_intc_resume_idle(void) |
| 137 | { |
| 138 | /* Re-enable autoidle */ |
| 139 | intc_writel(INTC_SYSCONFIG, 1); |
| 140 | } |
| 141 | |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 142 | /* XXX: FIQ and additional INTC support (only MPU at the moment) */ |
Lennert Buytenhek | df30347 | 2010-11-29 10:39:59 +0100 | [diff] [blame] | 143 | static void omap_ack_irq(struct irq_data *d) |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 144 | { |
Felipe Balbi | 71be00c | 2014-09-08 17:54:32 -0700 | [diff] [blame] | 145 | intc_writel(INTC_CONTROL, 0x1); |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 146 | } |
| 147 | |
Lennert Buytenhek | df30347 | 2010-11-29 10:39:59 +0100 | [diff] [blame] | 148 | static void omap_mask_ack_irq(struct irq_data *d) |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 149 | { |
Tony Lindgren | 667a11f | 2011-05-16 02:07:38 -0700 | [diff] [blame] | 150 | irq_gc_mask_disable_reg(d); |
Lennert Buytenhek | df30347 | 2010-11-29 10:39:59 +0100 | [diff] [blame] | 151 | omap_ack_irq(d); |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 152 | } |
| 153 | |
Felipe Balbi | a88ab43 | 2014-09-08 17:54:35 -0700 | [diff] [blame] | 154 | static void __init omap_irq_soft_reset(void) |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 155 | { |
| 156 | unsigned long tmp; |
| 157 | |
Felipe Balbi | 71be00c | 2014-09-08 17:54:32 -0700 | [diff] [blame] | 158 | tmp = intc_readl(INTC_REVISION) & 0xff; |
Felipe Balbi | a88ab43 | 2014-09-08 17:54:35 -0700 | [diff] [blame] | 159 | |
Paul Walmsley | 7852ec0 | 2012-07-26 00:54:26 -0600 | [diff] [blame] | 160 | pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n", |
Felipe Balbi | a88ab43 | 2014-09-08 17:54:35 -0700 | [diff] [blame] | 161 | omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs); |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 162 | |
Felipe Balbi | 71be00c | 2014-09-08 17:54:32 -0700 | [diff] [blame] | 163 | tmp = intc_readl(INTC_SYSCONFIG); |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 164 | tmp |= 1 << 1; /* soft reset */ |
Felipe Balbi | 71be00c | 2014-09-08 17:54:32 -0700 | [diff] [blame] | 165 | intc_writel(INTC_SYSCONFIG, tmp); |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 166 | |
Felipe Balbi | 71be00c | 2014-09-08 17:54:32 -0700 | [diff] [blame] | 167 | while (!(intc_readl(INTC_SYSSTATUS) & 0x1)) |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 168 | /* Wait for reset to complete */; |
Juha Yrjola | 375e12a | 2006-12-06 17:13:50 -0800 | [diff] [blame] | 169 | |
| 170 | /* Enable autoidle */ |
Felipe Balbi | 71be00c | 2014-09-08 17:54:32 -0700 | [diff] [blame] | 171 | intc_writel(INTC_SYSCONFIG, 1 << 0); |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 172 | } |
| 173 | |
Jouni Hogander | 9443453 | 2009-02-03 15:49:04 -0800 | [diff] [blame] | 174 | int omap_irq_pending(void) |
| 175 | { |
Felipe Balbi | a88ab43 | 2014-09-08 17:54:35 -0700 | [diff] [blame] | 176 | int irq; |
Jouni Hogander | 9443453 | 2009-02-03 15:49:04 -0800 | [diff] [blame] | 177 | |
Felipe Balbi | a88ab43 | 2014-09-08 17:54:35 -0700 | [diff] [blame] | 178 | for (irq = 0; irq < omap_nr_irqs; irq += 32) |
| 179 | if (intc_readl(INTC_PENDING_IRQ0 + |
| 180 | ((irq >> 5) << 5))) |
| 181 | return 1; |
Jouni Hogander | 9443453 | 2009-02-03 15:49:04 -0800 | [diff] [blame] | 182 | return 0; |
| 183 | } |
| 184 | |
Felipe Balbi | 131b48c | 2014-09-08 17:54:42 -0700 | [diff] [blame] | 185 | void omap3_intc_suspend(void) |
| 186 | { |
| 187 | /* A pending interrupt would prevent OMAP from entering suspend */ |
| 188 | omap_ack_irq(NULL); |
| 189 | } |
| 190 | |
Tony Lindgren | 667a11f | 2011-05-16 02:07:38 -0700 | [diff] [blame] | 191 | static __init void |
| 192 | omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) |
| 193 | { |
| 194 | struct irq_chip_generic *gc; |
| 195 | struct irq_chip_type *ct; |
| 196 | |
| 197 | gc = irq_alloc_generic_chip("INTC", 1, irq_start, base, |
| 198 | handle_level_irq); |
| 199 | ct = gc->chip_types; |
| 200 | ct->chip.irq_ack = omap_mask_ack_irq; |
| 201 | ct->chip.irq_mask = irq_gc_mask_disable_reg; |
| 202 | ct->chip.irq_unmask = irq_gc_unmask_enable_reg; |
NeilBrown | e3c83c2 | 2012-04-25 13:05:24 +1000 | [diff] [blame] | 203 | ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE; |
Tony Lindgren | 667a11f | 2011-05-16 02:07:38 -0700 | [diff] [blame] | 204 | |
Tony Lindgren | 667a11f | 2011-05-16 02:07:38 -0700 | [diff] [blame] | 205 | ct->regs.enable = INTC_MIR_CLEAR0; |
| 206 | ct->regs.disable = INTC_MIR_SET0; |
| 207 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, |
| 208 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); |
| 209 | } |
| 210 | |
Felipe Balbi | a74f0a1 | 2014-09-08 17:54:55 -0700 | [diff] [blame] | 211 | static void __init omap_init_irq(u32 base, struct device_node *node) |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 212 | { |
Felipe Balbi | a88ab43 | 2014-09-08 17:54:35 -0700 | [diff] [blame] | 213 | int j, irq_base; |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 214 | |
Tony Lindgren | 741e3a8 | 2011-05-17 03:51:26 -0700 | [diff] [blame] | 215 | omap_irq_base = ioremap(base, SZ_4K); |
| 216 | if (WARN_ON(!omap_irq_base)) |
| 217 | return; |
| 218 | |
Felipe Balbi | a74f0a1 | 2014-09-08 17:54:55 -0700 | [diff] [blame] | 219 | irq_base = irq_alloc_descs(-1, 0, omap_nr_irqs, 0); |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 220 | if (irq_base < 0) { |
| 221 | pr_warn("Couldn't allocate IRQ numbers\n"); |
| 222 | irq_base = 0; |
| 223 | } |
| 224 | |
Felipe Balbi | a74f0a1 | 2014-09-08 17:54:55 -0700 | [diff] [blame] | 225 | domain = irq_domain_add_legacy(node, omap_nr_irqs, irq_base, 0, |
Felipe Balbi | a88ab43 | 2014-09-08 17:54:35 -0700 | [diff] [blame] | 226 | &irq_domain_simple_ops, NULL); |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 227 | |
Felipe Balbi | a88ab43 | 2014-09-08 17:54:35 -0700 | [diff] [blame] | 228 | omap_irq_soft_reset(); |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 229 | |
Felipe Balbi | a88ab43 | 2014-09-08 17:54:35 -0700 | [diff] [blame] | 230 | for (j = 0; j < omap_nr_irqs; j += 32) |
| 231 | omap_alloc_gc(omap_irq_base + j, j + irq_base, 32); |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 232 | } |
| 233 | |
Felipe Balbi | 2aced89 | 2014-09-08 17:54:52 -0700 | [diff] [blame] | 234 | static asmlinkage void __exception_irq_entry |
| 235 | omap_intc_handle_irq(struct pt_regs *regs) |
Marc Zyngier | 2db1499 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 236 | { |
Felipe Balbi | d6a7c5c | 2014-09-08 17:54:57 -0700 | [diff] [blame^] | 237 | u32 irqnr = 0; |
Stefan Sørensen | 698b485 | 2014-03-06 16:27:15 +0100 | [diff] [blame] | 238 | int handled_irq = 0; |
Felipe Balbi | d6a7c5c | 2014-09-08 17:54:57 -0700 | [diff] [blame^] | 239 | int i; |
Marc Zyngier | 2db1499 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 240 | |
| 241 | do { |
Felipe Balbi | d6a7c5c | 2014-09-08 17:54:57 -0700 | [diff] [blame^] | 242 | for (i = 0; i < omap_nr_pending; i++) { |
| 243 | irqnr = intc_readl(INTC_PENDING_IRQ0 + (0x20 * i)); |
| 244 | if (irqnr) |
| 245 | goto out; |
| 246 | } |
Marc Zyngier | 2db1499 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 247 | |
| 248 | out: |
| 249 | if (!irqnr) |
| 250 | break; |
| 251 | |
Felipe Balbi | 1198365 | 2014-09-08 17:54:37 -0700 | [diff] [blame] | 252 | irqnr = intc_readl(INTC_SIR); |
Marc Zyngier | 2db1499 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 253 | irqnr &= ACTIVEIRQ_MASK; |
| 254 | |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 255 | if (irqnr) { |
| 256 | irqnr = irq_find_mapping(domain, irqnr); |
Marc Zyngier | 2db1499 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 257 | handle_IRQ(irqnr, regs); |
Stefan Sørensen | 698b485 | 2014-03-06 16:27:15 +0100 | [diff] [blame] | 258 | handled_irq = 1; |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 259 | } |
Marc Zyngier | 2db1499 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 260 | } while (irqnr); |
Stefan Sørensen | 698b485 | 2014-03-06 16:27:15 +0100 | [diff] [blame] | 261 | |
| 262 | /* If an irq is masked or deasserted while active, we will |
| 263 | * keep ending up here with no irq handled. So remove it from |
| 264 | * the INTC with an ack.*/ |
| 265 | if (!handled_irq) |
| 266 | omap_ack_irq(NULL); |
Marc Zyngier | 2db1499 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 267 | } |
| 268 | |
Felipe Balbi | a4d3c5d | 2014-09-08 17:54:51 -0700 | [diff] [blame] | 269 | void __init omap2_init_irq(void) |
| 270 | { |
Felipe Balbi | a74f0a1 | 2014-09-08 17:54:55 -0700 | [diff] [blame] | 271 | omap_nr_irqs = 96; |
Felipe Balbi | 52b1e12 | 2014-09-08 17:54:57 -0700 | [diff] [blame] | 272 | omap_nr_pending = 3; |
Felipe Balbi | a74f0a1 | 2014-09-08 17:54:55 -0700 | [diff] [blame] | 273 | omap_init_irq(OMAP24XX_IC_BASE, NULL); |
Felipe Balbi | 2aced89 | 2014-09-08 17:54:52 -0700 | [diff] [blame] | 274 | set_handle_irq(omap_intc_handle_irq); |
Felipe Balbi | a4d3c5d | 2014-09-08 17:54:51 -0700 | [diff] [blame] | 275 | } |
| 276 | |
| 277 | void __init omap3_init_irq(void) |
| 278 | { |
Felipe Balbi | a74f0a1 | 2014-09-08 17:54:55 -0700 | [diff] [blame] | 279 | omap_nr_irqs = 96; |
Felipe Balbi | 52b1e12 | 2014-09-08 17:54:57 -0700 | [diff] [blame] | 280 | omap_nr_pending = 3; |
Felipe Balbi | a74f0a1 | 2014-09-08 17:54:55 -0700 | [diff] [blame] | 281 | omap_init_irq(OMAP34XX_IC_BASE, NULL); |
Felipe Balbi | 2aced89 | 2014-09-08 17:54:52 -0700 | [diff] [blame] | 282 | set_handle_irq(omap_intc_handle_irq); |
Felipe Balbi | a4d3c5d | 2014-09-08 17:54:51 -0700 | [diff] [blame] | 283 | } |
| 284 | |
| 285 | void __init ti81xx_init_irq(void) |
| 286 | { |
Felipe Balbi | a74f0a1 | 2014-09-08 17:54:55 -0700 | [diff] [blame] | 287 | omap_nr_irqs = 96; |
Felipe Balbi | 52b1e12 | 2014-09-08 17:54:57 -0700 | [diff] [blame] | 288 | omap_nr_pending = 4; |
Felipe Balbi | a74f0a1 | 2014-09-08 17:54:55 -0700 | [diff] [blame] | 289 | omap_init_irq(OMAP34XX_IC_BASE, NULL); |
Felipe Balbi | 2aced89 | 2014-09-08 17:54:52 -0700 | [diff] [blame] | 290 | set_handle_irq(omap_intc_handle_irq); |
Felipe Balbi | a4d3c5d | 2014-09-08 17:54:51 -0700 | [diff] [blame] | 291 | } |
| 292 | |
Felipe Balbi | 00b6b03 | 2014-09-08 17:54:43 -0700 | [diff] [blame] | 293 | static int __init intc_of_init(struct device_node *node, |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 294 | struct device_node *parent) |
| 295 | { |
| 296 | struct resource res; |
Felipe Balbi | a74f0a1 | 2014-09-08 17:54:55 -0700 | [diff] [blame] | 297 | |
Felipe Balbi | 52b1e12 | 2014-09-08 17:54:57 -0700 | [diff] [blame] | 298 | omap_nr_pending = 3; |
Felipe Balbi | a74f0a1 | 2014-09-08 17:54:55 -0700 | [diff] [blame] | 299 | omap_nr_irqs = 96; |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 300 | |
| 301 | if (WARN_ON(!node)) |
| 302 | return -ENODEV; |
| 303 | |
| 304 | if (of_address_to_resource(node, 0, &res)) { |
| 305 | WARN(1, "unable to get intc registers\n"); |
| 306 | return -EINVAL; |
| 307 | } |
| 308 | |
Felipe Balbi | 52b1e12 | 2014-09-08 17:54:57 -0700 | [diff] [blame] | 309 | if (of_device_is_compatible(node, "ti,am33xx-intc")) { |
Felipe Balbi | a74f0a1 | 2014-09-08 17:54:55 -0700 | [diff] [blame] | 310 | omap_nr_irqs = 128; |
Felipe Balbi | 52b1e12 | 2014-09-08 17:54:57 -0700 | [diff] [blame] | 311 | omap_nr_pending = 4; |
| 312 | } |
Felipe Balbi | 470f30d | 2014-09-08 17:54:47 -0700 | [diff] [blame] | 313 | |
Felipe Balbi | a74f0a1 | 2014-09-08 17:54:55 -0700 | [diff] [blame] | 314 | omap_init_irq(res.start, of_node_get(node)); |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 315 | |
Felipe Balbi | 2aced89 | 2014-09-08 17:54:52 -0700 | [diff] [blame] | 316 | set_handle_irq(omap_intc_handle_irq); |
Felipe Balbi | b15c76b | 2014-09-08 17:54:43 -0700 | [diff] [blame] | 317 | |
Benoit Cousson | 52fa212 | 2011-11-30 19:21:07 +0100 | [diff] [blame] | 318 | return 0; |
| 319 | } |
| 320 | |
Felipe Balbi | a35db9a | 2014-09-08 17:54:46 -0700 | [diff] [blame] | 321 | IRQCHIP_DECLARE(omap2_intc, "ti,omap2-intc", intc_of_init); |
| 322 | IRQCHIP_DECLARE(omap3_intc, "ti,omap3-intc", intc_of_init); |
| 323 | IRQCHIP_DECLARE(am33xx_intc, "ti,am33xx-intc", intc_of_init); |