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Tony Lindgren1dbae812005-11-10 14:26:51 +00001/*
Uwe Zeisbergerf30c2262006-10-03 23:01:26 +02002 * linux/arch/arm/mach-omap2/irq.c
Tony Lindgren1dbae812005-11-10 14:26:51 +00003 *
4 * Interrupt handler for OMAP2 boards.
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/kernel.h>
Benoit Cousson52fa2122011-11-30 19:21:07 +010014#include <linux/module.h>
Tony Lindgren1dbae812005-11-10 14:26:51 +000015#include <linux/init.h>
Tony Lindgren1dbae812005-11-10 14:26:51 +000016#include <linux/interrupt.h>
Paul Walmsley2e7509e2008-10-09 17:51:28 +030017#include <linux/io.h>
Tony Lindgrenee0839c2012-02-24 10:34:35 -080018
Marc Zyngier2db14992011-09-06 09:56:17 +010019#include <asm/exception.h>
Tony Lindgren1dbae812005-11-10 14:26:51 +000020#include <asm/mach/irq.h>
Benoit Cousson52fa2122011-11-30 19:21:07 +010021#include <linux/irqdomain.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
R Sricharanc4082d42012-06-05 16:31:06 +053024#include <linux/of_irq.h>
Tony Lindgren1dbae812005-11-10 14:26:51 +000025
Tony Lindgrendbc04162012-08-31 10:59:07 -070026#include "soc.h"
Paul Walmsleye2ed89f2012-04-13 06:34:26 -060027#include "common.h"
Felipe Balbib65ecd42014-09-08 17:54:43 -070028#include "../../drivers/irqchip/irqchip.h"
Paul Walmsley2e7509e2008-10-09 17:51:28 +030029
30/* selected INTC register offsets */
31
32#define INTC_REVISION 0x0000
33#define INTC_SYSCONFIG 0x0010
34#define INTC_SYSSTATUS 0x0014
Tony Lindgren6ccc4c02008-12-10 17:36:52 -080035#define INTC_SIR 0x0040
Paul Walmsley2e7509e2008-10-09 17:51:28 +030036#define INTC_CONTROL 0x0048
Rajendra Nayak0addd612008-09-26 17:48:20 +053037#define INTC_PROTECTION 0x004C
38#define INTC_IDLE 0x0050
39#define INTC_THRESHOLD 0x0068
40#define INTC_MIR0 0x0084
Paul Walmsley2e7509e2008-10-09 17:51:28 +030041#define INTC_MIR_CLEAR0 0x0088
42#define INTC_MIR_SET0 0x008c
43#define INTC_PENDING_IRQ0 0x0098
Felipe Balbi11983652014-09-08 17:54:37 -070044#define INTC_PENDING_IRQ1 0x00b8
45#define INTC_PENDING_IRQ2 0x00d8
46#define INTC_PENDING_IRQ3 0x00f8
Felipe Balbi33c7c7b2014-09-08 17:54:32 -070047#define INTC_ILR0 0x0100
Tony Lindgren1dbae812005-11-10 14:26:51 +000048
Marc Zyngier2db14992011-09-06 09:56:17 +010049#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
Felipe Balbia88ab432014-09-08 17:54:35 -070050#define INTCPS_NR_ILR_REGS 128
Tony Lindgren3003ce32012-09-04 17:43:29 -070051#define INTCPS_NR_MIR_REGS 3
Marc Zyngier2db14992011-09-06 09:56:17 +010052
Tony Lindgren1dbae812005-11-10 14:26:51 +000053/*
54 * OMAP2 has a number of different interrupt controllers, each interrupt
55 * controller is identified as its own "bank". Register definitions are
56 * fairly consistent for each bank, but not all registers are implemented
57 * for each bank.. when in doubt, consult the TRM.
58 */
Tony Lindgren1dbae812005-11-10 14:26:51 +000059
Rajendra Nayak0addd612008-09-26 17:48:20 +053060/* Structure to save interrupt controller context */
Felipe Balbi272a8b02014-09-08 17:54:38 -070061struct omap_intc_regs {
Rajendra Nayak0addd612008-09-26 17:48:20 +053062 u32 sysconfig;
63 u32 protection;
64 u32 idle;
65 u32 threshold;
Felipe Balbia88ab432014-09-08 17:54:35 -070066 u32 ilr[INTCPS_NR_ILR_REGS];
Rajendra Nayak0addd612008-09-26 17:48:20 +053067 u32 mir[INTCPS_NR_MIR_REGS];
68};
Felipe Balbi131b48c2014-09-08 17:54:42 -070069static struct omap_intc_regs intc_context;
70
71static struct irq_domain *domain;
72static void __iomem *omap_irq_base;
Felipe Balbi52b1e122014-09-08 17:54:57 -070073static int omap_nr_pending = 3;
Felipe Balbi131b48c2014-09-08 17:54:42 -070074static int omap_nr_irqs = 96;
Rajendra Nayak0addd612008-09-26 17:48:20 +053075
Paul Walmsley2e7509e2008-10-09 17:51:28 +030076/* INTC bank register get/set */
Felipe Balbi71be00c2014-09-08 17:54:32 -070077static void intc_writel(u32 reg, u32 val)
Paul Walmsley2e7509e2008-10-09 17:51:28 +030078{
Felipe Balbi71be00c2014-09-08 17:54:32 -070079 writel_relaxed(val, omap_irq_base + reg);
Paul Walmsley2e7509e2008-10-09 17:51:28 +030080}
81
Felipe Balbi71be00c2014-09-08 17:54:32 -070082static u32 intc_readl(u32 reg)
Paul Walmsley2e7509e2008-10-09 17:51:28 +030083{
Felipe Balbi71be00c2014-09-08 17:54:32 -070084 return readl_relaxed(omap_irq_base + reg);
Paul Walmsley2e7509e2008-10-09 17:51:28 +030085}
86
Felipe Balbi131b48c2014-09-08 17:54:42 -070087void omap_intc_save_context(void)
88{
89 int i;
90
91 intc_context.sysconfig =
92 intc_readl(INTC_SYSCONFIG);
93 intc_context.protection =
94 intc_readl(INTC_PROTECTION);
95 intc_context.idle =
96 intc_readl(INTC_IDLE);
97 intc_context.threshold =
98 intc_readl(INTC_THRESHOLD);
99
100 for (i = 0; i < omap_nr_irqs; i++)
101 intc_context.ilr[i] =
102 intc_readl((INTC_ILR0 + 0x4 * i));
103 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
104 intc_context.mir[i] =
105 intc_readl(INTC_MIR0 + (0x20 * i));
106}
107
108void omap_intc_restore_context(void)
109{
110 int i;
111
112 intc_writel(INTC_SYSCONFIG, intc_context.sysconfig);
113 intc_writel(INTC_PROTECTION, intc_context.protection);
114 intc_writel(INTC_IDLE, intc_context.idle);
115 intc_writel(INTC_THRESHOLD, intc_context.threshold);
116
117 for (i = 0; i < omap_nr_irqs; i++)
118 intc_writel(INTC_ILR0 + 0x4 * i,
119 intc_context.ilr[i]);
120
121 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
122 intc_writel(INTC_MIR0 + 0x20 * i,
123 intc_context.mir[i]);
124 /* MIRs are saved and restore with other PRCM registers */
125}
126
127void omap3_intc_prepare_idle(void)
128{
129 /*
130 * Disable autoidle as it can stall interrupt controller,
131 * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
132 */
133 intc_writel(INTC_SYSCONFIG, 0);
134}
135
136void omap3_intc_resume_idle(void)
137{
138 /* Re-enable autoidle */
139 intc_writel(INTC_SYSCONFIG, 1);
140}
141
Tony Lindgren1dbae812005-11-10 14:26:51 +0000142/* XXX: FIQ and additional INTC support (only MPU at the moment) */
Lennert Buytenhekdf303472010-11-29 10:39:59 +0100143static void omap_ack_irq(struct irq_data *d)
Tony Lindgren1dbae812005-11-10 14:26:51 +0000144{
Felipe Balbi71be00c2014-09-08 17:54:32 -0700145 intc_writel(INTC_CONTROL, 0x1);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000146}
147
Lennert Buytenhekdf303472010-11-29 10:39:59 +0100148static void omap_mask_ack_irq(struct irq_data *d)
Tony Lindgren1dbae812005-11-10 14:26:51 +0000149{
Tony Lindgren667a11f2011-05-16 02:07:38 -0700150 irq_gc_mask_disable_reg(d);
Lennert Buytenhekdf303472010-11-29 10:39:59 +0100151 omap_ack_irq(d);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000152}
153
Felipe Balbia88ab432014-09-08 17:54:35 -0700154static void __init omap_irq_soft_reset(void)
Tony Lindgren1dbae812005-11-10 14:26:51 +0000155{
156 unsigned long tmp;
157
Felipe Balbi71be00c2014-09-08 17:54:32 -0700158 tmp = intc_readl(INTC_REVISION) & 0xff;
Felipe Balbia88ab432014-09-08 17:54:35 -0700159
Paul Walmsley7852ec02012-07-26 00:54:26 -0600160 pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
Felipe Balbia88ab432014-09-08 17:54:35 -0700161 omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000162
Felipe Balbi71be00c2014-09-08 17:54:32 -0700163 tmp = intc_readl(INTC_SYSCONFIG);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000164 tmp |= 1 << 1; /* soft reset */
Felipe Balbi71be00c2014-09-08 17:54:32 -0700165 intc_writel(INTC_SYSCONFIG, tmp);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000166
Felipe Balbi71be00c2014-09-08 17:54:32 -0700167 while (!(intc_readl(INTC_SYSSTATUS) & 0x1))
Tony Lindgren1dbae812005-11-10 14:26:51 +0000168 /* Wait for reset to complete */;
Juha Yrjola375e12a2006-12-06 17:13:50 -0800169
170 /* Enable autoidle */
Felipe Balbi71be00c2014-09-08 17:54:32 -0700171 intc_writel(INTC_SYSCONFIG, 1 << 0);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000172}
173
Jouni Hogander94434532009-02-03 15:49:04 -0800174int omap_irq_pending(void)
175{
Felipe Balbia88ab432014-09-08 17:54:35 -0700176 int irq;
Jouni Hogander94434532009-02-03 15:49:04 -0800177
Felipe Balbia88ab432014-09-08 17:54:35 -0700178 for (irq = 0; irq < omap_nr_irqs; irq += 32)
179 if (intc_readl(INTC_PENDING_IRQ0 +
180 ((irq >> 5) << 5)))
181 return 1;
Jouni Hogander94434532009-02-03 15:49:04 -0800182 return 0;
183}
184
Felipe Balbi131b48c2014-09-08 17:54:42 -0700185void omap3_intc_suspend(void)
186{
187 /* A pending interrupt would prevent OMAP from entering suspend */
188 omap_ack_irq(NULL);
189}
190
Tony Lindgren667a11f2011-05-16 02:07:38 -0700191static __init void
192omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
193{
194 struct irq_chip_generic *gc;
195 struct irq_chip_type *ct;
196
197 gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
198 handle_level_irq);
199 ct = gc->chip_types;
200 ct->chip.irq_ack = omap_mask_ack_irq;
201 ct->chip.irq_mask = irq_gc_mask_disable_reg;
202 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
NeilBrowne3c83c22012-04-25 13:05:24 +1000203 ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
Tony Lindgren667a11f2011-05-16 02:07:38 -0700204
Tony Lindgren667a11f2011-05-16 02:07:38 -0700205 ct->regs.enable = INTC_MIR_CLEAR0;
206 ct->regs.disable = INTC_MIR_SET0;
207 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
208 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
209}
210
Felipe Balbia74f0a12014-09-08 17:54:55 -0700211static void __init omap_init_irq(u32 base, struct device_node *node)
Tony Lindgren1dbae812005-11-10 14:26:51 +0000212{
Felipe Balbia88ab432014-09-08 17:54:35 -0700213 int j, irq_base;
Tony Lindgren1dbae812005-11-10 14:26:51 +0000214
Tony Lindgren741e3a82011-05-17 03:51:26 -0700215 omap_irq_base = ioremap(base, SZ_4K);
216 if (WARN_ON(!omap_irq_base))
217 return;
218
Felipe Balbia74f0a12014-09-08 17:54:55 -0700219 irq_base = irq_alloc_descs(-1, 0, omap_nr_irqs, 0);
Benoit Cousson52fa2122011-11-30 19:21:07 +0100220 if (irq_base < 0) {
221 pr_warn("Couldn't allocate IRQ numbers\n");
222 irq_base = 0;
223 }
224
Felipe Balbia74f0a12014-09-08 17:54:55 -0700225 domain = irq_domain_add_legacy(node, omap_nr_irqs, irq_base, 0,
Felipe Balbia88ab432014-09-08 17:54:35 -0700226 &irq_domain_simple_ops, NULL);
Benoit Cousson52fa2122011-11-30 19:21:07 +0100227
Felipe Balbia88ab432014-09-08 17:54:35 -0700228 omap_irq_soft_reset();
Tony Lindgren1dbae812005-11-10 14:26:51 +0000229
Felipe Balbia88ab432014-09-08 17:54:35 -0700230 for (j = 0; j < omap_nr_irqs; j += 32)
231 omap_alloc_gc(omap_irq_base + j, j + irq_base, 32);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000232}
233
Felipe Balbi2aced892014-09-08 17:54:52 -0700234static asmlinkage void __exception_irq_entry
235omap_intc_handle_irq(struct pt_regs *regs)
Marc Zyngier2db14992011-09-06 09:56:17 +0100236{
Felipe Balbid6a7c5c2014-09-08 17:54:57 -0700237 u32 irqnr = 0;
Stefan Sørensen698b4852014-03-06 16:27:15 +0100238 int handled_irq = 0;
Felipe Balbid6a7c5c2014-09-08 17:54:57 -0700239 int i;
Marc Zyngier2db14992011-09-06 09:56:17 +0100240
241 do {
Felipe Balbid6a7c5c2014-09-08 17:54:57 -0700242 for (i = 0; i < omap_nr_pending; i++) {
243 irqnr = intc_readl(INTC_PENDING_IRQ0 + (0x20 * i));
244 if (irqnr)
245 goto out;
246 }
Marc Zyngier2db14992011-09-06 09:56:17 +0100247
248out:
249 if (!irqnr)
250 break;
251
Felipe Balbi11983652014-09-08 17:54:37 -0700252 irqnr = intc_readl(INTC_SIR);
Marc Zyngier2db14992011-09-06 09:56:17 +0100253 irqnr &= ACTIVEIRQ_MASK;
254
Benoit Cousson52fa2122011-11-30 19:21:07 +0100255 if (irqnr) {
256 irqnr = irq_find_mapping(domain, irqnr);
Marc Zyngier2db14992011-09-06 09:56:17 +0100257 handle_IRQ(irqnr, regs);
Stefan Sørensen698b4852014-03-06 16:27:15 +0100258 handled_irq = 1;
Benoit Cousson52fa2122011-11-30 19:21:07 +0100259 }
Marc Zyngier2db14992011-09-06 09:56:17 +0100260 } while (irqnr);
Stefan Sørensen698b4852014-03-06 16:27:15 +0100261
262 /* If an irq is masked or deasserted while active, we will
263 * keep ending up here with no irq handled. So remove it from
264 * the INTC with an ack.*/
265 if (!handled_irq)
266 omap_ack_irq(NULL);
Marc Zyngier2db14992011-09-06 09:56:17 +0100267}
268
Felipe Balbia4d3c5d2014-09-08 17:54:51 -0700269void __init omap2_init_irq(void)
270{
Felipe Balbia74f0a12014-09-08 17:54:55 -0700271 omap_nr_irqs = 96;
Felipe Balbi52b1e122014-09-08 17:54:57 -0700272 omap_nr_pending = 3;
Felipe Balbia74f0a12014-09-08 17:54:55 -0700273 omap_init_irq(OMAP24XX_IC_BASE, NULL);
Felipe Balbi2aced892014-09-08 17:54:52 -0700274 set_handle_irq(omap_intc_handle_irq);
Felipe Balbia4d3c5d2014-09-08 17:54:51 -0700275}
276
277void __init omap3_init_irq(void)
278{
Felipe Balbia74f0a12014-09-08 17:54:55 -0700279 omap_nr_irqs = 96;
Felipe Balbi52b1e122014-09-08 17:54:57 -0700280 omap_nr_pending = 3;
Felipe Balbia74f0a12014-09-08 17:54:55 -0700281 omap_init_irq(OMAP34XX_IC_BASE, NULL);
Felipe Balbi2aced892014-09-08 17:54:52 -0700282 set_handle_irq(omap_intc_handle_irq);
Felipe Balbia4d3c5d2014-09-08 17:54:51 -0700283}
284
285void __init ti81xx_init_irq(void)
286{
Felipe Balbia74f0a12014-09-08 17:54:55 -0700287 omap_nr_irqs = 96;
Felipe Balbi52b1e122014-09-08 17:54:57 -0700288 omap_nr_pending = 4;
Felipe Balbia74f0a12014-09-08 17:54:55 -0700289 omap_init_irq(OMAP34XX_IC_BASE, NULL);
Felipe Balbi2aced892014-09-08 17:54:52 -0700290 set_handle_irq(omap_intc_handle_irq);
Felipe Balbia4d3c5d2014-09-08 17:54:51 -0700291}
292
Felipe Balbi00b6b032014-09-08 17:54:43 -0700293static int __init intc_of_init(struct device_node *node,
Benoit Cousson52fa2122011-11-30 19:21:07 +0100294 struct device_node *parent)
295{
296 struct resource res;
Felipe Balbia74f0a12014-09-08 17:54:55 -0700297
Felipe Balbi52b1e122014-09-08 17:54:57 -0700298 omap_nr_pending = 3;
Felipe Balbia74f0a12014-09-08 17:54:55 -0700299 omap_nr_irqs = 96;
Benoit Cousson52fa2122011-11-30 19:21:07 +0100300
301 if (WARN_ON(!node))
302 return -ENODEV;
303
304 if (of_address_to_resource(node, 0, &res)) {
305 WARN(1, "unable to get intc registers\n");
306 return -EINVAL;
307 }
308
Felipe Balbi52b1e122014-09-08 17:54:57 -0700309 if (of_device_is_compatible(node, "ti,am33xx-intc")) {
Felipe Balbia74f0a12014-09-08 17:54:55 -0700310 omap_nr_irqs = 128;
Felipe Balbi52b1e122014-09-08 17:54:57 -0700311 omap_nr_pending = 4;
312 }
Felipe Balbi470f30d2014-09-08 17:54:47 -0700313
Felipe Balbia74f0a12014-09-08 17:54:55 -0700314 omap_init_irq(res.start, of_node_get(node));
Benoit Cousson52fa2122011-11-30 19:21:07 +0100315
Felipe Balbi2aced892014-09-08 17:54:52 -0700316 set_handle_irq(omap_intc_handle_irq);
Felipe Balbib15c76b2014-09-08 17:54:43 -0700317
Benoit Cousson52fa2122011-11-30 19:21:07 +0100318 return 0;
319}
320
Felipe Balbia35db9a2014-09-08 17:54:46 -0700321IRQCHIP_DECLARE(omap2_intc, "ti,omap2-intc", intc_of_init);
322IRQCHIP_DECLARE(omap3_intc, "ti,omap3-intc", intc_of_init);
323IRQCHIP_DECLARE(am33xx_intc, "ti,am33xx-intc", intc_of_init);