Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.19 / dde3b0d64c3df7272082128133f0af592d7ac50f / . / arch / arm / boot / dts / am33xx.dtsi
blob: e7cabe2c890b0f9b875d5db27f94f5948b42c8c9 [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "ti,am33xx";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]15 interrupt-parent = <&intc>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]16
17 aliases {
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame^]18 serial0 = &uart0;
19 serial1 = &uart1;
20 serial2 = &uart2;
21 serial3 = &uart3;
22 serial4 = &uart4;
23 serial5 = &uart5;
AnilKumar Ch7a57ee82012-11-14 23:38:24 +0530[diff] [blame]24 d_can0 = &dcan0;
25 d_can1 = &dcan1;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]26 };
27
28 cpus {
29 cpu@0 {
30 compatible = "arm,cortex-a8";
AnilKumar Chefeedcf22012-08-31 15:07:20 +0530[diff] [blame]31
32 /*
33 * To consider voltage drop between PMIC and SoC,
34 * tolerance value is reduced to 2% from 4% and
35 * voltage value is increased as a precaution.
36 */
37 operating-points = <
38 /* kHz uV */
39 720000 1285000
40 600000 1225000
41 500000 1125000
42 275000 1125000
43 >;
44 voltage-tolerance = <2>; /* 2 percentage */
45 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]46 };
47 };
48
49 /*
50 * The soc node represents the soc top level view. It is uses for IPs
51 * that are not memory mapped in the MPU view or for the MPU itself.
52 */
53 soc {
54 compatible = "ti,omap-infra";
55 mpu {
56 compatible = "ti,omap3-mpu";
57 ti,hwmods = "mpu";
58 };
59 };
60
AnilKumar Chb552dfc2012-09-20 02:49:26 +0530[diff] [blame]61 am33xx_pinmux: pinmux@44e10800 {
62 compatible = "pinctrl-single";
63 reg = <0x44e10800 0x0238>;
64 #address-cells = <1>;
65 #size-cells = <0>;
66 pinctrl-single,register-width = <32>;
67 pinctrl-single,function-mask = <0x7f>;
68 };
69
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]70 /*
71 * XXX: Use a flat representation of the AM33XX interconnect.
72 * The real AM33XX interconnect network is quite complex.Since
73 * that will not bring real advantage to represent that in DT
74 * for the moment, just use a fake OCP bus entry to represent
75 * the whole bus hierarchy.
76 */
77 ocp {
78 compatible = "simple-bus";
79 #address-cells = <1>;
80 #size-cells = <1>;
81 ranges;
82 ti,hwmods = "l3_main";
83
84 intc: interrupt-controller@48200000 {
85 compatible = "ti,omap2-intc";
86 interrupt-controller;
87 #interrupt-cells = <1>;
88 ti,intc-size = <128>;
89 reg = <0x48200000 0x1000>;
90 };
91
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]92 gpio0: gpio@44e07000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]93 compatible = "ti,omap4-gpio";
94 ti,hwmods = "gpio1";
95 gpio-controller;
96 #gpio-cells = <2>;
97 interrupt-controller;
98 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]99 reg = <0x44e07000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]100 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]101 };
102
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]103 gpio1: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]104 compatible = "ti,omap4-gpio";
105 ti,hwmods = "gpio2";
106 gpio-controller;
107 #gpio-cells = <2>;
108 interrupt-controller;
109 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]110 reg = <0x4804c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]111 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]112 };
113
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]114 gpio2: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]115 compatible = "ti,omap4-gpio";
116 ti,hwmods = "gpio3";
117 gpio-controller;
118 #gpio-cells = <2>;
119 interrupt-controller;
120 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]121 reg = <0x481ac000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]122 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]123 };
124
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]125 gpio3: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]126 compatible = "ti,omap4-gpio";
127 ti,hwmods = "gpio4";
128 gpio-controller;
129 #gpio-cells = <2>;
130 interrupt-controller;
131 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]132 reg = <0x481ae000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]133 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]134 };
135
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame^]136 uart0: serial@44e09000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]137 compatible = "ti,omap3-uart";
138 ti,hwmods = "uart1";
139 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]140 reg = <0x44e09000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]141 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]142 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]143 };
144
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame^]145 uart1: serial@48022000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]146 compatible = "ti,omap3-uart";
147 ti,hwmods = "uart2";
148 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]149 reg = <0x48022000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]150 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]151 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]152 };
153
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame^]154 uart2: serial@48024000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]155 compatible = "ti,omap3-uart";
156 ti,hwmods = "uart3";
157 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]158 reg = <0x48024000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]159 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]160 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]161 };
162
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame^]163 uart3: serial@481a6000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]164 compatible = "ti,omap3-uart";
165 ti,hwmods = "uart4";
166 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]167 reg = <0x481a6000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]168 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]169 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]170 };
171
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame^]172 uart4: serial@481a8000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]173 compatible = "ti,omap3-uart";
174 ti,hwmods = "uart5";
175 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]176 reg = <0x481a8000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]177 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]178 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]179 };
180
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame^]181 uart5: serial@481aa000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]182 compatible = "ti,omap3-uart";
183 ti,hwmods = "uart6";
184 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]185 reg = <0x481aa000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]186 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]187 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]188 };
189
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]190 i2c0: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]191 compatible = "ti,omap4-i2c";
192 #address-cells = <1>;
193 #size-cells = <0>;
194 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]195 reg = <0x44e0b000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]196 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]197 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]198 };
199
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]200 i2c1: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]201 compatible = "ti,omap4-i2c";
202 #address-cells = <1>;
203 #size-cells = <0>;
204 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]205 reg = <0x4802a000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]206 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]207 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]208 };
209
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]210 i2c2: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]211 compatible = "ti,omap4-i2c";
212 #address-cells = <1>;
213 #size-cells = <0>;
214 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]215 reg = <0x4819c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]216 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]217 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]218 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]219
220 wdt2: wdt@44e35000 {
221 compatible = "ti,omap3-wdt";
222 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]223 reg = <0x44e35000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]224 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]225 };
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]226
227 dcan0: d_can@481cc000 {
228 compatible = "bosch,d_can";
229 ti,hwmods = "d_can0";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]230 reg = <0x481cc000 0x2000
231 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]232 interrupts = <52>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]233 status = "disabled";
234 };
235
236 dcan1: d_can@481d0000 {
237 compatible = "bosch,d_can";
238 ti,hwmods = "d_can1";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]239 reg = <0x481d0000 0x2000
240 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]241 interrupts = <55>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]242 status = "disabled";
243 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]244
245 timer1: timer@44e31000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]246 compatible = "ti,am335x-timer-1ms";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]247 reg = <0x44e31000 0x400>;
248 interrupts = <67>;
249 ti,hwmods = "timer1";
250 ti,timer-alwon;
251 };
252
253 timer2: timer@48040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]254 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]255 reg = <0x48040000 0x400>;
256 interrupts = <68>;
257 ti,hwmods = "timer2";
258 };
259
260 timer3: timer@48042000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]261 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]262 reg = <0x48042000 0x400>;
263 interrupts = <69>;
264 ti,hwmods = "timer3";
265 };
266
267 timer4: timer@48044000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]268 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]269 reg = <0x48044000 0x400>;
270 interrupts = <92>;
271 ti,hwmods = "timer4";
272 ti,timer-pwm;
273 };
274
275 timer5: timer@48046000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]276 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]277 reg = <0x48046000 0x400>;
278 interrupts = <93>;
279 ti,hwmods = "timer5";
280 ti,timer-pwm;
281 };
282
283 timer6: timer@48048000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]284 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]285 reg = <0x48048000 0x400>;
286 interrupts = <94>;
287 ti,hwmods = "timer6";
288 ti,timer-pwm;
289 };
290
291 timer7: timer@4804a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]292 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]293 reg = <0x4804a000 0x400>;
294 interrupts = <95>;
295 ti,hwmods = "timer7";
296 ti,timer-pwm;
297 };
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]298
299 rtc@44e3e000 {
300 compatible = "ti,da830-rtc";
301 reg = <0x44e3e000 0x1000>;
302 interrupts = <75
303 76>;
304 ti,hwmods = "rtc";
305 };
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]306
307 spi0: spi@48030000 {
308 compatible = "ti,omap4-mcspi";
309 #address-cells = <1>;
310 #size-cells = <0>;
311 reg = <0x48030000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]312 interrupts = <65>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]313 ti,spi-num-cs = <2>;
314 ti,hwmods = "spi0";
315 status = "disabled";
316 };
317
318 spi1: spi@481a0000 {
319 compatible = "ti,omap4-mcspi";
320 #address-cells = <1>;
321 #size-cells = <0>;
322 reg = <0x481a0000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]323 interrupts = <125>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]324 ti,spi-num-cs = <2>;
325 ti,hwmods = "spi1";
326 status = "disabled";
327 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]328
329 usb@47400000 {
330 compatible = "ti,musb-am33xx";
331 reg = <0x47400000 0x1000 /* usbss */
332 0x47401000 0x800 /* musb instance 0 */
333 0x47401800 0x800>; /* musb instance 1 */
334 interrupts = <17 /* usbss */
335 18 /* musb instance 0 */
336 19>; /* musb instance 1 */
337 multipoint = <1>;
338 num-eps = <16>;
339 ram-bits = <12>;
340 port0-mode = <3>;
341 port1-mode = <3>;
342 power = <250>;
343 ti,hwmods = "usb_otg_hs";
344 };
Linus Torvalds6be35c72012-12-12 18:07:07 -0800[diff] [blame]345
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]346 mac: ethernet@4a100000 {
347 compatible = "ti,cpsw";
348 ti,hwmods = "cpgmac0";
349 cpdma_channels = <8>;
350 ale_entries = <1024>;
351 bd_ram_size = <0x2000>;
352 no_bd_ram = <0>;
353 rx_descs = <64>;
354 mac_control = <0x20>;
355 slaves = <2>;
Mugunthan V Ne86ac132013-03-11 23:16:35 +0000[diff] [blame]356 active_slave = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]357 cpts_clock_mult = <0x80000000>;
358 cpts_clock_shift = <29>;
359 reg = <0x4a100000 0x800
360 0x4a101200 0x100>;
361 #address-cells = <1>;
362 #size-cells = <1>;
363 interrupt-parent = <&intc>;
364 /*
365 * c0_rx_thresh_pend
366 * c0_rx_pend
367 * c0_tx_pend
368 * c0_misc_pend
369 */
370 interrupts = <40 41 42 43>;
371 ranges;
372
373 davinci_mdio: mdio@4a101000 {
374 compatible = "ti,davinci_mdio";
375 #address-cells = <1>;
376 #size-cells = <0>;
377 ti,hwmods = "davinci_mdio";
378 bus_freq = <1000000>;
379 reg = <0x4a101000 0x100>;
380 };
381
382 cpsw_emac0: slave@4a100200 {
383 /* Filled in by U-Boot */
384 mac-address = [ 00 00 00 00 00 00 ];
385 };
386
387 cpsw_emac1: slave@4a100300 {
388 /* Filled in by U-Boot */
389 mac-address = [ 00 00 00 00 00 00 ];
390 };
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]391 };
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]392
393 ocmcram: ocmcram@40300000 {
394 compatible = "ti,am3352-ocmcram";
395 reg = <0x40300000 0x10000>;
396 ti,hwmods = "ocmcram";
397 ti,no_idle_on_suspend;
398 };
399
400 wkup_m3: wkup_m3@44d00000 {
401 compatible = "ti,am3353-wkup-m3";
402 reg = <0x44d00000 0x4000 /* M3 UMEM */
403 0x44d80000 0x2000>; /* M3 DMEM */
404 ti,hwmods = "wkup_m3";
405 };
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]406
407 gpmc: gpmc@50000000 {
408 compatible = "ti,am3352-gpmc";
409 ti,hwmods = "gpmc";
410 reg = <0x50000000 0x2000>;
411 interrupts = <100>;
Lars Poeschel00dddca2013-05-28 10:24:57 +0200[diff] [blame]412 gpmc,num-cs = <7>;
413 gpmc,num-waitpins = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]414 #address-cells = <2>;
415 #size-cells = <1>;
416 status = "disabled";
417 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]418 };
419};