blob: 979cf9197282ca1f315a0ca8430da4d527332cd8 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Synthesize TLB refill handlers at runtime.
7 *
Thiemo Seufere30ec452008-01-28 20:05:38 +00008 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
Maciej W. Rozycki619b6e12007-10-23 12:43:25 +01009 * Copyright (C) 2005, 2007 Maciej W. Rozycki
Ralf Baechle41c594a2006-04-05 09:45:45 +010010 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
11 *
12 * ... and the days got worse and worse and now you see
13 * I've gone completly out of my mind.
14 *
15 * They're coming to take me a away haha
16 * they're coming to take me a away hoho hihi haha
17 * to the funny farm where code is beautiful all the time ...
18 *
19 * (Condolences to Napoleon XIV)
Linus Torvalds1da177e2005-04-16 15:20:36 -070020 */
21
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/string.h>
25#include <linux/init.h>
26
Linus Torvalds1da177e2005-04-16 15:20:36 -070027#include <asm/mmu_context.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070028#include <asm/war.h>
29
Thiemo Seufere30ec452008-01-28 20:05:38 +000030#include "uasm.h"
31
Ralf Baechleaeffdbb2007-10-11 23:46:14 +010032static inline int r45k_bvahwbug(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070033{
34 /* XXX: We should probe for the presence of this bug, but we don't. */
35 return 0;
36}
37
Ralf Baechleaeffdbb2007-10-11 23:46:14 +010038static inline int r4k_250MHZhwbug(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070039{
40 /* XXX: We should probe for the presence of this bug, but we don't. */
41 return 0;
42}
43
Ralf Baechleaeffdbb2007-10-11 23:46:14 +010044static inline int __maybe_unused bcm1250_m3_war(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070045{
46 return BCM1250_M3_WAR;
47}
48
Ralf Baechleaeffdbb2007-10-11 23:46:14 +010049static inline int __maybe_unused r10000_llsc_war(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070050{
51 return R10000_LLSC_WAR;
52}
53
54/*
Maciej W. Rozycki8df5bea2006-08-23 14:26:50 +010055 * Found by experiment: At least some revisions of the 4kc throw under
56 * some circumstances a machine check exception, triggered by invalid
57 * values in the index register. Delaying the tlbp instruction until
58 * after the next branch, plus adding an additional nop in front of
59 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
60 * why; it's not an issue caused by the core RTL.
61 *
62 */
Ralf Baechle234fcd12008-03-08 09:56:28 +000063static int __cpuinit m4kc_tlbp_war(void)
Maciej W. Rozycki8df5bea2006-08-23 14:26:50 +010064{
65 return (current_cpu_data.processor_id & 0xffff00) ==
66 (PRID_COMP_MIPS | PRID_IMP_4KC);
67}
68
Thiemo Seufere30ec452008-01-28 20:05:38 +000069/* Handle labels (which must be positive integers). */
Linus Torvalds1da177e2005-04-16 15:20:36 -070070enum label_id {
Thiemo Seufere30ec452008-01-28 20:05:38 +000071 label_second_part = 1,
Linus Torvalds1da177e2005-04-16 15:20:36 -070072 label_leave,
Atsushi Nemoto656be922006-10-26 00:08:31 +090073#ifdef MODULE_START
74 label_module_alloc,
75#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070076 label_vmalloc,
77 label_vmalloc_done,
78 label_tlbw_hazard,
79 label_split,
80 label_nopage_tlbl,
81 label_nopage_tlbs,
82 label_nopage_tlbm,
83 label_smp_pgtable_change,
84 label_r3000_write_probe_fail,
Linus Torvalds1da177e2005-04-16 15:20:36 -070085};
86
Thiemo Seufere30ec452008-01-28 20:05:38 +000087UASM_L_LA(_second_part)
88UASM_L_LA(_leave)
Atsushi Nemoto656be922006-10-26 00:08:31 +090089#ifdef MODULE_START
Thiemo Seufere30ec452008-01-28 20:05:38 +000090UASM_L_LA(_module_alloc)
Atsushi Nemoto656be922006-10-26 00:08:31 +090091#endif
Thiemo Seufere30ec452008-01-28 20:05:38 +000092UASM_L_LA(_vmalloc)
93UASM_L_LA(_vmalloc_done)
94UASM_L_LA(_tlbw_hazard)
95UASM_L_LA(_split)
96UASM_L_LA(_nopage_tlbl)
97UASM_L_LA(_nopage_tlbs)
98UASM_L_LA(_nopage_tlbm)
99UASM_L_LA(_smp_pgtable_change)
100UASM_L_LA(_r3000_write_probe_fail)
Atsushi Nemoto656be922006-10-26 00:08:31 +0900101
Franck Bui-Huu92b1e6a2007-10-18 09:11:17 +0200102/*
103 * For debug purposes.
104 */
105static inline void dump_handler(const u32 *handler, int count)
106{
107 int i;
108
109 pr_debug("\t.set push\n");
110 pr_debug("\t.set noreorder\n");
111
112 for (i = 0; i < count; i++)
113 pr_debug("\t%p\t.word 0x%08x\n", &handler[i], handler[i]);
114
115 pr_debug("\t.set pop\n");
116}
117
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118/* The only general purpose registers allowed in TLB handlers. */
119#define K0 26
120#define K1 27
121
122/* Some CP0 registers */
Ralf Baechle41c594a2006-04-05 09:45:45 +0100123#define C0_INDEX 0, 0
124#define C0_ENTRYLO0 2, 0
125#define C0_TCBIND 2, 2
126#define C0_ENTRYLO1 3, 0
127#define C0_CONTEXT 4, 0
128#define C0_BADVADDR 8, 0
129#define C0_ENTRYHI 10, 0
130#define C0_EPC 14, 0
131#define C0_XCONTEXT 20, 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132
Ralf Baechle875d43e2005-09-03 15:56:16 -0700133#ifdef CONFIG_64BIT
Thiemo Seufere30ec452008-01-28 20:05:38 +0000134# define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135#else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000136# define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137#endif
138
139/* The worst case length of the handler is around 18 instructions for
140 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
141 * Maximum space available is 32 instructions for R3000 and 64
142 * instructions for R4000.
143 *
144 * We deliberately chose a buffer size of 128, so we won't scribble
145 * over anything important on overflow before we panic.
146 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000147static u32 tlb_handler[128] __cpuinitdata;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700148
149/* simply assume worst case size for labels and relocs */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000150static struct uasm_label labels[128] __cpuinitdata;
151static struct uasm_reloc relocs[128] __cpuinitdata;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700152
153/*
154 * The R3000 TLB handler is simple.
155 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000156static void __cpuinit build_r3000_tlb_refill_handler(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700157{
158 long pgdc = (long)pgd_current;
159 u32 *p;
160
161 memset(tlb_handler, 0, sizeof(tlb_handler));
162 p = tlb_handler;
163
Thiemo Seufere30ec452008-01-28 20:05:38 +0000164 uasm_i_mfc0(&p, K0, C0_BADVADDR);
165 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */
166 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1);
167 uasm_i_srl(&p, K0, K0, 22); /* load delay */
168 uasm_i_sll(&p, K0, K0, 2);
169 uasm_i_addu(&p, K1, K1, K0);
170 uasm_i_mfc0(&p, K0, C0_CONTEXT);
171 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */
172 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */
173 uasm_i_addu(&p, K1, K1, K0);
174 uasm_i_lw(&p, K0, 0, K1);
175 uasm_i_nop(&p); /* load delay */
176 uasm_i_mtc0(&p, K0, C0_ENTRYLO0);
177 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
178 uasm_i_tlbwr(&p); /* cp0 delay */
179 uasm_i_jr(&p, K1);
180 uasm_i_rfe(&p); /* branch delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181
182 if (p > tlb_handler + 32)
183 panic("TLB refill handler space exceeded");
184
Thiemo Seufere30ec452008-01-28 20:05:38 +0000185 pr_debug("Wrote TLB refill handler (%u instructions).\n",
186 (unsigned int)(p - tlb_handler));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700187
Ralf Baechle91b05e62006-03-29 18:53:00 +0100188 memcpy((void *)ebase, tlb_handler, 0x80);
Franck Bui-Huu92b1e6a2007-10-18 09:11:17 +0200189
190 dump_handler((u32 *)ebase, 32);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191}
192
193/*
194 * The R4000 TLB handler is much more complicated. We have two
195 * consecutive handler areas with 32 instructions space each.
196 * Since they aren't used at the same time, we can overflow in the
197 * other one.To keep things simple, we first assume linear space,
198 * then we relocate it to the final handler layout as needed.
199 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000200static u32 final_handler[64] __cpuinitdata;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201
202/*
203 * Hazards
204 *
205 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
206 * 2. A timing hazard exists for the TLBP instruction.
207 *
208 * stalling_instruction
209 * TLBP
210 *
211 * The JTLB is being read for the TLBP throughout the stall generated by the
212 * previous instruction. This is not really correct as the stalling instruction
213 * can modify the address used to access the JTLB. The failure symptom is that
214 * the TLBP instruction will use an address created for the stalling instruction
215 * and not the address held in C0_ENHI and thus report the wrong results.
216 *
217 * The software work-around is to not allow the instruction preceding the TLBP
218 * to stall - make it an NOP or some other instruction guaranteed not to stall.
219 *
220 * Errata 2 will not be fixed. This errata is also on the R5000.
221 *
222 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
223 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000224static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225{
Ralf Baechle10cc3522007-10-11 23:46:15 +0100226 switch (current_cpu_type()) {
Thomas Bogendoerfer326e2e12008-05-12 13:55:42 +0200227 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
Thiemo Seuferf5b4d952005-09-09 17:11:50 +0000228 case CPU_R4600:
Thomas Bogendoerfer326e2e12008-05-12 13:55:42 +0200229 case CPU_R4700:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700230 case CPU_R5000:
231 case CPU_R5000A:
232 case CPU_NEVADA:
Thiemo Seufere30ec452008-01-28 20:05:38 +0000233 uasm_i_nop(p);
234 uasm_i_tlbp(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235 break;
236
237 default:
Thiemo Seufere30ec452008-01-28 20:05:38 +0000238 uasm_i_tlbp(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239 break;
240 }
241}
242
243/*
244 * Write random or indexed TLB entry, and care about the hazards from
245 * the preceeding mtc0 and for the following eret.
246 */
247enum tlb_write_entry { tlb_random, tlb_indexed };
248
Ralf Baechle234fcd12008-03-08 09:56:28 +0000249static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
Thiemo Seufere30ec452008-01-28 20:05:38 +0000250 struct uasm_reloc **r,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251 enum tlb_write_entry wmode)
252{
253 void(*tlbw)(u32 **) = NULL;
254
255 switch (wmode) {
Thiemo Seufere30ec452008-01-28 20:05:38 +0000256 case tlb_random: tlbw = uasm_i_tlbwr; break;
257 case tlb_indexed: tlbw = uasm_i_tlbwi; break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258 }
259
Ralf Baechle161548b2008-01-29 10:14:54 +0000260 if (cpu_has_mips_r2) {
Thiemo Seufere30ec452008-01-28 20:05:38 +0000261 uasm_i_ehb(p);
Ralf Baechle161548b2008-01-29 10:14:54 +0000262 tlbw(p);
263 return;
264 }
265
Ralf Baechle10cc3522007-10-11 23:46:15 +0100266 switch (current_cpu_type()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267 case CPU_R4000PC:
268 case CPU_R4000SC:
269 case CPU_R4000MC:
270 case CPU_R4400PC:
271 case CPU_R4400SC:
272 case CPU_R4400MC:
273 /*
274 * This branch uses up a mtc0 hazard nop slot and saves
275 * two nops after the tlbw instruction.
276 */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000277 uasm_il_bgezl(p, r, 0, label_tlbw_hazard);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700278 tlbw(p);
Thiemo Seufere30ec452008-01-28 20:05:38 +0000279 uasm_l_tlbw_hazard(l, *p);
280 uasm_i_nop(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700281 break;
282
283 case CPU_R4600:
284 case CPU_R4700:
285 case CPU_R5000:
286 case CPU_R5000A:
Thiemo Seufere30ec452008-01-28 20:05:38 +0000287 uasm_i_nop(p);
Maciej W. Rozycki2c93e122005-06-30 10:51:01 +0000288 tlbw(p);
Thiemo Seufere30ec452008-01-28 20:05:38 +0000289 uasm_i_nop(p);
Maciej W. Rozycki2c93e122005-06-30 10:51:01 +0000290 break;
291
292 case CPU_R4300:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700293 case CPU_5KC:
294 case CPU_TX49XX:
295 case CPU_AU1000:
296 case CPU_AU1100:
297 case CPU_AU1500:
298 case CPU_AU1550:
Pete Popove3ad1c22005-03-01 06:33:16 +0000299 case CPU_AU1200:
Manuel Lauss237cfee2007-12-06 09:07:55 +0100300 case CPU_AU1210:
301 case CPU_AU1250:
Pete Popovbdf21b12005-07-14 17:47:57 +0000302 case CPU_PR4450:
Thiemo Seufere30ec452008-01-28 20:05:38 +0000303 uasm_i_nop(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304 tlbw(p);
305 break;
306
307 case CPU_R10000:
308 case CPU_R12000:
Kumba44d921b2006-05-16 22:23:59 -0400309 case CPU_R14000:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310 case CPU_4KC:
Thomas Bogendoerferb1ec4c82008-03-26 16:42:54 +0100311 case CPU_4KEC:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312 case CPU_SB1:
Andrew Isaacson93ce2f522005-10-19 23:56:20 -0700313 case CPU_SB1A:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700314 case CPU_4KSC:
315 case CPU_20KC:
316 case CPU_25KF:
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +0200317 case CPU_BCM3302:
318 case CPU_BCM4710:
Fuxin Zhang2a21c732007-06-06 14:52:43 +0800319 case CPU_LOONGSON2:
Maciej W. Rozycki8df5bea2006-08-23 14:26:50 +0100320 if (m4kc_tlbp_war())
Thiemo Seufere30ec452008-01-28 20:05:38 +0000321 uasm_i_nop(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700322 tlbw(p);
323 break;
324
325 case CPU_NEVADA:
Thiemo Seufere30ec452008-01-28 20:05:38 +0000326 uasm_i_nop(p); /* QED specifies 2 nops hazard */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700327 /*
328 * This branch uses up a mtc0 hazard nop slot and saves
329 * a nop after the tlbw instruction.
330 */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000331 uasm_il_bgezl(p, r, 0, label_tlbw_hazard);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700332 tlbw(p);
Thiemo Seufere30ec452008-01-28 20:05:38 +0000333 uasm_l_tlbw_hazard(l, *p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334 break;
335
336 case CPU_RM7000:
Thiemo Seufere30ec452008-01-28 20:05:38 +0000337 uasm_i_nop(p);
338 uasm_i_nop(p);
339 uasm_i_nop(p);
340 uasm_i_nop(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700341 tlbw(p);
342 break;
343
Linus Torvalds1da177e2005-04-16 15:20:36 -0700344 case CPU_RM9000:
345 /*
346 * When the JTLB is updated by tlbwi or tlbwr, a subsequent
347 * use of the JTLB for instructions should not occur for 4
348 * cpu cycles and use for data translations should not occur
349 * for 3 cpu cycles.
350 */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000351 uasm_i_ssnop(p);
352 uasm_i_ssnop(p);
353 uasm_i_ssnop(p);
354 uasm_i_ssnop(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700355 tlbw(p);
Thiemo Seufere30ec452008-01-28 20:05:38 +0000356 uasm_i_ssnop(p);
357 uasm_i_ssnop(p);
358 uasm_i_ssnop(p);
359 uasm_i_ssnop(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700360 break;
361
362 case CPU_VR4111:
363 case CPU_VR4121:
364 case CPU_VR4122:
365 case CPU_VR4181:
366 case CPU_VR4181A:
Thiemo Seufere30ec452008-01-28 20:05:38 +0000367 uasm_i_nop(p);
368 uasm_i_nop(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700369 tlbw(p);
Thiemo Seufere30ec452008-01-28 20:05:38 +0000370 uasm_i_nop(p);
371 uasm_i_nop(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700372 break;
373
374 case CPU_VR4131:
375 case CPU_VR4133:
Ralf Baechle7623deb2005-08-29 16:49:55 +0000376 case CPU_R5432:
Thiemo Seufere30ec452008-01-28 20:05:38 +0000377 uasm_i_nop(p);
378 uasm_i_nop(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700379 tlbw(p);
380 break;
381
382 default:
383 panic("No TLB refill handler yet (CPU type: %d)",
384 current_cpu_data.cputype);
385 break;
386 }
387}
388
Ralf Baechle875d43e2005-09-03 15:56:16 -0700389#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700390/*
391 * TMP and PTR are scratch.
392 * TMP will be clobbered, PTR will hold the pmd entry.
393 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000394static void __cpuinit
Thiemo Seufere30ec452008-01-28 20:05:38 +0000395build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396 unsigned int tmp, unsigned int ptr)
397{
398 long pgdc = (long)pgd_current;
399
400 /*
401 * The vmalloc handling is not in the hotpath.
402 */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000403 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
Atsushi Nemoto656be922006-10-26 00:08:31 +0900404#ifdef MODULE_START
Thiemo Seufere30ec452008-01-28 20:05:38 +0000405 uasm_il_bltz(p, r, tmp, label_module_alloc);
Atsushi Nemoto656be922006-10-26 00:08:31 +0900406#else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000407 uasm_il_bltz(p, r, tmp, label_vmalloc);
Atsushi Nemoto656be922006-10-26 00:08:31 +0900408#endif
Thiemo Seufere30ec452008-01-28 20:05:38 +0000409 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700410
411#ifdef CONFIG_SMP
Ralf Baechle41c594a2006-04-05 09:45:45 +0100412# ifdef CONFIG_MIPS_MT_SMTC
413 /*
414 * SMTC uses TCBind value as "CPU" index
415 */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000416 uasm_i_mfc0(p, ptr, C0_TCBIND);
417 uasm_i_dsrl(p, ptr, ptr, 19);
Ralf Baechle41c594a2006-04-05 09:45:45 +0100418# else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700419 /*
Thiemo Seufer1b3a6e92005-04-01 14:07:13 +0000420 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700421 * stored in CONTEXT.
422 */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000423 uasm_i_dmfc0(p, ptr, C0_CONTEXT);
424 uasm_i_dsrl(p, ptr, ptr, 23);
Ralf Baechle41c594a2006-04-05 09:45:45 +0100425#endif
Thiemo Seufere30ec452008-01-28 20:05:38 +0000426 UASM_i_LA_mostly(p, tmp, pgdc);
427 uasm_i_daddu(p, ptr, ptr, tmp);
428 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
429 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700430#else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000431 UASM_i_LA_mostly(p, ptr, pgdc);
432 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700433#endif
434
Thiemo Seufere30ec452008-01-28 20:05:38 +0000435 uasm_l_vmalloc_done(l, *p);
Ralf Baechle242954b2006-10-24 02:29:01 +0100436
437 if (PGDIR_SHIFT - 3 < 32) /* get pgd offset in bytes */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000438 uasm_i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3);
Ralf Baechle242954b2006-10-24 02:29:01 +0100439 else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000440 uasm_i_dsrl32(p, tmp, tmp, PGDIR_SHIFT - 3 - 32);
Ralf Baechle242954b2006-10-24 02:29:01 +0100441
Thiemo Seufere30ec452008-01-28 20:05:38 +0000442 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
443 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
444 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
445 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */
446 uasm_i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
447 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
448 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700449}
450
451/*
452 * BVADDR is the faulting address, PTR is scratch.
453 * PTR will hold the pgd for vmalloc.
454 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000455static void __cpuinit
Thiemo Seufere30ec452008-01-28 20:05:38 +0000456build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700457 unsigned int bvaddr, unsigned int ptr)
458{
459 long swpd = (long)swapper_pg_dir;
460
Atsushi Nemoto656be922006-10-26 00:08:31 +0900461#ifdef MODULE_START
462 long modd = (long)module_pg_dir;
463
Thiemo Seufere30ec452008-01-28 20:05:38 +0000464 uasm_l_module_alloc(l, *p);
Atsushi Nemoto656be922006-10-26 00:08:31 +0900465 /*
466 * Assumption:
467 * VMALLOC_START >= 0xc000000000000000UL
468 * MODULE_START >= 0xe000000000000000UL
469 */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000470 UASM_i_SLL(p, ptr, bvaddr, 2);
471 uasm_il_bgez(p, r, ptr, label_vmalloc);
Atsushi Nemoto656be922006-10-26 00:08:31 +0900472
Thiemo Seufere30ec452008-01-28 20:05:38 +0000473 if (uasm_in_compat_space_p(MODULE_START) &&
474 !uasm_rel_lo(MODULE_START)) {
475 uasm_i_lui(p, ptr, uasm_rel_hi(MODULE_START)); /* delay slot */
Atsushi Nemoto656be922006-10-26 00:08:31 +0900476 } else {
477 /* unlikely configuration */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000478 uasm_i_nop(p); /* delay slot */
479 UASM_i_LA(p, ptr, MODULE_START);
Atsushi Nemoto656be922006-10-26 00:08:31 +0900480 }
Thiemo Seufere30ec452008-01-28 20:05:38 +0000481 uasm_i_dsubu(p, bvaddr, bvaddr, ptr);
Atsushi Nemoto656be922006-10-26 00:08:31 +0900482
Thiemo Seufere30ec452008-01-28 20:05:38 +0000483 if (uasm_in_compat_space_p(modd) && !uasm_rel_lo(modd)) {
484 uasm_il_b(p, r, label_vmalloc_done);
485 uasm_i_lui(p, ptr, uasm_rel_hi(modd));
Atsushi Nemoto656be922006-10-26 00:08:31 +0900486 } else {
Thiemo Seufere30ec452008-01-28 20:05:38 +0000487 UASM_i_LA_mostly(p, ptr, modd);
488 uasm_il_b(p, r, label_vmalloc_done);
489 if (uasm_in_compat_space_p(modd))
490 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(modd));
Maciej W. Rozycki619b6e12007-10-23 12:43:25 +0100491 else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000492 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(modd));
Atsushi Nemoto656be922006-10-26 00:08:31 +0900493 }
494
Thiemo Seufere30ec452008-01-28 20:05:38 +0000495 uasm_l_vmalloc(l, *p);
496 if (uasm_in_compat_space_p(MODULE_START) &&
497 !uasm_rel_lo(MODULE_START) &&
Atsushi Nemoto656be922006-10-26 00:08:31 +0900498 MODULE_START << 32 == VMALLOC_START)
Thiemo Seufere30ec452008-01-28 20:05:38 +0000499 uasm_i_dsll32(p, ptr, ptr, 0); /* typical case */
Atsushi Nemoto656be922006-10-26 00:08:31 +0900500 else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000501 UASM_i_LA(p, ptr, VMALLOC_START);
Atsushi Nemoto656be922006-10-26 00:08:31 +0900502#else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000503 uasm_l_vmalloc(l, *p);
504 UASM_i_LA(p, ptr, VMALLOC_START);
Atsushi Nemoto656be922006-10-26 00:08:31 +0900505#endif
Thiemo Seufere30ec452008-01-28 20:05:38 +0000506 uasm_i_dsubu(p, bvaddr, bvaddr, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700507
Thiemo Seufere30ec452008-01-28 20:05:38 +0000508 if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) {
509 uasm_il_b(p, r, label_vmalloc_done);
510 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700511 } else {
Thiemo Seufere30ec452008-01-28 20:05:38 +0000512 UASM_i_LA_mostly(p, ptr, swpd);
513 uasm_il_b(p, r, label_vmalloc_done);
514 if (uasm_in_compat_space_p(swpd))
515 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd));
Maciej W. Rozycki619b6e12007-10-23 12:43:25 +0100516 else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000517 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700518 }
519}
520
Ralf Baechle875d43e2005-09-03 15:56:16 -0700521#else /* !CONFIG_64BIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700522
523/*
524 * TMP and PTR are scratch.
525 * TMP will be clobbered, PTR will hold the pgd entry.
526 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000527static void __cpuinit __maybe_unused
Linus Torvalds1da177e2005-04-16 15:20:36 -0700528build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
529{
530 long pgdc = (long)pgd_current;
531
532 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
533#ifdef CONFIG_SMP
Ralf Baechle41c594a2006-04-05 09:45:45 +0100534#ifdef CONFIG_MIPS_MT_SMTC
535 /*
536 * SMTC uses TCBind value as "CPU" index
537 */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000538 uasm_i_mfc0(p, ptr, C0_TCBIND);
539 UASM_i_LA_mostly(p, tmp, pgdc);
540 uasm_i_srl(p, ptr, ptr, 19);
Ralf Baechle41c594a2006-04-05 09:45:45 +0100541#else
542 /*
543 * smp_processor_id() << 3 is stored in CONTEXT.
544 */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000545 uasm_i_mfc0(p, ptr, C0_CONTEXT);
546 UASM_i_LA_mostly(p, tmp, pgdc);
547 uasm_i_srl(p, ptr, ptr, 23);
Ralf Baechle41c594a2006-04-05 09:45:45 +0100548#endif
Thiemo Seufere30ec452008-01-28 20:05:38 +0000549 uasm_i_addu(p, ptr, tmp, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700550#else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000551 UASM_i_LA_mostly(p, ptr, pgdc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700552#endif
Thiemo Seufere30ec452008-01-28 20:05:38 +0000553 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
554 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
555 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
556 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
557 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700558}
559
Ralf Baechle875d43e2005-09-03 15:56:16 -0700560#endif /* !CONFIG_64BIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700561
Ralf Baechle234fcd12008-03-08 09:56:28 +0000562static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700563{
Ralf Baechle242954b2006-10-24 02:29:01 +0100564 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
566
Ralf Baechle10cc3522007-10-11 23:46:15 +0100567 switch (current_cpu_type()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700568 case CPU_VR41XX:
569 case CPU_VR4111:
570 case CPU_VR4121:
571 case CPU_VR4122:
572 case CPU_VR4131:
573 case CPU_VR4181:
574 case CPU_VR4181A:
575 case CPU_VR4133:
576 shift += 2;
577 break;
578
579 default:
580 break;
581 }
582
583 if (shift)
Thiemo Seufere30ec452008-01-28 20:05:38 +0000584 UASM_i_SRL(p, ctx, ctx, shift);
585 uasm_i_andi(p, ctx, ctx, mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700586}
587
Ralf Baechle234fcd12008-03-08 09:56:28 +0000588static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700589{
590 /*
591 * Bug workaround for the Nevada. It seems as if under certain
592 * circumstances the move from cp0_context might produce a
593 * bogus result when the mfc0 instruction and its consumer are
594 * in a different cacheline or a load instruction, probably any
595 * memory reference, is between them.
596 */
Ralf Baechle10cc3522007-10-11 23:46:15 +0100597 switch (current_cpu_type()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700598 case CPU_NEVADA:
Thiemo Seufere30ec452008-01-28 20:05:38 +0000599 UASM_i_LW(p, ptr, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700600 GET_CONTEXT(p, tmp); /* get context reg */
601 break;
602
603 default:
604 GET_CONTEXT(p, tmp); /* get context reg */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000605 UASM_i_LW(p, ptr, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700606 break;
607 }
608
609 build_adjust_context(p, tmp);
Thiemo Seufere30ec452008-01-28 20:05:38 +0000610 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700611}
612
Ralf Baechle234fcd12008-03-08 09:56:28 +0000613static void __cpuinit build_update_entries(u32 **p, unsigned int tmp,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700614 unsigned int ptep)
615{
616 /*
617 * 64bit address support (36bit on a 32bit CPU) in a 32bit
618 * Kernel is a special case. Only a few CPUs use it.
619 */
620#ifdef CONFIG_64BIT_PHYS_ADDR
621 if (cpu_has_64bits) {
Thiemo Seufere30ec452008-01-28 20:05:38 +0000622 uasm_i_ld(p, tmp, 0, ptep); /* get even pte */
623 uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
624 uasm_i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */
625 uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
626 uasm_i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */
627 uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700628 } else {
629 int pte_off_even = sizeof(pte_t) / 2;
630 int pte_off_odd = pte_off_even + sizeof(pte_t);
631
632 /* The pte entries are pre-shifted */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000633 uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */
634 uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
635 uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */
636 uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700637 }
638#else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000639 UASM_i_LW(p, tmp, 0, ptep); /* get even pte */
640 UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641 if (r45k_bvahwbug())
642 build_tlb_probe_entry(p);
Thiemo Seufere30ec452008-01-28 20:05:38 +0000643 UASM_i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700644 if (r4k_250MHZhwbug())
Thiemo Seufere30ec452008-01-28 20:05:38 +0000645 uasm_i_mtc0(p, 0, C0_ENTRYLO0);
646 uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
647 UASM_i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700648 if (r45k_bvahwbug())
Thiemo Seufere30ec452008-01-28 20:05:38 +0000649 uasm_i_mfc0(p, tmp, C0_INDEX);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700650 if (r4k_250MHZhwbug())
Thiemo Seufere30ec452008-01-28 20:05:38 +0000651 uasm_i_mtc0(p, 0, C0_ENTRYLO1);
652 uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653#endif
654}
655
Ralf Baechle234fcd12008-03-08 09:56:28 +0000656static void __cpuinit build_r4000_tlb_refill_handler(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657{
658 u32 *p = tlb_handler;
Thiemo Seufere30ec452008-01-28 20:05:38 +0000659 struct uasm_label *l = labels;
660 struct uasm_reloc *r = relocs;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700661 u32 *f;
662 unsigned int final_len;
663
664 memset(tlb_handler, 0, sizeof(tlb_handler));
665 memset(labels, 0, sizeof(labels));
666 memset(relocs, 0, sizeof(relocs));
667 memset(final_handler, 0, sizeof(final_handler));
668
669 /*
670 * create the plain linear handler
671 */
672 if (bcm1250_m3_war()) {
Thiemo Seufere30ec452008-01-28 20:05:38 +0000673 UASM_i_MFC0(&p, K0, C0_BADVADDR);
674 UASM_i_MFC0(&p, K1, C0_ENTRYHI);
675 uasm_i_xor(&p, K0, K0, K1);
676 UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
677 uasm_il_bnez(&p, &r, K0, label_leave);
678 /* No need for uasm_i_nop */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700679 }
680
Ralf Baechle875d43e2005-09-03 15:56:16 -0700681#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700682 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
683#else
684 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
685#endif
686
687 build_get_ptep(&p, K0, K1);
688 build_update_entries(&p, K0, K1);
689 build_tlb_write_entry(&p, &l, &r, tlb_random);
Thiemo Seufere30ec452008-01-28 20:05:38 +0000690 uasm_l_leave(&l, p);
691 uasm_i_eret(&p); /* return from trap */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700692
Ralf Baechle875d43e2005-09-03 15:56:16 -0700693#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700694 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1);
695#endif
696
697 /*
698 * Overflow check: For the 64bit handler, we need at least one
699 * free instruction slot for the wrap-around branch. In worst
700 * case, if the intended insertion point is a delay slot, we
Matt LaPlante4b3f6862006-10-03 22:21:02 +0200701 * need three, with the second nop'ed and the third being
Linus Torvalds1da177e2005-04-16 15:20:36 -0700702 * unused.
703 */
Fuxin Zhang2a21c732007-06-06 14:52:43 +0800704 /* Loongson2 ebase is different than r4k, we have more space */
705#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700706 if ((p - tlb_handler) > 64)
707 panic("TLB refill handler space exceeded");
708#else
709 if (((p - tlb_handler) > 63)
710 || (((p - tlb_handler) > 61)
Thiemo Seufere30ec452008-01-28 20:05:38 +0000711 && uasm_insn_has_bdelay(relocs, tlb_handler + 29)))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700712 panic("TLB refill handler space exceeded");
713#endif
714
715 /*
716 * Now fold the handler in the TLB refill handler space.
717 */
Fuxin Zhang2a21c732007-06-06 14:52:43 +0800718#if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700719 f = final_handler;
720 /* Simplest case, just copy the handler. */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000721 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700722 final_len = p - tlb_handler;
Ralf Baechle875d43e2005-09-03 15:56:16 -0700723#else /* CONFIG_64BIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700724 f = final_handler + 32;
725 if ((p - tlb_handler) <= 32) {
726 /* Just copy the handler. */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000727 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700728 final_len = p - tlb_handler;
729 } else {
730 u32 *split = tlb_handler + 30;
731
732 /*
733 * Find the split point.
734 */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000735 if (uasm_insn_has_bdelay(relocs, split - 1))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700736 split--;
737
738 /* Copy first part of the handler. */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000739 uasm_copy_handler(relocs, labels, tlb_handler, split, f);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700740 f += split - tlb_handler;
741
742 /* Insert branch. */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000743 uasm_l_split(&l, final_handler);
744 uasm_il_b(&f, &r, label_split);
745 if (uasm_insn_has_bdelay(relocs, split))
746 uasm_i_nop(&f);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700747 else {
Thiemo Seufere30ec452008-01-28 20:05:38 +0000748 uasm_copy_handler(relocs, labels, split, split + 1, f);
749 uasm_move_labels(labels, f, f + 1, -1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700750 f++;
751 split++;
752 }
753
754 /* Copy the rest of the handler. */
Thiemo Seufere30ec452008-01-28 20:05:38 +0000755 uasm_copy_handler(relocs, labels, split, p, final_handler);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700756 final_len = (f - (final_handler + 32)) + (p - split);
757 }
Ralf Baechle875d43e2005-09-03 15:56:16 -0700758#endif /* CONFIG_64BIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700759
Thiemo Seufere30ec452008-01-28 20:05:38 +0000760 uasm_resolve_relocs(relocs, labels);
761 pr_debug("Wrote TLB refill handler (%u instructions).\n",
762 final_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700763
Ralf Baechle91b05e62006-03-29 18:53:00 +0100764 memcpy((void *)ebase, final_handler, 0x100);
Franck Bui-Huu92b1e6a2007-10-18 09:11:17 +0200765
766 dump_handler((u32 *)ebase, 64);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700767}
768
769/*
770 * TLB load/store/modify handlers.
771 *
772 * Only the fastpath gets synthesized at runtime, the slowpath for
773 * do_page_fault remains normal asm.
774 */
775extern void tlb_do_page_fault_0(void);
776extern void tlb_do_page_fault_1(void);
777
Linus Torvalds1da177e2005-04-16 15:20:36 -0700778/*
779 * 128 instructions for the fastpath handler is generous and should
780 * never be exceeded.
781 */
782#define FASTPATH_SIZE 128
783
Franck Bui-Huucbdbe072007-10-18 09:11:16 +0200784u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned;
785u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned;
786u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700787
Ralf Baechle234fcd12008-03-08 09:56:28 +0000788static void __cpuinit
Thiemo Seufere30ec452008-01-28 20:05:38 +0000789iPTE_LW(u32 **p, struct uasm_label **l, unsigned int pte, unsigned int ptr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700790{
791#ifdef CONFIG_SMP
792# ifdef CONFIG_64BIT_PHYS_ADDR
793 if (cpu_has_64bits)
Thiemo Seufere30ec452008-01-28 20:05:38 +0000794 uasm_i_lld(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700795 else
796# endif
Thiemo Seufere30ec452008-01-28 20:05:38 +0000797 UASM_i_LL(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798#else
799# ifdef CONFIG_64BIT_PHYS_ADDR
800 if (cpu_has_64bits)
Thiemo Seufere30ec452008-01-28 20:05:38 +0000801 uasm_i_ld(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700802 else
803# endif
Thiemo Seufere30ec452008-01-28 20:05:38 +0000804 UASM_i_LW(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700805#endif
806}
807
Ralf Baechle234fcd12008-03-08 09:56:28 +0000808static void __cpuinit
Thiemo Seufere30ec452008-01-28 20:05:38 +0000809iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +0000810 unsigned int mode)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700811{
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +0000812#ifdef CONFIG_64BIT_PHYS_ADDR
813 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
814#endif
815
Thiemo Seufere30ec452008-01-28 20:05:38 +0000816 uasm_i_ori(p, pte, pte, mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700817#ifdef CONFIG_SMP
818# ifdef CONFIG_64BIT_PHYS_ADDR
819 if (cpu_has_64bits)
Thiemo Seufere30ec452008-01-28 20:05:38 +0000820 uasm_i_scd(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700821 else
822# endif
Thiemo Seufere30ec452008-01-28 20:05:38 +0000823 UASM_i_SC(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700824
825 if (r10000_llsc_war())
Thiemo Seufere30ec452008-01-28 20:05:38 +0000826 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700827 else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000828 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700829
830# ifdef CONFIG_64BIT_PHYS_ADDR
831 if (!cpu_has_64bits) {
Thiemo Seufere30ec452008-01-28 20:05:38 +0000832 /* no uasm_i_nop needed */
833 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr);
834 uasm_i_ori(p, pte, pte, hwmode);
835 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr);
836 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
837 /* no uasm_i_nop needed */
838 uasm_i_lw(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700839 } else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000840 uasm_i_nop(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700841# else
Thiemo Seufere30ec452008-01-28 20:05:38 +0000842 uasm_i_nop(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700843# endif
844#else
845# ifdef CONFIG_64BIT_PHYS_ADDR
846 if (cpu_has_64bits)
Thiemo Seufere30ec452008-01-28 20:05:38 +0000847 uasm_i_sd(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700848 else
849# endif
Thiemo Seufere30ec452008-01-28 20:05:38 +0000850 UASM_i_SW(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700851
852# ifdef CONFIG_64BIT_PHYS_ADDR
853 if (!cpu_has_64bits) {
Thiemo Seufere30ec452008-01-28 20:05:38 +0000854 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr);
855 uasm_i_ori(p, pte, pte, hwmode);
856 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr);
857 uasm_i_lw(p, pte, 0, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700858 }
859# endif
860#endif
861}
862
863/*
864 * Check if PTE is present, if not then jump to LABEL. PTR points to
865 * the page table where this PTE is located, PTE will be re-loaded
866 * with it's original value.
867 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000868static void __cpuinit
Thiemo Seufere30ec452008-01-28 20:05:38 +0000869build_pte_present(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700870 unsigned int pte, unsigned int ptr, enum label_id lid)
871{
Thiemo Seufere30ec452008-01-28 20:05:38 +0000872 uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
873 uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
874 uasm_il_bnez(p, r, pte, lid);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +0000875 iPTE_LW(p, l, pte, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876}
877
878/* Make PTE valid, store result in PTR. */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000879static void __cpuinit
Thiemo Seufere30ec452008-01-28 20:05:38 +0000880build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700881 unsigned int ptr)
882{
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +0000883 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
884
885 iPTE_SW(p, r, pte, ptr, mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700886}
887
888/*
889 * Check if PTE can be written to, if not branch to LABEL. Regardless
890 * restore PTE with value from PTR when done.
891 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000892static void __cpuinit
Thiemo Seufere30ec452008-01-28 20:05:38 +0000893build_pte_writable(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700894 unsigned int pte, unsigned int ptr, enum label_id lid)
895{
Thiemo Seufere30ec452008-01-28 20:05:38 +0000896 uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
897 uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
898 uasm_il_bnez(p, r, pte, lid);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +0000899 iPTE_LW(p, l, pte, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700900}
901
902/* Make PTE writable, update software status bits as well, then store
903 * at PTR.
904 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000905static void __cpuinit
Thiemo Seufere30ec452008-01-28 20:05:38 +0000906build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700907 unsigned int ptr)
908{
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +0000909 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
910 | _PAGE_DIRTY);
911
912 iPTE_SW(p, r, pte, ptr, mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700913}
914
915/*
916 * Check if PTE can be modified, if not branch to LABEL. Regardless
917 * restore PTE with value from PTR when done.
918 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000919static void __cpuinit
Thiemo Seufere30ec452008-01-28 20:05:38 +0000920build_pte_modifiable(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700921 unsigned int pte, unsigned int ptr, enum label_id lid)
922{
Thiemo Seufere30ec452008-01-28 20:05:38 +0000923 uasm_i_andi(p, pte, pte, _PAGE_WRITE);
924 uasm_il_beqz(p, r, pte, lid);
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +0000925 iPTE_LW(p, l, pte, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700926}
927
928/*
929 * R3000 style TLB load/store/modify handlers.
930 */
931
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +0000932/*
933 * This places the pte into ENTRYLO0 and writes it with tlbwi.
934 * Then it returns.
935 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000936static void __cpuinit
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +0000937build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700938{
Thiemo Seufere30ec452008-01-28 20:05:38 +0000939 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
940 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
941 uasm_i_tlbwi(p);
942 uasm_i_jr(p, tmp);
943 uasm_i_rfe(p); /* branch delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700944}
945
946/*
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +0000947 * This places the pte into ENTRYLO0 and writes it with tlbwi
948 * or tlbwr as appropriate. This is because the index register
949 * may have the probe fail bit set as a result of a trap on a
950 * kseg2 access, i.e. without refill. Then it returns.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700951 */
Ralf Baechle234fcd12008-03-08 09:56:28 +0000952static void __cpuinit
Thiemo Seufere30ec452008-01-28 20:05:38 +0000953build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l,
954 struct uasm_reloc **r, unsigned int pte,
955 unsigned int tmp)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700956{
Thiemo Seufere30ec452008-01-28 20:05:38 +0000957 uasm_i_mfc0(p, tmp, C0_INDEX);
958 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
959 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
960 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */
961 uasm_i_tlbwi(p); /* cp0 delay */
962 uasm_i_jr(p, tmp);
963 uasm_i_rfe(p); /* branch delay */
964 uasm_l_r3000_write_probe_fail(l, *p);
965 uasm_i_tlbwr(p); /* cp0 delay */
966 uasm_i_jr(p, tmp);
967 uasm_i_rfe(p); /* branch delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700968}
969
Ralf Baechle234fcd12008-03-08 09:56:28 +0000970static void __cpuinit
Linus Torvalds1da177e2005-04-16 15:20:36 -0700971build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
972 unsigned int ptr)
973{
974 long pgdc = (long)pgd_current;
975
Thiemo Seufere30ec452008-01-28 20:05:38 +0000976 uasm_i_mfc0(p, pte, C0_BADVADDR);
977 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */
978 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
979 uasm_i_srl(p, pte, pte, 22); /* load delay */
980 uasm_i_sll(p, pte, pte, 2);
981 uasm_i_addu(p, ptr, ptr, pte);
982 uasm_i_mfc0(p, pte, C0_CONTEXT);
983 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */
984 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */
985 uasm_i_addu(p, ptr, ptr, pte);
986 uasm_i_lw(p, pte, 0, ptr);
987 uasm_i_tlbp(p); /* load delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700988}
989
Ralf Baechle234fcd12008-03-08 09:56:28 +0000990static void __cpuinit build_r3000_tlb_load_handler(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700991{
992 u32 *p = handle_tlbl;
Thiemo Seufere30ec452008-01-28 20:05:38 +0000993 struct uasm_label *l = labels;
994 struct uasm_reloc *r = relocs;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700995
996 memset(handle_tlbl, 0, sizeof(handle_tlbl));
997 memset(labels, 0, sizeof(labels));
998 memset(relocs, 0, sizeof(relocs));
999
1000 build_r3000_tlbchange_handler_head(&p, K0, K1);
1001 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl);
Thiemo Seufere30ec452008-01-28 20:05:38 +00001002 uasm_i_nop(&p); /* load delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001003 build_make_valid(&p, &r, K0, K1);
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001004 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001005
Thiemo Seufere30ec452008-01-28 20:05:38 +00001006 uasm_l_nopage_tlbl(&l, p);
1007 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1008 uasm_i_nop(&p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001009
1010 if ((p - handle_tlbl) > FASTPATH_SIZE)
1011 panic("TLB load handler fastpath space exceeded");
1012
Thiemo Seufere30ec452008-01-28 20:05:38 +00001013 uasm_resolve_relocs(relocs, labels);
1014 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1015 (unsigned int)(p - handle_tlbl));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001016
Franck Bui-Huu92b1e6a2007-10-18 09:11:17 +02001017 dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001018}
1019
Ralf Baechle234fcd12008-03-08 09:56:28 +00001020static void __cpuinit build_r3000_tlb_store_handler(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001021{
1022 u32 *p = handle_tlbs;
Thiemo Seufere30ec452008-01-28 20:05:38 +00001023 struct uasm_label *l = labels;
1024 struct uasm_reloc *r = relocs;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001025
1026 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1027 memset(labels, 0, sizeof(labels));
1028 memset(relocs, 0, sizeof(relocs));
1029
1030 build_r3000_tlbchange_handler_head(&p, K0, K1);
1031 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs);
Thiemo Seufere30ec452008-01-28 20:05:38 +00001032 uasm_i_nop(&p); /* load delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001033 build_make_write(&p, &r, K0, K1);
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001034 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001035
Thiemo Seufere30ec452008-01-28 20:05:38 +00001036 uasm_l_nopage_tlbs(&l, p);
1037 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1038 uasm_i_nop(&p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001039
1040 if ((p - handle_tlbs) > FASTPATH_SIZE)
1041 panic("TLB store handler fastpath space exceeded");
1042
Thiemo Seufere30ec452008-01-28 20:05:38 +00001043 uasm_resolve_relocs(relocs, labels);
1044 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1045 (unsigned int)(p - handle_tlbs));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001046
Franck Bui-Huu92b1e6a2007-10-18 09:11:17 +02001047 dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001048}
1049
Ralf Baechle234fcd12008-03-08 09:56:28 +00001050static void __cpuinit build_r3000_tlb_modify_handler(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001051{
1052 u32 *p = handle_tlbm;
Thiemo Seufere30ec452008-01-28 20:05:38 +00001053 struct uasm_label *l = labels;
1054 struct uasm_reloc *r = relocs;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001055
1056 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1057 memset(labels, 0, sizeof(labels));
1058 memset(relocs, 0, sizeof(relocs));
1059
1060 build_r3000_tlbchange_handler_head(&p, K0, K1);
1061 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm);
Thiemo Seufere30ec452008-01-28 20:05:38 +00001062 uasm_i_nop(&p); /* load delay */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001063 build_make_write(&p, &r, K0, K1);
Maciej W. Rozyckifded2e52005-06-13 20:24:00 +00001064 build_r3000_pte_reload_tlbwi(&p, K0, K1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001065
Thiemo Seufere30ec452008-01-28 20:05:38 +00001066 uasm_l_nopage_tlbm(&l, p);
1067 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1068 uasm_i_nop(&p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001069
1070 if ((p - handle_tlbm) > FASTPATH_SIZE)
1071 panic("TLB modify handler fastpath space exceeded");
1072
Thiemo Seufere30ec452008-01-28 20:05:38 +00001073 uasm_resolve_relocs(relocs, labels);
1074 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
1075 (unsigned int)(p - handle_tlbm));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001076
Franck Bui-Huu92b1e6a2007-10-18 09:11:17 +02001077 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001078}
1079
1080/*
1081 * R4000 style TLB load/store/modify handlers.
1082 */
Ralf Baechle234fcd12008-03-08 09:56:28 +00001083static void __cpuinit
Thiemo Seufere30ec452008-01-28 20:05:38 +00001084build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
1085 struct uasm_reloc **r, unsigned int pte,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001086 unsigned int ptr)
1087{
Ralf Baechle875d43e2005-09-03 15:56:16 -07001088#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001089 build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
1090#else
1091 build_get_pgde32(p, pte, ptr); /* get pgd in ptr */
1092#endif
1093
Thiemo Seufere30ec452008-01-28 20:05:38 +00001094 UASM_i_MFC0(p, pte, C0_BADVADDR);
1095 UASM_i_LW(p, ptr, 0, ptr);
1096 UASM_i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
1097 uasm_i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
1098 UASM_i_ADDU(p, ptr, ptr, pte);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001099
1100#ifdef CONFIG_SMP
Thiemo Seufere30ec452008-01-28 20:05:38 +00001101 uasm_l_smp_pgtable_change(l, *p);
1102#endif
Thiemo Seufer63b2d2f2005-04-28 08:52:57 +00001103 iPTE_LW(p, l, pte, ptr); /* get even pte */
Maciej W. Rozycki8df5bea2006-08-23 14:26:50 +01001104 if (!m4kc_tlbp_war())
1105 build_tlb_probe_entry(p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001106}
1107
Ralf Baechle234fcd12008-03-08 09:56:28 +00001108static void __cpuinit
Thiemo Seufere30ec452008-01-28 20:05:38 +00001109build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
1110 struct uasm_reloc **r, unsigned int tmp,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001111 unsigned int ptr)
1112{
Thiemo Seufere30ec452008-01-28 20:05:38 +00001113 uasm_i_ori(p, ptr, ptr, sizeof(pte_t));
1114 uasm_i_xori(p, ptr, ptr, sizeof(pte_t));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001115 build_update_entries(p, tmp, ptr);
1116 build_tlb_write_entry(p, l, r, tlb_indexed);
Thiemo Seufere30ec452008-01-28 20:05:38 +00001117 uasm_l_leave(l, *p);
1118 uasm_i_eret(p); /* return from trap */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001119
Ralf Baechle875d43e2005-09-03 15:56:16 -07001120#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001121 build_get_pgd_vmalloc64(p, l, r, tmp, ptr);
1122#endif
1123}
1124
Ralf Baechle234fcd12008-03-08 09:56:28 +00001125static void __cpuinit build_r4000_tlb_load_handler(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001126{
1127 u32 *p = handle_tlbl;
Thiemo Seufere30ec452008-01-28 20:05:38 +00001128 struct uasm_label *l = labels;
1129 struct uasm_reloc *r = relocs;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001130
1131 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1132 memset(labels, 0, sizeof(labels));
1133 memset(relocs, 0, sizeof(relocs));
1134
1135 if (bcm1250_m3_war()) {
Thiemo Seufere30ec452008-01-28 20:05:38 +00001136 UASM_i_MFC0(&p, K0, C0_BADVADDR);
1137 UASM_i_MFC0(&p, K1, C0_ENTRYHI);
1138 uasm_i_xor(&p, K0, K0, K1);
1139 UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
1140 uasm_il_bnez(&p, &r, K0, label_leave);
1141 /* No need for uasm_i_nop */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001142 }
1143
1144 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1145 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl);
Maciej W. Rozycki8df5bea2006-08-23 14:26:50 +01001146 if (m4kc_tlbp_war())
1147 build_tlb_probe_entry(&p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001148 build_make_valid(&p, &r, K0, K1);
1149 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1150
Thiemo Seufere30ec452008-01-28 20:05:38 +00001151 uasm_l_nopage_tlbl(&l, p);
1152 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1153 uasm_i_nop(&p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001154
1155 if ((p - handle_tlbl) > FASTPATH_SIZE)
1156 panic("TLB load handler fastpath space exceeded");
1157
Thiemo Seufere30ec452008-01-28 20:05:38 +00001158 uasm_resolve_relocs(relocs, labels);
1159 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1160 (unsigned int)(p - handle_tlbl));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001161
Franck Bui-Huu92b1e6a2007-10-18 09:11:17 +02001162 dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001163}
1164
Ralf Baechle234fcd12008-03-08 09:56:28 +00001165static void __cpuinit build_r4000_tlb_store_handler(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001166{
1167 u32 *p = handle_tlbs;
Thiemo Seufere30ec452008-01-28 20:05:38 +00001168 struct uasm_label *l = labels;
1169 struct uasm_reloc *r = relocs;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001170
1171 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1172 memset(labels, 0, sizeof(labels));
1173 memset(relocs, 0, sizeof(relocs));
1174
1175 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1176 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs);
Maciej W. Rozycki8df5bea2006-08-23 14:26:50 +01001177 if (m4kc_tlbp_war())
1178 build_tlb_probe_entry(&p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001179 build_make_write(&p, &r, K0, K1);
1180 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1181
Thiemo Seufere30ec452008-01-28 20:05:38 +00001182 uasm_l_nopage_tlbs(&l, p);
1183 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1184 uasm_i_nop(&p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001185
1186 if ((p - handle_tlbs) > FASTPATH_SIZE)
1187 panic("TLB store handler fastpath space exceeded");
1188
Thiemo Seufere30ec452008-01-28 20:05:38 +00001189 uasm_resolve_relocs(relocs, labels);
1190 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1191 (unsigned int)(p - handle_tlbs));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001192
Franck Bui-Huu92b1e6a2007-10-18 09:11:17 +02001193 dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001194}
1195
Ralf Baechle234fcd12008-03-08 09:56:28 +00001196static void __cpuinit build_r4000_tlb_modify_handler(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001197{
1198 u32 *p = handle_tlbm;
Thiemo Seufere30ec452008-01-28 20:05:38 +00001199 struct uasm_label *l = labels;
1200 struct uasm_reloc *r = relocs;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001201
1202 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1203 memset(labels, 0, sizeof(labels));
1204 memset(relocs, 0, sizeof(relocs));
1205
1206 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1207 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm);
Maciej W. Rozycki8df5bea2006-08-23 14:26:50 +01001208 if (m4kc_tlbp_war())
1209 build_tlb_probe_entry(&p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001210 /* Present and writable bits set, set accessed and dirty bits. */
1211 build_make_write(&p, &r, K0, K1);
1212 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1213
Thiemo Seufere30ec452008-01-28 20:05:38 +00001214 uasm_l_nopage_tlbm(&l, p);
1215 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1216 uasm_i_nop(&p);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001217
1218 if ((p - handle_tlbm) > FASTPATH_SIZE)
1219 panic("TLB modify handler fastpath space exceeded");
1220
Thiemo Seufere30ec452008-01-28 20:05:38 +00001221 uasm_resolve_relocs(relocs, labels);
1222 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
1223 (unsigned int)(p - handle_tlbm));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001224
Franck Bui-Huu92b1e6a2007-10-18 09:11:17 +02001225 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001226}
1227
Ralf Baechle234fcd12008-03-08 09:56:28 +00001228void __cpuinit build_tlb_refill_handler(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001229{
1230 /*
1231 * The refill handler is generated per-CPU, multi-node systems
1232 * may have local storage for it. The other handlers are only
1233 * needed once.
1234 */
1235 static int run_once = 0;
1236
Ralf Baechle10cc3522007-10-11 23:46:15 +01001237 switch (current_cpu_type()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001238 case CPU_R2000:
1239 case CPU_R3000:
1240 case CPU_R3000A:
1241 case CPU_R3081E:
1242 case CPU_TX3912:
1243 case CPU_TX3922:
1244 case CPU_TX3927:
1245 build_r3000_tlb_refill_handler();
1246 if (!run_once) {
1247 build_r3000_tlb_load_handler();
1248 build_r3000_tlb_store_handler();
1249 build_r3000_tlb_modify_handler();
1250 run_once++;
1251 }
1252 break;
1253
1254 case CPU_R6000:
1255 case CPU_R6000A:
1256 panic("No R6000 TLB refill handler yet");
1257 break;
1258
1259 case CPU_R8000:
1260 panic("No R8000 TLB refill handler yet");
1261 break;
1262
1263 default:
1264 build_r4000_tlb_refill_handler();
1265 if (!run_once) {
1266 build_r4000_tlb_load_handler();
1267 build_r4000_tlb_store_handler();
1268 build_r4000_tlb_modify_handler();
1269 run_once++;
1270 }
1271 }
1272}
Ralf Baechle1d40cfc2005-07-15 15:23:23 +00001273
Ralf Baechle234fcd12008-03-08 09:56:28 +00001274void __cpuinit flush_tlb_handlers(void)
Ralf Baechle1d40cfc2005-07-15 15:23:23 +00001275{
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +02001276 local_flush_icache_range((unsigned long)handle_tlbl,
Ralf Baechle1d40cfc2005-07-15 15:23:23 +00001277 (unsigned long)handle_tlbl + sizeof(handle_tlbl));
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +02001278 local_flush_icache_range((unsigned long)handle_tlbs,
Ralf Baechle1d40cfc2005-07-15 15:23:23 +00001279 (unsigned long)handle_tlbs + sizeof(handle_tlbs));
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +02001280 local_flush_icache_range((unsigned long)handle_tlbm,
Ralf Baechle1d40cfc2005-07-15 15:23:23 +00001281 (unsigned long)handle_tlbm + sizeof(handle_tlbm));
1282}