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Mika Westerbergd16a5aa2014-03-20 22:04:23 +08001/*
2 * Intel Low Power Subsystem PWM controller driver
3 *
4 * Copyright (C) 2014, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
6 * Author: Chew Kean Ho <kean.ho.chew@intel.com>
7 * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
8 * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
Alan Cox093e00b2014-04-18 19:17:40 +08009 * Author: Alan Cox <alan@linux.intel.com>
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080010 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
Mika Westerberg37670672015-11-18 13:25:18 +020016#include <linux/delay.h>
Thierry Redinge0c86a32014-08-23 00:22:45 +020017#include <linux/io.h>
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080018#include <linux/kernel.h>
19#include <linux/module.h>
Qipeng Zhaf080be22015-10-26 12:58:27 +020020#include <linux/pm_runtime.h>
qipeng.zha883e4d02015-11-17 17:20:15 +080021#include <linux/time.h>
Alan Cox093e00b2014-04-18 19:17:40 +080022
Andy Shevchenkoc558e392014-08-19 19:17:35 +030023#include "pwm-lpss.h"
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080024
25#define PWM 0x00000000
26#define PWM_ENABLE BIT(31)
27#define PWM_SW_UPDATE BIT(30)
28#define PWM_BASE_UNIT_SHIFT 8
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080029#define PWM_ON_TIME_DIV_MASK 0x000000ff
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080030
Mika Westerberg4e11f5a2015-10-20 16:53:05 +030031/* Size of each PWM register space if multiple */
32#define PWM_SIZE 0x400
33
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080034struct pwm_lpss_chip {
35 struct pwm_chip chip;
36 void __iomem *regs;
qipeng.zha883e4d02015-11-17 17:20:15 +080037 const struct pwm_lpss_boardinfo *info;
Alan Cox093e00b2014-04-18 19:17:40 +080038};
39
Alan Cox093e00b2014-04-18 19:17:40 +080040/* BayTrail */
Andy Shevchenkoc558e392014-08-19 19:17:35 +030041const struct pwm_lpss_boardinfo pwm_lpss_byt_info = {
Mika Westerberg4e11f5a2015-10-20 16:53:05 +030042 .clk_rate = 25000000,
43 .npwm = 1,
qipeng.zha883e4d02015-11-17 17:20:15 +080044 .base_unit_bits = 16,
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080045};
Andy Shevchenkoc558e392014-08-19 19:17:35 +030046EXPORT_SYMBOL_GPL(pwm_lpss_byt_info);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080047
Alan Cox373c5782014-08-19 17:18:29 +030048/* Braswell */
Andy Shevchenkoc558e392014-08-19 19:17:35 +030049const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = {
Mika Westerberg4e11f5a2015-10-20 16:53:05 +030050 .clk_rate = 19200000,
51 .npwm = 1,
qipeng.zha883e4d02015-11-17 17:20:15 +080052 .base_unit_bits = 16,
Alan Cox373c5782014-08-19 17:18:29 +030053};
Andy Shevchenkoc558e392014-08-19 19:17:35 +030054EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info);
Alan Cox373c5782014-08-19 17:18:29 +030055
Mika Westerberg87219cb2015-10-20 16:53:06 +030056/* Broxton */
57const struct pwm_lpss_boardinfo pwm_lpss_bxt_info = {
58 .clk_rate = 19200000,
59 .npwm = 4,
qipeng.zha883e4d02015-11-17 17:20:15 +080060 .base_unit_bits = 22,
Mika Westerberg87219cb2015-10-20 16:53:06 +030061};
62EXPORT_SYMBOL_GPL(pwm_lpss_bxt_info);
63
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080064static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
65{
66 return container_of(chip, struct pwm_lpss_chip, chip);
67}
68
Mika Westerberg4e11f5a2015-10-20 16:53:05 +030069static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
70{
71 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
72
73 return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
74}
75
76static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
77{
78 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
79
80 writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
81}
82
Mika Westerberg37670672015-11-18 13:25:18 +020083static void pwm_lpss_update(struct pwm_device *pwm)
84{
85 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_SW_UPDATE);
86 /* Give it some time to propagate */
87 usleep_range(10, 50);
88}
89
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080090static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm,
91 int duty_ns, int period_ns)
92{
93 struct pwm_lpss_chip *lpwm = to_lpwm(chip);
94 u8 on_time_div;
qipeng.zha883e4d02015-11-17 17:20:15 +080095 unsigned long c, base_unit_range;
96 unsigned long long base_unit, freq = NSEC_PER_SEC;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +080097 u32 ctrl;
98
99 do_div(freq, period_ns);
100
qipeng.zha883e4d02015-11-17 17:20:15 +0800101 /*
102 * The equation is:
Dan O'Donovane5ca4242016-06-01 15:31:12 +0100103 * base_unit = round(base_unit_range * freq / c)
qipeng.zha883e4d02015-11-17 17:20:15 +0800104 */
105 base_unit_range = BIT(lpwm->info->base_unit_bits);
Dan O'Donovane5ca4242016-06-01 15:31:12 +0100106 freq *= base_unit_range;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800107
qipeng.zha883e4d02015-11-17 17:20:15 +0800108 c = lpwm->info->clk_rate;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800109 if (!c)
110 return -EINVAL;
111
Dan O'Donovane5ca4242016-06-01 15:31:12 +0100112 base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800113
114 if (duty_ns <= 0)
115 duty_ns = 1;
116 on_time_div = 255 - (255 * duty_ns / period_ns);
117
Qipeng Zhaf080be22015-10-26 12:58:27 +0200118 pm_runtime_get_sync(chip->dev);
119
Mika Westerberg4e11f5a2015-10-20 16:53:05 +0300120 ctrl = pwm_lpss_read(pwm);
qipeng.zha883e4d02015-11-17 17:20:15 +0800121 ctrl &= ~PWM_ON_TIME_DIV_MASK;
122 ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT);
123 base_unit &= (base_unit_range - 1);
124 ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800125 ctrl |= on_time_div;
Mika Westerberg4e11f5a2015-10-20 16:53:05 +0300126 pwm_lpss_write(pwm, ctrl);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800127
Mika Westerberg37670672015-11-18 13:25:18 +0200128 /*
129 * If the PWM is already enabled we need to notify the hardware
130 * about the change by setting PWM_SW_UPDATE.
131 */
132 if (pwm_is_enabled(pwm))
133 pwm_lpss_update(pwm);
134
Qipeng Zhaf080be22015-10-26 12:58:27 +0200135 pm_runtime_put(chip->dev);
136
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800137 return 0;
138}
139
140static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm)
141{
Qipeng Zhaf080be22015-10-26 12:58:27 +0200142 pm_runtime_get_sync(chip->dev);
Mika Westerberg37670672015-11-18 13:25:18 +0200143
144 /*
145 * Hardware must first see PWM_SW_UPDATE before the PWM can be
146 * enabled.
147 */
148 pwm_lpss_update(pwm);
Mika Westerberg4e11f5a2015-10-20 16:53:05 +0300149 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800150 return 0;
151}
152
153static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm)
154{
Mika Westerberg4e11f5a2015-10-20 16:53:05 +0300155 pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
Qipeng Zhaf080be22015-10-26 12:58:27 +0200156 pm_runtime_put(chip->dev);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800157}
158
159static const struct pwm_ops pwm_lpss_ops = {
160 .config = pwm_lpss_config,
161 .enable = pwm_lpss_enable,
162 .disable = pwm_lpss_disable,
163 .owner = THIS_MODULE,
164};
165
Andy Shevchenkoc558e392014-08-19 19:17:35 +0300166struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
167 const struct pwm_lpss_boardinfo *info)
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800168{
169 struct pwm_lpss_chip *lpwm;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800170 int ret;
171
Alan Cox093e00b2014-04-18 19:17:40 +0800172 lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800173 if (!lpwm)
Alan Cox093e00b2014-04-18 19:17:40 +0800174 return ERR_PTR(-ENOMEM);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800175
Alan Cox093e00b2014-04-18 19:17:40 +0800176 lpwm->regs = devm_ioremap_resource(dev, r);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800177 if (IS_ERR(lpwm->regs))
Thierry Reding89c03392014-05-07 10:27:57 +0200178 return ERR_CAST(lpwm->regs);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800179
qipeng.zha883e4d02015-11-17 17:20:15 +0800180 lpwm->info = info;
Alan Cox093e00b2014-04-18 19:17:40 +0800181 lpwm->chip.dev = dev;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800182 lpwm->chip.ops = &pwm_lpss_ops;
183 lpwm->chip.base = -1;
Mika Westerberg4e11f5a2015-10-20 16:53:05 +0300184 lpwm->chip.npwm = info->npwm;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800185
186 ret = pwmchip_add(&lpwm->chip);
187 if (ret) {
Alan Cox093e00b2014-04-18 19:17:40 +0800188 dev_err(dev, "failed to add PWM chip: %d\n", ret);
189 return ERR_PTR(ret);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800190 }
191
Alan Cox093e00b2014-04-18 19:17:40 +0800192 return lpwm;
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800193}
Andy Shevchenkoc558e392014-08-19 19:17:35 +0300194EXPORT_SYMBOL_GPL(pwm_lpss_probe);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800195
Andy Shevchenkoc558e392014-08-19 19:17:35 +0300196int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800197{
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800198 return pwmchip_remove(&lpwm->chip);
199}
Andy Shevchenkoc558e392014-08-19 19:17:35 +0300200EXPORT_SYMBOL_GPL(pwm_lpss_remove);
Mika Westerbergd16a5aa2014-03-20 22:04:23 +0800201
202MODULE_DESCRIPTION("PWM driver for Intel LPSS");
203MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
204MODULE_LICENSE("GPL v2");