Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> |
| 3 | * Copyright (c) 2007-2008 Intel Corporation |
| 4 | * Jesse Barnes <jesse.barnes@intel.com> |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the next |
| 14 | * paragraph) shall be included in all copies or substantial portions of the |
| 15 | * Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 23 | * IN THE SOFTWARE. |
| 24 | */ |
| 25 | #ifndef __INTEL_DRV_H__ |
| 26 | #define __INTEL_DRV_H__ |
| 27 | |
| 28 | #include <linux/i2c.h> |
Jesse Barnes | 8ea3086 | 2012-01-03 08:05:39 -0800 | [diff] [blame] | 29 | #include "i915_drm.h" |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 30 | #include "i915_drv.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 31 | #include "drm_crtc.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 32 | #include "drm_crtc_helper.h" |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 33 | #include "drm_fb_helper.h" |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 34 | #include "drm_dp_helper.h" |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 35 | |
Chris Wilson | 481b6af | 2010-08-23 17:43:35 +0100 | [diff] [blame] | 36 | #define _wait_for(COND, MS, W) ({ \ |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 37 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \ |
| 38 | int ret__ = 0; \ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 39 | while (!(COND)) { \ |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 40 | if (time_after(jiffies, timeout__)) { \ |
| 41 | ret__ = -ETIMEDOUT; \ |
| 42 | break; \ |
| 43 | } \ |
Dave Airlie | cc1f719 | 2012-01-05 09:55:22 +0000 | [diff] [blame] | 44 | if (W && drm_can_sleep()) msleep(W); \ |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 45 | } \ |
| 46 | ret__; \ |
| 47 | }) |
| 48 | |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 49 | #define wait_for_atomic_us(COND, US) ({ \ |
| 50 | int i, ret__ = -ETIMEDOUT; \ |
| 51 | for (i = 0; i < (US); i++) { \ |
| 52 | if ((COND)) { \ |
| 53 | ret__ = 0; \ |
| 54 | break; \ |
| 55 | } \ |
| 56 | udelay(1); \ |
| 57 | } \ |
| 58 | ret__; \ |
| 59 | }) |
| 60 | |
Chris Wilson | 481b6af | 2010-08-23 17:43:35 +0100 | [diff] [blame] | 61 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
| 62 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) |
| 63 | |
Chris Wilson | 021357a | 2010-09-07 20:54:59 +0100 | [diff] [blame] | 64 | #define KHz(x) (1000*x) |
| 65 | #define MHz(x) KHz(1000*x) |
| 66 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 67 | /* |
| 68 | * Display related stuff |
| 69 | */ |
| 70 | |
| 71 | /* store information about an Ixxx DVO */ |
| 72 | /* The i830->i865 use multiple DVOs with multiple i2cs */ |
| 73 | /* the i915, i945 have a single sDVO i2c bus - which is different */ |
| 74 | #define MAX_OUTPUTS 6 |
| 75 | /* maximum connectors per crtcs in the mode set */ |
| 76 | #define INTELFB_CONN_LIMIT 4 |
| 77 | |
| 78 | #define INTEL_I2C_BUS_DVO 1 |
| 79 | #define INTEL_I2C_BUS_SDVO 2 |
| 80 | |
| 81 | /* these are outputs from the chip - integrated only |
| 82 | external chips are via DVO or SDVO output */ |
| 83 | #define INTEL_OUTPUT_UNUSED 0 |
| 84 | #define INTEL_OUTPUT_ANALOG 1 |
| 85 | #define INTEL_OUTPUT_DVO 2 |
| 86 | #define INTEL_OUTPUT_SDVO 3 |
| 87 | #define INTEL_OUTPUT_LVDS 4 |
| 88 | #define INTEL_OUTPUT_TVOUT 5 |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 89 | #define INTEL_OUTPUT_HDMI 6 |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 90 | #define INTEL_OUTPUT_DISPLAYPORT 7 |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 91 | #define INTEL_OUTPUT_EDP 8 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 92 | |
| 93 | #define INTEL_DVO_CHIP_NONE 0 |
| 94 | #define INTEL_DVO_CHIP_LVDS 1 |
| 95 | #define INTEL_DVO_CHIP_TMDS 2 |
| 96 | #define INTEL_DVO_CHIP_TVOUT 4 |
| 97 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 98 | /* drm_display_mode->private_flags */ |
| 99 | #define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0) |
| 100 | #define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT) |
Adam Jackson | 3b5c78a | 2011-12-13 15:41:00 -0800 | [diff] [blame] | 101 | #define INTEL_MODE_DP_FORCE_6BPC (0x10) |
Daniel Vetter | f9bef08 | 2012-04-15 19:53:19 +0200 | [diff] [blame] | 102 | /* This flag must be set by the encoder's mode_fixup if it changes the crtc |
| 103 | * timings in the mode to prevent the crtc fixup from overwriting them. |
| 104 | * Currently only lvds needs that. */ |
| 105 | #define INTEL_MODE_CRTC_TIMINGS_SET (0x20) |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 106 | |
| 107 | static inline void |
| 108 | intel_mode_set_pixel_multiplier(struct drm_display_mode *mode, |
| 109 | int multiplier) |
| 110 | { |
| 111 | mode->clock *= multiplier; |
| 112 | mode->private_flags |= multiplier; |
| 113 | } |
| 114 | |
| 115 | static inline int |
| 116 | intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode) |
| 117 | { |
| 118 | return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT; |
| 119 | } |
| 120 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 121 | struct intel_framebuffer { |
| 122 | struct drm_framebuffer base; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 123 | struct drm_i915_gem_object *obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 124 | }; |
| 125 | |
Chris Wilson | 37811fc | 2010-08-25 22:45:57 +0100 | [diff] [blame] | 126 | struct intel_fbdev { |
| 127 | struct drm_fb_helper helper; |
| 128 | struct intel_framebuffer ifb; |
| 129 | struct list_head fbdev_list; |
| 130 | struct drm_display_mode *our_mode; |
| 131 | }; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 132 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 133 | struct intel_encoder { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 134 | struct drm_encoder base; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 135 | int type; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 136 | bool needs_tv_clock; |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 137 | /* |
| 138 | * Intel hw has only one MUX where encoders could be clone, hence a |
| 139 | * simple flag is enough to compute the possible_clones mask. |
| 140 | */ |
| 141 | bool cloneable; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 142 | void (*hot_plug)(struct intel_encoder *); |
Ma Ling | f8aed70 | 2009-08-24 13:50:24 +0800 | [diff] [blame] | 143 | int crtc_mask; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 144 | }; |
| 145 | |
Zhenyu Wang | 5daa55e | 2010-03-30 14:39:28 +0800 | [diff] [blame] | 146 | struct intel_connector { |
| 147 | struct drm_connector base; |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 148 | struct intel_encoder *encoder; |
Zhenyu Wang | 5daa55e | 2010-03-30 14:39:28 +0800 | [diff] [blame] | 149 | }; |
| 150 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 151 | struct intel_crtc { |
| 152 | struct drm_crtc base; |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 153 | enum pipe pipe; |
| 154 | enum plane plane; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 155 | u8 lut_r[256], lut_g[256], lut_b[256]; |
| 156 | int dpms_mode; |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 157 | bool active; /* is the crtc on? independent of the dpms mode */ |
Chris Wilson | 93314b5 | 2012-06-13 17:36:55 +0100 | [diff] [blame] | 158 | bool primary_disabled; /* is the crtc obscured by a plane? */ |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 159 | bool lowfreq_avail; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 160 | struct intel_overlay *overlay; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 161 | struct intel_unpin_work *unpin_work; |
Adam Jackson | 77ffb59 | 2010-04-12 11:38:44 -0400 | [diff] [blame] | 162 | int fdi_lanes; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 163 | |
Daniel Vetter | e506a0c | 2012-07-05 12:17:29 +0200 | [diff] [blame] | 164 | /* Display surface base address adjustement for pageflips. Note that on |
| 165 | * gen4+ this only adjusts up to a tile, offsets within a tile are |
| 166 | * handled in the hw itself (with the TILEOFF register). */ |
| 167 | unsigned long dspaddr_offset; |
| 168 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 169 | struct drm_i915_gem_object *cursor_bo; |
Chris Wilson | cda4b7d | 2010-07-09 08:45:04 +0100 | [diff] [blame] | 170 | uint32_t cursor_addr; |
| 171 | int16_t cursor_x, cursor_y; |
| 172 | int16_t cursor_width, cursor_height; |
Chris Wilson | 6b383a7 | 2010-09-13 13:54:26 +0100 | [diff] [blame] | 173 | bool cursor_visible; |
Jesse Barnes | 5a35420 | 2011-06-24 12:19:22 -0700 | [diff] [blame] | 174 | unsigned int bpp; |
Jesse Barnes | 4b645f1 | 2011-10-12 09:51:31 -0700 | [diff] [blame] | 175 | |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 176 | /* We can share PLLs across outputs if the timings match */ |
| 177 | struct intel_pch_pll *pch_pll; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 178 | }; |
| 179 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 180 | struct intel_plane { |
| 181 | struct drm_plane base; |
| 182 | enum pipe pipe; |
| 183 | struct drm_i915_gem_object *obj; |
| 184 | int max_downscale; |
| 185 | u32 lut_r[1024], lut_g[1024], lut_b[1024]; |
| 186 | void (*update_plane)(struct drm_plane *plane, |
| 187 | struct drm_framebuffer *fb, |
| 188 | struct drm_i915_gem_object *obj, |
| 189 | int crtc_x, int crtc_y, |
| 190 | unsigned int crtc_w, unsigned int crtc_h, |
| 191 | uint32_t x, uint32_t y, |
| 192 | uint32_t src_w, uint32_t src_h); |
| 193 | void (*disable_plane)(struct drm_plane *plane); |
Jesse Barnes | 8ea3086 | 2012-01-03 08:05:39 -0800 | [diff] [blame] | 194 | int (*update_colorkey)(struct drm_plane *plane, |
| 195 | struct drm_intel_sprite_colorkey *key); |
| 196 | void (*get_colorkey)(struct drm_plane *plane, |
| 197 | struct drm_intel_sprite_colorkey *key); |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 198 | }; |
| 199 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 200 | struct intel_watermark_params { |
| 201 | unsigned long fifo_size; |
| 202 | unsigned long max_wm; |
| 203 | unsigned long default_wm; |
| 204 | unsigned long guard_size; |
| 205 | unsigned long cacheline_size; |
| 206 | }; |
| 207 | |
| 208 | struct cxsr_latency { |
| 209 | int is_desktop; |
| 210 | int is_ddr3; |
| 211 | unsigned long fsb_freq; |
| 212 | unsigned long mem_freq; |
| 213 | unsigned long display_sr; |
| 214 | unsigned long display_hpll_disable; |
| 215 | unsigned long cursor_sr; |
| 216 | unsigned long cursor_hpll_disable; |
| 217 | }; |
| 218 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 219 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
Zhenyu Wang | 5daa55e | 2010-03-30 14:39:28 +0800 | [diff] [blame] | 220 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 221 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 222 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 223 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 224 | |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 225 | #define DIP_HEADER_SIZE 5 |
| 226 | |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 227 | #define DIP_TYPE_AVI 0x82 |
| 228 | #define DIP_VERSION_AVI 0x2 |
| 229 | #define DIP_LEN_AVI 13 |
Paulo Zanoni | c846b61 | 2012-04-13 16:31:41 -0300 | [diff] [blame] | 230 | #define DIP_AVI_PR_1 0 |
| 231 | #define DIP_AVI_PR_2 1 |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 232 | |
Jesse Barnes | 2600521 | 2011-09-22 11:16:01 +0530 | [diff] [blame] | 233 | #define DIP_TYPE_SPD 0x83 |
Jesse Barnes | c0864cb | 2011-08-03 09:22:56 -0700 | [diff] [blame] | 234 | #define DIP_VERSION_SPD 0x1 |
| 235 | #define DIP_LEN_SPD 25 |
| 236 | #define DIP_SPD_UNKNOWN 0 |
| 237 | #define DIP_SPD_DSTB 0x1 |
| 238 | #define DIP_SPD_DVDP 0x2 |
| 239 | #define DIP_SPD_DVHS 0x3 |
| 240 | #define DIP_SPD_HDDVR 0x4 |
| 241 | #define DIP_SPD_DVC 0x5 |
| 242 | #define DIP_SPD_DSC 0x6 |
| 243 | #define DIP_SPD_VCD 0x7 |
| 244 | #define DIP_SPD_GAME 0x8 |
| 245 | #define DIP_SPD_PC 0x9 |
| 246 | #define DIP_SPD_BD 0xa |
| 247 | #define DIP_SPD_SCD 0xb |
| 248 | |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 249 | struct dip_infoframe { |
| 250 | uint8_t type; /* HB0 */ |
| 251 | uint8_t ver; /* HB1 */ |
| 252 | uint8_t len; /* HB2 - body len, not including checksum */ |
| 253 | uint8_t ecc; /* Header ECC */ |
| 254 | uint8_t checksum; /* PB0 */ |
| 255 | union { |
| 256 | struct { |
| 257 | /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */ |
| 258 | uint8_t Y_A_B_S; |
| 259 | /* PB2 - C 7:6, M 5:4, R 3:0 */ |
| 260 | uint8_t C_M_R; |
| 261 | /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */ |
| 262 | uint8_t ITC_EC_Q_SC; |
| 263 | /* PB4 - VIC 6:0 */ |
| 264 | uint8_t VIC; |
Paulo Zanoni | 0aa534d | 2012-04-13 16:31:40 -0300 | [diff] [blame] | 265 | /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */ |
| 266 | uint8_t YQ_CN_PR; |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 267 | /* PB6 to PB13 */ |
| 268 | uint16_t top_bar_end; |
| 269 | uint16_t bottom_bar_start; |
| 270 | uint16_t left_bar_end; |
| 271 | uint16_t right_bar_start; |
Daniel Vetter | 81014b9 | 2012-05-12 20:22:00 +0200 | [diff] [blame] | 272 | } __attribute__ ((packed)) avi; |
Jesse Barnes | c0864cb | 2011-08-03 09:22:56 -0700 | [diff] [blame] | 273 | struct { |
| 274 | uint8_t vn[8]; |
| 275 | uint8_t pd[16]; |
| 276 | uint8_t sdi; |
Daniel Vetter | 81014b9 | 2012-05-12 20:22:00 +0200 | [diff] [blame] | 277 | } __attribute__ ((packed)) spd; |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 278 | uint8_t payload[27]; |
| 279 | } __attribute__ ((packed)) body; |
| 280 | } __attribute__((packed)); |
| 281 | |
Eugeni Dodonov | f5bbfca | 2012-05-09 15:37:30 -0300 | [diff] [blame] | 282 | struct intel_hdmi { |
| 283 | struct intel_encoder base; |
| 284 | u32 sdvox_reg; |
| 285 | int ddc_bus; |
| 286 | int ddi_port; |
| 287 | uint32_t color_range; |
| 288 | bool has_hdmi_sink; |
| 289 | bool has_audio; |
| 290 | enum hdmi_force_audio force_audio; |
| 291 | void (*write_infoframe)(struct drm_encoder *encoder, |
| 292 | struct dip_infoframe *frame); |
Paulo Zanoni | 687f4d0 | 2012-05-28 16:42:48 -0300 | [diff] [blame] | 293 | void (*set_infoframes)(struct drm_encoder *encoder, |
| 294 | struct drm_display_mode *adjusted_mode); |
Eugeni Dodonov | f5bbfca | 2012-05-09 15:37:30 -0300 | [diff] [blame] | 295 | }; |
| 296 | |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 297 | #define DP_RECEIVER_CAP_SIZE 0xf |
| 298 | #define DP_LINK_CONFIGURATION_SIZE 9 |
| 299 | |
| 300 | struct intel_dp { |
| 301 | struct intel_encoder base; |
| 302 | uint32_t output_reg; |
| 303 | uint32_t DP; |
| 304 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; |
| 305 | bool has_audio; |
| 306 | enum hdmi_force_audio force_audio; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 307 | enum port port; |
Shobhit Kumar | 54d63ca | 2012-06-29 16:03:35 -0300 | [diff] [blame] | 308 | uint32_t color_range; |
| 309 | int dpms_mode; |
| 310 | uint8_t link_bw; |
| 311 | uint8_t lane_count; |
| 312 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
| 313 | struct i2c_adapter adapter; |
| 314 | struct i2c_algo_dp_aux_data algo; |
| 315 | bool is_pch_edp; |
| 316 | uint8_t train_set[4]; |
| 317 | int panel_power_up_delay; |
| 318 | int panel_power_down_delay; |
| 319 | int panel_power_cycle_delay; |
| 320 | int backlight_on_delay; |
| 321 | int backlight_off_delay; |
| 322 | struct drm_display_mode *panel_fixed_mode; /* for eDP */ |
| 323 | struct delayed_work panel_vdd_work; |
| 324 | bool want_panel_vdd; |
| 325 | struct edid *edid; /* cached EDID for eDP */ |
| 326 | int edid_mode_count; |
| 327 | }; |
| 328 | |
Chris Wilson | f875c15 | 2010-09-09 15:44:14 +0100 | [diff] [blame] | 329 | static inline struct drm_crtc * |
| 330 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) |
| 331 | { |
| 332 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 333 | return dev_priv->pipe_to_crtc_mapping[pipe]; |
| 334 | } |
| 335 | |
Chris Wilson | 417ae14 | 2011-01-19 15:04:42 +0000 | [diff] [blame] | 336 | static inline struct drm_crtc * |
| 337 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) |
| 338 | { |
| 339 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 340 | return dev_priv->plane_to_crtc_mapping[plane]; |
| 341 | } |
| 342 | |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 343 | struct intel_unpin_work { |
| 344 | struct work_struct work; |
| 345 | struct drm_device *dev; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 346 | struct drm_i915_gem_object *old_fb_obj; |
| 347 | struct drm_i915_gem_object *pending_flip_obj; |
Simon Farnsworth | 4e5359c | 2010-09-01 17:47:52 +0100 | [diff] [blame] | 348 | struct drm_pending_vblank_event *event; |
| 349 | int pending; |
| 350 | bool enable_stall_check; |
| 351 | }; |
| 352 | |
Chris Wilson | 1630fe7 | 2011-07-08 12:22:42 +0100 | [diff] [blame] | 353 | struct intel_fbc_work { |
| 354 | struct delayed_work work; |
| 355 | struct drm_crtc *crtc; |
| 356 | struct drm_framebuffer *fb; |
| 357 | int interval; |
| 358 | }; |
| 359 | |
Zhenyu Wang | 335af9a | 2010-03-30 14:39:31 +0800 | [diff] [blame] | 360 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
Eric Anholt | f0217c4 | 2009-12-01 11:56:30 -0800 | [diff] [blame] | 361 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 362 | extern void intel_attach_force_audio_property(struct drm_connector *connector); |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 363 | extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector); |
| 364 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 365 | extern void intel_crt_init(struct drm_device *dev); |
Daniel Vetter | 08d644a | 2012-07-12 20:19:59 +0200 | [diff] [blame] | 366 | extern void intel_hdmi_init(struct drm_device *dev, |
| 367 | int sdvox_reg, enum port port); |
Eugeni Dodonov | f5bbfca | 2012-05-09 15:37:30 -0300 | [diff] [blame] | 368 | extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); |
Eugeni Dodonov | f5bbfca | 2012-05-09 15:37:30 -0300 | [diff] [blame] | 369 | extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if); |
Daniel Vetter | eef4eac | 2012-03-23 23:43:35 +0100 | [diff] [blame] | 370 | extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, |
| 371 | bool is_sdvob); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 372 | extern void intel_dvo_init(struct drm_device *dev); |
| 373 | extern void intel_tv_init(struct drm_device *dev); |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame^] | 374 | extern void intel_mark_busy(struct drm_device *dev); |
| 375 | extern void intel_mark_idle(struct drm_device *dev); |
| 376 | extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj); |
| 377 | extern void intel_mark_fb_idle(struct drm_i915_gem_object *obj); |
Chris Wilson | c5d1b51 | 2010-11-29 18:00:23 +0000 | [diff] [blame] | 378 | extern bool intel_lvds_init(struct drm_device *dev); |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 379 | extern void intel_dp_init(struct drm_device *dev, int output_reg, |
| 380 | enum port port); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 381 | void |
| 382 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, |
| 383 | struct drm_display_mode *adjusted_mode); |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 384 | extern bool intel_dpd_is_edp(struct drm_device *dev); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 385 | extern void intel_edp_link_config(struct intel_encoder *, int *, int *); |
Daniel Vetter | 94bf2ce | 2012-06-04 18:39:19 +0200 | [diff] [blame] | 386 | extern int intel_edp_target_clock(struct intel_encoder *, |
| 387 | struct drm_display_mode *mode); |
Jesse Barnes | 814948a | 2010-10-07 16:01:09 -0700 | [diff] [blame] | 388 | extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder); |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 389 | extern int intel_plane_init(struct drm_device *dev, enum pipe pipe); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 390 | extern void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
| 391 | enum plane plane); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 392 | |
Chris Wilson | 9104183 | 2012-04-26 11:28:42 +0100 | [diff] [blame] | 393 | void intel_sanitize_pm(struct drm_device *dev); |
| 394 | |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 395 | /* intel_panel.c */ |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 396 | extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, |
| 397 | struct drm_display_mode *adjusted_mode); |
| 398 | extern void intel_pch_panel_fitting(struct drm_device *dev, |
| 399 | int fitting_mode, |
Daniel Vetter | cb1793c | 2012-06-04 18:39:21 +0200 | [diff] [blame] | 400 | const struct drm_display_mode *mode, |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 401 | struct drm_display_mode *adjusted_mode); |
Chris Wilson | a957355 | 2010-08-22 13:18:16 +0100 | [diff] [blame] | 402 | extern u32 intel_panel_get_max_backlight(struct drm_device *dev); |
| 403 | extern u32 intel_panel_get_backlight(struct drm_device *dev); |
| 404 | extern void intel_panel_set_backlight(struct drm_device *dev, u32 level); |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 405 | extern int intel_panel_setup_backlight(struct drm_device *dev); |
Daniel Vetter | 24ded20 | 2012-06-05 12:14:54 +0200 | [diff] [blame] | 406 | extern void intel_panel_enable_backlight(struct drm_device *dev, |
| 407 | enum pipe pipe); |
Chris Wilson | 47356eb | 2011-01-11 17:06:04 +0000 | [diff] [blame] | 408 | extern void intel_panel_disable_backlight(struct drm_device *dev); |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 409 | extern void intel_panel_destroy_backlight(struct drm_device *dev); |
Chris Wilson | fe16d94 | 2011-02-12 10:29:38 +0000 | [diff] [blame] | 410 | extern enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 411 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 412 | extern void intel_crtc_load_lut(struct drm_crtc *crtc); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 413 | extern void intel_encoder_prepare(struct drm_encoder *encoder); |
| 414 | extern void intel_encoder_commit(struct drm_encoder *encoder); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 415 | extern void intel_encoder_destroy(struct drm_encoder *encoder); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 416 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 417 | static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector) |
| 418 | { |
| 419 | return to_intel_connector(connector)->encoder; |
| 420 | } |
| 421 | |
| 422 | extern void intel_connector_attach_encoder(struct intel_connector *connector, |
| 423 | struct intel_encoder *encoder); |
| 424 | extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 425 | |
| 426 | extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, |
| 427 | struct drm_crtc *crtc); |
Carl Worth | 08d7b3d | 2009-04-29 14:43:54 -0700 | [diff] [blame] | 428 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
| 429 | struct drm_file *file_priv); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 430 | extern void intel_wait_for_vblank(struct drm_device *dev, int pipe); |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 431 | extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 432 | |
| 433 | struct intel_load_detect_pipe { |
Chris Wilson | d2dff87 | 2011-04-19 08:36:26 +0100 | [diff] [blame] | 434 | struct drm_framebuffer *release_fb; |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 435 | bool load_detect_temp; |
| 436 | int dpms_mode; |
| 437 | }; |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 438 | extern bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, |
| 439 | struct drm_connector *connector, |
| 440 | struct drm_display_mode *mode, |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 441 | struct intel_load_detect_pipe *old); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 442 | extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, |
Zhenyu Wang | c1c4397 | 2010-03-30 14:39:30 +0800 | [diff] [blame] | 443 | struct drm_connector *connector, |
Chris Wilson | 8261b19 | 2011-04-19 23:18:09 +0100 | [diff] [blame] | 444 | struct intel_load_detect_pipe *old); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 445 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 446 | extern void intelfb_restore(void); |
| 447 | extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
| 448 | u16 blue, int regno); |
Dave Airlie | b8c00ac | 2009-10-06 13:54:01 +1000 | [diff] [blame] | 449 | extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
| 450 | u16 *blue, int regno); |
Chris Wilson | 0cdab21 | 2010-12-05 17:27:06 +0000 | [diff] [blame] | 451 | extern void intel_enable_clock_gating(struct drm_device *dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 452 | |
Chris Wilson | 127bd2a | 2010-07-23 23:32:05 +0100 | [diff] [blame] | 453 | extern int intel_pin_and_fence_fb_obj(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 454 | struct drm_i915_gem_object *obj, |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 455 | struct intel_ring_buffer *pipelined); |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 456 | extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); |
Chris Wilson | 127bd2a | 2010-07-23 23:32:05 +0100 | [diff] [blame] | 457 | |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 458 | extern int intel_framebuffer_init(struct drm_device *dev, |
| 459 | struct intel_framebuffer *ifb, |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 460 | struct drm_mode_fb_cmd2 *mode_cmd, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 461 | struct drm_i915_gem_object *obj); |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 462 | extern int intel_fbdev_init(struct drm_device *dev); |
| 463 | extern void intel_fbdev_fini(struct drm_device *dev); |
Dave Airlie | 3fa016a | 2012-03-28 10:48:49 +0100 | [diff] [blame] | 464 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 465 | extern void intel_prepare_page_flip(struct drm_device *dev, int plane); |
| 466 | extern void intel_finish_page_flip(struct drm_device *dev, int pipe); |
Jesse Barnes | 1afe3e9 | 2010-03-26 10:35:20 -0700 | [diff] [blame] | 467 | extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 468 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 469 | extern void intel_setup_overlay(struct drm_device *dev); |
| 470 | extern void intel_cleanup_overlay(struct drm_device *dev); |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 471 | extern int intel_overlay_switch_off(struct intel_overlay *overlay); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 472 | extern int intel_overlay_put_image(struct drm_device *dev, void *data, |
| 473 | struct drm_file *file_priv); |
| 474 | extern int intel_overlay_attrs(struct drm_device *dev, void *data, |
| 475 | struct drm_file *file_priv); |
Dave Airlie | 4abe352 | 2010-03-30 05:34:18 +0000 | [diff] [blame] | 476 | |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 477 | extern void intel_fb_output_poll_changed(struct drm_device *dev); |
Dave Airlie | e8e7a2b | 2011-04-21 22:18:32 +0100 | [diff] [blame] | 478 | extern void intel_fb_restore_mode(struct drm_device *dev); |
Jesse Barnes | 645c62a | 2011-05-11 09:49:31 -0700 | [diff] [blame] | 479 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 480 | extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
| 481 | bool state); |
| 482 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
| 483 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) |
| 484 | |
Jesse Barnes | 645c62a | 2011-05-11 09:49:31 -0700 | [diff] [blame] | 485 | extern void intel_init_clock_gating(struct drm_device *dev); |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 486 | extern void intel_write_eld(struct drm_encoder *encoder, |
| 487 | struct drm_display_mode *mode); |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 488 | extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe); |
Eugeni Dodonov | 45244b8 | 2012-05-09 15:37:20 -0300 | [diff] [blame] | 489 | extern void intel_prepare_ddi(struct drm_device *dev); |
Eugeni Dodonov | c82e4d2 | 2012-05-09 15:37:21 -0300 | [diff] [blame] | 490 | extern void hsw_fdi_link_train(struct drm_crtc *crtc); |
Eugeni Dodonov | 0e72a5b | 2012-05-09 15:37:27 -0300 | [diff] [blame] | 491 | extern void intel_ddi_init(struct drm_device *dev, enum port port); |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 492 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 493 | /* For use by IVB LP watermark workaround in intel_sprite.c */ |
Chris Wilson | f681fa2 | 2012-04-14 21:56:08 +0100 | [diff] [blame] | 494 | extern void intel_update_watermarks(struct drm_device *dev); |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 495 | extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, |
| 496 | uint32_t sprite_width, |
| 497 | int pixel_size); |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 498 | extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe, |
| 499 | struct drm_display_mode *mode); |
Jesse Barnes | 8ea3086 | 2012-01-03 08:05:39 -0800 | [diff] [blame] | 500 | |
| 501 | extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
| 502 | struct drm_file *file_priv); |
| 503 | extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data, |
| 504 | struct drm_file *file_priv); |
| 505 | |
Jesse Barnes | 57f350b | 2012-03-28 13:39:25 -0700 | [diff] [blame] | 506 | extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg); |
| 507 | |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 508 | /* Power-related functions, located in intel_pm.c */ |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 509 | extern void intel_init_pm(struct drm_device *dev); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 510 | /* FBC */ |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 511 | extern bool intel_fbc_enabled(struct drm_device *dev); |
| 512 | extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); |
| 513 | extern void intel_update_fbc(struct drm_device *dev); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 514 | /* IPS */ |
| 515 | extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv); |
| 516 | extern void intel_gpu_ips_teardown(void); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 517 | |
Eugeni Dodonov | 0232e92 | 2012-07-06 15:42:36 -0300 | [diff] [blame] | 518 | extern void intel_init_power_wells(struct drm_device *dev); |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 519 | extern void intel_enable_gt_powersave(struct drm_device *dev); |
| 520 | extern void intel_disable_gt_powersave(struct drm_device *dev); |
Eugeni Dodonov | 6590190 | 2012-07-02 11:51:11 -0300 | [diff] [blame] | 521 | extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv); |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 522 | extern void ironlake_teardown_rc6(struct drm_device *dev); |
Daniel Vetter | b3daeae | 2012-04-26 23:28:13 +0200 | [diff] [blame] | 523 | |
Eugeni Dodonov | 72662e1 | 2012-05-09 15:37:31 -0300 | [diff] [blame] | 524 | extern void intel_ddi_dpms(struct drm_encoder *encoder, int mode); |
| 525 | extern void intel_ddi_mode_set(struct drm_encoder *encoder, |
| 526 | struct drm_display_mode *mode, |
| 527 | struct drm_display_mode *adjusted_mode); |
| 528 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 529 | #endif /* __INTEL_DRV_H__ */ |