Blame - drivers/scsi/qla2xxx/qla_dbg.c - kernel/msm-4.19

blob: 781ca5b09362f4cf59da21a308111075a3ec4796 [file] [log] [blame]

Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	1	/*
Andrew Vasquez	fa90c54	2005-10-27 11:10:08 -0700	[diff] [blame]	2	* QLogic Fibre Channel HBA Driver
Armen Baloyan	bd21eaf	2014-04-11 16:54:24 -0400	[diff] [blame]	3	* Copyright (c) 2003-2014 QLogic Corporation
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	4	*
Andrew Vasquez	fa90c54	2005-10-27 11:10:08 -0700	[diff] [blame]	5	* See LICENSE.qla2xxx for copyright and licensing details.
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	6	*/
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	7
				8	/*
				9	* Table for showing the current message id in use for particular level
				10	* Change this table for addition of log/debug messages.
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	11	* ----------------------------------------------------------------------
				12	* \| Level \| Last Value Used \| Holes \|
				13	* ----------------------------------------------------------------------
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	14	* \| Module Init and Probe \| 0x017d \| 0x004b,0x0141 \|
				15	* \| \| \| 0x0144,0x0146 \|
				16	* \| \| \| 0x015b-0x0160 \|
				17	* \| \| \| 0x016e-0x0170 \|
Joe Carnuccio	e8887c5	2014-04-11 16:54:17 -0400	[diff] [blame]	18	* \| Mailbox commands \| 0x118d \| 0x1018-0x1019 \|
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	19	* \| \| \| 0x10ca \|
Saurav Kashyap	6ddcfef	2013-08-27 01:37:53 -0400	[diff] [blame]	20	* \| \| \| 0x1115-0x1116 \|
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	21	* \| \| \| 0x111a-0x111b \|
				22	* \| \| \| 0x1155-0x1158 \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	23	* \| Device Discovery \| 0x2095 \| 0x2020-0x2022, \|
Bart Van Assche	6593d5b	2013-06-25 11:27:24 -0400	[diff] [blame]	24	* \| \| \| 0x2011-0x2012, \|
Saurav Kashyap	2a8593f	2012-08-22 14:21:27 -0400	[diff] [blame]	25	* \| \| \| 0x2016 \|
Chad Dupuis	36008cf	2013-10-03 03:21:13 -0400	[diff] [blame]	26	* \| Queue Command and IO tracing \| 0x3059 \| 0x3006-0x300b \|
Arun Easi	9e522cd	2012-08-22 14:21:31 -0400	[diff] [blame]	27	* \| \| \| 0x3027-0x3028 \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	28	* \| \| \| 0x303d-0x3041 \|
				29	* \| \| \| 0x302d,0x3033 \|
				30	* \| \| \| 0x3036,0x3038 \|
				31	* \| \| \| 0x303a \|
Armen Baloyan	e8f5e95	2013-10-30 03:38:17 -0400	[diff] [blame]	32	* \| DPC Thread \| 0x4023 \| 0x4002,0x4013 \|
Santosh Vernekar	454073c	2013-08-27 01:37:48 -0400	[diff] [blame]	33	* \| Async Events \| 0x5087 \| 0x502b-0x502f \|
Giridhar Malavali	9ba56b9	2012-02-09 11:15:36 -0800	[diff] [blame]	34	* \| \| \| 0x5047,0x5052 \|
Saurav Kashyap	6ddcfef	2013-08-27 01:37:53 -0400	[diff] [blame]	35	* \| \| \| 0x5084,0x5075 \|
Chad Dupuis	a78951b	2013-08-27 01:37:34 -0400	[diff] [blame]	36	* \| \| \| 0x503d,0x5044 \|
Armen Baloyan	faef62d	2014-02-26 04:15:17 -0500	[diff] [blame]	37	* \| \| \| 0x507b \|
Armen Baloyan	71e5600	2013-08-27 01:37:38 -0400	[diff] [blame]	38	* \| Timer Routines \| 0x6012 \| \|
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	39	* \| User Space Interactions \| 0x70e2 \| 0x7018,0x702e \|
				40	* \| \| \| 0x7020,0x7024 \|
				41	* \| \| \| 0x7039,0x7045 \|
				42	* \| \| \| 0x7073-0x7075 \|
				43	* \| \| \| 0x70a5-0x70a6 \|
				44	* \| \| \| 0x70a8,0x70ab \|
				45	* \| \| \| 0x70ad-0x70ae \|
				46	* \| \| \| 0x70d7-0x70db \|
				47	* \| \| \| 0x70de-0x70df \|
Armen Baloyan	5854771	2013-08-27 01:37:33 -0400	[diff] [blame]	48	* \| Task Management \| 0x803d \| 0x8025-0x8026 \|
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	49	* \| \| \| 0x800b,0x8039 \|
Saurav Kashyap	5f28d2d	2012-05-15 14:34:15 -0400	[diff] [blame]	50	* \| AER/EEH \| 0x9011 \| \|
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	51	* \| Virtual Port \| 0xa007 \| \|
Atul Deshmukh	27f4b72	2014-04-11 16:54:26 -0400	[diff] [blame]	52	* \| ISP82XX Specific \| 0xb157 \| 0xb002,0xb024 \|
Atul Deshmukh	7ec0eff	2013-08-27 01:37:28 -0400	[diff] [blame]	53	* \| \| \| 0xb09e,0xb0ae \|
Hiral Patel	a018d8f	2014-04-11 16:54:34 -0400	[diff] [blame]	54	* \| \| \| 0xb0c3,0xb0c6 \|
Atul Deshmukh	7ec0eff	2013-08-27 01:37:28 -0400	[diff] [blame]	55	* \| \| \| 0xb0e0-0xb0ef \|
				56	* \| \| \| 0xb085,0xb0dc \|
				57	* \| \| \| 0xb107,0xb108 \|
				58	* \| \| \| 0xb111,0xb11e \|
				59	* \| \| \| 0xb12c,0xb12d \|
				60	* \| \| \| 0xb13a,0xb142 \|
				61	* \| \| \| 0xb13c-0xb140 \|
Saurav Kashyap	6ddcfef	2013-08-27 01:37:53 -0400	[diff] [blame]	62	* \| \| \| 0xb149 \|
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	63	* \| MultiQ \| 0xc00c \| \|
Joe Carnuccio	c049640	2014-04-11 16:54:36 -0400	[diff] [blame]	64	* \| Misc \| 0xd212 \| 0xd017-0xd019 \|
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	65	* \| \| \| 0xd020 \|
Joe Carnuccio	c049640	2014-04-11 16:54:36 -0400	[diff] [blame]	66	* \| \| \| 0xd030-0xd0ff \|
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	67	* \| \| \| 0xd101-0xd1fe \|
Joe Carnuccio	c049640	2014-04-11 16:54:36 -0400	[diff] [blame]	68	* \| \| \| 0xd213-0xd2fe \|
Quinn Tran	f83adb6	2014-04-11 16:54:43 -0400	[diff] [blame^]	69	* \| Target Mode \| 0xe078 \| \|
Saurav Kashyap	6ddcfef	2013-08-27 01:37:53 -0400	[diff] [blame]	70	* \| Target Mode Management \| 0xf072 \| 0xf002-0xf003 \|
				71	* \| \| \| 0xf046-0xf049 \|
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	72	* \| Target Mode Task Management \| 0x1000b \| \|
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	73	* ----------------------------------------------------------------------
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	74	*/
				75
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	76	#include "qla_def.h"
				77
				78	#include <linux/delay.h>
				79
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	80	static uint32_t ql_dbg_offset = 0x800;
				81
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	82	static inline void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	83	qla2xxx_prep_dump(struct qla_hw_data ha, struct qla2xxx_fw_dump fw_dump)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	84	{
				85	fw_dump->fw_major_version = htonl(ha->fw_major_version);
				86	fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
				87	fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
				88	fw_dump->fw_attributes = htonl(ha->fw_attributes);
				89
				90	fw_dump->vendor = htonl(ha->pdev->vendor);
				91	fw_dump->device = htonl(ha->pdev->device);
				92	fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
				93	fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
				94	}
				95
				96	static inline void *
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	97	qla2xxx_copy_queues(struct qla_hw_data ha, void ptr)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	98	{
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	99	struct req_que *req = ha->req_q_map[0];
				100	struct rsp_que *rsp = ha->rsp_q_map[0];
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	101	/* Request queue. */
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	102	memcpy(ptr, req->ring, req->length *
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	103	sizeof(request_t));
				104
				105	/* Response queue. */
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	106	ptr += req->length * sizeof(request_t);
				107	memcpy(ptr, rsp->ring, rsp->length *
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	108	sizeof(response_t));
				109
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	110	return ptr + (rsp->length * sizeof(response_t));
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	111	}
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	112
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	113	int
				114	qla27xx_dump_mpi_ram(struct qla_hw_data ha, uint32_t addr, uint32_t ram,
				115	uint32_t ram_dwords, void **nxt)
				116	{
				117	int rval;
				118	uint32_t cnt, stat, timer, dwords, idx;
				119	uint16_t mb0, mb1;
				120	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				121	dma_addr_t dump_dma = ha->gid_list_dma;
				122	uint32_t dump = (uint32_t )ha->gid_list;
				123
				124	rval = QLA_SUCCESS;
				125	mb0 = 0;
				126
				127	WRT_REG_WORD(&reg->mailbox0, MBC_LOAD_DUMP_MPI_RAM);
				128	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				129
				130	dwords = qla2x00_gid_list_size(ha) / 4;
				131	for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
				132	cnt += dwords, addr += dwords) {
				133	if (cnt + dwords > ram_dwords)
				134	dwords = ram_dwords - cnt;
				135
				136	WRT_REG_WORD(&reg->mailbox1, LSW(addr));
				137	WRT_REG_WORD(&reg->mailbox8, MSW(addr));
				138
				139	WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
				140	WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
				141	WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
				142	WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
				143
				144	WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
				145	WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
				146
				147	WRT_REG_WORD(&reg->mailbox9, 0);
				148	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
				149
				150	ha->flags.mbox_int = 0;
				151	for (timer = 6000000; timer; timer--) {
				152	/* Check for pending interrupts. */
				153	stat = RD_REG_DWORD(&reg->host_status);
				154	if (stat & HSRX_RISC_INT) {
				155	stat &= 0xff;
				156
				157	if (stat == 0x1 \|\| stat == 0x2 \|\|
				158	stat == 0x10 \|\| stat == 0x11) {
				159	set_bit(MBX_INTERRUPT,
				160	&ha->mbx_cmd_flags);
				161
				162	mb0 = RD_REG_WORD(&reg->mailbox0);
				163	mb1 = RD_REG_WORD(&reg->mailbox1);
				164
				165	WRT_REG_DWORD(&reg->hccr,
				166	HCCRX_CLR_RISC_INT);
				167	RD_REG_DWORD(&reg->hccr);
				168	break;
				169	}
				170
				171	/* Clear this intr; it wasn't a mailbox intr */
				172	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
				173	RD_REG_DWORD(&reg->hccr);
				174	}
				175	udelay(5);
				176	}
				177	ha->flags.mbox_int = 1;
				178
				179	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
				180	rval = mb0 & MBS_MASK;
				181	for (idx = 0; idx < dwords; idx++)
				182	ram[cnt + idx] = IS_QLA27XX(ha) ?
				183	le32_to_cpu(dump[idx]) : swab32(dump[idx]);
				184	} else {
				185	rval = QLA_FUNCTION_FAILED;
				186	}
				187	}
				188
				189	*nxt = rval == QLA_SUCCESS ? &ram[cnt] : NULL;
				190	return rval;
				191	}
				192
				193	int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	194	qla24xx_dump_ram(struct qla_hw_data ha, uint32_t addr, uint32_t ram,
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	195	uint32_t ram_dwords, void **nxt)
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	196	{
				197	int rval;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	198	uint32_t cnt, stat, timer, dwords, idx;
				199	uint16_t mb0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	200	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	201	dma_addr_t dump_dma = ha->gid_list_dma;
				202	uint32_t dump = (uint32_t )ha->gid_list;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	203
				204	rval = QLA_SUCCESS;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	205	mb0 = 0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	206
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	207	WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	208	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				209
Chad Dupuis	642ef98	2012-02-09 11:15:57 -0800	[diff] [blame]	210	dwords = qla2x00_gid_list_size(ha) / 4;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	211	for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
				212	cnt += dwords, addr += dwords) {
				213	if (cnt + dwords > ram_dwords)
				214	dwords = ram_dwords - cnt;
				215
				216	WRT_REG_WORD(&reg->mailbox1, LSW(addr));
				217	WRT_REG_WORD(&reg->mailbox8, MSW(addr));
				218
				219	WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
				220	WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
				221	WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
				222	WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
				223
				224	WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
				225	WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	226	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
				227
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	228	ha->flags.mbox_int = 0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	229	for (timer = 6000000; timer; timer--) {
				230	/* Check for pending interrupts. */
				231	stat = RD_REG_DWORD(&reg->host_status);
				232	if (stat & HSRX_RISC_INT) {
				233	stat &= 0xff;
				234
				235	if (stat == 0x1 \|\| stat == 0x2 \|\|
				236	stat == 0x10 \|\| stat == 0x11) {
				237	set_bit(MBX_INTERRUPT,
				238	&ha->mbx_cmd_flags);
				239
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	240	mb0 = RD_REG_WORD(&reg->mailbox0);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	241
				242	WRT_REG_DWORD(&reg->hccr,
				243	HCCRX_CLR_RISC_INT);
				244	RD_REG_DWORD(&reg->hccr);
				245	break;
				246	}
				247
				248	/* Clear this intr; it wasn't a mailbox intr */
				249	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
				250	RD_REG_DWORD(&reg->hccr);
				251	}
				252	udelay(5);
				253	}
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	254	ha->flags.mbox_int = 1;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	255
				256	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	257	rval = mb0 & MBS_MASK;
				258	for (idx = 0; idx < dwords; idx++)
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	259	ram[cnt + idx] = IS_QLA27XX(ha) ?
				260	le32_to_cpu(dump[idx]) : swab32(dump[idx]);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	261	} else {
				262	rval = QLA_FUNCTION_FAILED;
				263	}
				264	}
				265
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	266	*nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	267	return rval;
				268	}
				269
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	270	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	271	qla24xx_dump_memory(struct qla_hw_data ha, uint32_t code_ram,
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	272	uint32_t cram_size, void **nxt)
				273	{
				274	int rval;
				275
				276	/* Code RAM. */
				277	rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
				278	if (rval != QLA_SUCCESS)
				279	return rval;
				280
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	281	set_bit(RISC_SRAM_DUMP_CMPL, &ha->fw_dump_cap_flags);
				282
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	283	/* External Memory. */
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	284	rval = qla24xx_dump_ram(ha, 0x100000, *nxt,
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	285	ha->fw_memory_size - 0x100000 + 1, nxt);
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	286	if (rval == QLA_SUCCESS)
				287	set_bit(RISC_EXT_MEM_DUMP_CMPL, &ha->fw_dump_cap_flags);
				288
				289	return rval;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	290	}
				291
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	292	static uint32_t *
				293	qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
				294	uint32_t count, uint32_t *buf)
				295	{
				296	uint32_t __iomem *dmp_reg;
				297
				298	WRT_REG_DWORD(&reg->iobase_addr, iobase);
				299	dmp_reg = &reg->iobase_window;
				300	while (count--)
				301	*buf++ = htonl(RD_REG_DWORD(dmp_reg++));
				302
				303	return buf;
				304	}
				305
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	306	void
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	307	qla24xx_pause_risc(struct device_reg_24xx __iomem reg, struct qla_hw_data ha)
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	308	{
Andrew Vasquez	c3b058a	2007-09-20 14:07:38 -0700	[diff] [blame]	309	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	310
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	311	/* 100 usec delay is sufficient enough for hardware to pause RISC */
				312	udelay(100);
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	313	if (RD_REG_DWORD(&reg->host_status) & HSRX_RISC_PAUSED)
				314	set_bit(RISC_PAUSE_CMPL, &ha->fw_dump_cap_flags);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	315	}
				316
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	317	int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	318	qla24xx_soft_reset(struct qla_hw_data *ha)
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	319	{
				320	int rval = QLA_SUCCESS;
				321	uint32_t cnt;
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	322	uint16_t wd;
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	323	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				324
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	325	/*
				326	* Reset RISC. The delay is dependent on system architecture.
				327	* Driver can proceed with the reset sequence after waiting
				328	* for a timeout period.
				329	*/
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	330	WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN\|MWB_4096_BYTES);
				331	for (cnt = 0; cnt < 30000; cnt++) {
				332	if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
				333	break;
				334
				335	udelay(10);
				336	}
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	337	if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
				338	set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	339
				340	WRT_REG_DWORD(&reg->ctrl_status,
				341	CSRX_ISP_SOFT_RESET\|CSRX_DMA_SHUTDOWN\|MWB_4096_BYTES);
				342	pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
				343
				344	udelay(100);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	345
				346	/* Wait for soft-reset to complete. */
				347	for (cnt = 0; cnt < 30000; cnt++) {
				348	if ((RD_REG_DWORD(&reg->ctrl_status) &
				349	CSRX_ISP_SOFT_RESET) == 0)
				350	break;
				351
				352	udelay(10);
				353	}
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	354	if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
				355	set_bit(ISP_RESET_CMPL, &ha->fw_dump_cap_flags);
				356
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	357	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
				358	RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
				359
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	360	for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	361	rval == QLA_SUCCESS; cnt--) {
				362	if (cnt)
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	363	udelay(10);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	364	else
				365	rval = QLA_FUNCTION_TIMEOUT;
				366	}
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	367	if (rval == QLA_SUCCESS)
				368	set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	369
				370	return rval;
				371	}
				372
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	373	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	374	qla2xxx_dump_ram(struct qla_hw_data ha, uint32_t addr, uint16_t ram,
Andrew Vasquez	e18e963	2009-06-17 10:30:31 -0700	[diff] [blame]	375	uint32_t ram_words, void **nxt)
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	376	{
				377	int rval;
				378	uint32_t cnt, stat, timer, words, idx;
				379	uint16_t mb0;
				380	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
				381	dma_addr_t dump_dma = ha->gid_list_dma;
				382	uint16_t dump = (uint16_t )ha->gid_list;
				383
				384	rval = QLA_SUCCESS;
				385	mb0 = 0;
				386
				387	WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
				388	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				389
Chad Dupuis	642ef98	2012-02-09 11:15:57 -0800	[diff] [blame]	390	words = qla2x00_gid_list_size(ha) / 2;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	391	for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
				392	cnt += words, addr += words) {
				393	if (cnt + words > ram_words)
				394	words = ram_words - cnt;
				395
				396	WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
				397	WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
				398
				399	WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
				400	WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
				401	WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
				402	WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
				403
				404	WRT_MAILBOX_REG(ha, reg, 4, words);
				405	WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
				406
				407	for (timer = 6000000; timer; timer--) {
				408	/* Check for pending interrupts. */
				409	stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
				410	if (stat & HSR_RISC_INT) {
				411	stat &= 0xff;
				412
				413	if (stat == 0x1 \|\| stat == 0x2) {
				414	set_bit(MBX_INTERRUPT,
				415	&ha->mbx_cmd_flags);
				416
				417	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				418
				419	/* Release mailbox registers. */
				420	WRT_REG_WORD(&reg->semaphore, 0);
				421	WRT_REG_WORD(&reg->hccr,
				422	HCCR_CLR_RISC_INT);
				423	RD_REG_WORD(&reg->hccr);
				424	break;
				425	} else if (stat == 0x10 \|\| stat == 0x11) {
				426	set_bit(MBX_INTERRUPT,
				427	&ha->mbx_cmd_flags);
				428
				429	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				430
				431	WRT_REG_WORD(&reg->hccr,
				432	HCCR_CLR_RISC_INT);
				433	RD_REG_WORD(&reg->hccr);
				434	break;
				435	}
				436
				437	/* clear this intr; it wasn't a mailbox intr */
				438	WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
				439	RD_REG_WORD(&reg->hccr);
				440	}
				441	udelay(5);
				442	}
				443
				444	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
				445	rval = mb0 & MBS_MASK;
				446	for (idx = 0; idx < words; idx++)
				447	ram[cnt + idx] = swab16(dump[idx]);
				448	} else {
				449	rval = QLA_FUNCTION_FAILED;
				450	}
				451	}
				452
				453	*nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
				454	return rval;
				455	}
				456
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	457	static inline void
				458	qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
				459	uint16_t *buf)
				460	{
				461	uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
				462
				463	while (count--)
				464	*buf++ = htons(RD_REG_WORD(dmp_reg++));
				465	}
				466
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	467	static inline void *
				468	qla24xx_copy_eft(struct qla_hw_data ha, void ptr)
				469	{
				470	if (!ha->eft)
				471	return ptr;
				472
				473	memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
				474	return ptr + ntohl(ha->fw_dump->eft_size);
				475	}
				476
				477	static inline void *
				478	qla25xx_copy_fce(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				479	{
				480	uint32_t cnt;
				481	uint32_t *iter_reg;
				482	struct qla2xxx_fce_chain *fcec = ptr;
				483
				484	if (!ha->fce)
				485	return ptr;
				486
				487	*last_chain = &fcec->type;
				488	fcec->type = __constant_htonl(DUMP_CHAIN_FCE);
				489	fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
				490	fce_calc_size(ha->fce_bufs));
				491	fcec->size = htonl(fce_calc_size(ha->fce_bufs));
				492	fcec->addr_l = htonl(LSD(ha->fce_dma));
				493	fcec->addr_h = htonl(MSD(ha->fce_dma));
				494
				495	iter_reg = fcec->eregs;
				496	for (cnt = 0; cnt < 8; cnt++)
				497	*iter_reg++ = htonl(ha->fce_mb[cnt]);
				498
				499	memcpy(iter_reg, ha->fce, ntohl(fcec->size));
				500
Giridhar Malavali	3cb0a67	2011-11-18 09:03:11 -0800	[diff] [blame]	501	return (char *)iter_reg + ntohl(fcec->size);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	502	}
				503
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	504	static inline void *
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	505	qla2xxx_copy_atioqueues(struct qla_hw_data ha, void ptr,
				506	uint32_t **last_chain)
				507	{
				508	struct qla2xxx_mqueue_chain *q;
				509	struct qla2xxx_mqueue_header *qh;
				510	uint32_t num_queues;
				511	int que;
				512	struct {
				513	int length;
				514	void *ring;
				515	} aq, *aqp;
				516
Arun Easi	00876ae	2013-03-25 02:21:37 -0400	[diff] [blame]	517	if (!ha->tgt.atio_ring)
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	518	return ptr;
				519
				520	num_queues = 1;
				521	aqp = &aq;
				522	aqp->length = ha->tgt.atio_q_length;
				523	aqp->ring = ha->tgt.atio_ring;
				524
				525	for (que = 0; que < num_queues; que++) {
				526	/* aqp = ha->atio_q_map[que]; */
				527	q = ptr;
				528	*last_chain = &q->type;
				529	q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
				530	q->chain_size = htonl(
				531	sizeof(struct qla2xxx_mqueue_chain) +
				532	sizeof(struct qla2xxx_mqueue_header) +
				533	(aqp->length * sizeof(request_t)));
				534	ptr += sizeof(struct qla2xxx_mqueue_chain);
				535
				536	/* Add header. */
				537	qh = ptr;
				538	qh->queue = __constant_htonl(TYPE_ATIO_QUEUE);
				539	qh->number = htonl(que);
				540	qh->size = htonl(aqp->length * sizeof(request_t));
				541	ptr += sizeof(struct qla2xxx_mqueue_header);
				542
				543	/* Add data. */
				544	memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t));
				545
				546	ptr += aqp->length * sizeof(request_t);
				547	}
				548
				549	return ptr;
				550	}
				551
				552	static inline void *
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	553	qla25xx_copy_mqueues(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				554	{
				555	struct qla2xxx_mqueue_chain *q;
				556	struct qla2xxx_mqueue_header *qh;
				557	struct req_que *req;
				558	struct rsp_que *rsp;
				559	int que;
				560
				561	if (!ha->mqenable)
				562	return ptr;
				563
				564	/* Request queues */
				565	for (que = 1; que < ha->max_req_queues; que++) {
				566	req = ha->req_q_map[que];
				567	if (!req)
				568	break;
				569
				570	/* Add chain. */
				571	q = ptr;
				572	*last_chain = &q->type;
				573	q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
				574	q->chain_size = htonl(
				575	sizeof(struct qla2xxx_mqueue_chain) +
				576	sizeof(struct qla2xxx_mqueue_header) +
				577	(req->length * sizeof(request_t)));
				578	ptr += sizeof(struct qla2xxx_mqueue_chain);
				579
				580	/* Add header. */
				581	qh = ptr;
				582	qh->queue = __constant_htonl(TYPE_REQUEST_QUEUE);
				583	qh->number = htonl(que);
				584	qh->size = htonl(req->length * sizeof(request_t));
				585	ptr += sizeof(struct qla2xxx_mqueue_header);
				586
				587	/* Add data. */
				588	memcpy(ptr, req->ring, req->length * sizeof(request_t));
				589	ptr += req->length * sizeof(request_t);
				590	}
				591
				592	/* Response queues */
				593	for (que = 1; que < ha->max_rsp_queues; que++) {
				594	rsp = ha->rsp_q_map[que];
				595	if (!rsp)
				596	break;
				597
				598	/* Add chain. */
				599	q = ptr;
				600	*last_chain = &q->type;
				601	q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
				602	q->chain_size = htonl(
				603	sizeof(struct qla2xxx_mqueue_chain) +
				604	sizeof(struct qla2xxx_mqueue_header) +
				605	(rsp->length * sizeof(response_t)));
				606	ptr += sizeof(struct qla2xxx_mqueue_chain);
				607
				608	/* Add header. */
				609	qh = ptr;
				610	qh->queue = __constant_htonl(TYPE_RESPONSE_QUEUE);
				611	qh->number = htonl(que);
				612	qh->size = htonl(rsp->length * sizeof(response_t));
				613	ptr += sizeof(struct qla2xxx_mqueue_header);
				614
				615	/* Add data. */
				616	memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t));
				617	ptr += rsp->length * sizeof(response_t);
				618	}
				619
				620	return ptr;
				621	}
				622
				623	static inline void *
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	624	qla25xx_copy_mq(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				625	{
				626	uint32_t cnt, que_idx;
Anirban Chakraborty	2afa19a	2009-04-06 22:33:40 -0700	[diff] [blame]	627	uint8_t que_cnt;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	628	struct qla2xxx_mq_chain *mq = ptr;
Andrew Vasquez	da9b1d5	2013-08-27 01:37:30 -0400	[diff] [blame]	629	device_reg_t __iomem *reg;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	630
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	631	if (!ha->mqenable \|\| IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	632	return ptr;
				633
				634	mq = ptr;
				635	*last_chain = &mq->type;
				636	mq->type = __constant_htonl(DUMP_CHAIN_MQ);
				637	mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain));
				638
Anirban Chakraborty	2afa19a	2009-04-06 22:33:40 -0700	[diff] [blame]	639	que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
				640	ha->max_req_queues : ha->max_rsp_queues;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	641	mq->count = htonl(que_cnt);
				642	for (cnt = 0; cnt < que_cnt; cnt++) {
Andrew Vasquez	da9b1d5	2013-08-27 01:37:30 -0400	[diff] [blame]	643	reg = ISP_QUE_REG(ha, cnt);
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	644	que_idx = cnt * 4;
Andrew Vasquez	da9b1d5	2013-08-27 01:37:30 -0400	[diff] [blame]	645	mq->qregs[que_idx] =
				646	htonl(RD_REG_DWORD(&reg->isp25mq.req_q_in));
				647	mq->qregs[que_idx+1] =
				648	htonl(RD_REG_DWORD(&reg->isp25mq.req_q_out));
				649	mq->qregs[que_idx+2] =
				650	htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_in));
				651	mq->qregs[que_idx+3] =
				652	htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_out));
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	653	}
				654
				655	return ptr + sizeof(struct qla2xxx_mq_chain);
				656	}
				657
Giridhar Malavali	08de284	2011-08-16 11:31:44 -0700	[diff] [blame]	658	void
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	659	qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval)
				660	{
				661	struct qla_hw_data *ha = vha->hw;
				662
				663	if (rval != QLA_SUCCESS) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	664	ql_log(ql_log_warn, vha, 0xd000,
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	665	"Failed to dump firmware (%x), dump status flags (0x%lx).\n",
				666	rval, ha->fw_dump_cap_flags);
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	667	ha->fw_dumped = 0;
				668	} else {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	669	ql_log(ql_log_info, vha, 0xd001,
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	670	"Firmware dump saved to temp buffer (%ld/%p), dump status flags (0x%lx).\n",
				671	vha->host_no, ha->fw_dump, ha->fw_dump_cap_flags);
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	672	ha->fw_dumped = 1;
				673	qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
				674	}
				675	}
				676
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	677	/**
				678	* qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
				679	* @ha: HA context
				680	* @hardware_locked: Called with the hardware_lock
				681	*/
				682	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	683	qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	684	{
				685	int rval;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	686	uint32_t cnt;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	687	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	3d71644	2005-07-06 10:30:26 -0700	[diff] [blame]	688	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	689	uint16_t __iomem *dmp_reg;
				690	unsigned long flags;
				691	struct qla2300_fw_dump *fw;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	692	void *nxt;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	693	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	694
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	695	flags = 0;
				696
				697	if (!hardware_locked)
				698	spin_lock_irqsave(&ha->hardware_lock, flags);
				699
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	700	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	701	ql_log(ql_log_warn, vha, 0xd002,
				702	"No buffer available for dump.\n");
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	703	goto qla2300_fw_dump_failed;
				704	}
				705
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	706	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	707	ql_log(ql_log_warn, vha, 0xd003,
				708	"Firmware has been previously dumped (%p) "
				709	"-- ignoring request.\n",
				710	ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	711	goto qla2300_fw_dump_failed;
				712	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	713	fw = &ha->fw_dump->isp.isp23;
				714	qla2xxx_prep_dump(ha, ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	715
				716	rval = QLA_SUCCESS;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	717	fw->hccr = htons(RD_REG_WORD(&reg->hccr));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	718
				719	/* Pause RISC. */
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	720	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	721	if (IS_QLA2300(ha)) {
				722	for (cnt = 30000;
				723	(RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				724	rval == QLA_SUCCESS; cnt--) {
				725	if (cnt)
				726	udelay(100);
				727	else
				728	rval = QLA_FUNCTION_TIMEOUT;
				729	}
				730	} else {
				731	RD_REG_WORD(&reg->hccr); /* PCI Posting. */
				732	udelay(10);
				733	}
				734
				735	if (rval == QLA_SUCCESS) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	736	dmp_reg = &reg->flash_address;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	737	for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	738	fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	739
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	740	dmp_reg = &reg->u.isp2300.req_q_in;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	741	for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	742	fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	743
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	744	dmp_reg = &reg->u.isp2300.mailbox0;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	745	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	746	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	747
				748	WRT_REG_WORD(&reg->ctrl_status, 0x40);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	749	qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	750
				751	WRT_REG_WORD(&reg->ctrl_status, 0x50);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	752	qla2xxx_read_window(reg, 48, fw->dma_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	753
				754	WRT_REG_WORD(&reg->ctrl_status, 0x00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	755	dmp_reg = &reg->risc_hw;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	756	for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	757	fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	758
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	759	WRT_REG_WORD(&reg->pcr, 0x2000);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	760	qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	761
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	762	WRT_REG_WORD(&reg->pcr, 0x2200);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	763	qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	764
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	765	WRT_REG_WORD(&reg->pcr, 0x2400);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	766	qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	767
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	768	WRT_REG_WORD(&reg->pcr, 0x2600);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	769	qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	770
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	771	WRT_REG_WORD(&reg->pcr, 0x2800);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	772	qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	773
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	774	WRT_REG_WORD(&reg->pcr, 0x2A00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	775	qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	776
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	777	WRT_REG_WORD(&reg->pcr, 0x2C00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	778	qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	779
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	780	WRT_REG_WORD(&reg->pcr, 0x2E00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	781	qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	782
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	783	WRT_REG_WORD(&reg->ctrl_status, 0x10);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	784	qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	785
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	786	WRT_REG_WORD(&reg->ctrl_status, 0x20);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	787	qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	788
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	789	WRT_REG_WORD(&reg->ctrl_status, 0x30);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	790	qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	791
				792	/* Reset RISC. */
				793	WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
				794	for (cnt = 0; cnt < 30000; cnt++) {
				795	if ((RD_REG_WORD(&reg->ctrl_status) &
				796	CSR_ISP_SOFT_RESET) == 0)
				797	break;
				798
				799	udelay(10);
				800	}
				801	}
				802
				803	if (!IS_QLA2300(ha)) {
				804	for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
				805	rval == QLA_SUCCESS; cnt--) {
				806	if (cnt)
				807	udelay(100);
				808	else
				809	rval = QLA_FUNCTION_TIMEOUT;
				810	}
				811	}
				812
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	813	/* Get RISC SRAM. */
				814	if (rval == QLA_SUCCESS)
				815	rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
				816	sizeof(fw->risc_ram) / 2, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	817
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	818	/* Get stack SRAM. */
				819	if (rval == QLA_SUCCESS)
				820	rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
				821	sizeof(fw->stack_ram) / 2, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	822
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	823	/* Get data SRAM. */
				824	if (rval == QLA_SUCCESS)
				825	rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
				826	ha->fw_memory_size - 0x11000 + 1, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	827
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	828	if (rval == QLA_SUCCESS)
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	829	qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	830
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	831	qla2xxx_dump_post_process(base_vha, rval);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	832
				833	qla2300_fw_dump_failed:
				834	if (!hardware_locked)
				835	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				836	}
				837
				838	/**
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	839	* qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
				840	* @ha: HA context
				841	* @hardware_locked: Called with the hardware_lock
				842	*/
				843	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	844	qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	845	{
				846	int rval;
				847	uint32_t cnt, timer;
				848	uint16_t risc_address;
				849	uint16_t mb0, mb2;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	850	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	3d71644	2005-07-06 10:30:26 -0700	[diff] [blame]	851	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	852	uint16_t __iomem *dmp_reg;
				853	unsigned long flags;
				854	struct qla2100_fw_dump *fw;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	855	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	856
				857	risc_address = 0;
				858	mb0 = mb2 = 0;
				859	flags = 0;
				860
				861	if (!hardware_locked)
				862	spin_lock_irqsave(&ha->hardware_lock, flags);
				863
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	864	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	865	ql_log(ql_log_warn, vha, 0xd004,
				866	"No buffer available for dump.\n");
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	867	goto qla2100_fw_dump_failed;
				868	}
				869
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	870	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	871	ql_log(ql_log_warn, vha, 0xd005,
				872	"Firmware has been previously dumped (%p) "
				873	"-- ignoring request.\n",
				874	ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	875	goto qla2100_fw_dump_failed;
				876	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	877	fw = &ha->fw_dump->isp.isp21;
				878	qla2xxx_prep_dump(ha, ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	879
				880	rval = QLA_SUCCESS;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	881	fw->hccr = htons(RD_REG_WORD(&reg->hccr));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	882
				883	/* Pause RISC. */
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	884	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	885	for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				886	rval == QLA_SUCCESS; cnt--) {
				887	if (cnt)
				888	udelay(100);
				889	else
				890	rval = QLA_FUNCTION_TIMEOUT;
				891	}
				892	if (rval == QLA_SUCCESS) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	893	dmp_reg = &reg->flash_address;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	894	for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	895	fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	896
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	897	dmp_reg = &reg->u.isp2100.mailbox0;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	898	for (cnt = 0; cnt < ha->mbx_count; cnt++) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	899	if (cnt == 8)
				900	dmp_reg = &reg->u_end.isp2200.mailbox8;
				901
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	902	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	903	}
				904
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	905	dmp_reg = &reg->u.isp2100.unused_2[0];
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	906	for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	907	fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	908
				909	WRT_REG_WORD(&reg->ctrl_status, 0x00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	910	dmp_reg = &reg->risc_hw;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	911	for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	912	fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	913
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	914	WRT_REG_WORD(&reg->pcr, 0x2000);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	915	qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	916
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	917	WRT_REG_WORD(&reg->pcr, 0x2100);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	918	qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	919
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	920	WRT_REG_WORD(&reg->pcr, 0x2200);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	921	qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	922
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	923	WRT_REG_WORD(&reg->pcr, 0x2300);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	924	qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	925
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	926	WRT_REG_WORD(&reg->pcr, 0x2400);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	927	qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	928
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	929	WRT_REG_WORD(&reg->pcr, 0x2500);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	930	qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	931
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	932	WRT_REG_WORD(&reg->pcr, 0x2600);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	933	qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	934
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	935	WRT_REG_WORD(&reg->pcr, 0x2700);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	936	qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	937
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	938	WRT_REG_WORD(&reg->ctrl_status, 0x10);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	939	qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	940
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	941	WRT_REG_WORD(&reg->ctrl_status, 0x20);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	942	qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	943
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	944	WRT_REG_WORD(&reg->ctrl_status, 0x30);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	945	qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	946
				947	/* Reset the ISP. */
				948	WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
				949	}
				950
				951	for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
				952	rval == QLA_SUCCESS; cnt--) {
				953	if (cnt)
				954	udelay(100);
				955	else
				956	rval = QLA_FUNCTION_TIMEOUT;
				957	}
				958
				959	/* Pause RISC. */
				960	if (rval == QLA_SUCCESS && (IS_QLA2200(ha) \|\| (IS_QLA2100(ha) &&
				961	(RD_REG_WORD(&reg->mctr) & (BIT_1 \| BIT_0)) != 0))) {
				962
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	963	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	964	for (cnt = 30000;
				965	(RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				966	rval == QLA_SUCCESS; cnt--) {
				967	if (cnt)
				968	udelay(100);
				969	else
				970	rval = QLA_FUNCTION_TIMEOUT;
				971	}
				972	if (rval == QLA_SUCCESS) {
				973	/* Set memory configuration and timing. */
				974	if (IS_QLA2100(ha))
				975	WRT_REG_WORD(&reg->mctr, 0xf1);
				976	else
				977	WRT_REG_WORD(&reg->mctr, 0xf2);
				978	RD_REG_WORD(&reg->mctr); /* PCI Posting. */
				979
				980	/* Release RISC. */
				981	WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
				982	}
				983	}
				984
				985	if (rval == QLA_SUCCESS) {
				986	/* Get RISC SRAM. */
				987	risc_address = 0x1000;
				988	WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
				989	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				990	}
				991	for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
				992	cnt++, risc_address++) {
				993	WRT_MAILBOX_REG(ha, reg, 1, risc_address);
				994	WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
				995
				996	for (timer = 6000000; timer != 0; timer--) {
				997	/* Check for pending interrupts. */
				998	if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
				999	if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
				1000	set_bit(MBX_INTERRUPT,
				1001	&ha->mbx_cmd_flags);
				1002
				1003	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				1004	mb2 = RD_MAILBOX_REG(ha, reg, 2);
				1005
				1006	WRT_REG_WORD(&reg->semaphore, 0);
				1007	WRT_REG_WORD(&reg->hccr,
				1008	HCCR_CLR_RISC_INT);
				1009	RD_REG_WORD(&reg->hccr);
				1010	break;
				1011	}
				1012	WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
				1013	RD_REG_WORD(&reg->hccr);
				1014	}
				1015	udelay(5);
				1016	}
				1017
				1018	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
				1019	rval = mb0 & MBS_MASK;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	1020	fw->risc_ram[cnt] = htons(mb2);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	1021	} else {
				1022	rval = QLA_FUNCTION_FAILED;
				1023	}
				1024	}
				1025
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	1026	if (rval == QLA_SUCCESS)
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1027	qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	1028
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1029	qla2xxx_dump_post_process(base_vha, rval);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	1030
				1031	qla2100_fw_dump_failed:
				1032	if (!hardware_locked)
				1033	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				1034	}
				1035
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1036	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1037	qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1038	{
				1039	int rval;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1040	uint32_t cnt;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1041	uint32_t risc_address;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1042	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1043	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1044	uint32_t __iomem *dmp_reg;
				1045	uint32_t *iter_reg;
				1046	uint16_t __iomem *mbx_reg;
				1047	unsigned long flags;
				1048	struct qla24xx_fw_dump *fw;
				1049	uint32_t ext_mem_cnt;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1050	void *nxt;
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1051	void *nxt_chain;
				1052	uint32_t *last_chain = NULL;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1053	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1054
Atul Deshmukh	7ec0eff	2013-08-27 01:37:28 -0400	[diff] [blame]	1055	if (IS_P3P_TYPE(ha))
Giridhar Malavali	a908301	2010-04-12 17:59:55 -0700	[diff] [blame]	1056	return;
				1057
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1058	risc_address = ext_mem_cnt = 0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1059	flags = 0;
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	1060	ha->fw_dump_cap_flags = 0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1061
				1062	if (!hardware_locked)
				1063	spin_lock_irqsave(&ha->hardware_lock, flags);
				1064
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	1065	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1066	ql_log(ql_log_warn, vha, 0xd006,
				1067	"No buffer available for dump.\n");
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1068	goto qla24xx_fw_dump_failed;
				1069	}
				1070
				1071	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1072	ql_log(ql_log_warn, vha, 0xd007,
				1073	"Firmware has been previously dumped (%p) "
				1074	"-- ignoring request.\n",
				1075	ha->fw_dump);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1076	goto qla24xx_fw_dump_failed;
				1077	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	1078	fw = &ha->fw_dump->isp.isp24;
				1079	qla2xxx_prep_dump(ha, ha->fw_dump);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1080
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	1081	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1082
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	1083	/*
				1084	* Pause RISC. No need to track timeout, as resetting the chip
				1085	* is the right approach incase of pause timeout
				1086	*/
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	1087	qla24xx_pause_risc(reg, ha);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1088
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1089	/* Host interface registers. */
				1090	dmp_reg = &reg->flash_addr;
				1091	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				1092	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1093
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1094	/* Disable interrupts. */
				1095	WRT_REG_DWORD(&reg->ictrl, 0);
				1096	RD_REG_DWORD(&reg->ictrl);
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1097
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1098	/* Shadow registers. */
				1099	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1100	RD_REG_DWORD(&reg->iobase_addr);
				1101	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1102	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1103
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1104	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1105	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1106
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1107	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1108	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1109
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1110	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1111	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1112
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1113	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1114	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1115
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1116	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1117	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1118
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1119	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1120	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1121
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1122	/* Mailbox registers. */
				1123	mbx_reg = &reg->mailbox0;
				1124	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1125	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1126
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1127	/* Transfer sequence registers. */
				1128	iter_reg = fw->xseq_gp_reg;
				1129	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1130	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1131	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1132	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1133	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1134	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1135	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1136	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1137
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1138	qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
				1139	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1140
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1141	/* Receive sequence registers. */
				1142	iter_reg = fw->rseq_gp_reg;
				1143	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1144	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1145	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1146	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1147	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1148	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1149	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1150	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1151
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1152	qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
				1153	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1154	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1155
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1156	/* Command DMA registers. */
				1157	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1158
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1159	/* Queues. */
				1160	iter_reg = fw->req0_dma_reg;
				1161	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1162	dmp_reg = &reg->iobase_q;
				1163	for (cnt = 0; cnt < 7; cnt++)
				1164	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1165
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1166	iter_reg = fw->resp0_dma_reg;
				1167	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1168	dmp_reg = &reg->iobase_q;
				1169	for (cnt = 0; cnt < 7; cnt++)
				1170	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1171
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1172	iter_reg = fw->req1_dma_reg;
				1173	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1174	dmp_reg = &reg->iobase_q;
				1175	for (cnt = 0; cnt < 7; cnt++)
				1176	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1177
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1178	/* Transmit DMA registers. */
				1179	iter_reg = fw->xmt0_dma_reg;
				1180	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1181	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1182
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1183	iter_reg = fw->xmt1_dma_reg;
				1184	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1185	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1186
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1187	iter_reg = fw->xmt2_dma_reg;
				1188	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1189	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1190
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1191	iter_reg = fw->xmt3_dma_reg;
				1192	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1193	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1194
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1195	iter_reg = fw->xmt4_dma_reg;
				1196	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1197	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1198
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1199	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1200
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1201	/* Receive DMA registers. */
				1202	iter_reg = fw->rcvt0_data_dma_reg;
				1203	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1204	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1205
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1206	iter_reg = fw->rcvt1_data_dma_reg;
				1207	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1208	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1209
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1210	/* RISC registers. */
				1211	iter_reg = fw->risc_gp_reg;
				1212	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1213	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1214	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1215	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1216	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1217	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1218	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1219	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1220
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1221	/* Local memory controller registers. */
				1222	iter_reg = fw->lmc_reg;
				1223	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1224	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1225	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1226	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1227	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1228	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1229	qla24xx_read_window(reg, 0x3060, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1230
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1231	/* Fibre Protocol Module registers. */
				1232	iter_reg = fw->fpm_hdw_reg;
				1233	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1234	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1235	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1236	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1237	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1238	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1239	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1240	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1241	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1242	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1243	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1244	qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1245
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1246	/* Frame Buffer registers. */
				1247	iter_reg = fw->fb_hdw_reg;
				1248	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1249	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1250	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1251	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1252	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1253	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1254	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1255	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1256	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1257	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1258	qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1259
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1260	rval = qla24xx_soft_reset(ha);
				1261	if (rval != QLA_SUCCESS)
				1262	goto qla24xx_fw_dump_failed_0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1263
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1264	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	1265	&nxt);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1266	if (rval != QLA_SUCCESS)
				1267	goto qla24xx_fw_dump_failed_0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1268
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1269	nxt = qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1270
				1271	qla24xx_copy_eft(ha, nxt);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1272
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1273	nxt_chain = (void *)ha->fw_dump + ha->chain_offset;
				1274	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
				1275	if (last_chain) {
				1276	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				1277	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				1278	}
				1279
				1280	/* Adjust valid length. */
				1281	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1282
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1283	qla24xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1284	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1285
				1286	qla24xx_fw_dump_failed:
				1287	if (!hardware_locked)
				1288	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				1289	}
				1290
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1291	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1292	qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1293	{
				1294	int rval;
				1295	uint32_t cnt;
				1296	uint32_t risc_address;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1297	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1298	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1299	uint32_t __iomem *dmp_reg;
				1300	uint32_t *iter_reg;
				1301	uint16_t __iomem *mbx_reg;
				1302	unsigned long flags;
				1303	struct qla25xx_fw_dump *fw;
				1304	uint32_t ext_mem_cnt;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1305	void nxt, nxt_chain;
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1306	uint32_t *last_chain = NULL;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1307	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1308
				1309	risc_address = ext_mem_cnt = 0;
				1310	flags = 0;
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	1311	ha->fw_dump_cap_flags = 0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1312
				1313	if (!hardware_locked)
				1314	spin_lock_irqsave(&ha->hardware_lock, flags);
				1315
				1316	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1317	ql_log(ql_log_warn, vha, 0xd008,
				1318	"No buffer available for dump.\n");
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1319	goto qla25xx_fw_dump_failed;
				1320	}
				1321
				1322	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1323	ql_log(ql_log_warn, vha, 0xd009,
				1324	"Firmware has been previously dumped (%p) "
				1325	"-- ignoring request.\n",
				1326	ha->fw_dump);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1327	goto qla25xx_fw_dump_failed;
				1328	}
				1329	fw = &ha->fw_dump->isp.isp25;
				1330	qla2xxx_prep_dump(ha, ha->fw_dump);
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1331	ha->fw_dump->version = __constant_htonl(2);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1332
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1333	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1334
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	1335	/*
				1336	* Pause RISC. No need to track timeout, as resetting the chip
				1337	* is the right approach incase of pause timeout
				1338	*/
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	1339	qla24xx_pause_risc(reg, ha);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1340
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1341	/* Host/Risc registers. */
				1342	iter_reg = fw->host_risc_reg;
				1343	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				1344	qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				1345
				1346	/* PCIe registers. */
				1347	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				1348	RD_REG_DWORD(&reg->iobase_addr);
				1349	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				1350	dmp_reg = &reg->iobase_c4;
				1351	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
				1352	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
				1353	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				1354	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1355
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1356	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				1357	RD_REG_DWORD(&reg->iobase_window);
				1358
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1359	/* Host interface registers. */
				1360	dmp_reg = &reg->flash_addr;
				1361	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				1362	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1363
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1364	/* Disable interrupts. */
				1365	WRT_REG_DWORD(&reg->ictrl, 0);
				1366	RD_REG_DWORD(&reg->ictrl);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1367
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1368	/* Shadow registers. */
				1369	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1370	RD_REG_DWORD(&reg->iobase_addr);
				1371	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1372	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1373
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1374	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1375	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1376
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1377	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1378	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1379
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1380	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1381	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1382
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1383	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1384	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1385
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1386	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1387	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1388
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1389	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1390	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1391
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1392	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				1393	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1394
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1395	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				1396	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1397
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1398	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				1399	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1400
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1401	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				1402	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1403
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1404	/* RISC I/O register. */
				1405	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				1406	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1407
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1408	/* Mailbox registers. */
				1409	mbx_reg = &reg->mailbox0;
				1410	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1411	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1412
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1413	/* Transfer sequence registers. */
				1414	iter_reg = fw->xseq_gp_reg;
				1415	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1416	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1417	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1418	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1419	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1420	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1421	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1422	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1423
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1424	iter_reg = fw->xseq_0_reg;
				1425	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				1426	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				1427	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1428
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1429	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1430
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1431	/* Receive sequence registers. */
				1432	iter_reg = fw->rseq_gp_reg;
				1433	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1434	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1435	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1436	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1437	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1438	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1439	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1440	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1441
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1442	iter_reg = fw->rseq_0_reg;
				1443	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				1444	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1445
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1446	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1447	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1448
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1449	/* Auxiliary sequence registers. */
				1450	iter_reg = fw->aseq_gp_reg;
				1451	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				1452	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				1453	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				1454	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				1455	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				1456	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				1457	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				1458	qla24xx_read_window(reg, 0xB070, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1459
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1460	iter_reg = fw->aseq_0_reg;
				1461	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				1462	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1463
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1464	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				1465	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1466
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1467	/* Command DMA registers. */
				1468	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1469
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1470	/* Queues. */
				1471	iter_reg = fw->req0_dma_reg;
				1472	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1473	dmp_reg = &reg->iobase_q;
				1474	for (cnt = 0; cnt < 7; cnt++)
				1475	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1476
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1477	iter_reg = fw->resp0_dma_reg;
				1478	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1479	dmp_reg = &reg->iobase_q;
				1480	for (cnt = 0; cnt < 7; cnt++)
				1481	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1482
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1483	iter_reg = fw->req1_dma_reg;
				1484	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1485	dmp_reg = &reg->iobase_q;
				1486	for (cnt = 0; cnt < 7; cnt++)
				1487	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1488
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1489	/* Transmit DMA registers. */
				1490	iter_reg = fw->xmt0_dma_reg;
				1491	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1492	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1493
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1494	iter_reg = fw->xmt1_dma_reg;
				1495	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1496	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1497
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1498	iter_reg = fw->xmt2_dma_reg;
				1499	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1500	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1501
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1502	iter_reg = fw->xmt3_dma_reg;
				1503	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1504	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1505
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1506	iter_reg = fw->xmt4_dma_reg;
				1507	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1508	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1509
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1510	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1511
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1512	/* Receive DMA registers. */
				1513	iter_reg = fw->rcvt0_data_dma_reg;
				1514	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1515	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1516
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1517	iter_reg = fw->rcvt1_data_dma_reg;
				1518	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1519	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1520
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1521	/* RISC registers. */
				1522	iter_reg = fw->risc_gp_reg;
				1523	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1524	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1525	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1526	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1527	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1528	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1529	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1530	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1531
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1532	/* Local memory controller registers. */
				1533	iter_reg = fw->lmc_reg;
				1534	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1535	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1536	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1537	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1538	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1539	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1540	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				1541	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1542
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1543	/* Fibre Protocol Module registers. */
				1544	iter_reg = fw->fpm_hdw_reg;
				1545	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1546	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1547	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1548	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1549	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1550	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1551	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1552	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1553	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1554	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1555	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1556	qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1557
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1558	/* Frame Buffer registers. */
				1559	iter_reg = fw->fb_hdw_reg;
				1560	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1561	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1562	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1563	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1564	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1565	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1566	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1567	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1568	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1569	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1570	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				1571	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1572
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1573	/* Multi queue registers */
				1574	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				1575	&last_chain);
				1576
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1577	rval = qla24xx_soft_reset(ha);
				1578	if (rval != QLA_SUCCESS)
				1579	goto qla25xx_fw_dump_failed_0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1580
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1581	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	1582	&nxt);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1583	if (rval != QLA_SUCCESS)
				1584	goto qla25xx_fw_dump_failed_0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1585
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1586	nxt = qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1587
Bart Van Assche	7f544d0	2013-06-25 11:27:27 -0400	[diff] [blame]	1588	qla24xx_copy_eft(ha, nxt);
Andrew Vasquez	df613b9	2008-01-17 09:02:17 -0800	[diff] [blame]	1589
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1590	/* Chain entries -- started with MQ. */
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1591	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				1592	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1593	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1594	if (last_chain) {
				1595	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				1596	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				1597	}
Andrew Vasquez	df613b9	2008-01-17 09:02:17 -0800	[diff] [blame]	1598
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1599	/* Adjust valid length. */
				1600	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1601
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1602	qla25xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1603	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1604
				1605	qla25xx_fw_dump_failed:
				1606	if (!hardware_locked)
				1607	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				1608	}
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1609
				1610	void
				1611	qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
				1612	{
				1613	int rval;
				1614	uint32_t cnt;
				1615	uint32_t risc_address;
				1616	struct qla_hw_data *ha = vha->hw;
				1617	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1618	uint32_t __iomem *dmp_reg;
				1619	uint32_t *iter_reg;
				1620	uint16_t __iomem *mbx_reg;
				1621	unsigned long flags;
				1622	struct qla81xx_fw_dump *fw;
				1623	uint32_t ext_mem_cnt;
				1624	void nxt, nxt_chain;
				1625	uint32_t *last_chain = NULL;
				1626	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
				1627
				1628	risc_address = ext_mem_cnt = 0;
				1629	flags = 0;
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	1630	ha->fw_dump_cap_flags = 0;
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1631
				1632	if (!hardware_locked)
				1633	spin_lock_irqsave(&ha->hardware_lock, flags);
				1634
				1635	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1636	ql_log(ql_log_warn, vha, 0xd00a,
				1637	"No buffer available for dump.\n");
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1638	goto qla81xx_fw_dump_failed;
				1639	}
				1640
				1641	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1642	ql_log(ql_log_warn, vha, 0xd00b,
				1643	"Firmware has been previously dumped (%p) "
				1644	"-- ignoring request.\n",
				1645	ha->fw_dump);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1646	goto qla81xx_fw_dump_failed;
				1647	}
				1648	fw = &ha->fw_dump->isp.isp81;
				1649	qla2xxx_prep_dump(ha, ha->fw_dump);
				1650
				1651	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1652
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	1653	/*
				1654	* Pause RISC. No need to track timeout, as resetting the chip
				1655	* is the right approach incase of pause timeout
				1656	*/
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	1657	qla24xx_pause_risc(reg, ha);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1658
				1659	/* Host/Risc registers. */
				1660	iter_reg = fw->host_risc_reg;
				1661	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				1662	qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				1663
				1664	/* PCIe registers. */
				1665	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				1666	RD_REG_DWORD(&reg->iobase_addr);
				1667	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				1668	dmp_reg = &reg->iobase_c4;
				1669	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
				1670	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
				1671	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				1672	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
				1673
				1674	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				1675	RD_REG_DWORD(&reg->iobase_window);
				1676
				1677	/* Host interface registers. */
				1678	dmp_reg = &reg->flash_addr;
				1679	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				1680	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
				1681
				1682	/* Disable interrupts. */
				1683	WRT_REG_DWORD(&reg->ictrl, 0);
				1684	RD_REG_DWORD(&reg->ictrl);
				1685
				1686	/* Shadow registers. */
				1687	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1688	RD_REG_DWORD(&reg->iobase_addr);
				1689	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1690	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1691
				1692	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1693	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1694
				1695	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1696	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1697
				1698	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1699	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1700
				1701	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1702	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1703
				1704	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1705	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1706
				1707	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1708	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1709
				1710	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				1711	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1712
				1713	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				1714	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1715
				1716	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				1717	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1718
				1719	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				1720	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1721
				1722	/* RISC I/O register. */
				1723	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				1724	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
				1725
				1726	/* Mailbox registers. */
				1727	mbx_reg = &reg->mailbox0;
				1728	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1729	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
				1730
				1731	/* Transfer sequence registers. */
				1732	iter_reg = fw->xseq_gp_reg;
				1733	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1734	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1735	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1736	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1737	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1738	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1739	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1740	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
				1741
				1742	iter_reg = fw->xseq_0_reg;
				1743	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				1744	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				1745	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
				1746
				1747	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
				1748
				1749	/* Receive sequence registers. */
				1750	iter_reg = fw->rseq_gp_reg;
				1751	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1752	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1753	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1754	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1755	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1756	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1757	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1758	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
				1759
				1760	iter_reg = fw->rseq_0_reg;
				1761	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				1762	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
				1763
				1764	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1765	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
				1766
				1767	/* Auxiliary sequence registers. */
				1768	iter_reg = fw->aseq_gp_reg;
				1769	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				1770	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				1771	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				1772	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				1773	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				1774	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				1775	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				1776	qla24xx_read_window(reg, 0xB070, 16, iter_reg);
				1777
				1778	iter_reg = fw->aseq_0_reg;
				1779	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				1780	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
				1781
				1782	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				1783	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
				1784
				1785	/* Command DMA registers. */
				1786	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
				1787
				1788	/* Queues. */
				1789	iter_reg = fw->req0_dma_reg;
				1790	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1791	dmp_reg = &reg->iobase_q;
				1792	for (cnt = 0; cnt < 7; cnt++)
				1793	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				1794
				1795	iter_reg = fw->resp0_dma_reg;
				1796	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1797	dmp_reg = &reg->iobase_q;
				1798	for (cnt = 0; cnt < 7; cnt++)
				1799	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				1800
				1801	iter_reg = fw->req1_dma_reg;
				1802	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1803	dmp_reg = &reg->iobase_q;
				1804	for (cnt = 0; cnt < 7; cnt++)
				1805	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				1806
				1807	/* Transmit DMA registers. */
				1808	iter_reg = fw->xmt0_dma_reg;
				1809	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1810	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
				1811
				1812	iter_reg = fw->xmt1_dma_reg;
				1813	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1814	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
				1815
				1816	iter_reg = fw->xmt2_dma_reg;
				1817	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1818	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
				1819
				1820	iter_reg = fw->xmt3_dma_reg;
				1821	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1822	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
				1823
				1824	iter_reg = fw->xmt4_dma_reg;
				1825	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1826	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
				1827
				1828	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
				1829
				1830	/* Receive DMA registers. */
				1831	iter_reg = fw->rcvt0_data_dma_reg;
				1832	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1833	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
				1834
				1835	iter_reg = fw->rcvt1_data_dma_reg;
				1836	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1837	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
				1838
				1839	/* RISC registers. */
				1840	iter_reg = fw->risc_gp_reg;
				1841	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1842	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1843	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1844	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1845	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1846	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1847	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1848	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
				1849
				1850	/* Local memory controller registers. */
				1851	iter_reg = fw->lmc_reg;
				1852	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1853	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1854	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1855	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1856	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1857	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1858	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				1859	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
				1860
				1861	/* Fibre Protocol Module registers. */
				1862	iter_reg = fw->fpm_hdw_reg;
				1863	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1864	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1865	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1866	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1867	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1868	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1869	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1870	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1871	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1872	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1873	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1874	iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
				1875	iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
				1876	qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
				1877
				1878	/* Frame Buffer registers. */
				1879	iter_reg = fw->fb_hdw_reg;
				1880	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1881	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1882	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1883	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1884	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1885	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1886	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1887	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1888	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1889	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1890	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				1891	iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
				1892	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
				1893
				1894	/* Multi queue registers */
				1895	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				1896	&last_chain);
				1897
				1898	rval = qla24xx_soft_reset(ha);
				1899	if (rval != QLA_SUCCESS)
				1900	goto qla81xx_fw_dump_failed_0;
				1901
				1902	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
				1903	&nxt);
				1904	if (rval != QLA_SUCCESS)
				1905	goto qla81xx_fw_dump_failed_0;
				1906
				1907	nxt = qla2xxx_copy_queues(ha, nxt);
				1908
Bart Van Assche	7f544d0	2013-06-25 11:27:27 -0400	[diff] [blame]	1909	qla24xx_copy_eft(ha, nxt);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1910
				1911	/* Chain entries -- started with MQ. */
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1912	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				1913	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1914	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1915	if (last_chain) {
				1916	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				1917	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				1918	}
				1919
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1920	/* Adjust valid length. */
				1921	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1922
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1923	qla81xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1924	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1925
				1926	qla81xx_fw_dump_failed:
				1927	if (!hardware_locked)
				1928	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				1929	}
				1930
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1931	void
				1932	qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
				1933	{
				1934	int rval;
				1935	uint32_t cnt, reg_data;
				1936	uint32_t risc_address;
				1937	struct qla_hw_data *ha = vha->hw;
				1938	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1939	uint32_t __iomem *dmp_reg;
				1940	uint32_t *iter_reg;
				1941	uint16_t __iomem *mbx_reg;
				1942	unsigned long flags;
				1943	struct qla83xx_fw_dump *fw;
				1944	uint32_t ext_mem_cnt;
				1945	void nxt, nxt_chain;
				1946	uint32_t *last_chain = NULL;
				1947	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
				1948
				1949	risc_address = ext_mem_cnt = 0;
				1950	flags = 0;
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	1951	ha->fw_dump_cap_flags = 0;
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1952
				1953	if (!hardware_locked)
				1954	spin_lock_irqsave(&ha->hardware_lock, flags);
				1955
				1956	if (!ha->fw_dump) {
				1957	ql_log(ql_log_warn, vha, 0xd00c,
				1958	"No buffer available for dump!!!\n");
				1959	goto qla83xx_fw_dump_failed;
				1960	}
				1961
				1962	if (ha->fw_dumped) {
				1963	ql_log(ql_log_warn, vha, 0xd00d,
				1964	"Firmware has been previously dumped (%p) -- ignoring "
				1965	"request...\n", ha->fw_dump);
				1966	goto qla83xx_fw_dump_failed;
				1967	}
				1968	fw = &ha->fw_dump->isp.isp83;
				1969	qla2xxx_prep_dump(ha, ha->fw_dump);
				1970
				1971	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1972
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	1973	/*
				1974	* Pause RISC. No need to track timeout, as resetting the chip
				1975	* is the right approach incase of pause timeout
				1976	*/
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	1977	qla24xx_pause_risc(reg, ha);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1978
				1979	WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
				1980	dmp_reg = &reg->iobase_window;
				1981	reg_data = RD_REG_DWORD(dmp_reg);
				1982	WRT_REG_DWORD(dmp_reg, 0);
				1983
				1984	dmp_reg = &reg->unused_4_1[0];
				1985	reg_data = RD_REG_DWORD(dmp_reg);
				1986	WRT_REG_DWORD(dmp_reg, 0);
				1987
				1988	WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
				1989	dmp_reg = &reg->unused_4_1[2];
				1990	reg_data = RD_REG_DWORD(dmp_reg);
				1991	WRT_REG_DWORD(dmp_reg, 0);
				1992
				1993	/* select PCR and disable ecc checking and correction */
				1994	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1995	RD_REG_DWORD(&reg->iobase_addr);
				1996	WRT_REG_DWORD(&reg->iobase_select, 0x60000000); /* write to F0h = PCR */
				1997
				1998	/* Host/Risc registers. */
				1999	iter_reg = fw->host_risc_reg;
				2000	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				2001	iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				2002	qla24xx_read_window(reg, 0x7040, 16, iter_reg);
				2003
				2004	/* PCIe registers. */
				2005	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				2006	RD_REG_DWORD(&reg->iobase_addr);
				2007	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				2008	dmp_reg = &reg->iobase_c4;
				2009	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
				2010	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
				2011	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				2012	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
				2013
				2014	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				2015	RD_REG_DWORD(&reg->iobase_window);
				2016
				2017	/* Host interface registers. */
				2018	dmp_reg = &reg->flash_addr;
				2019	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				2020	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
				2021
				2022	/* Disable interrupts. */
				2023	WRT_REG_DWORD(&reg->ictrl, 0);
				2024	RD_REG_DWORD(&reg->ictrl);
				2025
				2026	/* Shadow registers. */
				2027	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				2028	RD_REG_DWORD(&reg->iobase_addr);
				2029	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				2030	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2031
				2032	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				2033	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2034
				2035	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				2036	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2037
				2038	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				2039	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2040
				2041	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				2042	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2043
				2044	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				2045	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2046
				2047	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				2048	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2049
				2050	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				2051	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2052
				2053	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				2054	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2055
				2056	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				2057	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2058
				2059	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				2060	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2061
				2062	/* RISC I/O register. */
				2063	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				2064	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
				2065
				2066	/* Mailbox registers. */
				2067	mbx_reg = &reg->mailbox0;
				2068	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				2069	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
				2070
				2071	/* Transfer sequence registers. */
				2072	iter_reg = fw->xseq_gp_reg;
				2073	iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg);
				2074	iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg);
				2075	iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg);
				2076	iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg);
				2077	iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg);
				2078	iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg);
				2079	iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg);
				2080	iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg);
				2081	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				2082	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				2083	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				2084	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				2085	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				2086	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				2087	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				2088	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
				2089
				2090	iter_reg = fw->xseq_0_reg;
				2091	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				2092	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				2093	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
				2094
				2095	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
				2096
				2097	qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg);
				2098
				2099	/* Receive sequence registers. */
				2100	iter_reg = fw->rseq_gp_reg;
				2101	iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg);
				2102	iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg);
				2103	iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg);
				2104	iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg);
				2105	iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg);
				2106	iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg);
				2107	iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg);
				2108	iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg);
				2109	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				2110	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				2111	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				2112	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				2113	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				2114	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				2115	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				2116	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
				2117
				2118	iter_reg = fw->rseq_0_reg;
				2119	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				2120	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
				2121
				2122	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				2123	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
				2124	qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg);
				2125
				2126	/* Auxiliary sequence registers. */
				2127	iter_reg = fw->aseq_gp_reg;
				2128	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				2129	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				2130	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				2131	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				2132	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				2133	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				2134	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				2135	iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg);
				2136	iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg);
				2137	iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg);
				2138	iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg);
				2139	iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg);
				2140	iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg);
				2141	iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg);
				2142	iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg);
				2143	qla24xx_read_window(reg, 0xB170, 16, iter_reg);
				2144
				2145	iter_reg = fw->aseq_0_reg;
				2146	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				2147	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
				2148
				2149	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				2150	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
				2151	qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg);
				2152
				2153	/* Command DMA registers. */
				2154	iter_reg = fw->cmd_dma_reg;
				2155	iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg);
				2156	iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg);
				2157	iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg);
				2158	qla24xx_read_window(reg, 0x71F0, 16, iter_reg);
				2159
				2160	/* Queues. */
				2161	iter_reg = fw->req0_dma_reg;
				2162	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				2163	dmp_reg = &reg->iobase_q;
				2164	for (cnt = 0; cnt < 7; cnt++)
				2165	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				2166
				2167	iter_reg = fw->resp0_dma_reg;
				2168	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				2169	dmp_reg = &reg->iobase_q;
				2170	for (cnt = 0; cnt < 7; cnt++)
				2171	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				2172
				2173	iter_reg = fw->req1_dma_reg;
				2174	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				2175	dmp_reg = &reg->iobase_q;
				2176	for (cnt = 0; cnt < 7; cnt++)
				2177	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				2178
				2179	/* Transmit DMA registers. */
				2180	iter_reg = fw->xmt0_dma_reg;
				2181	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				2182	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
				2183
				2184	iter_reg = fw->xmt1_dma_reg;
				2185	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				2186	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
				2187
				2188	iter_reg = fw->xmt2_dma_reg;
				2189	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				2190	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
				2191
				2192	iter_reg = fw->xmt3_dma_reg;
				2193	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				2194	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
				2195
				2196	iter_reg = fw->xmt4_dma_reg;
				2197	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				2198	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
				2199
				2200	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
				2201
				2202	/* Receive DMA registers. */
				2203	iter_reg = fw->rcvt0_data_dma_reg;
				2204	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				2205	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
				2206
				2207	iter_reg = fw->rcvt1_data_dma_reg;
				2208	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				2209	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
				2210
				2211	/* RISC registers. */
				2212	iter_reg = fw->risc_gp_reg;
				2213	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				2214	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				2215	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				2216	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				2217	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				2218	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				2219	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				2220	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
				2221
				2222	/* Local memory controller registers. */
				2223	iter_reg = fw->lmc_reg;
				2224	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				2225	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				2226	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				2227	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				2228	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				2229	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				2230	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				2231	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
				2232
				2233	/* Fibre Protocol Module registers. */
				2234	iter_reg = fw->fpm_hdw_reg;
				2235	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				2236	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				2237	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				2238	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				2239	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				2240	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				2241	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				2242	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				2243	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				2244	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				2245	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				2246	iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
				2247	iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
				2248	iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
				2249	iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg);
				2250	qla24xx_read_window(reg, 0x40F0, 16, iter_reg);
				2251
				2252	/* RQ0 Array registers. */
				2253	iter_reg = fw->rq0_array_reg;
				2254	iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg);
				2255	iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg);
				2256	iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg);
				2257	iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg);
				2258	iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg);
				2259	iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg);
				2260	iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg);
				2261	iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg);
				2262	iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg);
				2263	iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg);
				2264	iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg);
				2265	iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg);
				2266	iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg);
				2267	iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg);
				2268	iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg);
				2269	qla24xx_read_window(reg, 0x5CF0, 16, iter_reg);
				2270
				2271	/* RQ1 Array registers. */
				2272	iter_reg = fw->rq1_array_reg;
				2273	iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg);
				2274	iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg);
				2275	iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg);
				2276	iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg);
				2277	iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg);
				2278	iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg);
				2279	iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg);
				2280	iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg);
				2281	iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg);
				2282	iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg);
				2283	iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg);
				2284	iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg);
				2285	iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg);
				2286	iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg);
				2287	iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg);
				2288	qla24xx_read_window(reg, 0x5DF0, 16, iter_reg);
				2289
				2290	/* RP0 Array registers. */
				2291	iter_reg = fw->rp0_array_reg;
				2292	iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg);
				2293	iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg);
				2294	iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg);
				2295	iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg);
				2296	iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg);
				2297	iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg);
				2298	iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg);
				2299	iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg);
				2300	iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg);
				2301	iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg);
				2302	iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg);
				2303	iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg);
				2304	iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg);
				2305	iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg);
				2306	iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg);
				2307	qla24xx_read_window(reg, 0x5EF0, 16, iter_reg);
				2308
				2309	/* RP1 Array registers. */
				2310	iter_reg = fw->rp1_array_reg;
				2311	iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg);
				2312	iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg);
				2313	iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg);
				2314	iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg);
				2315	iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg);
				2316	iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg);
				2317	iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg);
				2318	iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg);
				2319	iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg);
				2320	iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg);
				2321	iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg);
				2322	iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg);
				2323	iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg);
				2324	iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg);
				2325	iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg);
				2326	qla24xx_read_window(reg, 0x5FF0, 16, iter_reg);
				2327
				2328	iter_reg = fw->at0_array_reg;
				2329	iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg);
				2330	iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg);
				2331	iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg);
				2332	iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg);
				2333	iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg);
				2334	iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg);
				2335	iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg);
				2336	qla24xx_read_window(reg, 0x70F0, 16, iter_reg);
				2337
				2338	/* I/O Queue Control registers. */
				2339	qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg);
				2340
				2341	/* Frame Buffer registers. */
				2342	iter_reg = fw->fb_hdw_reg;
				2343	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				2344	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				2345	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				2346	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				2347	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				2348	iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg);
				2349	iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg);
				2350	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				2351	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				2352	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				2353	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				2354	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				2355	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				2356	iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
				2357	iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg);
				2358	iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg);
				2359	iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg);
				2360	iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg);
				2361	iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg);
				2362	iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg);
				2363	iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg);
				2364	iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg);
				2365	iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg);
				2366	iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg);
				2367	iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg);
				2368	iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg);
				2369	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
				2370
				2371	/* Multi queue registers */
				2372	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				2373	&last_chain);
				2374
				2375	rval = qla24xx_soft_reset(ha);
				2376	if (rval != QLA_SUCCESS) {
				2377	ql_log(ql_log_warn, vha, 0xd00e,
				2378	"SOFT RESET FAILED, forcing continuation of dump!!!\n");
				2379	rval = QLA_SUCCESS;
				2380
				2381	ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n");
				2382
				2383	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
				2384	RD_REG_DWORD(&reg->hccr);
				2385
				2386	WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
				2387	RD_REG_DWORD(&reg->hccr);
				2388
				2389	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
				2390	RD_REG_DWORD(&reg->hccr);
				2391
				2392	for (cnt = 30000; cnt && (RD_REG_WORD(&reg->mailbox0)); cnt--)
				2393	udelay(5);
				2394
				2395	if (!cnt) {
				2396	nxt = fw->code_ram;
Saurav Kashyap	8c0bc70	2012-11-21 02:40:35 -0500	[diff] [blame]	2397	nxt += sizeof(fw->code_ram);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2398	nxt += (ha->fw_memory_size - 0x100000 + 1);
				2399	goto copy_queue;
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	2400	} else {
				2401	set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2402	ql_log(ql_log_warn, vha, 0xd010,
				2403	"bigger hammer success?\n");
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	2404	}
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2405	}
				2406
				2407	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
				2408	&nxt);
				2409	if (rval != QLA_SUCCESS)
				2410	goto qla83xx_fw_dump_failed_0;
				2411
				2412	copy_queue:
				2413	nxt = qla2xxx_copy_queues(ha, nxt);
				2414
Bart Van Assche	7f544d0	2013-06-25 11:27:27 -0400	[diff] [blame]	2415	qla24xx_copy_eft(ha, nxt);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2416
				2417	/* Chain entries -- started with MQ. */
				2418	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				2419	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	2420	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2421	if (last_chain) {
				2422	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				2423	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				2424	}
				2425
				2426	/* Adjust valid length. */
				2427	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				2428
				2429	qla83xx_fw_dump_failed_0:
				2430	qla2xxx_dump_post_process(base_vha, rval);
				2431
				2432	qla83xx_fw_dump_failed:
				2433	if (!hardware_locked)
				2434	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				2435	}
				2436
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	2437	/****************************************************************************/
				2438	/* Driver Debug Functions. */
				2439	/****************************************************************************/
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2440
				2441	static inline int
				2442	ql_mask_match(uint32_t level)
				2443	{
				2444	if (ql2xextended_error_logging == 1)
				2445	ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
				2446	return (level & ql2xextended_error_logging) == level;
				2447	}
				2448
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2449	/*
				2450	* This function is for formatting and logging debug information.
				2451	* It is to be used when vha is available. It formats the message
				2452	* and logs it to the messages file.
				2453	* parameters:
				2454	* level: The level of the debug messages to be printed.
				2455	* If ql2xextended_error_logging value is correctly set,
				2456	* this message will appear in the messages file.
				2457	* vha: Pointer to the scsi_qla_host_t.
				2458	* id: This is a unique identifier for the level. It identifies the
				2459	* part of the code from where the message originated.
				2460	* msg: The message to be displayed.
				2461	*/
				2462	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2463	ql_dbg(uint32_t level, scsi_qla_host_t vha, int32_t id, const char fmt, ...)
				2464	{
				2465	va_list va;
				2466	struct va_format vaf;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2467
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2468	if (!ql_mask_match(level))
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2469	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2470
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2471	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2472
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2473	vaf.fmt = fmt;
				2474	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2475
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2476	if (vha != NULL) {
				2477	const struct pci_dev *pdev = vha->hw->pdev;
				2478	/* <module-name> <pci-name> <msg-id>:<host> Message */
				2479	pr_warn("%s [%s]-%04x:%ld: %pV",
				2480	QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset,
				2481	vha->host_no, &vaf);
				2482	} else {
				2483	pr_warn("%s [%s]-%04x: : %pV",
				2484	QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2485	}
				2486
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2487	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2488
				2489	}
				2490
				2491	/*
				2492	* This function is for formatting and logging debug information.
Masanari Iida	d6a0358	2012-08-22 14:20:58 -0400	[diff] [blame]	2493	* It is to be used when vha is not available and pci is available,
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2494	* i.e., before host allocation. It formats the message and logs it
				2495	* to the messages file.
				2496	* parameters:
				2497	* level: The level of the debug messages to be printed.
				2498	* If ql2xextended_error_logging value is correctly set,
				2499	* this message will appear in the messages file.
				2500	* pdev: Pointer to the struct pci_dev.
				2501	* id: This is a unique id for the level. It identifies the part
				2502	* of the code from where the message originated.
				2503	* msg: The message to be displayed.
				2504	*/
				2505	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2506	ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
				2507	const char *fmt, ...)
				2508	{
				2509	va_list va;
				2510	struct va_format vaf;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2511
				2512	if (pdev == NULL)
				2513	return;
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2514	if (!ql_mask_match(level))
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2515	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2516
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2517	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2518
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2519	vaf.fmt = fmt;
				2520	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2521
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2522	/* <module-name> <dev-name>:<msg-id> Message */
				2523	pr_warn("%s [%s]-%04x: : %pV",
				2524	QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2525
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2526	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2527	}
				2528
				2529	/*
				2530	* This function is for formatting and logging log messages.
				2531	* It is to be used when vha is available. It formats the message
				2532	* and logs it to the messages file. All the messages will be logged
				2533	* irrespective of value of ql2xextended_error_logging.
				2534	* parameters:
				2535	* level: The level of the log messages to be printed in the
				2536	* messages file.
				2537	* vha: Pointer to the scsi_qla_host_t
				2538	* id: This is a unique id for the level. It identifies the
				2539	* part of the code from where the message originated.
				2540	* msg: The message to be displayed.
				2541	*/
				2542	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2543	ql_log(uint32_t level, scsi_qla_host_t vha, int32_t id, const char fmt, ...)
				2544	{
				2545	va_list va;
				2546	struct va_format vaf;
				2547	char pbuf[128];
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2548
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2549	if (level > ql_errlev)
				2550	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2551
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2552	if (vha != NULL) {
				2553	const struct pci_dev *pdev = vha->hw->pdev;
				2554	/* <module-name> <msg-id>:<host> Message */
				2555	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ",
				2556	QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no);
				2557	} else {
				2558	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
				2559	QL_MSGHDR, "0000:00:00.0", id);
				2560	}
				2561	pbuf[sizeof(pbuf) - 1] = 0;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2562
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2563	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2564
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2565	vaf.fmt = fmt;
				2566	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2567
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2568	switch (level) {
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2569	case ql_log_fatal: /* FATAL LOG */
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2570	pr_crit("%s%pV", pbuf, &vaf);
				2571	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2572	case ql_log_warn:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2573	pr_err("%s%pV", pbuf, &vaf);
				2574	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2575	case ql_log_info:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2576	pr_warn("%s%pV", pbuf, &vaf);
				2577	break;
				2578	default:
				2579	pr_info("%s%pV", pbuf, &vaf);
				2580	break;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2581	}
				2582
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2583	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2584	}
				2585
				2586	/*
				2587	* This function is for formatting and logging log messages.
Masanari Iida	d6a0358	2012-08-22 14:20:58 -0400	[diff] [blame]	2588	* It is to be used when vha is not available and pci is available,
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2589	* i.e., before host allocation. It formats the message and logs
				2590	* it to the messages file. All the messages are logged irrespective
				2591	* of the value of ql2xextended_error_logging.
				2592	* parameters:
				2593	* level: The level of the log messages to be printed in the
				2594	* messages file.
				2595	* pdev: Pointer to the struct pci_dev.
				2596	* id: This is a unique id for the level. It identifies the
				2597	* part of the code from where the message originated.
				2598	* msg: The message to be displayed.
				2599	*/
				2600	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2601	ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
				2602	const char *fmt, ...)
				2603	{
				2604	va_list va;
				2605	struct va_format vaf;
				2606	char pbuf[128];
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2607
				2608	if (pdev == NULL)
				2609	return;
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2610	if (level > ql_errlev)
				2611	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2612
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2613	/* <module-name> <dev-name>:<msg-id> Message */
				2614	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
				2615	QL_MSGHDR, dev_name(&(pdev->dev)), id);
				2616	pbuf[sizeof(pbuf) - 1] = 0;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2617
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2618	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2619
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2620	vaf.fmt = fmt;
				2621	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2622
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2623	switch (level) {
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2624	case ql_log_fatal: /* FATAL LOG */
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2625	pr_crit("%s%pV", pbuf, &vaf);
				2626	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2627	case ql_log_warn:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2628	pr_err("%s%pV", pbuf, &vaf);
				2629	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2630	case ql_log_info:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2631	pr_warn("%s%pV", pbuf, &vaf);
				2632	break;
				2633	default:
				2634	pr_info("%s%pV", pbuf, &vaf);
				2635	break;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2636	}
				2637
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2638	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2639	}
				2640
				2641	void
				2642	ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
				2643	{
				2644	int i;
				2645	struct qla_hw_data *ha = vha->hw;
				2646	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
				2647	struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
				2648	struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
				2649	uint16_t __iomem *mbx_reg;
				2650
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2651	if (!ql_mask_match(level))
				2652	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2653
Atul Deshmukh	7ec0eff	2013-08-27 01:37:28 -0400	[diff] [blame]	2654	if (IS_P3P_TYPE(ha))
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2655	mbx_reg = &reg82->mailbox_in[0];
				2656	else if (IS_FWI2_CAPABLE(ha))
				2657	mbx_reg = &reg24->mailbox0;
				2658	else
				2659	mbx_reg = MAILBOX_REG(ha, reg, 0);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2660
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2661	ql_dbg(level, vha, id, "Mailbox registers:\n");
				2662	for (i = 0; i < 6; i++)
				2663	ql_dbg(level, vha, id,
				2664	"mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2665	}
				2666
				2667
				2668	void
				2669	ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
				2670	uint8_t *b, uint32_t size)
				2671	{
				2672	uint32_t cnt;
				2673	uint8_t c;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2674
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2675	if (!ql_mask_match(level))
				2676	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2677
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2678	ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 "
				2679	"9 Ah Bh Ch Dh Eh Fh\n");
				2680	ql_dbg(level, vha, id, "----------------------------------"
				2681	"----------------------------\n");
				2682
				2683	ql_dbg(level, vha, id, " ");
				2684	for (cnt = 0; cnt < size;) {
				2685	c = *b++;
				2686	printk("%02x", (uint32_t) c);
				2687	cnt++;
				2688	if (!(cnt % 16))
				2689	printk("\n");
				2690	else
				2691	printk(" ");
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2692	}
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2693	if (cnt % 16)
				2694	ql_dbg(level, vha, id, "\n");
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2695	}