Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 1 | /** |
| 2 | * core.h - DesignWare USB3 DRD Core Header |
| 3 | * |
| 4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 5 | * |
| 6 | * Authors: Felipe Balbi <balbi@ti.com>, |
| 7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> |
| 8 | * |
Felipe Balbi | 5945f78 | 2013-06-30 14:15:11 +0300 | [diff] [blame] | 9 | * This program is free software: you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 of |
| 11 | * the License as published by the Free Software Foundation. |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 12 | * |
Felipe Balbi | 5945f78 | 2013-06-30 14:15:11 +0300 | [diff] [blame] | 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 17 | */ |
| 18 | |
| 19 | #ifndef __DRIVERS_USB_DWC3_CORE_H |
| 20 | #define __DRIVERS_USB_DWC3_CORE_H |
| 21 | |
| 22 | #include <linux/device.h> |
| 23 | #include <linux/spinlock.h> |
Felipe Balbi | d07e881 | 2011-10-12 14:08:26 +0300 | [diff] [blame] | 24 | #include <linux/ioport.h> |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 25 | #include <linux/list.h> |
| 26 | #include <linux/dma-mapping.h> |
| 27 | #include <linux/mm.h> |
| 28 | #include <linux/debugfs.h> |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 29 | #include <linux/workqueue.h> |
| 30 | #include <linux/wait.h> |
| 31 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 32 | |
| 33 | #include <linux/usb/ch9.h> |
| 34 | #include <linux/usb/gadget.h> |
Ruchika Kharwar | a45c82b8 | 2013-07-06 07:52:49 -0500 | [diff] [blame] | 35 | #include <linux/usb/otg.h> |
Heikki Krogerus | 88bc9d1 | 2015-05-13 15:26:51 +0300 | [diff] [blame] | 36 | #include <linux/ulpi/interface.h> |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 37 | |
Kishon Vijay Abraham I | 5730348 | 2014-03-03 17:08:11 +0530 | [diff] [blame] | 38 | #include <linux/phy/phy.h> |
| 39 | |
Felipe Balbi | 2c4cbe6e5 | 2014-04-30 17:45:10 -0500 | [diff] [blame] | 40 | #define DWC3_MSG_MAX 500 |
| 41 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 42 | /* Global constants */ |
Felipe Balbi | 04c03d1 | 2015-12-02 10:06:45 -0600 | [diff] [blame] | 43 | #define DWC3_ZLP_BUF_SIZE 1024 /* size of a superspeed bulk */ |
Felipe Balbi | 3ef35fa | 2012-05-04 12:58:14 +0300 | [diff] [blame] | 44 | #define DWC3_EP0_BOUNCE_SIZE 512 |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 45 | #define DWC3_ENDPOINTS_NUM 32 |
Ido Shayevitz | 51249dc | 2012-04-24 14:18:39 +0300 | [diff] [blame] | 46 | #define DWC3_XHCI_RESOURCES_NUM 2 |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 47 | |
Felipe Balbi | 0ffcaf3 | 2013-12-19 13:04:28 -0600 | [diff] [blame] | 48 | #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ |
Felipe Balbi | 9bdd47c | 2016-12-23 14:40:40 +0200 | [diff] [blame] | 49 | #define DWC3_EVENT_BUFFERS_SIZE 4096 |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 50 | #define DWC3_EVENT_TYPE_MASK 0xfe |
| 51 | |
| 52 | #define DWC3_EVENT_TYPE_DEV 0 |
| 53 | #define DWC3_EVENT_TYPE_CARKIT 3 |
| 54 | #define DWC3_EVENT_TYPE_I2C 4 |
| 55 | |
| 56 | #define DWC3_DEVICE_EVENT_DISCONNECT 0 |
| 57 | #define DWC3_DEVICE_EVENT_RESET 1 |
| 58 | #define DWC3_DEVICE_EVENT_CONNECT_DONE 2 |
| 59 | #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3 |
| 60 | #define DWC3_DEVICE_EVENT_WAKEUP 4 |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 61 | #define DWC3_DEVICE_EVENT_HIBER_REQ 5 |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 62 | #define DWC3_DEVICE_EVENT_EOPF 6 |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 63 | /* For version 2.30a and above */ |
| 64 | #define DWC3_DEVICE_EVENT_SUSPEND 6 |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 65 | #define DWC3_DEVICE_EVENT_SOF 7 |
| 66 | #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9 |
| 67 | #define DWC3_DEVICE_EVENT_CMD_CMPL 10 |
| 68 | #define DWC3_DEVICE_EVENT_OVERFLOW 11 |
| 69 | |
| 70 | #define DWC3_GEVNTCOUNT_MASK 0xfffc |
John Youn | 26cac20 | 2016-11-14 12:32:43 -0800 | [diff] [blame] | 71 | #define DWC3_GEVNTCOUNT_EHB (1 << 31) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 72 | #define DWC3_GSNPSID_MASK 0xffff0000 |
| 73 | #define DWC3_GSNPSREV_MASK 0xffff |
| 74 | |
Ido Shayevitz | 51249dc | 2012-04-24 14:18:39 +0300 | [diff] [blame] | 75 | /* DWC3 registers memory space boundries */ |
| 76 | #define DWC3_XHCI_REGS_START 0x0 |
| 77 | #define DWC3_XHCI_REGS_END 0x7fff |
| 78 | #define DWC3_GLOBALS_REGS_START 0xc100 |
| 79 | #define DWC3_GLOBALS_REGS_END 0xc6ff |
| 80 | #define DWC3_DEVICE_REGS_START 0xc700 |
| 81 | #define DWC3_DEVICE_REGS_END 0xcbff |
| 82 | #define DWC3_OTG_REGS_START 0xcc00 |
| 83 | #define DWC3_OTG_REGS_END 0xccff |
| 84 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 85 | /* Global Registers */ |
| 86 | #define DWC3_GSBUSCFG0 0xc100 |
| 87 | #define DWC3_GSBUSCFG1 0xc104 |
| 88 | #define DWC3_GTXTHRCFG 0xc108 |
| 89 | #define DWC3_GRXTHRCFG 0xc10c |
| 90 | #define DWC3_GCTL 0xc110 |
| 91 | #define DWC3_GEVTEN 0xc114 |
| 92 | #define DWC3_GSTS 0xc118 |
William Wu | 475c8be | 2016-05-13 18:13:46 +0800 | [diff] [blame] | 93 | #define DWC3_GUCTL1 0xc11c |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 94 | #define DWC3_GSNPSID 0xc120 |
| 95 | #define DWC3_GGPIO 0xc124 |
| 96 | #define DWC3_GUID 0xc128 |
| 97 | #define DWC3_GUCTL 0xc12c |
| 98 | #define DWC3_GBUSERRADDR0 0xc130 |
| 99 | #define DWC3_GBUSERRADDR1 0xc134 |
| 100 | #define DWC3_GPRTBIMAP0 0xc138 |
| 101 | #define DWC3_GPRTBIMAP1 0xc13c |
| 102 | #define DWC3_GHWPARAMS0 0xc140 |
| 103 | #define DWC3_GHWPARAMS1 0xc144 |
| 104 | #define DWC3_GHWPARAMS2 0xc148 |
| 105 | #define DWC3_GHWPARAMS3 0xc14c |
| 106 | #define DWC3_GHWPARAMS4 0xc150 |
| 107 | #define DWC3_GHWPARAMS5 0xc154 |
| 108 | #define DWC3_GHWPARAMS6 0xc158 |
| 109 | #define DWC3_GHWPARAMS7 0xc15c |
| 110 | #define DWC3_GDBGFIFOSPACE 0xc160 |
| 111 | #define DWC3_GDBGLTSSM 0xc164 |
| 112 | #define DWC3_GPRTBIMAP_HS0 0xc180 |
| 113 | #define DWC3_GPRTBIMAP_HS1 0xc184 |
| 114 | #define DWC3_GPRTBIMAP_FS0 0xc188 |
| 115 | #define DWC3_GPRTBIMAP_FS1 0xc18c |
John Youn | 06281d4 | 2016-08-22 15:39:13 -0700 | [diff] [blame] | 116 | #define DWC3_GUCTL2 0xc19c |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 117 | |
John Youn | 690fb37 | 2015-09-04 19:15:10 -0700 | [diff] [blame] | 118 | #define DWC3_VER_NUMBER 0xc1a0 |
| 119 | #define DWC3_VER_TYPE 0xc1a4 |
| 120 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 121 | #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) |
| 122 | #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) |
| 123 | |
| 124 | #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) |
| 125 | |
| 126 | #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) |
| 127 | |
| 128 | #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) |
| 129 | #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) |
| 130 | |
| 131 | #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) |
| 132 | #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) |
| 133 | #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) |
| 134 | #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) |
| 135 | |
| 136 | #define DWC3_GHWPARAMS8 0xc600 |
Nikhil Badola | db2be4e | 2015-09-04 10:15:58 +0530 | [diff] [blame] | 137 | #define DWC3_GFLADJ 0xc630 |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 138 | |
| 139 | /* Device Registers */ |
| 140 | #define DWC3_DCFG 0xc700 |
| 141 | #define DWC3_DCTL 0xc704 |
| 142 | #define DWC3_DEVTEN 0xc708 |
| 143 | #define DWC3_DSTS 0xc70c |
| 144 | #define DWC3_DGCMDPAR 0xc710 |
| 145 | #define DWC3_DGCMD 0xc714 |
| 146 | #define DWC3_DALEPENA 0xc720 |
Felipe Balbi | 2eb8801 | 2016-04-12 16:53:39 +0300 | [diff] [blame] | 147 | |
| 148 | #define DWC3_DEP_BASE(n) (0xc800 + (n * 0x10)) |
| 149 | #define DWC3_DEPCMDPAR2 0x00 |
| 150 | #define DWC3_DEPCMDPAR1 0x04 |
| 151 | #define DWC3_DEPCMDPAR0 0x08 |
| 152 | #define DWC3_DEPCMD 0x0c |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 153 | |
John Youn | 26cac20 | 2016-11-14 12:32:43 -0800 | [diff] [blame] | 154 | #define DWC3_DEV_IMOD(n) (0xca00 + (n * 0x4)) |
| 155 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 156 | /* OTG Registers */ |
| 157 | #define DWC3_OCFG 0xcc00 |
| 158 | #define DWC3_OCTL 0xcc04 |
George Cherian | d4436c3 | 2013-03-14 16:05:24 +0530 | [diff] [blame] | 159 | #define DWC3_OEVT 0xcc08 |
| 160 | #define DWC3_OEVTEN 0xcc0C |
| 161 | #define DWC3_OSTS 0xcc10 |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 162 | |
| 163 | /* Bit fields */ |
| 164 | |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 165 | /* Global SoC Bus Configuration Register 1 */ |
| 166 | #define DWC3_GSBUSCFG1_PIPETRANSLIMIT_MASK (0x0f << 8) |
| 167 | #define DWC3_GSBUSCFG1_PIPETRANSLIMIT(n) ((n) << 8) |
| 168 | |
Felipe Balbi | cf6d867 | 2016-04-14 15:03:39 +0300 | [diff] [blame] | 169 | /* Global Debug Queue/FIFO Space Available Register */ |
| 170 | #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f) |
| 171 | #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0) |
| 172 | #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff) |
| 173 | |
| 174 | #define DWC3_TXFIFOQ 1 |
| 175 | #define DWC3_RXFIFOQ 3 |
| 176 | #define DWC3_TXREQQ 5 |
| 177 | #define DWC3_RXREQQ 7 |
| 178 | #define DWC3_RXINFOQ 9 |
| 179 | #define DWC3_DESCFETCHQ 13 |
| 180 | #define DWC3_EVENTQ 15 |
| 181 | |
Felipe Balbi | 2a58f9c | 2016-04-28 10:56:28 +0300 | [diff] [blame] | 182 | /* Global RX Threshold Configuration Register */ |
| 183 | #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19) |
| 184 | #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24) |
| 185 | #define DWC3_GRXTHRCFG_PKTCNTSEL (1 << 29) |
| 186 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 187 | /* Global Configuration Register */ |
Paul Zimmerman | 1d04679 | 2012-02-15 18:56:56 -0800 | [diff] [blame] | 188 | #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 189 | #define DWC3_GCTL_PWRDNSCALEMASK (0xFFF80000) |
Felipe Balbi | f4aadbe | 2011-09-08 17:39:59 +0300 | [diff] [blame] | 190 | #define DWC3_GCTL_U2RSTECN (1 << 16) |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 191 | #define DWC3_GCTL_SOFITPSYNC (1 << 10) |
| 192 | #define DWC3_GCTL_U2EXIT_LFPS (1 << 2) |
Paul Zimmerman | 1d04679 | 2012-02-15 18:56:56 -0800 | [diff] [blame] | 193 | #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 194 | #define DWC3_GCTL_CLK_BUS (0) |
| 195 | #define DWC3_GCTL_CLK_PIPE (1) |
| 196 | #define DWC3_GCTL_CLK_PIPEHALF (2) |
| 197 | #define DWC3_GCTL_CLK_MASK (3) |
| 198 | |
Felipe Balbi | 0b9fe32 | 2011-10-17 08:50:39 +0300 | [diff] [blame] | 199 | #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12) |
Paul Zimmerman | 1d04679 | 2012-02-15 18:56:56 -0800 | [diff] [blame] | 200 | #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 201 | #define DWC3_GCTL_PRTCAP_HOST 1 |
| 202 | #define DWC3_GCTL_PRTCAP_DEVICE 2 |
| 203 | #define DWC3_GCTL_PRTCAP_OTG 3 |
| 204 | |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 205 | #define DWC3_GCTL_CORESOFTRESET (1 << 11) |
Felipe Balbi | 183ca11 | 2014-02-25 14:08:51 -0600 | [diff] [blame] | 206 | #define DWC3_GCTL_SOFITPSYNC (1 << 10) |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 207 | #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) |
| 208 | #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) |
| 209 | #define DWC3_GCTL_DISSCRAMBLE (1 << 3) |
Huang Rui | 9a5b2f3 | 2014-10-28 19:54:27 +0800 | [diff] [blame] | 210 | #define DWC3_GCTL_U2EXIT_LFPS (1 << 2) |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 211 | #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) |
| 212 | #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 213 | |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 214 | /* Global User Control Register */ |
| 215 | #define DWC3_GUCTL_REFCLKPER (0x3FF << 22) |
| 216 | |
| 217 | /* Global Debug LTSSM Register */ |
| 218 | #define DWC3_GDBGLTSSM_LINKSTATE_MASK (0xF << 22) |
| 219 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 220 | /* Global USB2 PHY Configuration Register */ |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 221 | #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 222 | #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) |
William Wu | 16199f3 | 2016-08-16 22:44:37 +0800 | [diff] [blame] | 223 | #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30) |
Kyle Yan | 65be4a5 | 2016-10-31 15:05:00 -0700 | [diff] [blame] | 224 | |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 225 | #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) |
Heikki Krogerus | f699b94 | 2015-05-13 15:26:44 +0300 | [diff] [blame] | 226 | #define DWC3_GUSB2PHYCFG_ULPI_UTMI (1 << 4) |
John Youn | ec791d1 | 2015-10-02 20:30:57 -0700 | [diff] [blame] | 227 | #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) |
William Wu | 32f2ed8 | 2016-08-16 22:44:38 +0800 | [diff] [blame] | 228 | #define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3) |
| 229 | #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) |
| 230 | #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10) |
| 231 | #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) |
| 232 | #define USBTRDTIM_UTMI_8_BIT 9 |
| 233 | #define USBTRDTIM_UTMI_16_BIT 5 |
| 234 | #define UTMI_PHYIF_16_BIT 1 |
| 235 | #define UTMI_PHYIF_8_BIT 0 |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 236 | |
Heikki Krogerus | b5699ee | 2015-05-13 15:26:43 +0300 | [diff] [blame] | 237 | /* Global USB2 PHY Vendor Control Register */ |
| 238 | #define DWC3_GUSB2PHYACC_NEWREGREQ (1 << 25) |
| 239 | #define DWC3_GUSB2PHYACC_BUSY (1 << 23) |
| 240 | #define DWC3_GUSB2PHYACC_WRITE (1 << 22) |
| 241 | #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16) |
| 242 | #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8) |
| 243 | #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff) |
| 244 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 245 | /* Global USB3 PIPE Control Register */ |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 246 | #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) |
Huang Rui | b5a65c4 | 2014-10-28 19:54:28 +0800 | [diff] [blame] | 247 | #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29) |
Rajesh Bhagat | e58dd35 | 2016-03-14 14:40:50 +0530 | [diff] [blame] | 248 | #define DWC3_GUSB3PIPECTL_DISRXDETINP3 (1 << 28) |
Hemant Kumar | 58eb1df | 2017-01-27 14:51:07 -0800 | [diff] [blame] | 249 | #define DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX (1 << 27) |
Huang Rui | df31f5b | 2014-10-28 19:54:29 +0800 | [diff] [blame] | 250 | #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24) |
Huang Rui | a2a1d0f | 2014-10-28 19:54:30 +0800 | [diff] [blame] | 251 | #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) |
| 252 | #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) |
| 253 | #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1) |
Huang Rui | 41c06ff | 2014-10-28 19:54:31 +0800 | [diff] [blame] | 254 | #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18) |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 255 | #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) |
Huang Rui | fb67afc | 2014-10-28 19:54:32 +0800 | [diff] [blame] | 256 | #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9) |
Huang Rui | 14f4ac5 | 2014-10-28 19:54:33 +0800 | [diff] [blame] | 257 | #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8) |
Huang Rui | 6b6a0c9 | 2014-10-31 11:11:12 +0800 | [diff] [blame] | 258 | #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3) |
| 259 | #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1) |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 260 | #define DWC3_GUSB3PIPECTL_DELAYP1TRANS (1 << 18) |
| 261 | #define DWC3_GUSB3PIPECTL_ELASTIC_BUF_MODE (1 << 0) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 262 | |
Felipe Balbi | 457e84b | 2012-01-18 18:04:09 +0200 | [diff] [blame] | 263 | /* Global TX Fifo Size Register */ |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 264 | #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) |
| 265 | #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) |
Felipe Balbi | 457e84b | 2012-01-18 18:04:09 +0200 | [diff] [blame] | 266 | |
Felipe Balbi | 68d6a01 | 2013-06-12 21:09:26 +0300 | [diff] [blame] | 267 | /* Global Event Size Registers */ |
| 268 | #define DWC3_GEVNTSIZ_INTMASK (1 << 31) |
| 269 | #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) |
| 270 | |
Felipe Balbi | 4e99472 | 2016-05-13 14:09:59 +0300 | [diff] [blame] | 271 | /* Global HWPARAMS0 Register */ |
Thinh Nguyen | 9d6173e | 2016-09-06 19:22:03 -0700 | [diff] [blame] | 272 | #define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3) |
| 273 | #define DWC3_GHWPARAMS0_MODE_GADGET 0 |
| 274 | #define DWC3_GHWPARAMS0_MODE_HOST 1 |
| 275 | #define DWC3_GHWPARAMS0_MODE_DRD 2 |
Felipe Balbi | 4e99472 | 2016-05-13 14:09:59 +0300 | [diff] [blame] | 276 | #define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7) |
| 277 | #define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3) |
| 278 | #define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff) |
| 279 | #define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff) |
| 280 | #define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff) |
| 281 | |
Felipe Balbi | aabb707 | 2011-09-30 10:58:50 +0300 | [diff] [blame] | 282 | /* Global HWPARAMS1 Register */ |
Paul Zimmerman | 1d04679 | 2012-02-15 18:56:56 -0800 | [diff] [blame] | 283 | #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) |
Felipe Balbi | aabb707 | 2011-09-30 10:58:50 +0300 | [diff] [blame] | 284 | #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 |
| 285 | #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 286 | #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2 |
| 287 | #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) |
| 288 | #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) |
| 289 | |
Paul Zimmerman | 0e1e5c4 | 2014-05-23 11:39:24 -0700 | [diff] [blame] | 290 | /* Global HWPARAMS3 Register */ |
| 291 | #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) |
| 292 | #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 |
John Youn | 1f38f88 | 2016-02-05 17:08:31 -0800 | [diff] [blame] | 293 | #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1 |
| 294 | #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */ |
Paul Zimmerman | 0e1e5c4 | 2014-05-23 11:39:24 -0700 | [diff] [blame] | 295 | #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2) |
| 296 | #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 |
| 297 | #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 |
| 298 | #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 |
| 299 | #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 |
| 300 | #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4) |
| 301 | #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 |
| 302 | #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 |
| 303 | |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 304 | /* Global HWPARAMS4 Register */ |
| 305 | #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13) |
| 306 | #define DWC3_MAX_HIBER_SCRATCHBUFS 15 |
Felipe Balbi | aabb707 | 2011-09-30 10:58:50 +0300 | [diff] [blame] | 307 | |
Huang Rui | 946bd57 | 2014-10-28 19:54:23 +0800 | [diff] [blame] | 308 | /* Global HWPARAMS6 Register */ |
| 309 | #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) |
| 310 | |
Felipe Balbi | 4e99472 | 2016-05-13 14:09:59 +0300 | [diff] [blame] | 311 | /* Global HWPARAMS7 Register */ |
| 312 | #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff) |
| 313 | #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff) |
| 314 | |
Nikhil Badola | db2be4e | 2015-09-04 10:15:58 +0530 | [diff] [blame] | 315 | /* Global Frame Length Adjustment Register */ |
| 316 | #define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7) |
| 317 | #define DWC3_GFLADJ_30MHZ_MASK 0x3f |
| 318 | |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 319 | #define DWC3_GFLADJ_REFCLK_240MHZDECR_PLS1 (1 << 31) |
| 320 | #define DWC3_GFLADJ_REFCLK_240MHZ_DECR (0x7F << 24) |
| 321 | #define DWC3_GFLADJ_REFCLK_LPM_SEL (1 << 23) |
| 322 | #define DWC3_GFLADJ_REFCLK_FLADJ (0x3FFF << 8) |
| 323 | |
John Youn | 06281d4 | 2016-08-22 15:39:13 -0700 | [diff] [blame] | 324 | /* Global User Control Register 2 */ |
| 325 | #define DWC3_GUCTL2_RST_ACTBITLATER (1 << 14) |
| 326 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 327 | /* Device Configuration Register */ |
| 328 | #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3) |
| 329 | #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f) |
| 330 | |
| 331 | #define DWC3_DCFG_SPEED_MASK (7 << 0) |
John Youn | 1f38f88 | 2016-02-05 17:08:31 -0800 | [diff] [blame] | 332 | #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 333 | #define DWC3_DCFG_SUPERSPEED (4 << 0) |
| 334 | #define DWC3_DCFG_HIGHSPEED (0 << 0) |
Roger Quadros | 5e3c292 | 2017-01-03 14:32:09 +0200 | [diff] [blame] | 335 | #define DWC3_DCFG_FULLSPEED (1 << 0) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 336 | #define DWC3_DCFG_LOWSPEED (2 << 0) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 337 | |
Felipe Balbi | 676e349 | 2016-04-26 10:49:07 +0300 | [diff] [blame] | 338 | #define DWC3_DCFG_NUMP_SHIFT 17 |
Dan Carpenter | 9739861 | 2016-05-03 10:49:00 +0300 | [diff] [blame] | 339 | #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f) |
Felipe Balbi | 676e349 | 2016-04-26 10:49:07 +0300 | [diff] [blame] | 340 | #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT) |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 341 | #define DWC3_DCFG_LPM_CAP (1 << 22) |
| 342 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 343 | /* Device Control Register */ |
| 344 | #define DWC3_DCTL_RUN_STOP (1 << 31) |
| 345 | #define DWC3_DCTL_CSFTRST (1 << 30) |
| 346 | #define DWC3_DCTL_LSFTRST (1 << 29) |
| 347 | |
| 348 | #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24) |
Pratyush Anand | 7e39b81 | 2012-06-06 19:18:29 +0530 | [diff] [blame] | 349 | #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 350 | |
| 351 | #define DWC3_DCTL_APPL1RES (1 << 23) |
| 352 | |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 353 | /* These apply for core versions 1.87a and earlier */ |
| 354 | #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17) |
| 355 | #define DWC3_DCTL_TRGTULST(n) ((n) << 17) |
| 356 | #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2)) |
| 357 | #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3)) |
| 358 | #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4)) |
| 359 | #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5)) |
| 360 | #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6)) |
Felipe Balbi | 8db7ed1 | 2012-01-18 18:32:29 +0200 | [diff] [blame] | 361 | |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 362 | /* These apply for core versions 1.94a and later */ |
Huang Rui | 80caf7d | 2014-10-28 19:54:26 +0800 | [diff] [blame] | 363 | #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf) |
| 364 | #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20) |
Felipe Balbi | 8db7ed1 | 2012-01-18 18:32:29 +0200 | [diff] [blame] | 365 | |
Huang Rui | 80caf7d | 2014-10-28 19:54:26 +0800 | [diff] [blame] | 366 | #define DWC3_DCTL_KEEP_CONNECT (1 << 19) |
| 367 | #define DWC3_DCTL_L1_HIBER_EN (1 << 18) |
| 368 | #define DWC3_DCTL_CRS (1 << 17) |
| 369 | #define DWC3_DCTL_CSS (1 << 16) |
| 370 | |
| 371 | #define DWC3_DCTL_INITU2ENA (1 << 12) |
| 372 | #define DWC3_DCTL_ACCEPTU2ENA (1 << 11) |
| 373 | #define DWC3_DCTL_INITU1ENA (1 << 10) |
| 374 | #define DWC3_DCTL_ACCEPTU1ENA (1 << 9) |
| 375 | #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 376 | |
| 377 | #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5) |
| 378 | #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK) |
| 379 | |
| 380 | #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0)) |
| 381 | #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4)) |
| 382 | #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5)) |
| 383 | #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6)) |
| 384 | #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8)) |
| 385 | #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10)) |
| 386 | #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11)) |
| 387 | |
| 388 | /* Device Event Enable Register */ |
| 389 | #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12) |
| 390 | #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11) |
| 391 | #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10) |
| 392 | #define DWC3_DEVTEN_ERRTICERREN (1 << 9) |
| 393 | #define DWC3_DEVTEN_SOFEN (1 << 7) |
| 394 | #define DWC3_DEVTEN_EOPFEN (1 << 6) |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 395 | /* For version 2.30a and above*/ |
| 396 | #define DWC3_DEVTEN_SUSPEND (1 << 6) |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 397 | #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 398 | #define DWC3_DEVTEN_WKUPEVTEN (1 << 4) |
| 399 | #define DWC3_DEVTEN_ULSTCNGEN (1 << 3) |
| 400 | #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2) |
| 401 | #define DWC3_DEVTEN_USBRSTEN (1 << 1) |
| 402 | #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0) |
| 403 | |
| 404 | /* Device Status Register */ |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 405 | #define DWC3_DSTS_DCNRD (1 << 29) |
| 406 | |
| 407 | /* This applies for core versions 1.87a and earlier */ |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 408 | #define DWC3_DSTS_PWRUPREQ (1 << 24) |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 409 | |
| 410 | /* These apply for core versions 1.94a and later */ |
| 411 | #define DWC3_DSTS_RSS (1 << 25) |
| 412 | #define DWC3_DSTS_SSS (1 << 24) |
| 413 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 414 | #define DWC3_DSTS_COREIDLE (1 << 23) |
| 415 | #define DWC3_DSTS_DEVCTRLHLT (1 << 22) |
| 416 | |
| 417 | #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18) |
| 418 | #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) |
| 419 | |
| 420 | #define DWC3_DSTS_RXFIFOEMPTY (1 << 17) |
| 421 | |
Pratyush Anand | d05b818 | 2012-05-21 14:51:30 +0530 | [diff] [blame] | 422 | #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 423 | #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) |
| 424 | |
| 425 | #define DWC3_DSTS_CONNECTSPD (7 << 0) |
| 426 | |
John Youn | 1f38f88 | 2016-02-05 17:08:31 -0800 | [diff] [blame] | 427 | #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */ |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 428 | #define DWC3_DSTS_SUPERSPEED (4 << 0) |
| 429 | #define DWC3_DSTS_HIGHSPEED (0 << 0) |
Roger Quadros | 5e3c292 | 2017-01-03 14:32:09 +0200 | [diff] [blame] | 430 | #define DWC3_DSTS_FULLSPEED (1 << 0) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 431 | #define DWC3_DSTS_LOWSPEED (2 << 0) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 432 | |
| 433 | /* Device Generic Command Register */ |
| 434 | #define DWC3_DGCMD_SET_LMP 0x01 |
| 435 | #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02 |
| 436 | #define DWC3_DGCMD_XMIT_FUNCTION 0x03 |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 437 | #define DWC3_DGCMD_XMIT_DEV 0x07 |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 438 | |
| 439 | /* These apply for core versions 1.94a and later */ |
| 440 | #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04 |
| 441 | #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05 |
| 442 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 443 | #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09 |
| 444 | #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a |
| 445 | #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c |
| 446 | #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10 |
| 447 | |
Subbaraya Sundeep Bhatta | 459e210 | 2015-05-21 15:46:46 +0530 | [diff] [blame] | 448 | #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F) |
Felipe Balbi | b09bb64 | 2012-04-24 16:19:11 +0300 | [diff] [blame] | 449 | #define DWC3_DGCMD_CMDACT (1 << 10) |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 450 | #define DWC3_DGCMD_CMDIOC (1 << 8) |
| 451 | |
| 452 | /* Device Generic Command Parameter Register */ |
| 453 | #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0) |
| 454 | #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0) |
| 455 | #define DWC3_DGCMDPAR_RX_FIFO (0 << 5) |
| 456 | #define DWC3_DGCMDPAR_TX_FIFO (1 << 5) |
| 457 | #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0) |
| 458 | #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0) |
Felipe Balbi | b09bb64 | 2012-04-24 16:19:11 +0300 | [diff] [blame] | 459 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 460 | /* Device Endpoint Command Register */ |
| 461 | #define DWC3_DEPCMD_PARAM_SHIFT 16 |
Paul Zimmerman | 1d04679 | 2012-02-15 18:56:56 -0800 | [diff] [blame] | 462 | #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT) |
Felipe Balbi | 835fadb | 2013-12-19 14:02:53 -0600 | [diff] [blame] | 463 | #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f) |
Subbaraya Sundeep Bhatta | 459e210 | 2015-05-21 15:46:46 +0530 | [diff] [blame] | 464 | #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 465 | #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11) |
John Youn | 50c763f | 2016-05-31 17:49:56 -0700 | [diff] [blame] | 466 | #define DWC3_DEPCMD_CLEARPENDIN (1 << 11) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 467 | #define DWC3_DEPCMD_CMDACT (1 << 10) |
| 468 | #define DWC3_DEPCMD_CMDIOC (1 << 8) |
| 469 | |
| 470 | #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0) |
| 471 | #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0) |
| 472 | #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0) |
| 473 | #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0) |
| 474 | #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0) |
| 475 | #define DWC3_DEPCMD_SETSTALL (0x04 << 0) |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 476 | /* This applies for core versions 1.90a and earlier */ |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 477 | #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0) |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 478 | /* This applies for core versions 1.94a and later */ |
| 479 | #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 480 | #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0) |
| 481 | #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0) |
| 482 | |
Felipe Balbi | a81d6b7 | 2016-09-22 12:25:28 +0300 | [diff] [blame] | 483 | #define DWC3_DEPCMD_CMD(x) ((x) & 0xf) |
| 484 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 485 | /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ |
| 486 | #define DWC3_DALEPENA_EP(n) (1 << n) |
| 487 | |
| 488 | #define DWC3_DEPCMD_TYPE_CONTROL 0 |
| 489 | #define DWC3_DEPCMD_TYPE_ISOC 1 |
| 490 | #define DWC3_DEPCMD_TYPE_BULK 2 |
| 491 | #define DWC3_DEPCMD_TYPE_INTR 3 |
| 492 | |
John Youn | 26cac20 | 2016-11-14 12:32:43 -0800 | [diff] [blame] | 493 | #define DWC3_DEV_IMOD_COUNT_SHIFT 16 |
| 494 | #define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16) |
| 495 | #define DWC3_DEV_IMOD_INTERVAL_SHIFT 0 |
| 496 | #define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0) |
| 497 | |
Mayank Rana | 861da2b | 2016-07-13 13:47:57 -0700 | [diff] [blame] | 498 | #define DWC_CTRL_COUNT 10 |
| 499 | #define NUM_LOG_PAGES 12 |
| 500 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 501 | /* Structures */ |
| 502 | |
Felipe Balbi | f6bafc6 | 2012-02-06 11:04:53 +0200 | [diff] [blame] | 503 | struct dwc3_trb; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 504 | |
| 505 | /** |
| 506 | * struct dwc3_event_buffer - Software event buffer representation |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 507 | * @buf: _THE_ buffer |
| 508 | * @length: size of this buffer |
Felipe Balbi | abed411 | 2011-07-04 20:20:04 +0300 | [diff] [blame] | 509 | * @lpos: event offset |
Felipe Balbi | 60d04bb | 2011-07-04 20:23:14 +0300 | [diff] [blame] | 510 | * @count: cache of last read event count register |
Felipe Balbi | abed411 | 2011-07-04 20:20:04 +0300 | [diff] [blame] | 511 | * @flags: flags related to this event buffer |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 512 | * @dma: dma_addr_t |
| 513 | * @dwc: pointer to DWC controller |
| 514 | */ |
| 515 | struct dwc3_event_buffer { |
| 516 | void *buf; |
| 517 | unsigned length; |
| 518 | unsigned int lpos; |
Felipe Balbi | 60d04bb | 2011-07-04 20:23:14 +0300 | [diff] [blame] | 519 | unsigned int count; |
Felipe Balbi | abed411 | 2011-07-04 20:20:04 +0300 | [diff] [blame] | 520 | unsigned int flags; |
| 521 | |
| 522 | #define DWC3_EVENT_PENDING BIT(0) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 523 | |
| 524 | dma_addr_t dma; |
| 525 | |
| 526 | struct dwc3 *dwc; |
| 527 | }; |
| 528 | |
Mayank Rana | 0c667b4 | 2017-02-09 11:56:51 -0800 | [diff] [blame] | 529 | struct dwc3_gadget_events { |
| 530 | unsigned int disconnect; |
| 531 | unsigned int reset; |
| 532 | unsigned int connect; |
| 533 | unsigned int wakeup; |
| 534 | unsigned int link_status_change; |
| 535 | unsigned int eopf; |
| 536 | unsigned int suspend; |
| 537 | unsigned int sof; |
| 538 | unsigned int erratic_error; |
| 539 | unsigned int overflow; |
| 540 | unsigned int vendor_dev_test_lmp; |
| 541 | unsigned int cmdcmplt; |
| 542 | unsigned int unknown_event; |
| 543 | }; |
| 544 | |
| 545 | struct dwc3_ep_events { |
| 546 | unsigned int xfercomplete; |
| 547 | unsigned int xfernotready; |
| 548 | unsigned int control_data; |
| 549 | unsigned int control_status; |
| 550 | unsigned int xferinprogress; |
| 551 | unsigned int rxtxfifoevent; |
| 552 | unsigned int streamevent; |
| 553 | unsigned int epcmdcomplete; |
| 554 | unsigned int unknown_event; |
| 555 | unsigned int total; |
| 556 | }; |
| 557 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 558 | #define DWC3_EP_FLAG_STALLED (1 << 0) |
| 559 | #define DWC3_EP_FLAG_WEDGED (1 << 1) |
| 560 | |
| 561 | #define DWC3_EP_DIRECTION_TX true |
| 562 | #define DWC3_EP_DIRECTION_RX false |
| 563 | |
Felipe Balbi | 8495036 | 2016-03-10 14:40:31 +0200 | [diff] [blame] | 564 | #define DWC3_TRB_NUM 256 |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 565 | |
| 566 | /** |
| 567 | * struct dwc3_ep - device side endpoint representation |
| 568 | * @endpoint: usb endpoint |
Felipe Balbi | aa3342c | 2016-03-14 11:01:31 +0200 | [diff] [blame] | 569 | * @pending_list: list of pending requests for this endpoint |
| 570 | * @started_list: list of started requests on this endpoint |
Felipe Balbi | 74674cb | 2016-04-13 16:44:39 +0300 | [diff] [blame] | 571 | * @lock: spinlock for endpoint request queue traversal |
Felipe Balbi | 2eb8801 | 2016-04-12 16:53:39 +0300 | [diff] [blame] | 572 | * @regs: pointer to first endpoint register |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 573 | * @trb_pool: array of transaction buffers |
| 574 | * @trb_pool_dma: dma address of @trb_pool |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 575 | * @num_trbs: num of trbs in the trb dma pool |
Felipe Balbi | 53fd881 | 2016-04-04 15:33:41 +0300 | [diff] [blame] | 576 | * @trb_enqueue: enqueue 'pointer' into TRB array |
| 577 | * @trb_dequeue: dequeue 'pointer' into TRB array |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 578 | * @desc: usb_endpoint_descriptor pointer |
| 579 | * @dwc: pointer to DWC controller |
Paul Zimmerman | 4cfcf87 | 2012-04-27 13:56:23 +0300 | [diff] [blame] | 580 | * @saved_state: ep state saved during hibernation |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 581 | * @flags: endpoint flags (wedged, stalled, ...) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 582 | * @number: endpoint number (1 - 15) |
| 583 | * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK |
Felipe Balbi | b4996a8 | 2012-06-06 12:04:13 +0300 | [diff] [blame] | 584 | * @resource_index: Resource transfer index |
Huang Rui | c75f52f | 2013-06-12 23:43:11 +0800 | [diff] [blame] | 585 | * @interval: the interval on which the ISOC transfer is started |
Felipe Balbi | 68d34c8 | 2016-05-30 13:34:58 +0300 | [diff] [blame] | 586 | * @allocated_requests: number of requests allocated |
| 587 | * @queued_requests: number of requests queued for transfer |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 588 | * @name: a human readable name e.g. ep1out-bulk |
| 589 | * @direction: true for TX, false for RX |
Felipe Balbi | 879631a | 2011-09-30 10:58:47 +0300 | [diff] [blame] | 590 | * @stream_capable: true when streams are enabled |
Mayank Rana | 0c667b4 | 2017-02-09 11:56:51 -0800 | [diff] [blame] | 591 | * @dbg_ep_events: different events counter for endpoint |
| 592 | * @dbg_ep_events_diff: differential events counter for endpoint |
| 593 | * @dbg_ep_events_ts: timestamp for previous event counters |
Mayank Rana | ac1200c | 2017-04-25 13:48:46 -0700 | [diff] [blame] | 594 | * @fifo_depth: allocated TXFIFO depth |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 595 | */ |
| 596 | struct dwc3_ep { |
| 597 | struct usb_ep endpoint; |
Felipe Balbi | aa3342c | 2016-03-14 11:01:31 +0200 | [diff] [blame] | 598 | struct list_head pending_list; |
| 599 | struct list_head started_list; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 600 | |
Felipe Balbi | 74674cb | 2016-04-13 16:44:39 +0300 | [diff] [blame] | 601 | spinlock_t lock; |
Felipe Balbi | 2eb8801 | 2016-04-12 16:53:39 +0300 | [diff] [blame] | 602 | void __iomem *regs; |
| 603 | |
Felipe Balbi | f6bafc6 | 2012-02-06 11:04:53 +0200 | [diff] [blame] | 604 | struct dwc3_trb *trb_pool; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 605 | dma_addr_t trb_pool_dma; |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 606 | u32 num_trbs; |
Felipe Balbi | c90bfae | 2011-11-29 13:11:21 +0200 | [diff] [blame] | 607 | const struct usb_ss_ep_comp_descriptor *comp_desc; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 608 | struct dwc3 *dwc; |
| 609 | |
Paul Zimmerman | 4cfcf87 | 2012-04-27 13:56:23 +0300 | [diff] [blame] | 610 | u32 saved_state; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 611 | unsigned flags; |
| 612 | #define DWC3_EP_ENABLED (1 << 0) |
| 613 | #define DWC3_EP_STALL (1 << 1) |
| 614 | #define DWC3_EP_WEDGE (1 << 2) |
| 615 | #define DWC3_EP_BUSY (1 << 4) |
| 616 | #define DWC3_EP_PENDING_REQUEST (1 << 5) |
Pratyush Anand | d6d6ec7 | 2012-05-25 18:54:56 +0530 | [diff] [blame] | 617 | #define DWC3_EP_MISSED_ISOC (1 << 6) |
Felipe Balbi | cf23b5b | 2016-10-21 13:07:09 +0300 | [diff] [blame] | 618 | #define DWC3_EP_TRANSFER_STARTED (1 << 8) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 619 | |
Felipe Balbi | 984f66a | 2011-08-27 22:26:00 +0300 | [diff] [blame] | 620 | /* This last one is specific to EP0 */ |
| 621 | #define DWC3_EP0_DIR_IN (1 << 31) |
| 622 | |
Felipe Balbi | c28f825 | 2016-04-05 12:42:15 +0300 | [diff] [blame] | 623 | /* |
| 624 | * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will |
| 625 | * use a u8 type here. If anybody decides to increase number of TRBs to |
| 626 | * anything larger than 256 - I can't see why people would want to do |
| 627 | * this though - then this type needs to be changed. |
| 628 | * |
| 629 | * By using u8 types we ensure that our % operator when incrementing |
| 630 | * enqueue and dequeue get optimized away by the compiler. |
| 631 | */ |
| 632 | u8 trb_enqueue; |
| 633 | u8 trb_dequeue; |
| 634 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 635 | u8 number; |
| 636 | u8 type; |
Felipe Balbi | b4996a8 | 2012-06-06 12:04:13 +0300 | [diff] [blame] | 637 | u8 resource_index; |
Felipe Balbi | 68d34c8 | 2016-05-30 13:34:58 +0300 | [diff] [blame] | 638 | u32 allocated_requests; |
| 639 | u32 queued_requests; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 640 | u32 interval; |
| 641 | |
| 642 | char name[20]; |
| 643 | |
| 644 | unsigned direction:1; |
Felipe Balbi | 879631a | 2011-09-30 10:58:47 +0300 | [diff] [blame] | 645 | unsigned stream_capable:1; |
Mayank Rana | 0c667b4 | 2017-02-09 11:56:51 -0800 | [diff] [blame] | 646 | struct dwc3_ep_events dbg_ep_events; |
| 647 | struct dwc3_ep_events dbg_ep_events_diff; |
| 648 | struct timespec dbg_ep_events_ts; |
Mayank Rana | ac1200c | 2017-04-25 13:48:46 -0700 | [diff] [blame] | 649 | int fifo_depth; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 650 | }; |
| 651 | |
| 652 | enum dwc3_phy { |
| 653 | DWC3_PHY_UNKNOWN = 0, |
| 654 | DWC3_PHY_USB3, |
| 655 | DWC3_PHY_USB2, |
| 656 | }; |
| 657 | |
Felipe Balbi | b53c772 | 2011-08-30 15:50:40 +0300 | [diff] [blame] | 658 | enum dwc3_ep0_next { |
| 659 | DWC3_EP0_UNKNOWN = 0, |
| 660 | DWC3_EP0_COMPLETE, |
Felipe Balbi | b53c772 | 2011-08-30 15:50:40 +0300 | [diff] [blame] | 661 | DWC3_EP0_NRDY_DATA, |
| 662 | DWC3_EP0_NRDY_STATUS, |
| 663 | }; |
| 664 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 665 | enum dwc3_ep0_state { |
| 666 | EP0_UNCONNECTED = 0, |
Felipe Balbi | c7fcdeb | 2011-08-27 22:28:36 +0300 | [diff] [blame] | 667 | EP0_SETUP_PHASE, |
| 668 | EP0_DATA_PHASE, |
| 669 | EP0_STATUS_PHASE, |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 670 | }; |
| 671 | |
| 672 | enum dwc3_link_state { |
| 673 | /* In SuperSpeed */ |
| 674 | DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */ |
| 675 | DWC3_LINK_STATE_U1 = 0x01, |
| 676 | DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */ |
| 677 | DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */ |
| 678 | DWC3_LINK_STATE_SS_DIS = 0x04, |
| 679 | DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */ |
| 680 | DWC3_LINK_STATE_SS_INACT = 0x06, |
| 681 | DWC3_LINK_STATE_POLL = 0x07, |
| 682 | DWC3_LINK_STATE_RECOV = 0x08, |
| 683 | DWC3_LINK_STATE_HRESET = 0x09, |
| 684 | DWC3_LINK_STATE_CMPLY = 0x0a, |
| 685 | DWC3_LINK_STATE_LPBK = 0x0b, |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 686 | DWC3_LINK_STATE_RESET = 0x0e, |
| 687 | DWC3_LINK_STATE_RESUME = 0x0f, |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 688 | DWC3_LINK_STATE_MASK = 0x0f, |
| 689 | }; |
| 690 | |
Felipe Balbi | f6bafc6 | 2012-02-06 11:04:53 +0200 | [diff] [blame] | 691 | /* TRB Length, PCM and Status */ |
| 692 | #define DWC3_TRB_SIZE_MASK (0x00ffffff) |
| 693 | #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK) |
| 694 | #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24) |
Pratyush Anand | 389f282 | 2012-05-21 12:46:26 +0530 | [diff] [blame] | 695 | #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 696 | |
Felipe Balbi | f6bafc6 | 2012-02-06 11:04:53 +0200 | [diff] [blame] | 697 | #define DWC3_TRBSTS_OK 0 |
| 698 | #define DWC3_TRBSTS_MISSED_ISOC 1 |
| 699 | #define DWC3_TRBSTS_SETUP_PENDING 2 |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 700 | #define DWC3_TRB_STS_XFER_IN_PROG 4 |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 701 | |
Felipe Balbi | f6bafc6 | 2012-02-06 11:04:53 +0200 | [diff] [blame] | 702 | /* TRB Control */ |
| 703 | #define DWC3_TRB_CTRL_HWO (1 << 0) |
| 704 | #define DWC3_TRB_CTRL_LST (1 << 1) |
| 705 | #define DWC3_TRB_CTRL_CHN (1 << 2) |
| 706 | #define DWC3_TRB_CTRL_CSP (1 << 3) |
| 707 | #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4) |
| 708 | #define DWC3_TRB_CTRL_ISP_IMI (1 << 10) |
| 709 | #define DWC3_TRB_CTRL_IOC (1 << 11) |
| 710 | #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14) |
| 711 | |
Felipe Balbi | b058f3e | 2016-04-14 16:05:54 +0300 | [diff] [blame] | 712 | #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4)) |
Felipe Balbi | f6bafc6 | 2012-02-06 11:04:53 +0200 | [diff] [blame] | 713 | #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1) |
| 714 | #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2) |
| 715 | #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3) |
| 716 | #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4) |
| 717 | #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5) |
| 718 | #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6) |
| 719 | #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7) |
| 720 | #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 721 | |
| 722 | /** |
Felipe Balbi | f6bafc6 | 2012-02-06 11:04:53 +0200 | [diff] [blame] | 723 | * struct dwc3_trb - transfer request block (hw format) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 724 | * @bpl: DW0-3 |
| 725 | * @bph: DW4-7 |
| 726 | * @size: DW8-B |
| 727 | * @trl: DWC-F |
| 728 | */ |
Felipe Balbi | f6bafc6 | 2012-02-06 11:04:53 +0200 | [diff] [blame] | 729 | struct dwc3_trb { |
| 730 | u32 bpl; |
| 731 | u32 bph; |
| 732 | u32 size; |
| 733 | u32 ctrl; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 734 | } __packed; |
| 735 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 736 | /** |
Felipe Balbi | a329949 | 2011-09-30 10:58:48 +0300 | [diff] [blame] | 737 | * dwc3_hwparams - copy of HWPARAMS registers |
| 738 | * @hwparams0 - GHWPARAMS0 |
| 739 | * @hwparams1 - GHWPARAMS1 |
| 740 | * @hwparams2 - GHWPARAMS2 |
| 741 | * @hwparams3 - GHWPARAMS3 |
| 742 | * @hwparams4 - GHWPARAMS4 |
| 743 | * @hwparams5 - GHWPARAMS5 |
| 744 | * @hwparams6 - GHWPARAMS6 |
| 745 | * @hwparams7 - GHWPARAMS7 |
| 746 | * @hwparams8 - GHWPARAMS8 |
| 747 | */ |
| 748 | struct dwc3_hwparams { |
| 749 | u32 hwparams0; |
| 750 | u32 hwparams1; |
| 751 | u32 hwparams2; |
| 752 | u32 hwparams3; |
| 753 | u32 hwparams4; |
| 754 | u32 hwparams5; |
| 755 | u32 hwparams6; |
| 756 | u32 hwparams7; |
| 757 | u32 hwparams8; |
| 758 | }; |
| 759 | |
Felipe Balbi | 0949e99 | 2011-10-12 10:44:56 +0300 | [diff] [blame] | 760 | /* HWPARAMS0 */ |
| 761 | #define DWC3_MODE(n) ((n) & 0x7) |
| 762 | |
Felipe Balbi | 457e84b | 2012-01-18 18:04:09 +0200 | [diff] [blame] | 763 | #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8) |
| 764 | |
Felipe Balbi | 0949e99 | 2011-10-12 10:44:56 +0300 | [diff] [blame] | 765 | /* HWPARAMS1 */ |
Felipe Balbi | 457e84b | 2012-01-18 18:04:09 +0200 | [diff] [blame] | 766 | #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15) |
| 767 | |
Felipe Balbi | 789451f6 | 2011-05-05 15:53:10 +0300 | [diff] [blame] | 768 | /* HWPARAMS3 */ |
| 769 | #define DWC3_NUM_IN_EPS_MASK (0x1f << 18) |
| 770 | #define DWC3_NUM_EPS_MASK (0x3f << 12) |
| 771 | #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \ |
| 772 | (DWC3_NUM_EPS_MASK)) >> 12) |
| 773 | #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \ |
| 774 | (DWC3_NUM_IN_EPS_MASK)) >> 18) |
| 775 | |
Felipe Balbi | 457e84b | 2012-01-18 18:04:09 +0200 | [diff] [blame] | 776 | /* HWPARAMS7 */ |
| 777 | #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) |
Felipe Balbi | 9f622b2 | 2011-10-12 10:31:04 +0300 | [diff] [blame] | 778 | |
Felipe Balbi | 5ef68c5 | 2016-04-05 11:33:30 +0300 | [diff] [blame] | 779 | /** |
| 780 | * struct dwc3_request - representation of a transfer request |
| 781 | * @request: struct usb_request to be transferred |
| 782 | * @list: a list_head used for request queueing |
| 783 | * @dep: struct dwc3_ep owning this request |
Felipe Balbi | 0b3e4af | 2016-08-12 13:10:10 +0300 | [diff] [blame] | 784 | * @sg: pointer to first incomplete sg |
| 785 | * @num_pending_sgs: counter to pending sgs |
Felipe Balbi | 5ef68c5 | 2016-04-05 11:33:30 +0300 | [diff] [blame] | 786 | * @first_trb_index: index to first trb used by this request |
| 787 | * @epnum: endpoint number to which this request refers |
| 788 | * @trb: pointer to struct dwc3_trb |
| 789 | * @trb_dma: DMA address of @trb |
| 790 | * @direction: IN or OUT direction flag |
| 791 | * @mapped: true when request has been dma-mapped |
| 792 | * @queued: true when request has been queued to HW |
| 793 | */ |
Sebastian Andrzej Siewior | e0ce0b0 | 2011-11-25 12:03:46 +0100 | [diff] [blame] | 794 | struct dwc3_request { |
| 795 | struct usb_request request; |
| 796 | struct list_head list; |
| 797 | struct dwc3_ep *dep; |
Felipe Balbi | 0b3e4af | 2016-08-12 13:10:10 +0300 | [diff] [blame] | 798 | struct scatterlist *sg; |
Sebastian Andrzej Siewior | e0ce0b0 | 2011-11-25 12:03:46 +0100 | [diff] [blame] | 799 | |
Felipe Balbi | 0b3e4af | 2016-08-12 13:10:10 +0300 | [diff] [blame] | 800 | unsigned num_pending_sgs; |
Felipe Balbi | c28f825 | 2016-04-05 12:42:15 +0300 | [diff] [blame] | 801 | u8 first_trb_index; |
Sebastian Andrzej Siewior | e0ce0b0 | 2011-11-25 12:03:46 +0100 | [diff] [blame] | 802 | u8 epnum; |
Felipe Balbi | f6bafc6 | 2012-02-06 11:04:53 +0200 | [diff] [blame] | 803 | struct dwc3_trb *trb; |
Sebastian Andrzej Siewior | e0ce0b0 | 2011-11-25 12:03:46 +0100 | [diff] [blame] | 804 | dma_addr_t trb_dma; |
| 805 | |
| 806 | unsigned direction:1; |
| 807 | unsigned mapped:1; |
Felipe Balbi | aa3342c | 2016-03-14 11:01:31 +0200 | [diff] [blame] | 808 | unsigned started:1; |
Sebastian Andrzej Siewior | e0ce0b0 | 2011-11-25 12:03:46 +0100 | [diff] [blame] | 809 | }; |
| 810 | |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 811 | /* |
| 812 | * struct dwc3_scratchpad_array - hibernation scratchpad array |
| 813 | * (format defined by hw) |
| 814 | */ |
| 815 | struct dwc3_scratchpad_array { |
| 816 | __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS]; |
| 817 | }; |
| 818 | |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 819 | #define DWC3_CONTROLLER_ERROR_EVENT 0 |
| 820 | #define DWC3_CONTROLLER_RESET_EVENT 1 |
| 821 | #define DWC3_CONTROLLER_POST_RESET_EVENT 2 |
| 822 | #define DWC3_CORE_PM_SUSPEND_EVENT 3 |
| 823 | #define DWC3_CORE_PM_RESUME_EVENT 4 |
| 824 | #define DWC3_CONTROLLER_CONNDONE_EVENT 5 |
| 825 | #define DWC3_CONTROLLER_NOTIFY_OTG_EVENT 6 |
| 826 | #define DWC3_CONTROLLER_SET_CURRENT_DRAW_EVENT 7 |
| 827 | #define DWC3_CONTROLLER_RESTART_USB_SESSION 8 |
| 828 | |
Mayank Rana | f4918d3 | 2016-12-15 13:35:55 -0800 | [diff] [blame] | 829 | /* USB GSI event buffer related notification */ |
| 830 | #define DWC3_GSI_EVT_BUF_ALLOC 9 |
| 831 | #define DWC3_GSI_EVT_BUF_SETUP 10 |
| 832 | #define DWC3_GSI_EVT_BUF_CLEANUP 11 |
| 833 | #define DWC3_GSI_EVT_BUF_FREE 12 |
| 834 | |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 835 | #define MAX_INTR_STATS 10 |
| 836 | |
Felipe Balbi | a329949 | 2011-09-30 10:58:48 +0300 | [diff] [blame] | 837 | /** |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 838 | * struct dwc3 - representation of our controller |
Felipe Balbi | 91db07d | 2011-08-27 01:40:52 +0300 | [diff] [blame] | 839 | * @ctrl_req: usb control request which is used for ep0 |
| 840 | * @ep0_trb: trb which is used for the ctrl_req |
Felipe Balbi | 5812b1c | 2011-08-27 22:07:53 +0300 | [diff] [blame] | 841 | * @ep0_bounce: bounce buffer for ep0 |
Felipe Balbi | 04c03d1 | 2015-12-02 10:06:45 -0600 | [diff] [blame] | 842 | * @zlp_buf: used when request->zero is set |
Felipe Balbi | 91db07d | 2011-08-27 01:40:52 +0300 | [diff] [blame] | 843 | * @setup_buf: used while precessing STD USB requests |
| 844 | * @ctrl_req_addr: dma address of ctrl_req |
| 845 | * @ep0_trb: dma address of ep0_trb |
| 846 | * @ep0_usb_req: dummy req used while handling STD USB requests |
Felipe Balbi | 5812b1c | 2011-08-27 22:07:53 +0300 | [diff] [blame] | 847 | * @ep0_bounce_addr: dma address of ep0_bounce |
Felipe Balbi | 0ffcaf3 | 2013-12-19 13:04:28 -0600 | [diff] [blame] | 848 | * @scratch_addr: dma address of scratchbuf |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 849 | * @lock: for synchronizing |
| 850 | * @dev: pointer to our struct device |
Felipe Balbi | d07e881 | 2011-10-12 14:08:26 +0300 | [diff] [blame] | 851 | * @xhci: pointer to our xHCI child |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 852 | * @event_buffer_list: a list of event buffers |
| 853 | * @gadget: device side representation of the peripheral controller |
| 854 | * @gadget_driver: pointer to the gadget driver |
| 855 | * @regs: base address for our registers |
| 856 | * @regs_size: address space size |
Felipe Balbi | bcdb327 | 2016-05-16 10:42:23 +0300 | [diff] [blame] | 857 | * @fladj: frame length adjustment |
Felipe Balbi | 3f308d1 | 2016-05-16 14:17:06 +0300 | [diff] [blame] | 858 | * @irq_gadget: peripheral controller's IRQ number |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 859 | * @reg_phys: physical base address of dwc3 core register address space |
Felipe Balbi | 0ffcaf3 | 2013-12-19 13:04:28 -0600 | [diff] [blame] | 860 | * @nr_scratch: number of scratch buffers |
Felipe Balbi | fae2b90 | 2011-10-14 13:00:30 +0300 | [diff] [blame] | 861 | * @u1u2: only used on revisions <1.83a for workaround |
Vamsi Krishna Samavedam | 86ed20b | 2017-01-31 13:55:38 -0800 | [diff] [blame] | 862 | * @maximum_speed: maximum speed to operate as requested by sw |
| 863 | * @max_hw_supp_speed: maximum speed supported by hw design |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 864 | * @revision: revision register contents |
Ruchika Kharwar | a45c82b8 | 2013-07-06 07:52:49 -0500 | [diff] [blame] | 865 | * @dr_mode: requested mode of operation |
William Wu | 32f2ed8 | 2016-08-16 22:44:38 +0800 | [diff] [blame] | 866 | * @hsphy_mode: UTMI phy mode, one of following: |
| 867 | * - USBPHY_INTERFACE_MODE_UTMI |
| 868 | * - USBPHY_INTERFACE_MODE_UTMIW |
Felipe Balbi | 51e1e7b | 2012-07-19 14:09:48 +0300 | [diff] [blame] | 869 | * @usb2_phy: pointer to USB2 PHY |
| 870 | * @usb3_phy: pointer to USB3 PHY |
Kishon Vijay Abraham I | 5730348 | 2014-03-03 17:08:11 +0530 | [diff] [blame] | 871 | * @usb2_generic_phy: pointer to USB2 PHY |
| 872 | * @usb3_generic_phy: pointer to USB3 PHY |
Heikki Krogerus | 88bc9d1 | 2015-05-13 15:26:51 +0300 | [diff] [blame] | 873 | * @ulpi: pointer to ulpi interface |
Felipe Balbi | 7415f17 | 2012-04-30 14:56:33 +0300 | [diff] [blame] | 874 | * @dcfg: saved contents of DCFG register |
| 875 | * @gctl: saved contents of GCTL register |
Felipe Balbi | c12a0d8 | 2012-04-25 10:45:05 +0300 | [diff] [blame] | 876 | * @isoch_delay: wValue from Set Isochronous Delay request; |
Felipe Balbi | 865e09e | 2012-04-24 16:19:49 +0300 | [diff] [blame] | 877 | * @u2sel: parameter from Set SEL request. |
| 878 | * @u2pel: parameter from Set SEL request. |
| 879 | * @u1sel: parameter from Set SEL request. |
| 880 | * @u1pel: parameter from Set SEL request. |
Felipe Balbi | 789451f6 | 2011-05-05 15:53:10 +0300 | [diff] [blame] | 881 | * @num_out_eps: number of out endpoints |
| 882 | * @num_in_eps: number of in endpoints |
Felipe Balbi | b53c772 | 2011-08-30 15:50:40 +0300 | [diff] [blame] | 883 | * @ep0_next_event: hold the next expected event |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 884 | * @ep0state: state of endpoint zero |
| 885 | * @link_state: link state |
| 886 | * @speed: device speed (super, high, full, low) |
| 887 | * @mem: points to start of memory which is used for this struct. |
Felipe Balbi | a329949 | 2011-09-30 10:58:48 +0300 | [diff] [blame] | 888 | * @hwparams: copy of hwparams registers |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 889 | * @root: debugfs root folder pointer |
Felipe Balbi | f2b685d | 2013-12-19 12:12:37 -0600 | [diff] [blame] | 890 | * @regset: debugfs pointer to regdump file |
| 891 | * @test_mode: true when we're entering a USB test mode |
| 892 | * @test_mode_nr: test feature selector |
Huang Rui | 80caf7d | 2014-10-28 19:54:26 +0800 | [diff] [blame] | 893 | * @lpm_nyet_threshold: LPM NYET response threshold |
Huang Rui | 460d098 | 2014-10-31 11:11:18 +0800 | [diff] [blame] | 894 | * @hird_threshold: HIRD threshold |
Heikki Krogerus | 3e10a2c | 2015-05-13 15:26:49 +0300 | [diff] [blame] | 895 | * @hsphy_interface: "utmi" or "ulpi" |
Felipe Balbi | fc8bb91 | 2016-05-16 13:14:48 +0300 | [diff] [blame] | 896 | * @connected: true when we're connected to a host, false otherwise |
Felipe Balbi | f2b685d | 2013-12-19 12:12:37 -0600 | [diff] [blame] | 897 | * @delayed_status: true when gadget driver asks for delayed status |
| 898 | * @ep0_bounced: true when we used bounce buffer |
| 899 | * @ep0_expect_in: true when we expect a DATA IN transfer |
Felipe Balbi | 81bc559 | 2013-12-19 12:14:29 -0600 | [diff] [blame] | 900 | * @has_hibernation: true when dwc3 was configured with Hibernation |
Arnd Bergmann | 42695fc | 2016-11-17 17:13:47 +0530 | [diff] [blame] | 901 | * @sysdev_is_parent: true when dwc3 device has a parent driver |
Huang Rui | 80caf7d | 2014-10-28 19:54:26 +0800 | [diff] [blame] | 902 | * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that |
| 903 | * there's now way for software to detect this in runtime. |
Huang Rui | 460d098 | 2014-10-31 11:11:18 +0800 | [diff] [blame] | 904 | * @is_utmi_l1_suspend: the core asserts output signal |
| 905 | * 0 - utmi_sleep_n |
| 906 | * 1 - utmi_l1_suspend_n |
Huang Rui | 946bd57 | 2014-10-28 19:54:23 +0800 | [diff] [blame] | 907 | * @is_fpga: true when we are using the FPGA board |
Felipe Balbi | fc8bb91 | 2016-05-16 13:14:48 +0300 | [diff] [blame] | 908 | * @pending_events: true when we have pending IRQs to be handled |
Mayank Rana | a8e4de6 | 2016-12-13 17:11:15 -0800 | [diff] [blame] | 909 | * @needs_fifo_resize: not all users might want fifo resizing, flag it |
Felipe Balbi | f2b685d | 2013-12-19 12:12:37 -0600 | [diff] [blame] | 910 | * @pullups_connected: true when Run/Stop bit is set |
Felipe Balbi | f2b685d | 2013-12-19 12:12:37 -0600 | [diff] [blame] | 911 | * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround |
| 912 | * @start_config_issued: true when StartConfig command has been issued |
| 913 | * @three_stage_setup: set if we perform a three phase setup |
Robert Baldyga | eac68e8 | 2015-03-09 15:06:12 +0100 | [diff] [blame] | 914 | * @usb3_lpm_capable: set if hadrware supports Link Power Management |
Huang Rui | 3b81221 | 2014-10-28 19:54:25 +0800 | [diff] [blame] | 915 | * @disable_scramble_quirk: set if we enable the disable scramble quirk |
Huang Rui | 9a5b2f3 | 2014-10-28 19:54:27 +0800 | [diff] [blame] | 916 | * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk |
Huang Rui | b5a65c4 | 2014-10-28 19:54:28 +0800 | [diff] [blame] | 917 | * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk |
Huang Rui | df31f5b | 2014-10-28 19:54:29 +0800 | [diff] [blame] | 918 | * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk |
Huang Rui | a2a1d0f | 2014-10-28 19:54:30 +0800 | [diff] [blame] | 919 | * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk |
Huang Rui | 41c06ff | 2014-10-28 19:54:31 +0800 | [diff] [blame] | 920 | * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk |
Huang Rui | fb67afc | 2014-10-28 19:54:32 +0800 | [diff] [blame] | 921 | * @lfps_filter_quirk: set if we enable LFPS filter quirk |
Huang Rui | 14f4ac5 | 2014-10-28 19:54:33 +0800 | [diff] [blame] | 922 | * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk |
Huang Rui | 59acfa2 | 2014-10-31 11:11:13 +0800 | [diff] [blame] | 923 | * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy |
Huang Rui | 0effe0a | 2014-10-31 11:11:14 +0800 | [diff] [blame] | 924 | * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy |
John Youn | ec791d1 | 2015-10-02 20:30:57 -0700 | [diff] [blame] | 925 | * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG, |
| 926 | * disabling the suspend signal to the PHY. |
William Wu | 16199f3 | 2016-08-16 22:44:37 +0800 | [diff] [blame] | 927 | * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists |
| 928 | * in GUSB2PHYCFG, specify that USB2 PHY doesn't |
| 929 | * provide a free-running PHY clock. |
William Wu | 00fe081 | 2016-08-16 22:44:39 +0800 | [diff] [blame] | 930 | * @dis_del_phy_power_chg_quirk: set if we disable delay phy power |
| 931 | * change quirk. |
Huang Rui | 6b6a0c9 | 2014-10-31 11:11:12 +0800 | [diff] [blame] | 932 | * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk |
| 933 | * @tx_de_emphasis: Tx de-emphasis value |
| 934 | * 0 - -6dB de-emphasis |
| 935 | * 1 - -3.5dB de-emphasis |
| 936 | * 2 - No de-emphasis |
| 937 | * 3 - Reserved |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 938 | * @is_drd: device supports dual-role or not |
| 939 | * @err_evt_seen: previous event in queue was erratic error |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 940 | * @in_lpm: indicates if controller is in low power mode (no clocks) |
| 941 | * @tx_fifo_size: Available RAM size for TX fifo allocation |
| 942 | * @irq: irq number |
| 943 | * @bh: tasklet which handles the interrupt |
| 944 | * @irq_cnt: total irq count |
| 945 | * @bh_completion_time: time taken for taklet completion |
| 946 | * @bh_handled_evt_cnt: no. of events handled by tasklet per interrupt |
| 947 | * @bh_dbg_index: index for capturing bh_completion_time and bh_handled_evt_cnt |
| 948 | * @wait_linkstate: waitqueue for waiting LINK to move into required state |
| 949 | * @vbus_draw: current to be drawn from USB |
Mayank Rana | 861da2b | 2016-07-13 13:47:57 -0700 | [diff] [blame] | 950 | * @index: dwc3 instance's number |
| 951 | * @dwc_ipc_log_ctxt: dwc3 ipc log context |
Mayank Rana | ac1200c | 2017-04-25 13:48:46 -0700 | [diff] [blame] | 952 | * @last_fifo_depth: total TXFIFO depth of all enabled USB IN/INT endpoints |
John Youn | 26cac20 | 2016-11-14 12:32:43 -0800 | [diff] [blame] | 953 | * @imod_interval: set the interrupt moderation interval in 250ns |
| 954 | * increments or 0 to disable. |
Mayank Rana | 51519df | 2017-09-25 16:48:39 -0700 | [diff] [blame] | 955 | * @create_reg_debugfs: create debugfs entry to allow dwc3 register dump |
Mayank Rana | e27420f | 2017-10-10 15:44:19 -0700 | [diff] [blame] | 956 | * @xhci_imod_value: imod value to use with xhci |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 957 | */ |
| 958 | struct dwc3 { |
| 959 | struct usb_ctrlrequest *ctrl_req; |
Felipe Balbi | f6bafc6 | 2012-02-06 11:04:53 +0200 | [diff] [blame] | 960 | struct dwc3_trb *ep0_trb; |
Felipe Balbi | 5812b1c | 2011-08-27 22:07:53 +0300 | [diff] [blame] | 961 | void *ep0_bounce; |
Felipe Balbi | 04c03d1 | 2015-12-02 10:06:45 -0600 | [diff] [blame] | 962 | void *zlp_buf; |
Felipe Balbi | 0ffcaf3 | 2013-12-19 13:04:28 -0600 | [diff] [blame] | 963 | void *scratchbuf; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 964 | u8 *setup_buf; |
| 965 | dma_addr_t ctrl_req_addr; |
| 966 | dma_addr_t ep0_trb_addr; |
Felipe Balbi | 5812b1c | 2011-08-27 22:07:53 +0300 | [diff] [blame] | 967 | dma_addr_t ep0_bounce_addr; |
Felipe Balbi | 0ffcaf3 | 2013-12-19 13:04:28 -0600 | [diff] [blame] | 968 | dma_addr_t scratch_addr; |
Sebastian Andrzej Siewior | e0ce0b0 | 2011-11-25 12:03:46 +0100 | [diff] [blame] | 969 | struct dwc3_request ep0_usb_req; |
Felipe Balbi | 789451f6 | 2011-05-05 15:53:10 +0300 | [diff] [blame] | 970 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 971 | /* device lock */ |
| 972 | spinlock_t lock; |
Felipe Balbi | 789451f6 | 2011-05-05 15:53:10 +0300 | [diff] [blame] | 973 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 974 | struct device *dev; |
Arnd Bergmann | 42695fc | 2016-11-17 17:13:47 +0530 | [diff] [blame] | 975 | struct device *sysdev; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 976 | |
Felipe Balbi | d07e881 | 2011-10-12 14:08:26 +0300 | [diff] [blame] | 977 | struct platform_device *xhci; |
Ido Shayevitz | 51249dc | 2012-04-24 14:18:39 +0300 | [diff] [blame] | 978 | struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; |
Felipe Balbi | d07e881 | 2011-10-12 14:08:26 +0300 | [diff] [blame] | 979 | |
Felipe Balbi | 696c8b1 | 2016-03-30 09:37:03 +0300 | [diff] [blame] | 980 | struct dwc3_event_buffer *ev_buf; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 981 | struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; |
| 982 | |
| 983 | struct usb_gadget gadget; |
| 984 | struct usb_gadget_driver *gadget_driver; |
| 985 | |
Felipe Balbi | 51e1e7b | 2012-07-19 14:09:48 +0300 | [diff] [blame] | 986 | struct usb_phy *usb2_phy; |
| 987 | struct usb_phy *usb3_phy; |
| 988 | |
Kishon Vijay Abraham I | 5730348 | 2014-03-03 17:08:11 +0530 | [diff] [blame] | 989 | struct phy *usb2_generic_phy; |
| 990 | struct phy *usb3_generic_phy; |
| 991 | |
Heikki Krogerus | 88bc9d1 | 2015-05-13 15:26:51 +0300 | [diff] [blame] | 992 | struct ulpi *ulpi; |
| 993 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 994 | void __iomem *regs; |
| 995 | size_t regs_size; |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 996 | phys_addr_t reg_phys; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 997 | |
Ruchika Kharwar | a45c82b8 | 2013-07-06 07:52:49 -0500 | [diff] [blame] | 998 | enum usb_dr_mode dr_mode; |
William Wu | 32f2ed8 | 2016-08-16 22:44:38 +0800 | [diff] [blame] | 999 | enum usb_phy_interface hsphy_mode; |
Ruchika Kharwar | a45c82b8 | 2013-07-06 07:52:49 -0500 | [diff] [blame] | 1000 | |
Felipe Balbi | bcdb327 | 2016-05-16 10:42:23 +0300 | [diff] [blame] | 1001 | u32 fladj; |
Felipe Balbi | 3f308d1 | 2016-05-16 14:17:06 +0300 | [diff] [blame] | 1002 | u32 irq_gadget; |
Felipe Balbi | 0ffcaf3 | 2013-12-19 13:04:28 -0600 | [diff] [blame] | 1003 | u32 nr_scratch; |
Felipe Balbi | fae2b90 | 2011-10-14 13:00:30 +0300 | [diff] [blame] | 1004 | u32 u1u2; |
Felipe Balbi | 6c167fc | 2011-10-07 22:55:04 +0300 | [diff] [blame] | 1005 | u32 maximum_speed; |
Vamsi Krishna Samavedam | 86ed20b | 2017-01-31 13:55:38 -0800 | [diff] [blame] | 1006 | u32 max_hw_supp_speed; |
John Youn | 690fb37 | 2015-09-04 19:15:10 -0700 | [diff] [blame] | 1007 | |
| 1008 | /* |
| 1009 | * All 3.1 IP version constants are greater than the 3.0 IP |
| 1010 | * version constants. This works for most version checks in |
| 1011 | * dwc3. However, in the future, this may not apply as |
| 1012 | * features may be developed on newer versions of the 3.0 IP |
| 1013 | * that are not in the 3.1 IP. |
| 1014 | */ |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 1015 | u32 revision; |
| 1016 | |
| 1017 | #define DWC3_REVISION_173A 0x5533173a |
| 1018 | #define DWC3_REVISION_175A 0x5533175a |
| 1019 | #define DWC3_REVISION_180A 0x5533180a |
| 1020 | #define DWC3_REVISION_183A 0x5533183a |
| 1021 | #define DWC3_REVISION_185A 0x5533185a |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 1022 | #define DWC3_REVISION_187A 0x5533187a |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 1023 | #define DWC3_REVISION_188A 0x5533188a |
| 1024 | #define DWC3_REVISION_190A 0x5533190a |
Paul Zimmerman | 2c61a8e | 2012-02-15 18:56:58 -0800 | [diff] [blame] | 1025 | #define DWC3_REVISION_194A 0x5533194a |
Felipe Balbi | 1522d70 | 2012-03-23 12:10:48 +0200 | [diff] [blame] | 1026 | #define DWC3_REVISION_200A 0x5533200a |
| 1027 | #define DWC3_REVISION_202A 0x5533202a |
| 1028 | #define DWC3_REVISION_210A 0x5533210a |
| 1029 | #define DWC3_REVISION_220A 0x5533220a |
Felipe Balbi | 7ac6a59 | 2012-09-18 21:22:32 +0300 | [diff] [blame] | 1030 | #define DWC3_REVISION_230A 0x5533230a |
| 1031 | #define DWC3_REVISION_240A 0x5533240a |
| 1032 | #define DWC3_REVISION_250A 0x5533250a |
Felipe Balbi | dbf5aaf | 2014-03-04 09:35:02 -0600 | [diff] [blame] | 1033 | #define DWC3_REVISION_260A 0x5533260a |
| 1034 | #define DWC3_REVISION_270A 0x5533270a |
| 1035 | #define DWC3_REVISION_280A 0x5533280a |
John Youn | 512e475 | 2016-08-19 11:57:52 -0700 | [diff] [blame] | 1036 | #define DWC3_REVISION_300A 0x5533300a |
| 1037 | #define DWC3_REVISION_310A 0x5533310a |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 1038 | |
John Youn | 690fb37 | 2015-09-04 19:15:10 -0700 | [diff] [blame] | 1039 | /* |
| 1040 | * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really |
| 1041 | * just so dwc31 revisions are always larger than dwc3. |
| 1042 | */ |
| 1043 | #define DWC3_REVISION_IS_DWC31 0x80000000 |
John Youn | e77c561 | 2016-05-20 16:34:23 -0700 | [diff] [blame] | 1044 | #define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_DWC31) |
John Youn | 26cac20 | 2016-11-14 12:32:43 -0800 | [diff] [blame] | 1045 | #define DWC3_USB31_REVISION_120A (0x3132302a | DWC3_REVISION_IS_DWC31) |
John Youn | 690fb37 | 2015-09-04 19:15:10 -0700 | [diff] [blame] | 1046 | |
Felipe Balbi | b53c772 | 2011-08-30 15:50:40 +0300 | [diff] [blame] | 1047 | enum dwc3_ep0_next ep0_next_event; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 1048 | enum dwc3_ep0_state ep0state; |
| 1049 | enum dwc3_link_state link_state; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 1050 | |
Felipe Balbi | c12a0d8 | 2012-04-25 10:45:05 +0300 | [diff] [blame] | 1051 | u16 isoch_delay; |
Felipe Balbi | 865e09e | 2012-04-24 16:19:49 +0300 | [diff] [blame] | 1052 | u16 u2sel; |
| 1053 | u16 u2pel; |
| 1054 | u8 u1sel; |
| 1055 | u8 u1pel; |
| 1056 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 1057 | u8 speed; |
Felipe Balbi | 865e09e | 2012-04-24 16:19:49 +0300 | [diff] [blame] | 1058 | |
Felipe Balbi | 789451f6 | 2011-05-05 15:53:10 +0300 | [diff] [blame] | 1059 | u8 num_out_eps; |
| 1060 | u8 num_in_eps; |
| 1061 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 1062 | void *mem; |
| 1063 | |
Felipe Balbi | a329949 | 2011-09-30 10:58:48 +0300 | [diff] [blame] | 1064 | struct dwc3_hwparams hwparams; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 1065 | struct dentry *root; |
Felipe Balbi | d766802 | 2013-01-18 10:21:34 +0200 | [diff] [blame] | 1066 | struct debugfs_regset32 *regset; |
Gerard Cauvy | 3b63736 | 2012-02-10 12:21:18 +0200 | [diff] [blame] | 1067 | |
| 1068 | u8 test_mode; |
| 1069 | u8 test_mode_nr; |
Huang Rui | 80caf7d | 2014-10-28 19:54:26 +0800 | [diff] [blame] | 1070 | u8 lpm_nyet_threshold; |
Huang Rui | 460d098 | 2014-10-31 11:11:18 +0800 | [diff] [blame] | 1071 | u8 hird_threshold; |
Felipe Balbi | f2b685d | 2013-12-19 12:12:37 -0600 | [diff] [blame] | 1072 | |
Heikki Krogerus | 3e10a2c | 2015-05-13 15:26:49 +0300 | [diff] [blame] | 1073 | const char *hsphy_interface; |
| 1074 | |
Felipe Balbi | fc8bb91 | 2016-05-16 13:14:48 +0300 | [diff] [blame] | 1075 | unsigned connected:1; |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 1076 | void (*notify_event)(struct dwc3 *, unsigned int); |
| 1077 | struct work_struct wakeup_work; |
| 1078 | |
Felipe Balbi | f2b685d | 2013-12-19 12:12:37 -0600 | [diff] [blame] | 1079 | unsigned delayed_status:1; |
| 1080 | unsigned ep0_bounced:1; |
| 1081 | unsigned ep0_expect_in:1; |
Felipe Balbi | 81bc559 | 2013-12-19 12:14:29 -0600 | [diff] [blame] | 1082 | unsigned has_hibernation:1; |
Arnd Bergmann | 42695fc | 2016-11-17 17:13:47 +0530 | [diff] [blame] | 1083 | unsigned sysdev_is_parent:1; |
Huang Rui | 80caf7d | 2014-10-28 19:54:26 +0800 | [diff] [blame] | 1084 | unsigned has_lpm_erratum:1; |
Huang Rui | 460d098 | 2014-10-31 11:11:18 +0800 | [diff] [blame] | 1085 | unsigned is_utmi_l1_suspend:1; |
Huang Rui | 946bd57 | 2014-10-28 19:54:23 +0800 | [diff] [blame] | 1086 | unsigned is_fpga:1; |
Felipe Balbi | fc8bb91 | 2016-05-16 13:14:48 +0300 | [diff] [blame] | 1087 | unsigned pending_events:1; |
Mayank Rana | a8e4de6 | 2016-12-13 17:11:15 -0800 | [diff] [blame] | 1088 | unsigned needs_fifo_resize:1; |
Felipe Balbi | f2b685d | 2013-12-19 12:12:37 -0600 | [diff] [blame] | 1089 | unsigned pullups_connected:1; |
Felipe Balbi | f2b685d | 2013-12-19 12:12:37 -0600 | [diff] [blame] | 1090 | unsigned setup_packet_pending:1; |
Felipe Balbi | f2b685d | 2013-12-19 12:12:37 -0600 | [diff] [blame] | 1091 | unsigned three_stage_setup:1; |
Robert Baldyga | eac68e8 | 2015-03-09 15:06:12 +0100 | [diff] [blame] | 1092 | unsigned usb3_lpm_capable:1; |
Huang Rui | 3b81221 | 2014-10-28 19:54:25 +0800 | [diff] [blame] | 1093 | |
| 1094 | unsigned disable_scramble_quirk:1; |
Huang Rui | 9a5b2f3 | 2014-10-28 19:54:27 +0800 | [diff] [blame] | 1095 | unsigned u2exit_lfps_quirk:1; |
Huang Rui | b5a65c4 | 2014-10-28 19:54:28 +0800 | [diff] [blame] | 1096 | unsigned u2ss_inp3_quirk:1; |
Huang Rui | df31f5b | 2014-10-28 19:54:29 +0800 | [diff] [blame] | 1097 | unsigned req_p1p2p3_quirk:1; |
Huang Rui | a2a1d0f | 2014-10-28 19:54:30 +0800 | [diff] [blame] | 1098 | unsigned del_p1p2p3_quirk:1; |
Huang Rui | 41c06ff | 2014-10-28 19:54:31 +0800 | [diff] [blame] | 1099 | unsigned del_phy_power_chg_quirk:1; |
Huang Rui | fb67afc | 2014-10-28 19:54:32 +0800 | [diff] [blame] | 1100 | unsigned lfps_filter_quirk:1; |
Huang Rui | 14f4ac5 | 2014-10-28 19:54:33 +0800 | [diff] [blame] | 1101 | unsigned rx_detect_poll_quirk:1; |
Huang Rui | 59acfa2 | 2014-10-31 11:11:13 +0800 | [diff] [blame] | 1102 | unsigned dis_u3_susphy_quirk:1; |
Huang Rui | 0effe0a | 2014-10-31 11:11:14 +0800 | [diff] [blame] | 1103 | unsigned dis_u2_susphy_quirk:1; |
John Youn | ec791d1 | 2015-10-02 20:30:57 -0700 | [diff] [blame] | 1104 | unsigned dis_enblslpm_quirk:1; |
Rajesh Bhagat | e58dd35 | 2016-03-14 14:40:50 +0530 | [diff] [blame] | 1105 | unsigned dis_rxdet_inp3_quirk:1; |
William Wu | 16199f3 | 2016-08-16 22:44:37 +0800 | [diff] [blame] | 1106 | unsigned dis_u2_freeclk_exists_quirk:1; |
William Wu | 00fe081 | 2016-08-16 22:44:39 +0800 | [diff] [blame] | 1107 | unsigned dis_del_phy_power_chg_quirk:1; |
Huang Rui | 6b6a0c9 | 2014-10-31 11:11:12 +0800 | [diff] [blame] | 1108 | |
| 1109 | unsigned tx_de_emphasis_quirk:1; |
| 1110 | unsigned tx_de_emphasis:2; |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 1111 | unsigned is_drd:1; |
| 1112 | /* Indicate if the gadget was powered by the otg driver */ |
| 1113 | unsigned vbus_active:1; |
| 1114 | /* Indicate if software connect was issued by the usb_gadget_driver */ |
| 1115 | unsigned softconnect:1; |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 1116 | unsigned err_evt_seen:1; |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 1117 | /* Indicate if need to disable controller internal clkgating */ |
| 1118 | unsigned disable_clk_gating:1; |
| 1119 | unsigned enable_bus_suspend:1; |
| 1120 | |
| 1121 | atomic_t in_lpm; |
| 1122 | int tx_fifo_size; |
| 1123 | bool b_suspend; |
| 1124 | unsigned int vbus_draw; |
| 1125 | |
John Youn | 26cac20 | 2016-11-14 12:32:43 -0800 | [diff] [blame] | 1126 | u16 imod_interval; |
| 1127 | |
Mayank Rana | f616a7f | 2017-03-20 16:10:39 -0700 | [diff] [blame] | 1128 | struct workqueue_struct *dwc_wq; |
| 1129 | struct work_struct bh_work; |
| 1130 | |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 1131 | /* IRQ timing statistics */ |
| 1132 | int irq; |
Hemant Kumar | 4387417 | 2016-08-25 16:17:48 -0700 | [diff] [blame] | 1133 | unsigned long ep_cmd_timeout_cnt; |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 1134 | unsigned long irq_cnt; |
| 1135 | unsigned int bh_completion_time[MAX_INTR_STATS]; |
| 1136 | unsigned int bh_handled_evt_cnt[MAX_INTR_STATS]; |
| 1137 | unsigned int bh_dbg_index; |
| 1138 | ktime_t irq_start_time[MAX_INTR_STATS]; |
| 1139 | ktime_t t_pwr_evt_irq; |
| 1140 | unsigned int irq_completion_time[MAX_INTR_STATS]; |
| 1141 | unsigned int irq_event_count[MAX_INTR_STATS]; |
| 1142 | unsigned int irq_dbg_index; |
| 1143 | |
Hemant Kumar | e4f2781 | 2017-01-27 18:31:22 -0800 | [diff] [blame] | 1144 | unsigned long l1_remote_wakeup_cnt; |
| 1145 | |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 1146 | wait_queue_head_t wait_linkstate; |
Mayank Rana | 861da2b | 2016-07-13 13:47:57 -0700 | [diff] [blame] | 1147 | unsigned int index; |
| 1148 | void *dwc_ipc_log_ctxt; |
Mayank Rana | ac1200c | 2017-04-25 13:48:46 -0700 | [diff] [blame] | 1149 | int last_fifo_depth; |
Mayank Rana | 0c667b4 | 2017-02-09 11:56:51 -0800 | [diff] [blame] | 1150 | struct dwc3_gadget_events dbg_gadget_events; |
Mayank Rana | 51519df | 2017-09-25 16:48:39 -0700 | [diff] [blame] | 1151 | bool create_reg_debugfs; |
Mayank Rana | e27420f | 2017-10-10 15:44:19 -0700 | [diff] [blame] | 1152 | u32 xhci_imod_value; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 1153 | }; |
| 1154 | |
| 1155 | /* -------------------------------------------------------------------------- */ |
| 1156 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 1157 | /* -------------------------------------------------------------------------- */ |
| 1158 | |
| 1159 | struct dwc3_event_type { |
| 1160 | u32 is_devspec:1; |
Huang Rui | 1974d49 | 2013-06-27 01:08:11 +0800 | [diff] [blame] | 1161 | u32 type:7; |
| 1162 | u32 reserved8_31:24; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 1163 | } __packed; |
| 1164 | |
| 1165 | #define DWC3_DEPEVT_XFERCOMPLETE 0x01 |
| 1166 | #define DWC3_DEPEVT_XFERINPROGRESS 0x02 |
| 1167 | #define DWC3_DEPEVT_XFERNOTREADY 0x03 |
| 1168 | #define DWC3_DEPEVT_RXTXFIFOEVT 0x04 |
| 1169 | #define DWC3_DEPEVT_STREAMEVT 0x06 |
| 1170 | #define DWC3_DEPEVT_EPCMDCMPLT 0x07 |
| 1171 | |
| 1172 | /** |
| 1173 | * struct dwc3_event_depvt - Device Endpoint Events |
| 1174 | * @one_bit: indicates this is an endpoint event (not used) |
| 1175 | * @endpoint_number: number of the endpoint |
| 1176 | * @endpoint_event: The event we have: |
| 1177 | * 0x00 - Reserved |
| 1178 | * 0x01 - XferComplete |
| 1179 | * 0x02 - XferInProgress |
| 1180 | * 0x03 - XferNotReady |
| 1181 | * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun) |
| 1182 | * 0x05 - Reserved |
| 1183 | * 0x06 - StreamEvt |
| 1184 | * 0x07 - EPCmdCmplt |
| 1185 | * @reserved11_10: Reserved, don't use. |
| 1186 | * @status: Indicates the status of the event. Refer to databook for |
| 1187 | * more information. |
| 1188 | * @parameters: Parameters of the current event. Refer to databook for |
| 1189 | * more information. |
| 1190 | */ |
| 1191 | struct dwc3_event_depevt { |
| 1192 | u32 one_bit:1; |
| 1193 | u32 endpoint_number:5; |
| 1194 | u32 endpoint_event:4; |
| 1195 | u32 reserved11_10:2; |
| 1196 | u32 status:4; |
Felipe Balbi | 40aa41fb | 2012-01-18 17:06:03 +0200 | [diff] [blame] | 1197 | |
| 1198 | /* Within XferNotReady */ |
| 1199 | #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3) |
| 1200 | |
| 1201 | /* Within XferComplete */ |
Paul Zimmerman | 1d04679 | 2012-02-15 18:56:56 -0800 | [diff] [blame] | 1202 | #define DEPEVT_STATUS_BUSERR (1 << 0) |
| 1203 | #define DEPEVT_STATUS_SHORT (1 << 1) |
| 1204 | #define DEPEVT_STATUS_IOC (1 << 2) |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 1205 | #define DEPEVT_STATUS_LST (1 << 3) |
Felipe Balbi | dc137f0 | 2011-08-27 22:04:32 +0300 | [diff] [blame] | 1206 | |
Felipe Balbi | 879631a | 2011-09-30 10:58:47 +0300 | [diff] [blame] | 1207 | /* Stream event only */ |
| 1208 | #define DEPEVT_STREAMEVT_FOUND 1 |
| 1209 | #define DEPEVT_STREAMEVT_NOTFOUND 2 |
| 1210 | |
Felipe Balbi | dc137f0 | 2011-08-27 22:04:32 +0300 | [diff] [blame] | 1211 | /* Control-only Status */ |
Felipe Balbi | dc137f0 | 2011-08-27 22:04:32 +0300 | [diff] [blame] | 1212 | #define DEPEVT_STATUS_CONTROL_DATA 1 |
| 1213 | #define DEPEVT_STATUS_CONTROL_STATUS 2 |
| 1214 | |
Konrad Leszczynski | 7b9cc7a | 2016-02-12 15:21:46 +0000 | [diff] [blame] | 1215 | /* In response to Start Transfer */ |
| 1216 | #define DEPEVT_TRANSFER_NO_RESOURCE 1 |
| 1217 | #define DEPEVT_TRANSFER_BUS_EXPIRY 2 |
| 1218 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 1219 | u32 parameters:16; |
| 1220 | } __packed; |
| 1221 | |
| 1222 | /** |
| 1223 | * struct dwc3_event_devt - Device Events |
| 1224 | * @one_bit: indicates this is a non-endpoint event (not used) |
| 1225 | * @device_event: indicates it's a device event. Should read as 0x00 |
| 1226 | * @type: indicates the type of device event. |
| 1227 | * 0 - DisconnEvt |
| 1228 | * 1 - USBRst |
| 1229 | * 2 - ConnectDone |
| 1230 | * 3 - ULStChng |
| 1231 | * 4 - WkUpEvt |
| 1232 | * 5 - Reserved |
| 1233 | * 6 - EOPF |
| 1234 | * 7 - SOF |
| 1235 | * 8 - Reserved |
| 1236 | * 9 - ErrticErr |
| 1237 | * 10 - CmdCmplt |
| 1238 | * 11 - EvntOverflow |
| 1239 | * 12 - VndrDevTstRcved |
| 1240 | * @reserved15_12: Reserved, not used |
| 1241 | * @event_info: Information about this event |
Huang Rui | 06f9b6e | 2014-01-07 17:45:50 +0800 | [diff] [blame] | 1242 | * @reserved31_25: Reserved, not used |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 1243 | */ |
| 1244 | struct dwc3_event_devt { |
| 1245 | u32 one_bit:1; |
| 1246 | u32 device_event:7; |
| 1247 | u32 type:4; |
| 1248 | u32 reserved15_12:4; |
Huang Rui | 06f9b6e | 2014-01-07 17:45:50 +0800 | [diff] [blame] | 1249 | u32 event_info:9; |
| 1250 | u32 reserved31_25:7; |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 1251 | } __packed; |
| 1252 | |
| 1253 | /** |
| 1254 | * struct dwc3_event_gevt - Other Core Events |
| 1255 | * @one_bit: indicates this is a non-endpoint event (not used) |
| 1256 | * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event. |
| 1257 | * @phy_port_number: self-explanatory |
| 1258 | * @reserved31_12: Reserved, not used. |
| 1259 | */ |
| 1260 | struct dwc3_event_gevt { |
| 1261 | u32 one_bit:1; |
| 1262 | u32 device_event:7; |
| 1263 | u32 phy_port_number:4; |
| 1264 | u32 reserved31_12:20; |
| 1265 | } __packed; |
| 1266 | |
| 1267 | /** |
| 1268 | * union dwc3_event - representation of Event Buffer contents |
| 1269 | * @raw: raw 32-bit event |
| 1270 | * @type: the type of the event |
| 1271 | * @depevt: Device Endpoint Event |
| 1272 | * @devt: Device Event |
| 1273 | * @gevt: Global Event |
| 1274 | */ |
| 1275 | union dwc3_event { |
| 1276 | u32 raw; |
| 1277 | struct dwc3_event_type type; |
| 1278 | struct dwc3_event_depevt depevt; |
| 1279 | struct dwc3_event_devt devt; |
| 1280 | struct dwc3_event_gevt gevt; |
| 1281 | }; |
| 1282 | |
Felipe Balbi | 6101830 | 2014-03-04 09:23:50 -0600 | [diff] [blame] | 1283 | /** |
| 1284 | * struct dwc3_gadget_ep_cmd_params - representation of endpoint command |
| 1285 | * parameters |
| 1286 | * @param2: third parameter |
| 1287 | * @param1: second parameter |
| 1288 | * @param0: first parameter |
| 1289 | */ |
| 1290 | struct dwc3_gadget_ep_cmd_params { |
| 1291 | u32 param2; |
| 1292 | u32 param1; |
| 1293 | u32 param0; |
| 1294 | }; |
| 1295 | |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 1296 | /* |
| 1297 | * DWC3 Features to be used as Driver Data |
| 1298 | */ |
| 1299 | |
| 1300 | #define DWC3_HAS_PERIPHERAL BIT(0) |
| 1301 | #define DWC3_HAS_XHCI BIT(1) |
| 1302 | #define DWC3_HAS_OTG BIT(3) |
| 1303 | |
Felipe Balbi | d07e881 | 2011-10-12 14:08:26 +0300 | [diff] [blame] | 1304 | /* prototypes */ |
Sebastian Andrzej Siewior | 3140e8c | 2011-10-31 22:25:40 +0100 | [diff] [blame] | 1305 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode); |
Felipe Balbi | cf6d867 | 2016-04-14 15:03:39 +0300 | [diff] [blame] | 1306 | u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type); |
Mayank Rana | ac1200c | 2017-04-25 13:48:46 -0700 | [diff] [blame] | 1307 | int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc, struct dwc3_ep *dep); |
Sebastian Andrzej Siewior | 3140e8c | 2011-10-31 22:25:40 +0100 | [diff] [blame] | 1308 | |
John Youn | 15c6451 | 2016-11-10 17:08:48 -0800 | [diff] [blame] | 1309 | /* check whether we are on the DWC_usb3 core */ |
| 1310 | static inline bool dwc3_is_usb3(struct dwc3 *dwc) |
| 1311 | { |
| 1312 | return !(dwc->revision & DWC3_REVISION_IS_DWC31); |
| 1313 | } |
| 1314 | |
John Youn | c4137a9 | 2016-02-05 17:08:18 -0800 | [diff] [blame] | 1315 | /* check whether we are on the DWC_usb31 core */ |
| 1316 | static inline bool dwc3_is_usb31(struct dwc3 *dwc) |
| 1317 | { |
| 1318 | return !!(dwc->revision & DWC3_REVISION_IS_DWC31); |
| 1319 | } |
| 1320 | |
John Youn | 26cac20 | 2016-11-14 12:32:43 -0800 | [diff] [blame] | 1321 | bool dwc3_has_imod(struct dwc3 *dwc); |
| 1322 | |
Vivek Gautam | 388e5c5 | 2013-01-15 16:09:21 +0530 | [diff] [blame] | 1323 | #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) |
Felipe Balbi | d07e881 | 2011-10-12 14:08:26 +0300 | [diff] [blame] | 1324 | int dwc3_host_init(struct dwc3 *dwc); |
| 1325 | void dwc3_host_exit(struct dwc3 *dwc); |
Vivek Gautam | 388e5c5 | 2013-01-15 16:09:21 +0530 | [diff] [blame] | 1326 | #else |
| 1327 | static inline int dwc3_host_init(struct dwc3 *dwc) |
| 1328 | { return 0; } |
| 1329 | static inline void dwc3_host_exit(struct dwc3 *dwc) |
| 1330 | { } |
| 1331 | #endif |
Felipe Balbi | d07e881 | 2011-10-12 14:08:26 +0300 | [diff] [blame] | 1332 | |
Vivek Gautam | 388e5c5 | 2013-01-15 16:09:21 +0530 | [diff] [blame] | 1333 | #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) |
Felipe Balbi | f80b45e | 2011-10-12 14:15:49 +0300 | [diff] [blame] | 1334 | int dwc3_gadget_init(struct dwc3 *dwc); |
| 1335 | void dwc3_gadget_exit(struct dwc3 *dwc); |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 1336 | void dwc3_gadget_restart(struct dwc3 *dwc); |
Felipe Balbi | 6101830 | 2014-03-04 09:23:50 -0600 | [diff] [blame] | 1337 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode); |
| 1338 | int dwc3_gadget_get_link_state(struct dwc3 *dwc); |
| 1339 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); |
Felipe Balbi | 2cd4718 | 2016-04-12 16:42:43 +0300 | [diff] [blame] | 1340 | int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, |
| 1341 | struct dwc3_gadget_ep_cmd_params *params); |
Felipe Balbi | 3ece0ec | 2014-09-05 09:47:44 -0500 | [diff] [blame] | 1342 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param); |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 1343 | void dwc3_gadget_enable_irq(struct dwc3 *dwc); |
| 1344 | void dwc3_gadget_disable_irq(struct dwc3 *dwc); |
Vivek Gautam | 388e5c5 | 2013-01-15 16:09:21 +0530 | [diff] [blame] | 1345 | #else |
| 1346 | static inline int dwc3_gadget_init(struct dwc3 *dwc) |
| 1347 | { return 0; } |
| 1348 | static inline void dwc3_gadget_exit(struct dwc3 *dwc) |
| 1349 | { } |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 1350 | static inline void dwc3_gadget_restart(struct dwc3 *dwc) |
| 1351 | { } |
Felipe Balbi | 6101830 | 2014-03-04 09:23:50 -0600 | [diff] [blame] | 1352 | static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) |
| 1353 | { return 0; } |
| 1354 | static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc) |
| 1355 | { return 0; } |
| 1356 | static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc, |
| 1357 | enum dwc3_link_state state) |
| 1358 | { return 0; } |
| 1359 | |
Felipe Balbi | 2cd4718 | 2016-04-12 16:42:43 +0300 | [diff] [blame] | 1360 | static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, |
| 1361 | struct dwc3_gadget_ep_cmd_params *params) |
Felipe Balbi | 6101830 | 2014-03-04 09:23:50 -0600 | [diff] [blame] | 1362 | { return 0; } |
| 1363 | static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, |
| 1364 | int cmd, u32 param) |
| 1365 | { return 0; } |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 1366 | static inline void dwc3_gadget_enable_irq(struct dwc3 *dwc) |
| 1367 | { } |
| 1368 | static inline void dwc3_gadget_disable_irq(struct dwc3 *dwc) |
| 1369 | { } |
Vivek Gautam | 388e5c5 | 2013-01-15 16:09:21 +0530 | [diff] [blame] | 1370 | #endif |
Felipe Balbi | f80b45e | 2011-10-12 14:15:49 +0300 | [diff] [blame] | 1371 | |
Felipe Balbi | 7415f17 | 2012-04-30 14:56:33 +0300 | [diff] [blame] | 1372 | /* power management interface */ |
| 1373 | #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) |
Felipe Balbi | 7415f17 | 2012-04-30 14:56:33 +0300 | [diff] [blame] | 1374 | int dwc3_gadget_suspend(struct dwc3 *dwc); |
| 1375 | int dwc3_gadget_resume(struct dwc3 *dwc); |
Felipe Balbi | fc8bb91 | 2016-05-16 13:14:48 +0300 | [diff] [blame] | 1376 | void dwc3_gadget_process_pending_events(struct dwc3 *dwc); |
Felipe Balbi | 7415f17 | 2012-04-30 14:56:33 +0300 | [diff] [blame] | 1377 | #else |
Felipe Balbi | 7415f17 | 2012-04-30 14:56:33 +0300 | [diff] [blame] | 1378 | static inline int dwc3_gadget_suspend(struct dwc3 *dwc) |
| 1379 | { |
| 1380 | return 0; |
| 1381 | } |
| 1382 | |
| 1383 | static inline int dwc3_gadget_resume(struct dwc3 *dwc) |
| 1384 | { |
| 1385 | return 0; |
| 1386 | } |
Felipe Balbi | fc8bb91 | 2016-05-16 13:14:48 +0300 | [diff] [blame] | 1387 | |
| 1388 | static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc) |
| 1389 | { |
| 1390 | } |
Felipe Balbi | 7415f17 | 2012-04-30 14:56:33 +0300 | [diff] [blame] | 1391 | #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */ |
| 1392 | |
Heikki Krogerus | 88bc9d1 | 2015-05-13 15:26:51 +0300 | [diff] [blame] | 1393 | #if IS_ENABLED(CONFIG_USB_DWC3_ULPI) |
| 1394 | int dwc3_ulpi_init(struct dwc3 *dwc); |
| 1395 | void dwc3_ulpi_exit(struct dwc3 *dwc); |
| 1396 | #else |
| 1397 | static inline int dwc3_ulpi_init(struct dwc3 *dwc) |
| 1398 | { return 0; } |
| 1399 | static inline void dwc3_ulpi_exit(struct dwc3 *dwc) |
| 1400 | { } |
| 1401 | #endif |
| 1402 | |
Mayank Rana | a99689a | 2016-08-10 17:39:47 -0700 | [diff] [blame] | 1403 | int dwc3_core_init(struct dwc3 *dwc); |
| 1404 | int dwc3_core_pre_init(struct dwc3 *dwc); |
| 1405 | void dwc3_post_host_reset_core_init(struct dwc3 *dwc); |
| 1406 | int dwc3_event_buffers_setup(struct dwc3 *dwc); |
| 1407 | void dwc3_usb3_phy_suspend(struct dwc3 *dwc, int suspend); |
| 1408 | |
| 1409 | extern void dwc3_set_notifier( |
| 1410 | void (*notify)(struct dwc3 *dwc3, unsigned int event)); |
| 1411 | extern int dwc3_notify_event(struct dwc3 *dwc3, unsigned int event); |
Felipe Balbi | 72246da | 2011-08-19 18:10:58 +0300 | [diff] [blame] | 1412 | #endif /* __DRIVERS_USB_DWC3_CORE_H */ |