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Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +08001/*
2 * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2 only.
7 */
8
Jean-Christophe PLAGNIOL-VILLARD6db64d22013-05-15 01:21:50 +08009#include "skeleton.dtsi"
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +080010#include <dt-bindings/pinctrl/at91.h>
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +080011#include <dt-bindings/interrupt-controller/irq.h>
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +080012#include <dt-bindings/gpio/gpio.h>
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080013
14/ {
15 model = "Atmel AT91SAM9263 family SoC";
16 compatible = "atmel,at91sam9263";
17 interrupt-parent = <&aic>;
18
19 aliases {
20 serial0 = &dbgu;
21 serial1 = &usart0;
22 serial2 = &usart1;
23 serial3 = &usart2;
24 gpio0 = &pioA;
25 gpio1 = &pioB;
26 gpio2 = &pioC;
27 gpio3 = &pioD;
28 gpio4 = &pioE;
29 tcb0 = &tcb0;
Ludovic Desroches05dcd362012-09-12 08:42:16 +020030 i2c0 = &i2c0;
Bo Shen099343c2012-11-07 11:41:41 +080031 ssc0 = &ssc0;
32 ssc1 = &ssc1;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080033 };
34 cpus {
35 cpu@0 {
36 compatible = "arm,arm926ejs";
37 };
38 };
39
40 memory {
41 reg = <0x20000000 0x08000000>;
42 };
43
44 ahb {
45 compatible = "simple-bus";
46 #address-cells = <1>;
47 #size-cells = <1>;
48 ranges;
49
50 apb {
51 compatible = "simple-bus";
52 #address-cells = <1>;
53 #size-cells = <1>;
54 ranges;
55
56 aic: interrupt-controller@fffff000 {
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020057 #interrupt-cells = <3>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080058 compatible = "atmel,at91rm9200-aic";
59 interrupt-controller;
60 reg = <0xfffff000 0x200>;
Jean-Christophe PLAGNIOL-VILLARDc6573942012-04-09 19:36:36 +080061 atmel,external-irqs = <30 31>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080062 };
63
64 pmc: pmc@fffffc00 {
65 compatible = "atmel,at91rm9200-pmc";
66 reg = <0xfffffc00 0x100>;
67 };
68
69 ramc: ramc@ffffe200 {
70 compatible = "atmel,at91sam9260-sdramc";
71 reg = <0xffffe200 0x200
72 0xffffe800 0x200>;
73 };
74
75 pit: timer@fffffd30 {
76 compatible = "atmel,at91sam9260-pit";
77 reg = <0xfffffd30 0xf>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +080078 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080079 };
80
81 tcb0: timer@fff7c000 {
82 compatible = "atmel,at91rm9200-tcb";
83 reg = <0xfff7c000 0x100>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +080084 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080085 };
86
87 rstc@fffffd00 {
88 compatible = "atmel,at91sam9260-rstc";
89 reg = <0xfffffd00 0x10>;
90 };
91
92 shdwc@fffffd10 {
93 compatible = "atmel,at91sam9260-shdwc";
94 reg = <0xfffffd10 0x10>;
95 };
96
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +080097 pinctrl@fffff200 {
98 #address-cells = <1>;
99 #size-cells = <1>;
100 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
101 ranges = <0xfffff200 0xfffff200 0xa00>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800102
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800103 atmel,mux-mask = <
104 /* A B */
105 0xfffffffb 0xffffe07f /* pioA */
106 0x0007ffff 0x39072fff /* pioB */
107 0xffffffff 0x3ffffff8 /* pioC */
108 0xfffffbff 0xffffffff /* pioD */
109 0xffe00fff 0xfbfcff00 /* pioE */
110 >;
111
112 /* shared pinctrl settings */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800113 dbgu {
114 pinctrl_dbgu: dbgu-0 {
115 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800116 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC30 periph A */
117 AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC31 periph with pullup */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800118 };
119 };
120
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800121 usart0 {
122 pinctrl_usart0: usart0-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800123 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800124 <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA26 periph A with pullup */
125 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800126 };
127
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800128 pinctrl_usart0_rts: usart0_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800129 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800130 <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA28 periph A */
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800131 };
132
133 pinctrl_usart0_cts: usart0_cts-0 {
134 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800135 <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA29 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800136 };
137 };
138
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800139 usart1 {
140 pinctrl_usart1: usart1-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800141 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800142 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A with pullup */
143 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD1 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800144 };
145
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800146 pinctrl_usart1_rts: usart1_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800147 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800148 <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD7 periph B */
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800149 };
150
151 pinctrl_usart1_cts: usart1_cts-0 {
152 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800153 <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD8 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800154 };
155 };
156
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800157 usart2 {
158 pinctrl_usart2: usart2-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800159 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800160 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A with pullup */
161 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD3 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800162 };
163
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800164 pinctrl_usart2_rts: usart2_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800165 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800166 <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD5 periph B */
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800167 };
168
169 pinctrl_usart2_cts: usart2_cts-0 {
170 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800171 <AT91_PIOD 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD6 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800172 };
173 };
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800174
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800175 nand {
176 pinctrl_nand: nand-0 {
177 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800178 <AT91_PIOA 22 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PA22 gpio RDY pin pull_up*/
179 AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD15 gpio enable pin pull_up */
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800180 };
181 };
182
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800183 macb {
184 pinctrl_macb_rmii: macb_rmii-0 {
185 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800186 <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */
187 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */
188 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */
189 AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */
190 AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */
191 AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */
192 AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */
193 AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */
194 AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */
195 AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800196 };
197
198 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
199 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800200 <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */
201 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */
202 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC22 periph B */
203 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC23 periph B */
204 AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC24 periph B */
205 AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */
206 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */
207 AT91_PIOE 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE22 periph B */
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800208 };
209 };
210
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800211 mmc0 {
212 pinctrl_mmc0_clk: mmc0_clk-0 {
213 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800214 <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA12 periph A */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800215 };
216
217 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
218 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800219 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
220 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA0 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800221 };
222
223 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
224 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800225 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */
226 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */
227 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800228 };
229
230 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
231 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800232 <AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
233 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA17 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800234 };
235
236 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
237 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800238 <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
239 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
240 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800241 };
242 };
243
244 mmc1 {
245 pinctrl_mmc1_clk: mmc1_clk-0 {
246 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800247 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800248 };
249
250 pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 {
251 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800252 <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
253 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA8 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800254 };
255
256 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
257 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800258 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */
259 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */
260 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800261 };
262
263 pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 {
264 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800265 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA21 periph A with pullup */
266 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA22 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800267 };
268
269 pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 {
270 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800271 <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA23 periph A with pullup */
272 AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */
273 AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA25 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800274 };
275 };
276
Bo Shen544ae6b2013-01-11 15:08:30 +0100277 ssc0 {
278 pinctrl_ssc0_tx: ssc0_tx-0 {
279 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800280 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB0 periph B */
281 AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB1 periph B */
282 AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */
Bo Shen544ae6b2013-01-11 15:08:30 +0100283 };
284
285 pinctrl_ssc0_rx: ssc0_rx-0 {
286 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800287 <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B */
288 AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B */
289 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B */
Bo Shen544ae6b2013-01-11 15:08:30 +0100290 };
291 };
292
293 ssc1 {
294 pinctrl_ssc1_tx: ssc1_tx-0 {
295 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800296 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
297 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
298 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
Bo Shen544ae6b2013-01-11 15:08:30 +0100299 };
300
301 pinctrl_ssc1_rx: ssc1_rx-0 {
302 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800303 <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
304 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */
305 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
Bo Shen544ae6b2013-01-11 15:08:30 +0100306 };
307 };
308
Wenyou Yanga68b7282013-04-03 14:03:52 +0800309 spi0 {
310 pinctrl_spi0: spi0-0 {
311 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800312 <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA0 periph B SPI0_MISO pin */
313 AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA1 periph B SPI0_MOSI pin */
314 AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA2 periph B SPI0_SPCK pin */
Wenyou Yanga68b7282013-04-03 14:03:52 +0800315 };
316 };
317
318 spi1 {
319 pinctrl_spi1: spi1-0 {
320 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800321 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A SPI1_MISO pin */
322 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A SPI1_MOSI pin */
323 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A SPI1_SPCK pin */
Wenyou Yanga68b7282013-04-03 14:03:52 +0800324 };
325 };
326
Boris BREZILLON028633c2013-05-24 10:05:56 +0000327 tcb0 {
328 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
329 atmel,pins = <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
330 };
331
332 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
333 atmel,pins = <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
334 };
335
336 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
337 atmel,pins = <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
338 };
339
340 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
341 atmel,pins = <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
342 };
343
344 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
345 atmel,pins = <AT91_PIOE 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
346 };
347
348 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
349 atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
350 };
351
352 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
353 atmel,pins = <AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
354 };
355
356 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
357 atmel,pins = <AT91_PIOE 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
358 };
359
360 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
361 atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
362 };
363 };
364
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800365 pioA: gpio@fffff200 {
366 compatible = "atmel,at91rm9200-gpio";
367 reg = <0xfffff200 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800368 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800369 #gpio-cells = <2>;
370 gpio-controller;
371 interrupt-controller;
372 #interrupt-cells = <2>;
373 };
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800374
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800375 pioB: gpio@fffff400 {
376 compatible = "atmel,at91rm9200-gpio";
377 reg = <0xfffff400 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800378 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800379 #gpio-cells = <2>;
380 gpio-controller;
381 interrupt-controller;
382 #interrupt-cells = <2>;
383 };
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800384
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800385 pioC: gpio@fffff600 {
386 compatible = "atmel,at91rm9200-gpio";
387 reg = <0xfffff600 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800388 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800389 #gpio-cells = <2>;
390 gpio-controller;
391 interrupt-controller;
392 #interrupt-cells = <2>;
393 };
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800394
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800395 pioD: gpio@fffff800 {
396 compatible = "atmel,at91rm9200-gpio";
397 reg = <0xfffff800 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800398 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800399 #gpio-cells = <2>;
400 gpio-controller;
401 interrupt-controller;
402 #interrupt-cells = <2>;
403 };
404
405 pioE: gpio@fffffa00 {
406 compatible = "atmel,at91rm9200-gpio";
407 reg = <0xfffffa00 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800408 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800409 #gpio-cells = <2>;
410 gpio-controller;
411 interrupt-controller;
412 #interrupt-cells = <2>;
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800413 };
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800414 };
415
416 dbgu: serial@ffffee00 {
417 compatible = "atmel,at91sam9260-usart";
418 reg = <0xffffee00 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800419 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800420 pinctrl-names = "default";
421 pinctrl-0 = <&pinctrl_dbgu>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800422 status = "disabled";
423 };
424
425 usart0: serial@fff8c000 {
426 compatible = "atmel,at91sam9260-usart";
427 reg = <0xfff8c000 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800428 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800429 atmel,use-dma-rx;
430 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800431 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800432 pinctrl-0 = <&pinctrl_usart0>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800433 status = "disabled";
434 };
435
436 usart1: serial@fff90000 {
437 compatible = "atmel,at91sam9260-usart";
438 reg = <0xfff90000 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800439 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800440 atmel,use-dma-rx;
441 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800442 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800443 pinctrl-0 = <&pinctrl_usart1>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800444 status = "disabled";
445 };
446
447 usart2: serial@fff94000 {
448 compatible = "atmel,at91sam9260-usart";
449 reg = <0xfff94000 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800450 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800451 atmel,use-dma-rx;
452 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800453 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800454 pinctrl-0 = <&pinctrl_usart2>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800455 status = "disabled";
456 };
457
Bo Shen099343c2012-11-07 11:41:41 +0800458 ssc0: ssc@fff98000 {
459 compatible = "atmel,at91rm9200-ssc";
460 reg = <0xfff98000 0x4000>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800461 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
Bo Shen544ae6b2013-01-11 15:08:30 +0100462 pinctrl-names = "default";
463 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
Bo Shen315656b2012-12-13 10:05:07 +0800464 status = "disabled";
Bo Shen099343c2012-11-07 11:41:41 +0800465 };
466
467 ssc1: ssc@fff9c000 {
468 compatible = "atmel,at91rm9200-ssc";
469 reg = <0xfff9c000 0x4000>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800470 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
Bo Shen544ae6b2013-01-11 15:08:30 +0100471 pinctrl-names = "default";
472 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
Bo Shen315656b2012-12-13 10:05:07 +0800473 status = "disabled";
Bo Shen099343c2012-11-07 11:41:41 +0800474 };
475
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800476 macb0: ethernet@fffbc000 {
477 compatible = "cdns,at32ap7000-macb", "cdns,macb";
478 reg = <0xfffbc000 0x100>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800479 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800480 pinctrl-names = "default";
481 pinctrl-0 = <&pinctrl_macb_rmii>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800482 status = "disabled";
483 };
484
485 usb1: gadget@fff78000 {
486 compatible = "atmel,at91rm9200-udc";
487 reg = <0xfff78000 0x4000>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800488 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800489 status = "disabled";
490 };
Ludovic Desroches05dcd362012-09-12 08:42:16 +0200491
492 i2c0: i2c@fff88000 {
493 compatible = "atmel,at91sam9263-i2c";
494 reg = <0xfff88000 0x100>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800495 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
Ludovic Desroches05dcd362012-09-12 08:42:16 +0200496 #address-cells = <1>;
497 #size-cells = <0>;
498 status = "disabled";
499 };
Ludovic Desroches98731372012-11-19 12:23:36 +0100500
501 mmc0: mmc@fff80000 {
502 compatible = "atmel,hsmci";
503 reg = <0xfff80000 0x600>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800504 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
Ludovic Desroches98731372012-11-19 12:23:36 +0100505 #address-cells = <1>;
506 #size-cells = <0>;
507 status = "disabled";
508 };
509
510 mmc1: mmc@fff84000 {
511 compatible = "atmel,hsmci";
512 reg = <0xfff84000 0x600>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800513 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
Ludovic Desroches98731372012-11-19 12:23:36 +0100514 #address-cells = <1>;
515 #size-cells = <0>;
516 status = "disabled";
517 };
Linus Torvaldsdb5b0ae2012-12-13 10:39:26 -0800518
Fabio Porcedda7492e7c2012-11-12 09:37:26 +0100519 watchdog@fffffd40 {
520 compatible = "atmel,at91sam9260-wdt";
521 reg = <0xfffffd40 0x10>;
522 status = "disabled";
523 };
Richard Genoudd50f88a2013-04-03 14:02:18 +0800524
525 spi0: spi@fffa4000 {
526 #address-cells = <1>;
527 #size-cells = <0>;
528 compatible = "atmel,at91rm9200-spi";
529 reg = <0xfffa4000 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800530 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
Wenyou Yanga68b7282013-04-03 14:03:52 +0800531 pinctrl-names = "default";
532 pinctrl-0 = <&pinctrl_spi0>;
Richard Genoudd50f88a2013-04-03 14:02:18 +0800533 status = "disabled";
534 };
535
536 spi1: spi@fffa8000 {
537 #address-cells = <1>;
538 #size-cells = <0>;
539 compatible = "atmel,at91rm9200-spi";
540 reg = <0xfffa8000 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800541 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>;
Wenyou Yanga68b7282013-04-03 14:03:52 +0800542 pinctrl-names = "default";
543 pinctrl-0 = <&pinctrl_spi1>;
Richard Genoudd50f88a2013-04-03 14:02:18 +0800544 status = "disabled";
545 };
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800546 };
547
548 nand0: nand@40000000 {
549 compatible = "atmel,at91rm9200-nand";
550 #address-cells = <1>;
551 #size-cells = <1>;
552 reg = <0x40000000 0x10000000
553 0xffffe000 0x200
554 >;
555 atmel,nand-addr-offset = <21>;
556 atmel,nand-cmd-offset = <22>;
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800557 pinctrl-names = "default";
558 pinctrl-0 = <&pinctrl_nand>;
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800559 gpios = <&pioA 22 GPIO_ACTIVE_HIGH
560 &pioD 15 GPIO_ACTIVE_HIGH
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800561 0
562 >;
563 status = "disabled";
564 };
565
566 usb0: ohci@00a00000 {
567 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
568 reg = <0x00a00000 0x100000>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800569 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800570 status = "disabled";
571 };
572 };
573
574 i2c@0 {
575 compatible = "i2c-gpio";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800576 gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
577 &pioB 5 GPIO_ACTIVE_HIGH /* scl */
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800578 >;
579 i2c-gpio,sda-open-drain;
580 i2c-gpio,scl-open-drain;
581 i2c-gpio,delay-us = <2>; /* ~100 kHz */
582 #address-cells = <1>;
583 #size-cells = <0>;
584 status = "disabled";
585 };
586};