Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Performance counter x86 architecture code |
| 3 | * |
Ingo Molnar | 9814451 | 2009-04-29 14:52:50 +0200 | [diff] [blame] | 4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
| 5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar |
| 6 | * Copyright (C) 2009 Jaswinder Singh Rajput |
| 7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter |
| 8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 9 | * |
| 10 | * For licencing details see kernel-base/COPYING |
| 11 | */ |
| 12 | |
| 13 | #include <linux/perf_counter.h> |
| 14 | #include <linux/capability.h> |
| 15 | #include <linux/notifier.h> |
| 16 | #include <linux/hardirq.h> |
| 17 | #include <linux/kprobes.h> |
Thomas Gleixner | 4ac1329 | 2008-12-09 21:43:39 +0100 | [diff] [blame] | 18 | #include <linux/module.h> |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 19 | #include <linux/kdebug.h> |
| 20 | #include <linux/sched.h> |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 21 | #include <linux/uaccess.h> |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 22 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 23 | #include <asm/apic.h> |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 24 | #include <asm/stacktrace.h> |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 25 | #include <asm/nmi.h> |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 26 | |
Ingo Molnar | 862a1a5 | 2008-12-17 13:09:20 +0100 | [diff] [blame] | 27 | static u64 perf_counter_mask __read_mostly; |
Ingo Molnar | 703e937 | 2008-12-17 10:51:15 +0100 | [diff] [blame] | 28 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 29 | struct cpu_hw_counters { |
Ingo Molnar | 862a1a5 | 2008-12-17 13:09:20 +0100 | [diff] [blame] | 30 | struct perf_counter *counters[X86_PMC_IDX_MAX]; |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 31 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
| 32 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
Mike Galbraith | 4b39fd9 | 2009-01-23 14:36:16 +0100 | [diff] [blame] | 33 | unsigned long interrupts; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 34 | int enabled; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 35 | }; |
| 36 | |
| 37 | /* |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 38 | * struct x86_pmu - generic x86 pmu |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 39 | */ |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 40 | struct x86_pmu { |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 41 | const char *name; |
| 42 | int version; |
Yong Wang | a328810 | 2009-06-03 13:12:55 +0800 | [diff] [blame] | 43 | int (*handle_irq)(struct pt_regs *); |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 44 | void (*disable_all)(void); |
| 45 | void (*enable_all)(void); |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 46 | void (*enable)(struct hw_perf_counter *, int); |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 47 | void (*disable)(struct hw_perf_counter *, int); |
Jaswinder Singh Rajput | 169e41e | 2009-02-28 18:37:49 +0530 | [diff] [blame] | 48 | unsigned eventsel; |
| 49 | unsigned perfctr; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 50 | u64 (*event_map)(int); |
| 51 | u64 (*raw_event)(u64); |
Jaswinder Singh Rajput | 169e41e | 2009-02-28 18:37:49 +0530 | [diff] [blame] | 52 | int max_events; |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 53 | int num_counters; |
| 54 | int num_counters_fixed; |
| 55 | int counter_bits; |
| 56 | u64 counter_mask; |
Robert Richter | c619b8f | 2009-04-29 12:47:23 +0200 | [diff] [blame] | 57 | u64 max_period; |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 58 | u64 intel_ctrl; |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 59 | }; |
| 60 | |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 61 | static struct x86_pmu x86_pmu __read_mostly; |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 62 | |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 63 | static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = { |
| 64 | .enabled = 1, |
| 65 | }; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 66 | |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 67 | /* |
| 68 | * Intel PerfMon v3. Used on Core2 and later. |
| 69 | */ |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 70 | static const u64 intel_perfmon_event_map[] = |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 71 | { |
Peter Zijlstra | f4dbfa8 | 2009-06-11 14:06:28 +0200 | [diff] [blame] | 72 | [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, |
| 73 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, |
| 74 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, |
| 75 | [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, |
| 76 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, |
| 77 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, |
| 78 | [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 79 | }; |
| 80 | |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 81 | static u64 intel_pmu_event_map(int event) |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 82 | { |
| 83 | return intel_perfmon_event_map[event]; |
| 84 | } |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 85 | |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 86 | /* |
| 87 | * Generalized hw caching related event table, filled |
| 88 | * in on a per model basis. A value of 0 means |
| 89 | * 'not supported', -1 means 'event makes no sense on |
| 90 | * this CPU', any other value means the raw event |
| 91 | * ID. |
| 92 | */ |
| 93 | |
| 94 | #define C(x) PERF_COUNT_HW_CACHE_##x |
| 95 | |
| 96 | static u64 __read_mostly hw_cache_event_ids |
| 97 | [PERF_COUNT_HW_CACHE_MAX] |
| 98 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 99 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; |
| 100 | |
| 101 | static const u64 nehalem_hw_cache_event_ids |
| 102 | [PERF_COUNT_HW_CACHE_MAX] |
| 103 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 104 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = |
| 105 | { |
| 106 | [ C(L1D) ] = { |
| 107 | [ C(OP_READ) ] = { |
| 108 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ |
| 109 | [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ |
| 110 | }, |
| 111 | [ C(OP_WRITE) ] = { |
| 112 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ |
| 113 | [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ |
| 114 | }, |
| 115 | [ C(OP_PREFETCH) ] = { |
| 116 | [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ |
| 117 | [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ |
| 118 | }, |
| 119 | }, |
| 120 | [ C(L1I ) ] = { |
| 121 | [ C(OP_READ) ] = { |
Yong Wang | fecc8ac | 2009-06-09 21:15:53 +0800 | [diff] [blame] | 122 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 123 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ |
| 124 | }, |
| 125 | [ C(OP_WRITE) ] = { |
| 126 | [ C(RESULT_ACCESS) ] = -1, |
| 127 | [ C(RESULT_MISS) ] = -1, |
| 128 | }, |
| 129 | [ C(OP_PREFETCH) ] = { |
| 130 | [ C(RESULT_ACCESS) ] = 0x0, |
| 131 | [ C(RESULT_MISS) ] = 0x0, |
| 132 | }, |
| 133 | }, |
Peter Zijlstra | 8be6e8f | 2009-06-11 14:19:11 +0200 | [diff] [blame] | 134 | [ C(LL ) ] = { |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 135 | [ C(OP_READ) ] = { |
| 136 | [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */ |
| 137 | [ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */ |
| 138 | }, |
| 139 | [ C(OP_WRITE) ] = { |
| 140 | [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */ |
| 141 | [ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */ |
| 142 | }, |
| 143 | [ C(OP_PREFETCH) ] = { |
Peter Zijlstra | 8be6e8f | 2009-06-11 14:19:11 +0200 | [diff] [blame] | 144 | [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */ |
| 145 | [ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */ |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 146 | }, |
| 147 | }, |
| 148 | [ C(DTLB) ] = { |
| 149 | [ C(OP_READ) ] = { |
| 150 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ |
| 151 | [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ |
| 152 | }, |
| 153 | [ C(OP_WRITE) ] = { |
| 154 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ |
| 155 | [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ |
| 156 | }, |
| 157 | [ C(OP_PREFETCH) ] = { |
| 158 | [ C(RESULT_ACCESS) ] = 0x0, |
| 159 | [ C(RESULT_MISS) ] = 0x0, |
| 160 | }, |
| 161 | }, |
| 162 | [ C(ITLB) ] = { |
| 163 | [ C(OP_READ) ] = { |
| 164 | [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ |
Yong Wang | fecc8ac | 2009-06-09 21:15:53 +0800 | [diff] [blame] | 165 | [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 166 | }, |
| 167 | [ C(OP_WRITE) ] = { |
| 168 | [ C(RESULT_ACCESS) ] = -1, |
| 169 | [ C(RESULT_MISS) ] = -1, |
| 170 | }, |
| 171 | [ C(OP_PREFETCH) ] = { |
| 172 | [ C(RESULT_ACCESS) ] = -1, |
| 173 | [ C(RESULT_MISS) ] = -1, |
| 174 | }, |
| 175 | }, |
| 176 | [ C(BPU ) ] = { |
| 177 | [ C(OP_READ) ] = { |
| 178 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ |
| 179 | [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ |
| 180 | }, |
| 181 | [ C(OP_WRITE) ] = { |
| 182 | [ C(RESULT_ACCESS) ] = -1, |
| 183 | [ C(RESULT_MISS) ] = -1, |
| 184 | }, |
| 185 | [ C(OP_PREFETCH) ] = { |
| 186 | [ C(RESULT_ACCESS) ] = -1, |
| 187 | [ C(RESULT_MISS) ] = -1, |
| 188 | }, |
| 189 | }, |
| 190 | }; |
| 191 | |
| 192 | static const u64 core2_hw_cache_event_ids |
| 193 | [PERF_COUNT_HW_CACHE_MAX] |
| 194 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 195 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = |
| 196 | { |
Thomas Gleixner | 0312af8 | 2009-06-08 07:42:04 +0200 | [diff] [blame] | 197 | [ C(L1D) ] = { |
| 198 | [ C(OP_READ) ] = { |
| 199 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ |
| 200 | [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ |
| 201 | }, |
| 202 | [ C(OP_WRITE) ] = { |
| 203 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ |
| 204 | [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ |
| 205 | }, |
| 206 | [ C(OP_PREFETCH) ] = { |
| 207 | [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ |
| 208 | [ C(RESULT_MISS) ] = 0, |
| 209 | }, |
| 210 | }, |
| 211 | [ C(L1I ) ] = { |
| 212 | [ C(OP_READ) ] = { |
| 213 | [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ |
| 214 | [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ |
| 215 | }, |
| 216 | [ C(OP_WRITE) ] = { |
| 217 | [ C(RESULT_ACCESS) ] = -1, |
| 218 | [ C(RESULT_MISS) ] = -1, |
| 219 | }, |
| 220 | [ C(OP_PREFETCH) ] = { |
| 221 | [ C(RESULT_ACCESS) ] = 0, |
| 222 | [ C(RESULT_MISS) ] = 0, |
| 223 | }, |
| 224 | }, |
Peter Zijlstra | 8be6e8f | 2009-06-11 14:19:11 +0200 | [diff] [blame] | 225 | [ C(LL ) ] = { |
Thomas Gleixner | 0312af8 | 2009-06-08 07:42:04 +0200 | [diff] [blame] | 226 | [ C(OP_READ) ] = { |
| 227 | [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ |
| 228 | [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ |
| 229 | }, |
| 230 | [ C(OP_WRITE) ] = { |
| 231 | [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ |
| 232 | [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ |
| 233 | }, |
| 234 | [ C(OP_PREFETCH) ] = { |
| 235 | [ C(RESULT_ACCESS) ] = 0, |
| 236 | [ C(RESULT_MISS) ] = 0, |
| 237 | }, |
| 238 | }, |
| 239 | [ C(DTLB) ] = { |
| 240 | [ C(OP_READ) ] = { |
| 241 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ |
| 242 | [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ |
| 243 | }, |
| 244 | [ C(OP_WRITE) ] = { |
| 245 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ |
| 246 | [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ |
| 247 | }, |
| 248 | [ C(OP_PREFETCH) ] = { |
| 249 | [ C(RESULT_ACCESS) ] = 0, |
| 250 | [ C(RESULT_MISS) ] = 0, |
| 251 | }, |
| 252 | }, |
| 253 | [ C(ITLB) ] = { |
| 254 | [ C(OP_READ) ] = { |
| 255 | [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ |
| 256 | [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ |
| 257 | }, |
| 258 | [ C(OP_WRITE) ] = { |
| 259 | [ C(RESULT_ACCESS) ] = -1, |
| 260 | [ C(RESULT_MISS) ] = -1, |
| 261 | }, |
| 262 | [ C(OP_PREFETCH) ] = { |
| 263 | [ C(RESULT_ACCESS) ] = -1, |
| 264 | [ C(RESULT_MISS) ] = -1, |
| 265 | }, |
| 266 | }, |
| 267 | [ C(BPU ) ] = { |
| 268 | [ C(OP_READ) ] = { |
| 269 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ |
| 270 | [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ |
| 271 | }, |
| 272 | [ C(OP_WRITE) ] = { |
| 273 | [ C(RESULT_ACCESS) ] = -1, |
| 274 | [ C(RESULT_MISS) ] = -1, |
| 275 | }, |
| 276 | [ C(OP_PREFETCH) ] = { |
| 277 | [ C(RESULT_ACCESS) ] = -1, |
| 278 | [ C(RESULT_MISS) ] = -1, |
| 279 | }, |
| 280 | }, |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 281 | }; |
| 282 | |
| 283 | static const u64 atom_hw_cache_event_ids |
| 284 | [PERF_COUNT_HW_CACHE_MAX] |
| 285 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 286 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = |
| 287 | { |
Thomas Gleixner | ad68922 | 2009-06-08 09:30:41 +0200 | [diff] [blame] | 288 | [ C(L1D) ] = { |
| 289 | [ C(OP_READ) ] = { |
| 290 | [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ |
| 291 | [ C(RESULT_MISS) ] = 0, |
| 292 | }, |
| 293 | [ C(OP_WRITE) ] = { |
Yong Wang | fecc8ac | 2009-06-09 21:15:53 +0800 | [diff] [blame] | 294 | [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ |
Thomas Gleixner | ad68922 | 2009-06-08 09:30:41 +0200 | [diff] [blame] | 295 | [ C(RESULT_MISS) ] = 0, |
| 296 | }, |
| 297 | [ C(OP_PREFETCH) ] = { |
| 298 | [ C(RESULT_ACCESS) ] = 0x0, |
| 299 | [ C(RESULT_MISS) ] = 0, |
| 300 | }, |
| 301 | }, |
| 302 | [ C(L1I ) ] = { |
| 303 | [ C(OP_READ) ] = { |
Yong Wang | fecc8ac | 2009-06-09 21:15:53 +0800 | [diff] [blame] | 304 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ |
| 305 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ |
Thomas Gleixner | ad68922 | 2009-06-08 09:30:41 +0200 | [diff] [blame] | 306 | }, |
| 307 | [ C(OP_WRITE) ] = { |
| 308 | [ C(RESULT_ACCESS) ] = -1, |
| 309 | [ C(RESULT_MISS) ] = -1, |
| 310 | }, |
| 311 | [ C(OP_PREFETCH) ] = { |
| 312 | [ C(RESULT_ACCESS) ] = 0, |
| 313 | [ C(RESULT_MISS) ] = 0, |
| 314 | }, |
| 315 | }, |
Peter Zijlstra | 8be6e8f | 2009-06-11 14:19:11 +0200 | [diff] [blame] | 316 | [ C(LL ) ] = { |
Thomas Gleixner | ad68922 | 2009-06-08 09:30:41 +0200 | [diff] [blame] | 317 | [ C(OP_READ) ] = { |
| 318 | [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ |
| 319 | [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ |
| 320 | }, |
| 321 | [ C(OP_WRITE) ] = { |
| 322 | [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ |
| 323 | [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ |
| 324 | }, |
| 325 | [ C(OP_PREFETCH) ] = { |
| 326 | [ C(RESULT_ACCESS) ] = 0, |
| 327 | [ C(RESULT_MISS) ] = 0, |
| 328 | }, |
| 329 | }, |
| 330 | [ C(DTLB) ] = { |
| 331 | [ C(OP_READ) ] = { |
Yong Wang | fecc8ac | 2009-06-09 21:15:53 +0800 | [diff] [blame] | 332 | [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ |
Thomas Gleixner | ad68922 | 2009-06-08 09:30:41 +0200 | [diff] [blame] | 333 | [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ |
| 334 | }, |
| 335 | [ C(OP_WRITE) ] = { |
Yong Wang | fecc8ac | 2009-06-09 21:15:53 +0800 | [diff] [blame] | 336 | [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ |
Thomas Gleixner | ad68922 | 2009-06-08 09:30:41 +0200 | [diff] [blame] | 337 | [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ |
| 338 | }, |
| 339 | [ C(OP_PREFETCH) ] = { |
| 340 | [ C(RESULT_ACCESS) ] = 0, |
| 341 | [ C(RESULT_MISS) ] = 0, |
| 342 | }, |
| 343 | }, |
| 344 | [ C(ITLB) ] = { |
| 345 | [ C(OP_READ) ] = { |
| 346 | [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ |
| 347 | [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ |
| 348 | }, |
| 349 | [ C(OP_WRITE) ] = { |
| 350 | [ C(RESULT_ACCESS) ] = -1, |
| 351 | [ C(RESULT_MISS) ] = -1, |
| 352 | }, |
| 353 | [ C(OP_PREFETCH) ] = { |
| 354 | [ C(RESULT_ACCESS) ] = -1, |
| 355 | [ C(RESULT_MISS) ] = -1, |
| 356 | }, |
| 357 | }, |
| 358 | [ C(BPU ) ] = { |
| 359 | [ C(OP_READ) ] = { |
| 360 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ |
| 361 | [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ |
| 362 | }, |
| 363 | [ C(OP_WRITE) ] = { |
| 364 | [ C(RESULT_ACCESS) ] = -1, |
| 365 | [ C(RESULT_MISS) ] = -1, |
| 366 | }, |
| 367 | [ C(OP_PREFETCH) ] = { |
| 368 | [ C(RESULT_ACCESS) ] = -1, |
| 369 | [ C(RESULT_MISS) ] = -1, |
| 370 | }, |
| 371 | }, |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 372 | }; |
| 373 | |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 374 | static u64 intel_pmu_raw_event(u64 event) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 375 | { |
Peter Zijlstra | 82bae4f8 | 2009-03-13 12:21:31 +0100 | [diff] [blame] | 376 | #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL |
| 377 | #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL |
Peter Zijlstra | ff99be5 | 2009-05-25 17:39:03 +0200 | [diff] [blame] | 378 | #define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL |
| 379 | #define CORE_EVNTSEL_INV_MASK 0x00800000ULL |
Peter Zijlstra | 82bae4f8 | 2009-03-13 12:21:31 +0100 | [diff] [blame] | 380 | #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 381 | |
Ingo Molnar | 128f048 | 2009-06-03 22:19:36 +0200 | [diff] [blame] | 382 | #define CORE_EVNTSEL_MASK \ |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 383 | (CORE_EVNTSEL_EVENT_MASK | \ |
| 384 | CORE_EVNTSEL_UNIT_MASK | \ |
Peter Zijlstra | ff99be5 | 2009-05-25 17:39:03 +0200 | [diff] [blame] | 385 | CORE_EVNTSEL_EDGE_MASK | \ |
| 386 | CORE_EVNTSEL_INV_MASK | \ |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 387 | CORE_EVNTSEL_COUNTER_MASK) |
| 388 | |
| 389 | return event & CORE_EVNTSEL_MASK; |
| 390 | } |
| 391 | |
Jaswinder Singh Rajput | f4db43a | 2009-06-13 01:06:21 +0530 | [diff] [blame] | 392 | static const u64 amd_hw_cache_event_ids |
Thomas Gleixner | f86748e | 2009-06-08 22:33:10 +0200 | [diff] [blame] | 393 | [PERF_COUNT_HW_CACHE_MAX] |
| 394 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 395 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = |
| 396 | { |
| 397 | [ C(L1D) ] = { |
| 398 | [ C(OP_READ) ] = { |
Jaswinder Singh Rajput | f4db43a | 2009-06-13 01:06:21 +0530 | [diff] [blame] | 399 | [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ |
| 400 | [ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */ |
Thomas Gleixner | f86748e | 2009-06-08 22:33:10 +0200 | [diff] [blame] | 401 | }, |
| 402 | [ C(OP_WRITE) ] = { |
Jaswinder Singh Rajput | f4db43a | 2009-06-13 01:06:21 +0530 | [diff] [blame] | 403 | [ C(RESULT_ACCESS) ] = 0x0042, /* Data Cache Refills from L2 */ |
Thomas Gleixner | f86748e | 2009-06-08 22:33:10 +0200 | [diff] [blame] | 404 | [ C(RESULT_MISS) ] = 0, |
| 405 | }, |
| 406 | [ C(OP_PREFETCH) ] = { |
Jaswinder Singh Rajput | f4db43a | 2009-06-13 01:06:21 +0530 | [diff] [blame] | 407 | [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */ |
| 408 | [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */ |
Thomas Gleixner | f86748e | 2009-06-08 22:33:10 +0200 | [diff] [blame] | 409 | }, |
| 410 | }, |
| 411 | [ C(L1I ) ] = { |
| 412 | [ C(OP_READ) ] = { |
| 413 | [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches */ |
| 414 | [ C(RESULT_MISS) ] = 0x0081, /* Instruction cache misses */ |
| 415 | }, |
| 416 | [ C(OP_WRITE) ] = { |
| 417 | [ C(RESULT_ACCESS) ] = -1, |
| 418 | [ C(RESULT_MISS) ] = -1, |
| 419 | }, |
| 420 | [ C(OP_PREFETCH) ] = { |
Jaswinder Singh Rajput | f4db43a | 2009-06-13 01:06:21 +0530 | [diff] [blame] | 421 | [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */ |
Thomas Gleixner | f86748e | 2009-06-08 22:33:10 +0200 | [diff] [blame] | 422 | [ C(RESULT_MISS) ] = 0, |
| 423 | }, |
| 424 | }, |
Peter Zijlstra | 8be6e8f | 2009-06-11 14:19:11 +0200 | [diff] [blame] | 425 | [ C(LL ) ] = { |
Thomas Gleixner | f86748e | 2009-06-08 22:33:10 +0200 | [diff] [blame] | 426 | [ C(OP_READ) ] = { |
Jaswinder Singh Rajput | f4db43a | 2009-06-13 01:06:21 +0530 | [diff] [blame] | 427 | [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */ |
| 428 | [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */ |
Thomas Gleixner | f86748e | 2009-06-08 22:33:10 +0200 | [diff] [blame] | 429 | }, |
| 430 | [ C(OP_WRITE) ] = { |
Jaswinder Singh Rajput | f4db43a | 2009-06-13 01:06:21 +0530 | [diff] [blame] | 431 | [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */ |
Thomas Gleixner | f86748e | 2009-06-08 22:33:10 +0200 | [diff] [blame] | 432 | [ C(RESULT_MISS) ] = 0, |
| 433 | }, |
| 434 | [ C(OP_PREFETCH) ] = { |
| 435 | [ C(RESULT_ACCESS) ] = 0, |
| 436 | [ C(RESULT_MISS) ] = 0, |
| 437 | }, |
| 438 | }, |
| 439 | [ C(DTLB) ] = { |
| 440 | [ C(OP_READ) ] = { |
Jaswinder Singh Rajput | f4db43a | 2009-06-13 01:06:21 +0530 | [diff] [blame] | 441 | [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ |
| 442 | [ C(RESULT_MISS) ] = 0x0046, /* L1 DTLB and L2 DLTB Miss */ |
Thomas Gleixner | f86748e | 2009-06-08 22:33:10 +0200 | [diff] [blame] | 443 | }, |
| 444 | [ C(OP_WRITE) ] = { |
| 445 | [ C(RESULT_ACCESS) ] = 0, |
| 446 | [ C(RESULT_MISS) ] = 0, |
| 447 | }, |
| 448 | [ C(OP_PREFETCH) ] = { |
| 449 | [ C(RESULT_ACCESS) ] = 0, |
| 450 | [ C(RESULT_MISS) ] = 0, |
| 451 | }, |
| 452 | }, |
| 453 | [ C(ITLB) ] = { |
| 454 | [ C(OP_READ) ] = { |
| 455 | [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */ |
| 456 | [ C(RESULT_MISS) ] = 0x0085, /* Instr. fetch ITLB misses */ |
| 457 | }, |
| 458 | [ C(OP_WRITE) ] = { |
| 459 | [ C(RESULT_ACCESS) ] = -1, |
| 460 | [ C(RESULT_MISS) ] = -1, |
| 461 | }, |
| 462 | [ C(OP_PREFETCH) ] = { |
| 463 | [ C(RESULT_ACCESS) ] = -1, |
| 464 | [ C(RESULT_MISS) ] = -1, |
| 465 | }, |
| 466 | }, |
| 467 | [ C(BPU ) ] = { |
| 468 | [ C(OP_READ) ] = { |
| 469 | [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr. */ |
| 470 | [ C(RESULT_MISS) ] = 0x00c3, /* Retired Mispredicted BI */ |
| 471 | }, |
| 472 | [ C(OP_WRITE) ] = { |
| 473 | [ C(RESULT_ACCESS) ] = -1, |
| 474 | [ C(RESULT_MISS) ] = -1, |
| 475 | }, |
| 476 | [ C(OP_PREFETCH) ] = { |
| 477 | [ C(RESULT_ACCESS) ] = -1, |
| 478 | [ C(RESULT_MISS) ] = -1, |
| 479 | }, |
| 480 | }, |
| 481 | }; |
| 482 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 483 | /* |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 484 | * AMD Performance Monitor K7 and later. |
| 485 | */ |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 486 | static const u64 amd_perfmon_event_map[] = |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 487 | { |
Peter Zijlstra | f4dbfa8 | 2009-06-11 14:06:28 +0200 | [diff] [blame] | 488 | [PERF_COUNT_HW_CPU_CYCLES] = 0x0076, |
| 489 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, |
| 490 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0080, |
| 491 | [PERF_COUNT_HW_CACHE_MISSES] = 0x0081, |
| 492 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, |
| 493 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 494 | }; |
| 495 | |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 496 | static u64 amd_pmu_event_map(int event) |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 497 | { |
| 498 | return amd_perfmon_event_map[event]; |
| 499 | } |
| 500 | |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 501 | static u64 amd_pmu_raw_event(u64 event) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 502 | { |
Peter Zijlstra | 82bae4f8 | 2009-03-13 12:21:31 +0100 | [diff] [blame] | 503 | #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL |
| 504 | #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL |
Peter Zijlstra | ff99be5 | 2009-05-25 17:39:03 +0200 | [diff] [blame] | 505 | #define K7_EVNTSEL_EDGE_MASK 0x000040000ULL |
| 506 | #define K7_EVNTSEL_INV_MASK 0x000800000ULL |
Peter Zijlstra | 82bae4f8 | 2009-03-13 12:21:31 +0100 | [diff] [blame] | 507 | #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 508 | |
| 509 | #define K7_EVNTSEL_MASK \ |
| 510 | (K7_EVNTSEL_EVENT_MASK | \ |
| 511 | K7_EVNTSEL_UNIT_MASK | \ |
Peter Zijlstra | ff99be5 | 2009-05-25 17:39:03 +0200 | [diff] [blame] | 512 | K7_EVNTSEL_EDGE_MASK | \ |
| 513 | K7_EVNTSEL_INV_MASK | \ |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 514 | K7_EVNTSEL_COUNTER_MASK) |
| 515 | |
| 516 | return event & K7_EVNTSEL_MASK; |
| 517 | } |
| 518 | |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 519 | /* |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 520 | * Propagate counter elapsed time into the generic counter. |
| 521 | * Can only be executed on the CPU where the counter is active. |
| 522 | * Returns the delta events processed. |
| 523 | */ |
Robert Richter | 4b7bfd0 | 2009-04-29 12:47:22 +0200 | [diff] [blame] | 524 | static u64 |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 525 | x86_perf_counter_update(struct perf_counter *counter, |
| 526 | struct hw_perf_counter *hwc, int idx) |
| 527 | { |
Peter Zijlstra | ec3232b | 2009-05-13 09:45:19 +0200 | [diff] [blame] | 528 | int shift = 64 - x86_pmu.counter_bits; |
| 529 | u64 prev_raw_count, new_raw_count; |
| 530 | s64 delta; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 531 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 532 | /* |
| 533 | * Careful: an NMI might modify the previous counter value. |
| 534 | * |
| 535 | * Our tactic to handle this is to first atomically read and |
| 536 | * exchange a new raw count - then add that new-prev delta |
| 537 | * count to the generic counter atomically: |
| 538 | */ |
| 539 | again: |
| 540 | prev_raw_count = atomic64_read(&hwc->prev_count); |
| 541 | rdmsrl(hwc->counter_base + idx, new_raw_count); |
| 542 | |
| 543 | if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, |
| 544 | new_raw_count) != prev_raw_count) |
| 545 | goto again; |
| 546 | |
| 547 | /* |
| 548 | * Now we have the new raw value and have updated the prev |
| 549 | * timestamp already. We can now calculate the elapsed delta |
| 550 | * (counter-)time and add that to the generic counter. |
| 551 | * |
| 552 | * Careful, not all hw sign-extends above the physical width |
Peter Zijlstra | ec3232b | 2009-05-13 09:45:19 +0200 | [diff] [blame] | 553 | * of the count. |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 554 | */ |
Peter Zijlstra | ec3232b | 2009-05-13 09:45:19 +0200 | [diff] [blame] | 555 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
| 556 | delta >>= shift; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 557 | |
| 558 | atomic64_add(delta, &counter->count); |
| 559 | atomic64_sub(delta, &hwc->period_left); |
Robert Richter | 4b7bfd0 | 2009-04-29 12:47:22 +0200 | [diff] [blame] | 560 | |
| 561 | return new_raw_count; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 562 | } |
| 563 | |
Peter Zijlstra | ba77813 | 2009-05-04 18:47:44 +0200 | [diff] [blame] | 564 | static atomic_t active_counters; |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 565 | static DEFINE_MUTEX(pmc_reserve_mutex); |
| 566 | |
| 567 | static bool reserve_pmc_hardware(void) |
| 568 | { |
| 569 | int i; |
| 570 | |
| 571 | if (nmi_watchdog == NMI_LOCAL_APIC) |
| 572 | disable_lapic_nmi_watchdog(); |
| 573 | |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 574 | for (i = 0; i < x86_pmu.num_counters; i++) { |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 575 | if (!reserve_perfctr_nmi(x86_pmu.perfctr + i)) |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 576 | goto perfctr_fail; |
| 577 | } |
| 578 | |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 579 | for (i = 0; i < x86_pmu.num_counters; i++) { |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 580 | if (!reserve_evntsel_nmi(x86_pmu.eventsel + i)) |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 581 | goto eventsel_fail; |
| 582 | } |
| 583 | |
| 584 | return true; |
| 585 | |
| 586 | eventsel_fail: |
| 587 | for (i--; i >= 0; i--) |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 588 | release_evntsel_nmi(x86_pmu.eventsel + i); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 589 | |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 590 | i = x86_pmu.num_counters; |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 591 | |
| 592 | perfctr_fail: |
| 593 | for (i--; i >= 0; i--) |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 594 | release_perfctr_nmi(x86_pmu.perfctr + i); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 595 | |
| 596 | if (nmi_watchdog == NMI_LOCAL_APIC) |
| 597 | enable_lapic_nmi_watchdog(); |
| 598 | |
| 599 | return false; |
| 600 | } |
| 601 | |
| 602 | static void release_pmc_hardware(void) |
| 603 | { |
| 604 | int i; |
| 605 | |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 606 | for (i = 0; i < x86_pmu.num_counters; i++) { |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 607 | release_perfctr_nmi(x86_pmu.perfctr + i); |
| 608 | release_evntsel_nmi(x86_pmu.eventsel + i); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 609 | } |
| 610 | |
| 611 | if (nmi_watchdog == NMI_LOCAL_APIC) |
| 612 | enable_lapic_nmi_watchdog(); |
| 613 | } |
| 614 | |
| 615 | static void hw_perf_counter_destroy(struct perf_counter *counter) |
| 616 | { |
Peter Zijlstra | ba77813 | 2009-05-04 18:47:44 +0200 | [diff] [blame] | 617 | if (atomic_dec_and_mutex_lock(&active_counters, &pmc_reserve_mutex)) { |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 618 | release_pmc_hardware(); |
| 619 | mutex_unlock(&pmc_reserve_mutex); |
| 620 | } |
| 621 | } |
| 622 | |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 623 | static inline int x86_pmu_initialized(void) |
| 624 | { |
| 625 | return x86_pmu.handle_irq != NULL; |
| 626 | } |
| 627 | |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 628 | static inline int |
| 629 | set_ext_hw_attr(struct hw_perf_counter *hwc, struct perf_counter_attr *attr) |
| 630 | { |
| 631 | unsigned int cache_type, cache_op, cache_result; |
| 632 | u64 config, val; |
| 633 | |
| 634 | config = attr->config; |
| 635 | |
| 636 | cache_type = (config >> 0) & 0xff; |
| 637 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) |
| 638 | return -EINVAL; |
| 639 | |
| 640 | cache_op = (config >> 8) & 0xff; |
| 641 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) |
| 642 | return -EINVAL; |
| 643 | |
| 644 | cache_result = (config >> 16) & 0xff; |
| 645 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) |
| 646 | return -EINVAL; |
| 647 | |
| 648 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; |
| 649 | |
| 650 | if (val == 0) |
| 651 | return -ENOENT; |
| 652 | |
| 653 | if (val == -1) |
| 654 | return -EINVAL; |
| 655 | |
| 656 | hwc->config |= val; |
| 657 | |
| 658 | return 0; |
| 659 | } |
| 660 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 661 | /* |
Peter Zijlstra | 0d48696 | 2009-06-02 19:22:16 +0200 | [diff] [blame] | 662 | * Setup the hardware configuration for a given attr_type |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 663 | */ |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 664 | static int __hw_perf_counter_init(struct perf_counter *counter) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 665 | { |
Peter Zijlstra | 0d48696 | 2009-06-02 19:22:16 +0200 | [diff] [blame] | 666 | struct perf_counter_attr *attr = &counter->attr; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 667 | struct hw_perf_counter *hwc = &counter->hw; |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 668 | int err; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 669 | |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 670 | if (!x86_pmu_initialized()) |
| 671 | return -ENODEV; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 672 | |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 673 | err = 0; |
Peter Zijlstra | ba77813 | 2009-05-04 18:47:44 +0200 | [diff] [blame] | 674 | if (!atomic_inc_not_zero(&active_counters)) { |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 675 | mutex_lock(&pmc_reserve_mutex); |
Peter Zijlstra | ba77813 | 2009-05-04 18:47:44 +0200 | [diff] [blame] | 676 | if (atomic_read(&active_counters) == 0 && !reserve_pmc_hardware()) |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 677 | err = -EBUSY; |
| 678 | else |
Peter Zijlstra | ba77813 | 2009-05-04 18:47:44 +0200 | [diff] [blame] | 679 | atomic_inc(&active_counters); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 680 | mutex_unlock(&pmc_reserve_mutex); |
| 681 | } |
| 682 | if (err) |
| 683 | return err; |
| 684 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 685 | /* |
Paul Mackerras | 0475f9e | 2009-02-11 14:35:35 +1100 | [diff] [blame] | 686 | * Generate PMC IRQs: |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 687 | * (keep 'enabled' bit clear for now) |
| 688 | */ |
Paul Mackerras | 0475f9e | 2009-02-11 14:35:35 +1100 | [diff] [blame] | 689 | hwc->config = ARCH_PERFMON_EVENTSEL_INT; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 690 | |
| 691 | /* |
Paul Mackerras | 0475f9e | 2009-02-11 14:35:35 +1100 | [diff] [blame] | 692 | * Count user and OS events unless requested not to. |
| 693 | */ |
Peter Zijlstra | 0d48696 | 2009-06-02 19:22:16 +0200 | [diff] [blame] | 694 | if (!attr->exclude_user) |
Paul Mackerras | 0475f9e | 2009-02-11 14:35:35 +1100 | [diff] [blame] | 695 | hwc->config |= ARCH_PERFMON_EVENTSEL_USR; |
Peter Zijlstra | 0d48696 | 2009-06-02 19:22:16 +0200 | [diff] [blame] | 696 | if (!attr->exclude_kernel) |
Paul Mackerras | 0475f9e | 2009-02-11 14:35:35 +1100 | [diff] [blame] | 697 | hwc->config |= ARCH_PERFMON_EVENTSEL_OS; |
| 698 | |
Peter Zijlstra | bd2b5b1 | 2009-06-10 13:40:57 +0200 | [diff] [blame] | 699 | if (!hwc->sample_period) { |
Peter Zijlstra | b23f332 | 2009-06-02 15:13:03 +0200 | [diff] [blame] | 700 | hwc->sample_period = x86_pmu.max_period; |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 701 | hwc->last_period = hwc->sample_period; |
Peter Zijlstra | bd2b5b1 | 2009-06-10 13:40:57 +0200 | [diff] [blame] | 702 | atomic64_set(&hwc->period_left, hwc->sample_period); |
| 703 | } |
Ingo Molnar | d2517a4 | 2009-05-17 10:04:45 +0200 | [diff] [blame] | 704 | |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 705 | counter->destroy = hw_perf_counter_destroy; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 706 | |
| 707 | /* |
Thomas Gleixner | dfa7c89 | 2008-12-08 19:35:37 +0100 | [diff] [blame] | 708 | * Raw event type provide the config in the event structure |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 709 | */ |
Ingo Molnar | a21ca2c | 2009-06-06 09:58:57 +0200 | [diff] [blame] | 710 | if (attr->type == PERF_TYPE_RAW) { |
| 711 | hwc->config |= x86_pmu.raw_event(attr->config); |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 712 | return 0; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 713 | } |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 714 | |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 715 | if (attr->type == PERF_TYPE_HW_CACHE) |
| 716 | return set_ext_hw_attr(hwc, attr); |
| 717 | |
| 718 | if (attr->config >= x86_pmu.max_events) |
| 719 | return -EINVAL; |
| 720 | /* |
| 721 | * The generic map: |
| 722 | */ |
| 723 | hwc->config |= x86_pmu.event_map(attr->config); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 724 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 725 | return 0; |
| 726 | } |
| 727 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 728 | static void intel_pmu_disable_all(void) |
Thomas Gleixner | 4ac1329 | 2008-12-09 21:43:39 +0100 | [diff] [blame] | 729 | { |
Ingo Molnar | 862a1a5 | 2008-12-17 13:09:20 +0100 | [diff] [blame] | 730 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); |
Thomas Gleixner | 4ac1329 | 2008-12-09 21:43:39 +0100 | [diff] [blame] | 731 | } |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 732 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 733 | static void amd_pmu_disable_all(void) |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 734 | { |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 735 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 736 | int idx; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 737 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 738 | if (!cpuc->enabled) |
| 739 | return; |
| 740 | |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 741 | cpuc->enabled = 0; |
Peter Zijlstra | 60b3df9 | 2009-03-13 12:21:30 +0100 | [diff] [blame] | 742 | /* |
| 743 | * ensure we write the disable before we start disabling the |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 744 | * counters proper, so that amd_pmu_enable_counter() does the |
| 745 | * right thing. |
Peter Zijlstra | 60b3df9 | 2009-03-13 12:21:30 +0100 | [diff] [blame] | 746 | */ |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 747 | barrier(); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 748 | |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 749 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 750 | u64 val; |
| 751 | |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 752 | if (!test_bit(idx, cpuc->active_mask)) |
Robert Richter | 4295ee6 | 2009-04-29 12:47:01 +0200 | [diff] [blame] | 753 | continue; |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 754 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); |
Robert Richter | 4295ee6 | 2009-04-29 12:47:01 +0200 | [diff] [blame] | 755 | if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE)) |
| 756 | continue; |
| 757 | val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE; |
| 758 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 759 | } |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 760 | } |
| 761 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 762 | void hw_perf_disable(void) |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 763 | { |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 764 | if (!x86_pmu_initialized()) |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 765 | return; |
| 766 | return x86_pmu.disable_all(); |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 767 | } |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 768 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 769 | static void intel_pmu_enable_all(void) |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 770 | { |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 771 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 772 | } |
| 773 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 774 | static void amd_pmu_enable_all(void) |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 775 | { |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 776 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 777 | int idx; |
| 778 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 779 | if (cpuc->enabled) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 780 | return; |
| 781 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 782 | cpuc->enabled = 1; |
| 783 | barrier(); |
| 784 | |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 785 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
Robert Richter | 4295ee6 | 2009-04-29 12:47:01 +0200 | [diff] [blame] | 786 | u64 val; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 787 | |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 788 | if (!test_bit(idx, cpuc->active_mask)) |
Robert Richter | 4295ee6 | 2009-04-29 12:47:01 +0200 | [diff] [blame] | 789 | continue; |
| 790 | rdmsrl(MSR_K7_EVNTSEL0 + idx, val); |
| 791 | if (val & ARCH_PERFMON_EVENTSEL0_ENABLE) |
| 792 | continue; |
| 793 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; |
| 794 | wrmsrl(MSR_K7_EVNTSEL0 + idx, val); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 795 | } |
| 796 | } |
| 797 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 798 | void hw_perf_enable(void) |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 799 | { |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 800 | if (!x86_pmu_initialized()) |
Ingo Molnar | 2b9ff0d | 2008-12-14 18:36:30 +0100 | [diff] [blame] | 801 | return; |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 802 | x86_pmu.enable_all(); |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 803 | } |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 804 | |
Robert Richter | 19d84da | 2009-04-29 12:47:25 +0200 | [diff] [blame] | 805 | static inline u64 intel_pmu_get_status(void) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 806 | { |
| 807 | u64 status; |
| 808 | |
| 809 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); |
| 810 | |
| 811 | return status; |
| 812 | } |
| 813 | |
Robert Richter | dee5d90 | 2009-04-29 12:47:07 +0200 | [diff] [blame] | 814 | static inline void intel_pmu_ack_status(u64 ack) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 815 | { |
| 816 | wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); |
| 817 | } |
| 818 | |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 819 | static inline void x86_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 820 | { |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 821 | int err; |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 822 | err = checking_wrmsrl(hwc->config_base + idx, |
| 823 | hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE); |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 824 | } |
| 825 | |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 826 | static inline void x86_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 827 | { |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 828 | int err; |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 829 | err = checking_wrmsrl(hwc->config_base + idx, |
| 830 | hwc->config); |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 831 | } |
| 832 | |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 833 | static inline void |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 834 | intel_pmu_disable_fixed(struct hw_perf_counter *hwc, int __idx) |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 835 | { |
| 836 | int idx = __idx - X86_PMC_IDX_FIXED; |
| 837 | u64 ctrl_val, mask; |
| 838 | int err; |
| 839 | |
| 840 | mask = 0xfULL << (idx * 4); |
| 841 | |
| 842 | rdmsrl(hwc->config_base, ctrl_val); |
| 843 | ctrl_val &= ~mask; |
| 844 | err = checking_wrmsrl(hwc->config_base, ctrl_val); |
| 845 | } |
| 846 | |
| 847 | static inline void |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 848 | intel_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 849 | { |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 850 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
| 851 | intel_pmu_disable_fixed(hwc, idx); |
| 852 | return; |
| 853 | } |
| 854 | |
| 855 | x86_pmu_disable_counter(hwc, idx); |
| 856 | } |
| 857 | |
| 858 | static inline void |
| 859 | amd_pmu_disable_counter(struct hw_perf_counter *hwc, int idx) |
| 860 | { |
| 861 | x86_pmu_disable_counter(hwc, idx); |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 862 | } |
| 863 | |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 864 | static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 865 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 866 | /* |
| 867 | * Set the next IRQ period, based on the hwc->period_left value. |
| 868 | * To be called with the counter disabled in hw: |
| 869 | */ |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 870 | static int |
Robert Richter | 26816c2 | 2009-04-29 12:47:08 +0200 | [diff] [blame] | 871 | x86_perf_counter_set_period(struct perf_counter *counter, |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 872 | struct hw_perf_counter *hwc, int idx) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 873 | { |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 874 | s64 left = atomic64_read(&hwc->period_left); |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 875 | s64 period = hwc->sample_period; |
| 876 | int err, ret = 0; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 877 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 878 | /* |
| 879 | * If we are way outside a reasoable range then just skip forward: |
| 880 | */ |
| 881 | if (unlikely(left <= -period)) { |
| 882 | left = period; |
| 883 | atomic64_set(&hwc->period_left, left); |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 884 | hwc->last_period = period; |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 885 | ret = 1; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 886 | } |
| 887 | |
| 888 | if (unlikely(left <= 0)) { |
| 889 | left += period; |
| 890 | atomic64_set(&hwc->period_left, left); |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 891 | hwc->last_period = period; |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 892 | ret = 1; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 893 | } |
Ingo Molnar | 1c80f4b | 2009-05-15 08:25:22 +0200 | [diff] [blame] | 894 | /* |
| 895 | * Quirk: certain CPUs dont like it if just 1 event is left: |
| 896 | */ |
| 897 | if (unlikely(left < 2)) |
| 898 | left = 2; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 899 | |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 900 | if (left > x86_pmu.max_period) |
| 901 | left = x86_pmu.max_period; |
| 902 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 903 | per_cpu(prev_left[idx], smp_processor_id()) = left; |
| 904 | |
| 905 | /* |
| 906 | * The hw counter starts counting from this counter offset, |
| 907 | * mark it to be able to extra future deltas: |
| 908 | */ |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 909 | atomic64_set(&hwc->prev_count, (u64)-left); |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 910 | |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 911 | err = checking_wrmsrl(hwc->counter_base + idx, |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 912 | (u64)(-left) & x86_pmu.counter_mask); |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 913 | |
| 914 | return ret; |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 915 | } |
| 916 | |
| 917 | static inline void |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 918 | intel_pmu_enable_fixed(struct hw_perf_counter *hwc, int __idx) |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 919 | { |
| 920 | int idx = __idx - X86_PMC_IDX_FIXED; |
| 921 | u64 ctrl_val, bits, mask; |
| 922 | int err; |
| 923 | |
| 924 | /* |
Paul Mackerras | 0475f9e | 2009-02-11 14:35:35 +1100 | [diff] [blame] | 925 | * Enable IRQ generation (0x8), |
| 926 | * and enable ring-3 counting (0x2) and ring-0 counting (0x1) |
| 927 | * if requested: |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 928 | */ |
Paul Mackerras | 0475f9e | 2009-02-11 14:35:35 +1100 | [diff] [blame] | 929 | bits = 0x8ULL; |
| 930 | if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) |
| 931 | bits |= 0x2; |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 932 | if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) |
| 933 | bits |= 0x1; |
| 934 | bits <<= (idx * 4); |
| 935 | mask = 0xfULL << (idx * 4); |
| 936 | |
| 937 | rdmsrl(hwc->config_base, ctrl_val); |
| 938 | ctrl_val &= ~mask; |
| 939 | ctrl_val |= bits; |
| 940 | err = checking_wrmsrl(hwc->config_base, ctrl_val); |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 941 | } |
| 942 | |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 943 | static void intel_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 944 | { |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 945 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
| 946 | intel_pmu_enable_fixed(hwc, idx); |
| 947 | return; |
| 948 | } |
| 949 | |
| 950 | x86_pmu_enable_counter(hwc, idx); |
| 951 | } |
| 952 | |
| 953 | static void amd_pmu_enable_counter(struct hw_perf_counter *hwc, int idx) |
| 954 | { |
| 955 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
| 956 | |
| 957 | if (cpuc->enabled) |
| 958 | x86_pmu_enable_counter(hwc, idx); |
Jaswinder Singh Rajput | 2b583d8 | 2008-12-27 19:15:43 +0530 | [diff] [blame] | 959 | else |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 960 | x86_pmu_disable_counter(hwc, idx); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 961 | } |
| 962 | |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 963 | static int |
| 964 | fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc) |
Ingo Molnar | 862a1a5 | 2008-12-17 13:09:20 +0100 | [diff] [blame] | 965 | { |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 966 | unsigned int event; |
| 967 | |
Robert Richter | ef7b3e0 | 2009-04-29 12:47:24 +0200 | [diff] [blame] | 968 | if (!x86_pmu.num_counters_fixed) |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 969 | return -1; |
| 970 | |
Yong Wang | dff5da6 | 2009-06-12 16:08:55 +0800 | [diff] [blame] | 971 | /* |
| 972 | * Quirk, IA32_FIXED_CTRs do not work on current Atom processors: |
| 973 | */ |
| 974 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && |
| 975 | boot_cpu_data.x86_model == 28) |
| 976 | return -1; |
| 977 | |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 978 | event = hwc->config & ARCH_PERFMON_EVENT_MASK; |
| 979 | |
Peter Zijlstra | f4dbfa8 | 2009-06-11 14:06:28 +0200 | [diff] [blame] | 980 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_INSTRUCTIONS))) |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 981 | return X86_PMC_IDX_FIXED_INSTRUCTIONS; |
Peter Zijlstra | f4dbfa8 | 2009-06-11 14:06:28 +0200 | [diff] [blame] | 982 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_CPU_CYCLES))) |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 983 | return X86_PMC_IDX_FIXED_CPU_CYCLES; |
Peter Zijlstra | f4dbfa8 | 2009-06-11 14:06:28 +0200 | [diff] [blame] | 984 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_BUS_CYCLES))) |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 985 | return X86_PMC_IDX_FIXED_BUS_CYCLES; |
| 986 | |
Ingo Molnar | 862a1a5 | 2008-12-17 13:09:20 +0100 | [diff] [blame] | 987 | return -1; |
| 988 | } |
| 989 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 990 | /* |
| 991 | * Find a PMC slot for the freshly enabled / scheduled in counter: |
| 992 | */ |
Robert Richter | 4aeb0b4 | 2009-04-29 12:47:03 +0200 | [diff] [blame] | 993 | static int x86_pmu_enable(struct perf_counter *counter) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 994 | { |
| 995 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
| 996 | struct hw_perf_counter *hwc = &counter->hw; |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 997 | int idx; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 998 | |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 999 | idx = fixed_mode_idx(counter, hwc); |
| 1000 | if (idx >= 0) { |
| 1001 | /* |
| 1002 | * Try to get the fixed counter, if that is already taken |
| 1003 | * then try to get a generic counter: |
| 1004 | */ |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 1005 | if (test_and_set_bit(idx, cpuc->used_mask)) |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1006 | goto try_generic; |
Ingo Molnar | 0dff86a | 2008-12-23 12:28:12 +0100 | [diff] [blame] | 1007 | |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1008 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
| 1009 | /* |
| 1010 | * We set it so that counter_base + idx in wrmsr/rdmsr maps to |
| 1011 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: |
| 1012 | */ |
| 1013 | hwc->counter_base = |
| 1014 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1015 | hwc->idx = idx; |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1016 | } else { |
| 1017 | idx = hwc->idx; |
| 1018 | /* Try to get the previous generic counter again */ |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 1019 | if (test_and_set_bit(idx, cpuc->used_mask)) { |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1020 | try_generic: |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 1021 | idx = find_first_zero_bit(cpuc->used_mask, |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 1022 | x86_pmu.num_counters); |
| 1023 | if (idx == x86_pmu.num_counters) |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1024 | return -EAGAIN; |
| 1025 | |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 1026 | set_bit(idx, cpuc->used_mask); |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1027 | hwc->idx = idx; |
| 1028 | } |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 1029 | hwc->config_base = x86_pmu.eventsel; |
| 1030 | hwc->counter_base = x86_pmu.perfctr; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1031 | } |
| 1032 | |
Yong Wang | c323d95 | 2009-05-29 13:28:35 +0800 | [diff] [blame] | 1033 | perf_counters_lapic_init(); |
Ingo Molnar | 53b441a | 2009-05-25 21:41:28 +0200 | [diff] [blame] | 1034 | |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 1035 | x86_pmu.disable(hwc, idx); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1036 | |
Ingo Molnar | 862a1a5 | 2008-12-17 13:09:20 +0100 | [diff] [blame] | 1037 | cpuc->counters[idx] = counter; |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 1038 | set_bit(idx, cpuc->active_mask); |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 1039 | |
Robert Richter | 26816c2 | 2009-04-29 12:47:08 +0200 | [diff] [blame] | 1040 | x86_perf_counter_set_period(counter, hwc, idx); |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 1041 | x86_pmu.enable(hwc, idx); |
Ingo Molnar | 95cdd2e | 2008-12-21 13:50:42 +0100 | [diff] [blame] | 1042 | |
| 1043 | return 0; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1044 | } |
| 1045 | |
Peter Zijlstra | a78ac32 | 2009-05-25 17:39:05 +0200 | [diff] [blame] | 1046 | static void x86_pmu_unthrottle(struct perf_counter *counter) |
| 1047 | { |
| 1048 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
| 1049 | struct hw_perf_counter *hwc = &counter->hw; |
| 1050 | |
| 1051 | if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX || |
| 1052 | cpuc->counters[hwc->idx] != counter)) |
| 1053 | return; |
| 1054 | |
| 1055 | x86_pmu.enable(hwc, hwc->idx); |
| 1056 | } |
| 1057 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1058 | void perf_counter_print_debug(void) |
| 1059 | { |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1060 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
Ingo Molnar | 0dff86a | 2008-12-23 12:28:12 +0100 | [diff] [blame] | 1061 | struct cpu_hw_counters *cpuc; |
Peter Zijlstra | 5bb9efe | 2009-05-13 08:12:51 +0200 | [diff] [blame] | 1062 | unsigned long flags; |
Ingo Molnar | 1e12567 | 2008-12-09 12:18:18 +0100 | [diff] [blame] | 1063 | int cpu, idx; |
| 1064 | |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 1065 | if (!x86_pmu.num_counters) |
Ingo Molnar | 1e12567 | 2008-12-09 12:18:18 +0100 | [diff] [blame] | 1066 | return; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1067 | |
Peter Zijlstra | 5bb9efe | 2009-05-13 08:12:51 +0200 | [diff] [blame] | 1068 | local_irq_save(flags); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1069 | |
| 1070 | cpu = smp_processor_id(); |
Ingo Molnar | 0dff86a | 2008-12-23 12:28:12 +0100 | [diff] [blame] | 1071 | cpuc = &per_cpu(cpu_hw_counters, cpu); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1072 | |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 1073 | if (x86_pmu.version >= 2) { |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1074 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
| 1075 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); |
| 1076 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); |
| 1077 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1078 | |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1079 | pr_info("\n"); |
| 1080 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); |
| 1081 | pr_info("CPU#%d: status: %016llx\n", cpu, status); |
| 1082 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); |
| 1083 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1084 | } |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 1085 | pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used_mask); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1086 | |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 1087 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 1088 | rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl); |
| 1089 | rdmsrl(x86_pmu.perfctr + idx, pmc_count); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1090 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1091 | prev_left = per_cpu(prev_left[idx], cpu); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1092 | |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1093 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1094 | cpu, idx, pmc_ctrl); |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1095 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1096 | cpu, idx, pmc_count); |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1097 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1098 | cpu, idx, prev_left); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1099 | } |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 1100 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1101 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
| 1102 | |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1103 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1104 | cpu, idx, pmc_count); |
| 1105 | } |
Peter Zijlstra | 5bb9efe | 2009-05-13 08:12:51 +0200 | [diff] [blame] | 1106 | local_irq_restore(flags); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1107 | } |
| 1108 | |
Robert Richter | 4aeb0b4 | 2009-04-29 12:47:03 +0200 | [diff] [blame] | 1109 | static void x86_pmu_disable(struct perf_counter *counter) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1110 | { |
| 1111 | struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters); |
| 1112 | struct hw_perf_counter *hwc = &counter->hw; |
Robert Richter | 6f00cad | 2009-04-29 12:47:17 +0200 | [diff] [blame] | 1113 | int idx = hwc->idx; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1114 | |
Robert Richter | 0953423 | 2009-04-29 12:47:16 +0200 | [diff] [blame] | 1115 | /* |
| 1116 | * Must be done before we disable, otherwise the nmi handler |
| 1117 | * could reenable again: |
| 1118 | */ |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 1119 | clear_bit(idx, cpuc->active_mask); |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 1120 | x86_pmu.disable(hwc, idx); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1121 | |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1122 | /* |
| 1123 | * Make sure the cleared pointer becomes visible before we |
| 1124 | * (potentially) free the counter: |
| 1125 | */ |
Robert Richter | 527e26a | 2009-04-29 12:47:02 +0200 | [diff] [blame] | 1126 | barrier(); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1127 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1128 | /* |
| 1129 | * Drain the remaining delta count out of a counter |
| 1130 | * that we are disabling: |
| 1131 | */ |
| 1132 | x86_perf_counter_update(counter, hwc, idx); |
Robert Richter | 0953423 | 2009-04-29 12:47:16 +0200 | [diff] [blame] | 1133 | cpuc->counters[idx] = NULL; |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 1134 | clear_bit(idx, cpuc->used_mask); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1135 | } |
| 1136 | |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 1137 | /* |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1138 | * Save and restart an expired counter. Called by NMI contexts, |
| 1139 | * so it has to be careful about preempting normal counter ops: |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 1140 | */ |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 1141 | static int intel_pmu_save_and_restart(struct perf_counter *counter) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1142 | { |
| 1143 | struct hw_perf_counter *hwc = &counter->hw; |
| 1144 | int idx = hwc->idx; |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 1145 | int ret; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1146 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1147 | x86_perf_counter_update(counter, hwc, idx); |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 1148 | ret = x86_perf_counter_set_period(counter, hwc, idx); |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 1149 | |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1150 | if (counter->state == PERF_COUNTER_STATE_ACTIVE) |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 1151 | intel_pmu_enable_counter(hwc, idx); |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 1152 | |
| 1153 | return ret; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1154 | } |
| 1155 | |
Ingo Molnar | aaba980 | 2009-05-26 08:10:00 +0200 | [diff] [blame] | 1156 | static void intel_pmu_reset(void) |
| 1157 | { |
| 1158 | unsigned long flags; |
| 1159 | int idx; |
| 1160 | |
| 1161 | if (!x86_pmu.num_counters) |
| 1162 | return; |
| 1163 | |
| 1164 | local_irq_save(flags); |
| 1165 | |
| 1166 | printk("clearing PMU state on CPU#%d\n", smp_processor_id()); |
| 1167 | |
| 1168 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
| 1169 | checking_wrmsrl(x86_pmu.eventsel + idx, 0ull); |
| 1170 | checking_wrmsrl(x86_pmu.perfctr + idx, 0ull); |
| 1171 | } |
| 1172 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
| 1173 | checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); |
| 1174 | } |
| 1175 | |
| 1176 | local_irq_restore(flags); |
| 1177 | } |
| 1178 | |
| 1179 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1180 | /* |
| 1181 | * This handler is triggered by the local APIC, so the APIC IRQ handling |
| 1182 | * rules apply: |
| 1183 | */ |
Yong Wang | a328810 | 2009-06-03 13:12:55 +0800 | [diff] [blame] | 1184 | static int intel_pmu_handle_irq(struct pt_regs *regs) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1185 | { |
Peter Zijlstra | df1a132 | 2009-06-10 21:02:22 +0200 | [diff] [blame] | 1186 | struct perf_sample_data data; |
Ingo Molnar | 9029a5e | 2009-05-15 08:26:20 +0200 | [diff] [blame] | 1187 | struct cpu_hw_counters *cpuc; |
Ingo Molnar | 9029a5e | 2009-05-15 08:26:20 +0200 | [diff] [blame] | 1188 | int bit, cpu, loops; |
Mike Galbraith | 4b39fd9 | 2009-01-23 14:36:16 +0100 | [diff] [blame] | 1189 | u64 ack, status; |
Ingo Molnar | 9029a5e | 2009-05-15 08:26:20 +0200 | [diff] [blame] | 1190 | |
Peter Zijlstra | df1a132 | 2009-06-10 21:02:22 +0200 | [diff] [blame] | 1191 | data.regs = regs; |
| 1192 | data.addr = 0; |
| 1193 | |
Ingo Molnar | 9029a5e | 2009-05-15 08:26:20 +0200 | [diff] [blame] | 1194 | cpu = smp_processor_id(); |
| 1195 | cpuc = &per_cpu(cpu_hw_counters, cpu); |
Ingo Molnar | 43874d2 | 2008-12-09 12:23:59 +0100 | [diff] [blame] | 1196 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 1197 | perf_disable(); |
Robert Richter | 19d84da | 2009-04-29 12:47:25 +0200 | [diff] [blame] | 1198 | status = intel_pmu_get_status(); |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 1199 | if (!status) { |
| 1200 | perf_enable(); |
| 1201 | return 0; |
| 1202 | } |
Ingo Molnar | 87b9cf4 | 2008-12-08 14:20:16 +0100 | [diff] [blame] | 1203 | |
Ingo Molnar | 9029a5e | 2009-05-15 08:26:20 +0200 | [diff] [blame] | 1204 | loops = 0; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1205 | again: |
Ingo Molnar | 9029a5e | 2009-05-15 08:26:20 +0200 | [diff] [blame] | 1206 | if (++loops > 100) { |
| 1207 | WARN_ONCE(1, "perfcounters: irq loop stuck!\n"); |
Ingo Molnar | 34adc80 | 2009-05-20 20:13:28 +0200 | [diff] [blame] | 1208 | perf_counter_print_debug(); |
Ingo Molnar | aaba980 | 2009-05-26 08:10:00 +0200 | [diff] [blame] | 1209 | intel_pmu_reset(); |
| 1210 | perf_enable(); |
Ingo Molnar | 9029a5e | 2009-05-15 08:26:20 +0200 | [diff] [blame] | 1211 | return 1; |
| 1212 | } |
| 1213 | |
Mike Galbraith | d278c48 | 2009-02-09 07:38:50 +0100 | [diff] [blame] | 1214 | inc_irq_stat(apic_perf_irqs); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1215 | ack = status; |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1216 | for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { |
Ingo Molnar | 862a1a5 | 2008-12-17 13:09:20 +0100 | [diff] [blame] | 1217 | struct perf_counter *counter = cpuc->counters[bit]; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1218 | |
| 1219 | clear_bit(bit, (unsigned long *) &status); |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 1220 | if (!test_bit(bit, cpuc->active_mask)) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1221 | continue; |
| 1222 | |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 1223 | if (!intel_pmu_save_and_restart(counter)) |
| 1224 | continue; |
| 1225 | |
Peter Zijlstra | df1a132 | 2009-06-10 21:02:22 +0200 | [diff] [blame] | 1226 | if (perf_counter_overflow(counter, 1, &data)) |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 1227 | intel_pmu_disable_counter(&counter->hw, bit); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1228 | } |
| 1229 | |
Robert Richter | dee5d90 | 2009-04-29 12:47:07 +0200 | [diff] [blame] | 1230 | intel_pmu_ack_status(ack); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1231 | |
| 1232 | /* |
| 1233 | * Repeat if there is more work to be done: |
| 1234 | */ |
Robert Richter | 19d84da | 2009-04-29 12:47:25 +0200 | [diff] [blame] | 1235 | status = intel_pmu_get_status(); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1236 | if (status) |
| 1237 | goto again; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 1238 | |
Peter Zijlstra | 48e22d5 | 2009-05-25 17:39:04 +0200 | [diff] [blame] | 1239 | perf_enable(); |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 1240 | |
| 1241 | return 1; |
Mike Galbraith | 1b023a9 | 2009-01-23 10:13:01 +0100 | [diff] [blame] | 1242 | } |
| 1243 | |
Yong Wang | a328810 | 2009-06-03 13:12:55 +0800 | [diff] [blame] | 1244 | static int amd_pmu_handle_irq(struct pt_regs *regs) |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 1245 | { |
Peter Zijlstra | df1a132 | 2009-06-10 21:02:22 +0200 | [diff] [blame] | 1246 | struct perf_sample_data data; |
Ingo Molnar | 9029a5e | 2009-05-15 08:26:20 +0200 | [diff] [blame] | 1247 | struct cpu_hw_counters *cpuc; |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 1248 | struct perf_counter *counter; |
| 1249 | struct hw_perf_counter *hwc; |
Peter Zijlstra | df1a132 | 2009-06-10 21:02:22 +0200 | [diff] [blame] | 1250 | int cpu, idx, handled = 0; |
Ingo Molnar | 9029a5e | 2009-05-15 08:26:20 +0200 | [diff] [blame] | 1251 | u64 val; |
| 1252 | |
Peter Zijlstra | df1a132 | 2009-06-10 21:02:22 +0200 | [diff] [blame] | 1253 | data.regs = regs; |
| 1254 | data.addr = 0; |
| 1255 | |
Ingo Molnar | 9029a5e | 2009-05-15 08:26:20 +0200 | [diff] [blame] | 1256 | cpu = smp_processor_id(); |
| 1257 | cpuc = &per_cpu(cpu_hw_counters, cpu); |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 1258 | |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 1259 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 1260 | if (!test_bit(idx, cpuc->active_mask)) |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 1261 | continue; |
Peter Zijlstra | 962bf7a | 2009-05-13 13:21:36 +0200 | [diff] [blame] | 1262 | |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 1263 | counter = cpuc->counters[idx]; |
| 1264 | hwc = &counter->hw; |
Peter Zijlstra | a4016a7 | 2009-05-14 14:52:17 +0200 | [diff] [blame] | 1265 | |
Robert Richter | 4b7bfd0 | 2009-04-29 12:47:22 +0200 | [diff] [blame] | 1266 | val = x86_perf_counter_update(counter, hwc, idx); |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 1267 | if (val & (1ULL << (x86_pmu.counter_bits - 1))) |
Peter Zijlstra | 48e22d5 | 2009-05-25 17:39:04 +0200 | [diff] [blame] | 1268 | continue; |
Peter Zijlstra | 962bf7a | 2009-05-13 13:21:36 +0200 | [diff] [blame] | 1269 | |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 1270 | /* |
| 1271 | * counter overflow |
| 1272 | */ |
| 1273 | handled = 1; |
| 1274 | data.period = counter->hw.last_period; |
| 1275 | |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 1276 | if (!x86_perf_counter_set_period(counter, hwc, idx)) |
| 1277 | continue; |
| 1278 | |
Peter Zijlstra | df1a132 | 2009-06-10 21:02:22 +0200 | [diff] [blame] | 1279 | if (perf_counter_overflow(counter, 1, &data)) |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 1280 | amd_pmu_disable_counter(hwc, idx); |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 1281 | } |
Peter Zijlstra | 962bf7a | 2009-05-13 13:21:36 +0200 | [diff] [blame] | 1282 | |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 1283 | if (handled) |
| 1284 | inc_irq_stat(apic_perf_irqs); |
| 1285 | |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 1286 | return handled; |
| 1287 | } |
Robert Richter | 39d81ea | 2009-04-29 12:47:05 +0200 | [diff] [blame] | 1288 | |
Peter Zijlstra | b6276f3 | 2009-04-06 11:45:03 +0200 | [diff] [blame] | 1289 | void smp_perf_pending_interrupt(struct pt_regs *regs) |
| 1290 | { |
| 1291 | irq_enter(); |
| 1292 | ack_APIC_irq(); |
| 1293 | inc_irq_stat(apic_pending_irqs); |
| 1294 | perf_counter_do_pending(); |
| 1295 | irq_exit(); |
| 1296 | } |
| 1297 | |
| 1298 | void set_perf_counter_pending(void) |
| 1299 | { |
| 1300 | apic->send_IPI_self(LOCAL_PENDING_VECTOR); |
| 1301 | } |
| 1302 | |
Yong Wang | c323d95 | 2009-05-29 13:28:35 +0800 | [diff] [blame] | 1303 | void perf_counters_lapic_init(void) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1304 | { |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 1305 | if (!x86_pmu_initialized()) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1306 | return; |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 1307 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1308 | /* |
Yong Wang | c323d95 | 2009-05-29 13:28:35 +0800 | [diff] [blame] | 1309 | * Always use NMI for PMU |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1310 | */ |
Yong Wang | c323d95 | 2009-05-29 13:28:35 +0800 | [diff] [blame] | 1311 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1312 | } |
| 1313 | |
| 1314 | static int __kprobes |
| 1315 | perf_counter_nmi_handler(struct notifier_block *self, |
| 1316 | unsigned long cmd, void *__args) |
| 1317 | { |
| 1318 | struct die_args *args = __args; |
| 1319 | struct pt_regs *regs; |
| 1320 | |
Peter Zijlstra | ba77813 | 2009-05-04 18:47:44 +0200 | [diff] [blame] | 1321 | if (!atomic_read(&active_counters)) |
Peter Zijlstra | 63a809a | 2009-05-01 12:23:17 +0200 | [diff] [blame] | 1322 | return NOTIFY_DONE; |
| 1323 | |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 1324 | switch (cmd) { |
| 1325 | case DIE_NMI: |
| 1326 | case DIE_NMI_IPI: |
| 1327 | break; |
| 1328 | |
| 1329 | default: |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1330 | return NOTIFY_DONE; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 1331 | } |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1332 | |
| 1333 | regs = args->regs; |
| 1334 | |
| 1335 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
Peter Zijlstra | a4016a7 | 2009-05-14 14:52:17 +0200 | [diff] [blame] | 1336 | /* |
| 1337 | * Can't rely on the handled return value to say it was our NMI, two |
| 1338 | * counters could trigger 'simultaneously' raising two back-to-back NMIs. |
| 1339 | * |
| 1340 | * If the first NMI handles both, the latter will be empty and daze |
| 1341 | * the CPU. |
| 1342 | */ |
Yong Wang | a328810 | 2009-06-03 13:12:55 +0800 | [diff] [blame] | 1343 | x86_pmu.handle_irq(regs); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1344 | |
Peter Zijlstra | a4016a7 | 2009-05-14 14:52:17 +0200 | [diff] [blame] | 1345 | return NOTIFY_STOP; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1346 | } |
| 1347 | |
| 1348 | static __read_mostly struct notifier_block perf_counter_nmi_notifier = { |
Mike Galbraith | 5b75af0 | 2009-02-04 17:11:34 +0100 | [diff] [blame] | 1349 | .notifier_call = perf_counter_nmi_handler, |
| 1350 | .next = NULL, |
| 1351 | .priority = 1 |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1352 | }; |
| 1353 | |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 1354 | static struct x86_pmu intel_pmu = { |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 1355 | .name = "Intel", |
Robert Richter | 39d81ea | 2009-04-29 12:47:05 +0200 | [diff] [blame] | 1356 | .handle_irq = intel_pmu_handle_irq, |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 1357 | .disable_all = intel_pmu_disable_all, |
| 1358 | .enable_all = intel_pmu_enable_all, |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 1359 | .enable = intel_pmu_enable_counter, |
| 1360 | .disable = intel_pmu_disable_counter, |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1361 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, |
| 1362 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 1363 | .event_map = intel_pmu_event_map, |
| 1364 | .raw_event = intel_pmu_raw_event, |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1365 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), |
Robert Richter | c619b8f | 2009-04-29 12:47:23 +0200 | [diff] [blame] | 1366 | /* |
| 1367 | * Intel PMCs cannot be accessed sanely above 32 bit width, |
| 1368 | * so we install an artificial 1<<31 period regardless of |
| 1369 | * the generic counter period: |
| 1370 | */ |
| 1371 | .max_period = (1ULL << 31) - 1, |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1372 | }; |
| 1373 | |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 1374 | static struct x86_pmu amd_pmu = { |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 1375 | .name = "AMD", |
Robert Richter | 39d81ea | 2009-04-29 12:47:05 +0200 | [diff] [blame] | 1376 | .handle_irq = amd_pmu_handle_irq, |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 1377 | .disable_all = amd_pmu_disable_all, |
| 1378 | .enable_all = amd_pmu_enable_all, |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 1379 | .enable = amd_pmu_enable_counter, |
| 1380 | .disable = amd_pmu_disable_counter, |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1381 | .eventsel = MSR_K7_EVNTSEL0, |
| 1382 | .perfctr = MSR_K7_PERFCTR0, |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 1383 | .event_map = amd_pmu_event_map, |
| 1384 | .raw_event = amd_pmu_raw_event, |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1385 | .max_events = ARRAY_SIZE(amd_perfmon_event_map), |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 1386 | .num_counters = 4, |
| 1387 | .counter_bits = 48, |
| 1388 | .counter_mask = (1ULL << 48) - 1, |
Robert Richter | c619b8f | 2009-04-29 12:47:23 +0200 | [diff] [blame] | 1389 | /* use highest bit to detect overflow */ |
| 1390 | .max_period = (1ULL << 47) - 1, |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1391 | }; |
| 1392 | |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 1393 | static int intel_pmu_init(void) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1394 | { |
Ingo Molnar | 703e937 | 2008-12-17 10:51:15 +0100 | [diff] [blame] | 1395 | union cpuid10_edx edx; |
Ingo Molnar | 7bb497b | 2009-03-18 08:59:21 +0100 | [diff] [blame] | 1396 | union cpuid10_eax eax; |
| 1397 | unsigned int unused; |
| 1398 | unsigned int ebx; |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 1399 | int version; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1400 | |
Robert Richter | da1a776 | 2009-04-29 12:46:58 +0200 | [diff] [blame] | 1401 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 1402 | return -ENODEV; |
Robert Richter | da1a776 | 2009-04-29 12:46:58 +0200 | [diff] [blame] | 1403 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1404 | /* |
| 1405 | * Check whether the Architectural PerfMon supports |
| 1406 | * Branch Misses Retired Event or not. |
| 1407 | */ |
Ingo Molnar | 703e937 | 2008-12-17 10:51:15 +0100 | [diff] [blame] | 1408 | cpuid(10, &eax.full, &ebx, &unused, &edx.full); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1409 | if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED) |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 1410 | return -ENODEV; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1411 | |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 1412 | version = eax.split.version_id; |
| 1413 | if (version < 2) |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 1414 | return -ENODEV; |
Ingo Molnar | 7bb497b | 2009-03-18 08:59:21 +0100 | [diff] [blame] | 1415 | |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1416 | x86_pmu = intel_pmu; |
| 1417 | x86_pmu.version = version; |
| 1418 | x86_pmu.num_counters = eax.split.num_counters; |
| 1419 | x86_pmu.counter_bits = eax.split.bit_width; |
| 1420 | x86_pmu.counter_mask = (1ULL << eax.split.bit_width) - 1; |
Ingo Molnar | 066d7de | 2009-05-04 19:04:09 +0200 | [diff] [blame] | 1421 | |
| 1422 | /* |
| 1423 | * Quirk: v2 perfmon does not report fixed-purpose counters, so |
| 1424 | * assume at least 3 counters: |
| 1425 | */ |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1426 | x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3); |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1427 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 1428 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); |
| 1429 | |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 1430 | /* |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1431 | * Install the hw-cache-events table: |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 1432 | */ |
| 1433 | switch (boot_cpu_data.x86_model) { |
Yong Wang | dc81081 | 2009-06-10 17:06:12 +0800 | [diff] [blame] | 1434 | case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */ |
| 1435 | case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */ |
| 1436 | case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */ |
| 1437 | case 29: /* six-core 45 nm xeon "Dunnington" */ |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 1438 | memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, |
Thomas Gleixner | 820a644 | 2009-06-08 19:10:25 +0200 | [diff] [blame] | 1439 | sizeof(hw_cache_event_ids)); |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 1440 | |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1441 | pr_cont("Core2 events, "); |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 1442 | break; |
| 1443 | default: |
| 1444 | case 26: |
| 1445 | memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, |
Thomas Gleixner | 820a644 | 2009-06-08 19:10:25 +0200 | [diff] [blame] | 1446 | sizeof(hw_cache_event_ids)); |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 1447 | |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1448 | pr_cont("Nehalem/Corei7 events, "); |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 1449 | break; |
| 1450 | case 28: |
| 1451 | memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, |
Thomas Gleixner | 820a644 | 2009-06-08 19:10:25 +0200 | [diff] [blame] | 1452 | sizeof(hw_cache_event_ids)); |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 1453 | |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1454 | pr_cont("Atom events, "); |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 1455 | break; |
| 1456 | } |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 1457 | return 0; |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1458 | } |
| 1459 | |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 1460 | static int amd_pmu_init(void) |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1461 | { |
Jaswinder Singh Rajput | 4d2be12 | 2009-06-11 15:28:09 +0530 | [diff] [blame] | 1462 | /* Performance-monitoring supported from K7 and later: */ |
| 1463 | if (boot_cpu_data.x86 < 6) |
| 1464 | return -ENODEV; |
| 1465 | |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 1466 | x86_pmu = amd_pmu; |
Thomas Gleixner | f86748e | 2009-06-08 22:33:10 +0200 | [diff] [blame] | 1467 | |
Jaswinder Singh Rajput | f4db43a | 2009-06-13 01:06:21 +0530 | [diff] [blame] | 1468 | /* Events are common for all AMDs */ |
| 1469 | memcpy(hw_cache_event_ids, amd_hw_cache_event_ids, |
| 1470 | sizeof(hw_cache_event_ids)); |
Thomas Gleixner | f86748e | 2009-06-08 22:33:10 +0200 | [diff] [blame] | 1471 | |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 1472 | return 0; |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1473 | } |
| 1474 | |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1475 | void __init init_hw_perf_counters(void) |
| 1476 | { |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 1477 | int err; |
| 1478 | |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1479 | pr_info("Performance Counters: "); |
| 1480 | |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1481 | switch (boot_cpu_data.x86_vendor) { |
| 1482 | case X86_VENDOR_INTEL: |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 1483 | err = intel_pmu_init(); |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1484 | break; |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1485 | case X86_VENDOR_AMD: |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 1486 | err = amd_pmu_init(); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1487 | break; |
Robert Richter | 4138960 | 2009-04-29 12:47:00 +0200 | [diff] [blame] | 1488 | default: |
| 1489 | return; |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1490 | } |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1491 | if (err != 0) { |
| 1492 | pr_cont("no PMU driver, software counters only.\n"); |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1493 | return; |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1494 | } |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1495 | |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1496 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 1497 | |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 1498 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { |
| 1499 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1500 | WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!", |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 1501 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1502 | } |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 1503 | perf_counter_mask = (1 << x86_pmu.num_counters) - 1; |
| 1504 | perf_max_counters = x86_pmu.num_counters; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1505 | |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 1506 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
| 1507 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; |
Ingo Molnar | 703e937 | 2008-12-17 10:51:15 +0100 | [diff] [blame] | 1508 | WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!", |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 1509 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
Ingo Molnar | 703e937 | 2008-12-17 10:51:15 +0100 | [diff] [blame] | 1510 | } |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1511 | |
Robert Richter | 0933e5c | 2009-04-29 12:47:12 +0200 | [diff] [blame] | 1512 | perf_counter_mask |= |
| 1513 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; |
Ingo Molnar | 862a1a5 | 2008-12-17 13:09:20 +0100 | [diff] [blame] | 1514 | |
Yong Wang | c323d95 | 2009-05-29 13:28:35 +0800 | [diff] [blame] | 1515 | perf_counters_lapic_init(); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1516 | register_die_notifier(&perf_counter_nmi_notifier); |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1517 | |
| 1518 | pr_info("... version: %d\n", x86_pmu.version); |
| 1519 | pr_info("... bit width: %d\n", x86_pmu.counter_bits); |
| 1520 | pr_info("... generic counters: %d\n", x86_pmu.num_counters); |
| 1521 | pr_info("... value mask: %016Lx\n", x86_pmu.counter_mask); |
| 1522 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
| 1523 | pr_info("... fixed-purpose counters: %d\n", x86_pmu.num_counters_fixed); |
| 1524 | pr_info("... counter mask: %016Lx\n", perf_counter_mask); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1525 | } |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1526 | |
Robert Richter | bb775fc | 2009-04-29 12:47:14 +0200 | [diff] [blame] | 1527 | static inline void x86_pmu_read(struct perf_counter *counter) |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1528 | { |
| 1529 | x86_perf_counter_update(counter, &counter->hw, counter->hw.idx); |
| 1530 | } |
| 1531 | |
Robert Richter | 4aeb0b4 | 2009-04-29 12:47:03 +0200 | [diff] [blame] | 1532 | static const struct pmu pmu = { |
| 1533 | .enable = x86_pmu_enable, |
| 1534 | .disable = x86_pmu_disable, |
| 1535 | .read = x86_pmu_read, |
Peter Zijlstra | a78ac32 | 2009-05-25 17:39:05 +0200 | [diff] [blame] | 1536 | .unthrottle = x86_pmu_unthrottle, |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1537 | }; |
| 1538 | |
Robert Richter | 4aeb0b4 | 2009-04-29 12:47:03 +0200 | [diff] [blame] | 1539 | const struct pmu *hw_perf_counter_init(struct perf_counter *counter) |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1540 | { |
| 1541 | int err; |
| 1542 | |
| 1543 | err = __hw_perf_counter_init(counter); |
| 1544 | if (err) |
Peter Zijlstra | 9ea98e1 | 2009-03-30 19:07:09 +0200 | [diff] [blame] | 1545 | return ERR_PTR(err); |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1546 | |
Robert Richter | 4aeb0b4 | 2009-04-29 12:47:03 +0200 | [diff] [blame] | 1547 | return &pmu; |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1548 | } |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1549 | |
| 1550 | /* |
| 1551 | * callchain support |
| 1552 | */ |
| 1553 | |
| 1554 | static inline |
| 1555 | void callchain_store(struct perf_callchain_entry *entry, unsigned long ip) |
| 1556 | { |
| 1557 | if (entry->nr < MAX_STACK_DEPTH) |
| 1558 | entry->ip[entry->nr++] = ip; |
| 1559 | } |
| 1560 | |
| 1561 | static DEFINE_PER_CPU(struct perf_callchain_entry, irq_entry); |
| 1562 | static DEFINE_PER_CPU(struct perf_callchain_entry, nmi_entry); |
| 1563 | |
| 1564 | |
| 1565 | static void |
| 1566 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) |
| 1567 | { |
| 1568 | /* Ignore warnings */ |
| 1569 | } |
| 1570 | |
| 1571 | static void backtrace_warning(void *data, char *msg) |
| 1572 | { |
| 1573 | /* Ignore warnings */ |
| 1574 | } |
| 1575 | |
| 1576 | static int backtrace_stack(void *data, char *name) |
| 1577 | { |
Ingo Molnar | 038e836 | 2009-06-15 09:57:59 +0200 | [diff] [blame^] | 1578 | /* Process all stacks: */ |
| 1579 | return 0; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1580 | } |
| 1581 | |
| 1582 | static void backtrace_address(void *data, unsigned long addr, int reliable) |
| 1583 | { |
| 1584 | struct perf_callchain_entry *entry = data; |
| 1585 | |
| 1586 | if (reliable) |
| 1587 | callchain_store(entry, addr); |
| 1588 | } |
| 1589 | |
| 1590 | static const struct stacktrace_ops backtrace_ops = { |
| 1591 | .warning = backtrace_warning, |
| 1592 | .warning_symbol = backtrace_warning_symbol, |
| 1593 | .stack = backtrace_stack, |
| 1594 | .address = backtrace_address, |
| 1595 | }; |
| 1596 | |
Ingo Molnar | 038e836 | 2009-06-15 09:57:59 +0200 | [diff] [blame^] | 1597 | #include "../dumpstack.h" |
| 1598 | |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1599 | static void |
| 1600 | perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) |
| 1601 | { |
| 1602 | unsigned long bp; |
| 1603 | char *stack; |
Peter Zijlstra | 5872bdb8 | 2009-04-02 11:12:03 +0200 | [diff] [blame] | 1604 | int nr = entry->nr; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1605 | |
Ingo Molnar | 038e836 | 2009-06-15 09:57:59 +0200 | [diff] [blame^] | 1606 | callchain_store(entry, regs->ip); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1607 | |
| 1608 | stack = ((char *)regs + sizeof(struct pt_regs)); |
| 1609 | #ifdef CONFIG_FRAME_POINTER |
Ingo Molnar | 038e836 | 2009-06-15 09:57:59 +0200 | [diff] [blame^] | 1610 | get_bp(bp); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1611 | #else |
| 1612 | bp = 0; |
| 1613 | #endif |
| 1614 | |
Ingo Molnar | 038e836 | 2009-06-15 09:57:59 +0200 | [diff] [blame^] | 1615 | dump_trace(NULL, regs, (void *)&stack, bp, &backtrace_ops, entry); |
Peter Zijlstra | 5872bdb8 | 2009-04-02 11:12:03 +0200 | [diff] [blame] | 1616 | |
| 1617 | entry->kernel = entry->nr - nr; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1618 | } |
| 1619 | |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1620 | static int copy_stack_frame(const void __user *fp, struct stack_frame *frame) |
| 1621 | { |
| 1622 | int ret; |
| 1623 | |
| 1624 | if (!access_ok(VERIFY_READ, fp, sizeof(*frame))) |
| 1625 | return 0; |
| 1626 | |
| 1627 | ret = 1; |
| 1628 | pagefault_disable(); |
| 1629 | if (__copy_from_user_inatomic(frame, fp, sizeof(*frame))) |
| 1630 | ret = 0; |
| 1631 | pagefault_enable(); |
| 1632 | |
| 1633 | return ret; |
| 1634 | } |
| 1635 | |
| 1636 | static void |
| 1637 | perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) |
| 1638 | { |
| 1639 | struct stack_frame frame; |
| 1640 | const void __user *fp; |
Peter Zijlstra | 5872bdb8 | 2009-04-02 11:12:03 +0200 | [diff] [blame] | 1641 | int nr = entry->nr; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1642 | |
Ingo Molnar | 5a6cec3 | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1643 | if (!user_mode(regs)) |
| 1644 | regs = task_pt_regs(current); |
| 1645 | |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1646 | fp = (void __user *)regs->bp; |
| 1647 | |
| 1648 | callchain_store(entry, regs->ip); |
| 1649 | |
| 1650 | while (entry->nr < MAX_STACK_DEPTH) { |
Ingo Molnar | 038e836 | 2009-06-15 09:57:59 +0200 | [diff] [blame^] | 1651 | frame.next_frame = NULL; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1652 | frame.return_address = 0; |
| 1653 | |
| 1654 | if (!copy_stack_frame(fp, &frame)) |
| 1655 | break; |
| 1656 | |
Ingo Molnar | 5a6cec3 | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1657 | if ((unsigned long)fp < regs->sp) |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1658 | break; |
| 1659 | |
| 1660 | callchain_store(entry, frame.return_address); |
Ingo Molnar | 038e836 | 2009-06-15 09:57:59 +0200 | [diff] [blame^] | 1661 | fp = frame.next_frame; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1662 | } |
Peter Zijlstra | 5872bdb8 | 2009-04-02 11:12:03 +0200 | [diff] [blame] | 1663 | |
| 1664 | entry->user = entry->nr - nr; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1665 | } |
| 1666 | |
| 1667 | static void |
| 1668 | perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) |
| 1669 | { |
| 1670 | int is_user; |
| 1671 | |
| 1672 | if (!regs) |
| 1673 | return; |
| 1674 | |
| 1675 | is_user = user_mode(regs); |
| 1676 | |
| 1677 | if (!current || current->pid == 0) |
| 1678 | return; |
| 1679 | |
| 1680 | if (is_user && current->state != TASK_RUNNING) |
| 1681 | return; |
| 1682 | |
| 1683 | if (!is_user) |
| 1684 | perf_callchain_kernel(regs, entry); |
| 1685 | |
| 1686 | if (current->mm) |
| 1687 | perf_callchain_user(regs, entry); |
| 1688 | } |
| 1689 | |
| 1690 | struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) |
| 1691 | { |
| 1692 | struct perf_callchain_entry *entry; |
| 1693 | |
| 1694 | if (in_nmi()) |
| 1695 | entry = &__get_cpu_var(nmi_entry); |
| 1696 | else |
| 1697 | entry = &__get_cpu_var(irq_entry); |
| 1698 | |
| 1699 | entry->nr = 0; |
Peter Zijlstra | 5872bdb8 | 2009-04-02 11:12:03 +0200 | [diff] [blame] | 1700 | entry->hv = 0; |
| 1701 | entry->kernel = 0; |
| 1702 | entry->user = 0; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1703 | |
| 1704 | perf_do_callchain(regs, entry); |
| 1705 | |
| 1706 | return entry; |
| 1707 | } |