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gerrit-public.fairphone.software / kernel / msm-4.9 / 03b5357c3005e097f314136bade3683a0525b68f / . / drivers / dma / coh901318.c
blob: f7100dc6b8e22b1b64bcfb9ecfb85bd96cbefc8c [file] [log] [blame]
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1/*
2 * driver/dma/coh901318.c
3 *
4 * Copyright (C) 2007-2009 ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 * DMA driver for COH 901 318
7 * Author: Per Friden <per.friden@stericsson.com>
8 */
9
10#include <linux/init.h>
11#include <linux/module.h>
12#include <linux/kernel.h> /* printk() */
13#include <linux/fs.h> /* everything... */
Alexey Dobriyanb7f080c2011-06-16 11:01:34 +0000[diff] [blame]14#include <linux/scatterlist.h>
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]15#include <linux/slab.h> /* kmalloc() */
16#include <linux/dmaengine.h>
17#include <linux/platform_device.h>
18#include <linux/device.h>
19#include <linux/irqreturn.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/uaccess.h>
23#include <linux/debugfs.h>
Linus Walleij9f575d92013-01-04 10:35:06 +0100[diff] [blame]24#include <linux/platform_data/dma-coh901318.h>
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]25
Linus Walleij2b9277a2013-01-04 13:56:16 +0100[diff] [blame]26#include "coh901318.h"
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]27#include "coh901318_lli.h"
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +0000[diff] [blame]28#include "dmaengine.h"
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]29
Linus Walleij03b53572013-01-04 14:07:51 +0100[diff] [blame^]30#define COH901318_MOD32_MASK (0x1F)
31#define COH901318_WORD_MASK (0xFFFFFFFF)
32/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
33#define COH901318_INT_STATUS1 (0x0000)
34#define COH901318_INT_STATUS2 (0x0004)
35/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
36#define COH901318_TC_INT_STATUS1 (0x0008)
37#define COH901318_TC_INT_STATUS2 (0x000C)
38/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
39#define COH901318_TC_INT_CLEAR1 (0x0010)
40#define COH901318_TC_INT_CLEAR2 (0x0014)
41/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
42#define COH901318_RAW_TC_INT_STATUS1 (0x0018)
43#define COH901318_RAW_TC_INT_STATUS2 (0x001C)
44/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
45#define COH901318_BE_INT_STATUS1 (0x0020)
46#define COH901318_BE_INT_STATUS2 (0x0024)
47/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
48#define COH901318_BE_INT_CLEAR1 (0x0028)
49#define COH901318_BE_INT_CLEAR2 (0x002C)
50/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
51#define COH901318_RAW_BE_INT_STATUS1 (0x0030)
52#define COH901318_RAW_BE_INT_STATUS2 (0x0034)
53
54/*
55 * CX_CFG - Channel Configuration Registers 32bit (R/W)
56 */
57#define COH901318_CX_CFG (0x0100)
58#define COH901318_CX_CFG_SPACING (0x04)
59/* Channel enable activates tha dma job */
60#define COH901318_CX_CFG_CH_ENABLE (0x00000001)
61#define COH901318_CX_CFG_CH_DISABLE (0x00000000)
62/* Request Mode */
63#define COH901318_CX_CFG_RM_MASK (0x00000006)
64#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1)
65#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1)
66#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1)
67#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1)
68#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1)
69/* Linked channel request field. RM must == 11 */
70#define COH901318_CX_CFG_LCRF_SHIFT 3
71#define COH901318_CX_CFG_LCRF_MASK (0x000001F8)
72#define COH901318_CX_CFG_LCR_DISABLE (0x00000000)
73/* Terminal Counter Interrupt Request Mask */
74#define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200)
75#define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000)
76/* Bus Error interrupt Mask */
77#define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400)
78#define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000)
79
80/*
81 * CX_STAT - Channel Status Registers 32bit (R/-)
82 */
83#define COH901318_CX_STAT (0x0200)
84#define COH901318_CX_STAT_SPACING (0x04)
85#define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008)
86#define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004)
87#define COH901318_CX_STAT_ACTIVE (0x00000002)
88#define COH901318_CX_STAT_ENABLED (0x00000001)
89
90/*
91 * CX_CTRL - Channel Control Registers 32bit (R/W)
92 */
93#define COH901318_CX_CTRL (0x0400)
94#define COH901318_CX_CTRL_SPACING (0x10)
95/* Transfer Count Enable */
96#define COH901318_CX_CTRL_TC_ENABLE (0x00001000)
97#define COH901318_CX_CTRL_TC_DISABLE (0x00000000)
98/* Transfer Count Value 0 - 4095 */
99#define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF)
100/* Burst count */
101#define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000)
102#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13)
103#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13)
104#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13)
105#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13)
106#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13)
107#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13)
108#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13)
109#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13)
110/* Source bus size */
111#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000)
112#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16)
113#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16)
114#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16)
115/* Source address increment */
116#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000)
117#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000)
118/* Destination Bus Size */
119#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000)
120#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19)
121#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19)
122#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19)
123/* Destination address increment */
124#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000)
125#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000)
126/* Master Mode (Master2 is only connected to MSL) */
127#define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000)
128#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22)
129#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22)
130#define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22)
131#define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22)
132/* Terminal Count flag to PER enable */
133#define COH901318_CX_CTRL_TCP_ENABLE (0x01000000)
134#define COH901318_CX_CTRL_TCP_DISABLE (0x00000000)
135/* Terminal Count flags to CPU enable */
136#define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000)
137#define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000)
138/* Hand shake to peripheral */
139#define COH901318_CX_CTRL_HSP_ENABLE (0x04000000)
140#define COH901318_CX_CTRL_HSP_DISABLE (0x00000000)
141#define COH901318_CX_CTRL_HSS_ENABLE (0x08000000)
142#define COH901318_CX_CTRL_HSS_DISABLE (0x00000000)
143/* DMA mode */
144#define COH901318_CX_CTRL_DDMA_MASK (0x30000000)
145#define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28)
146#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28)
147#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28)
148/* Primary Request Data Destination */
149#define COH901318_CX_CTRL_PRDD_MASK (0x40000000)
150#define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30)
151#define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30)
152
153/*
154 * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
155 */
156#define COH901318_CX_SRC_ADDR (0x0404)
157#define COH901318_CX_SRC_ADDR_SPACING (0x10)
158
159/*
160 * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
161 */
162#define COH901318_CX_DST_ADDR (0x0408)
163#define COH901318_CX_DST_ADDR_SPACING (0x10)
164
165/*
166 * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
167 */
168#define COH901318_CX_LNK_ADDR (0x040C)
169#define COH901318_CX_LNK_ADDR_SPACING (0x10)
170#define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001)
171
172/**
173 * struct coh901318_params - parameters for DMAC configuration
174 * @config: DMA config register
175 * @ctrl_lli_last: DMA control register for the last lli in the list
176 * @ctrl_lli: DMA control register for an lli
177 * @ctrl_lli_chained: DMA control register for a chained lli
178 */
179struct coh901318_params {
180 u32 config;
181 u32 ctrl_lli_last;
182 u32 ctrl_lli;
183 u32 ctrl_lli_chained;
184};
185
186/**
187 * struct coh_dma_channel - dma channel base
188 * @name: ascii name of dma channel
189 * @number: channel id number
190 * @desc_nbr_max: number of preallocated descriptors
191 * @priority_high: prio of channel, 0 low otherwise high.
192 * @param: configuration parameters
193 */
194struct coh_dma_channel {
195 const char name[32];
196 const int number;
197 const int desc_nbr_max;
198 const int priority_high;
199 const struct coh901318_params param;
200};
201
202/**
203 * dma_access_memory_state_t - register dma for memory access
204 *
205 * @dev: The dma device
206 * @active: 1 means dma intends to access memory
207 * 0 means dma wont access memory
208 */
209typedef void (*dma_access_memory_state_t)(struct device *dev,
210 bool active);
211
212/**
213 * struct powersave - DMA power save structure
214 * @lock: lock protecting data in this struct
215 * @started_channels: bit mask indicating active dma channels
216 */
217struct powersave {
218 spinlock_t lock;
219 u64 started_channels;
220};
221
222/**
223 * struct coh901318_platform - platform arch structure
224 * @chans_slave: specifying dma slave channels
225 * @chans_memcpy: specifying dma memcpy channels
226 * @access_memory_state: requesting DMA memory access (on / off)
227 * @chan_conf: dma channel configurations
228 * @max_channels: max number of dma chanenls
229 */
230struct coh901318_platform {
231 const int *chans_slave;
232 const int *chans_memcpy;
233 const dma_access_memory_state_t access_memory_state;
234 const struct coh_dma_channel *chan_conf;
235 const int max_channels;
236};
237
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]238/* points out all dma slave channels.
239 * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
240 * Select all channels from A to B, end of list is marked with -1,-1
241 */
242static int dma_slave_channels[] = {
243 U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
244 U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
245
246/* points out all dma memcpy channels. */
247static int dma_memcpy_channels[] = {
248 U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
249
250/** register dma for memory access
251 *
252 * active 1 means dma intends to access memory
253 * 0 means dma wont access memory
254 */
255static void coh901318_access_memory_state(struct device *dev, bool active)
256{
257}
258
259#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
260 COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
261 COH901318_CX_CFG_LCR_DISABLE | \
262 COH901318_CX_CFG_TC_IRQ_ENABLE | \
263 COH901318_CX_CFG_BE_IRQ_ENABLE)
264#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
265 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
266 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
267 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
268 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
269 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
270 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
271 COH901318_CX_CTRL_TCP_DISABLE | \
272 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
273 COH901318_CX_CTRL_HSP_DISABLE | \
274 COH901318_CX_CTRL_HSS_DISABLE | \
275 COH901318_CX_CTRL_DDMA_LEGACY | \
276 COH901318_CX_CTRL_PRDD_SOURCE)
277#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
278 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
279 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
280 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
281 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
282 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
283 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
284 COH901318_CX_CTRL_TCP_DISABLE | \
285 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
286 COH901318_CX_CTRL_HSP_DISABLE | \
287 COH901318_CX_CTRL_HSS_DISABLE | \
288 COH901318_CX_CTRL_DDMA_LEGACY | \
289 COH901318_CX_CTRL_PRDD_SOURCE)
290#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
291 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
292 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
293 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
294 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
295 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
296 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
297 COH901318_CX_CTRL_TCP_DISABLE | \
298 COH901318_CX_CTRL_TC_IRQ_ENABLE | \
299 COH901318_CX_CTRL_HSP_DISABLE | \
300 COH901318_CX_CTRL_HSS_DISABLE | \
301 COH901318_CX_CTRL_DDMA_LEGACY | \
302 COH901318_CX_CTRL_PRDD_SOURCE)
303
304const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
305 {
306 .number = U300_DMA_MSL_TX_0,
307 .name = "MSL TX 0",
308 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]309 },
310 {
311 .number = U300_DMA_MSL_TX_1,
312 .name = "MSL TX 1",
313 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]314 .param.config = COH901318_CX_CFG_CH_DISABLE |
315 COH901318_CX_CFG_LCR_DISABLE |
316 COH901318_CX_CFG_TC_IRQ_ENABLE |
317 COH901318_CX_CFG_BE_IRQ_ENABLE,
318 .param.ctrl_lli_chained = 0 |
319 COH901318_CX_CTRL_TC_ENABLE |
320 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
321 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
322 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
323 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
324 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
325 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
326 COH901318_CX_CTRL_TCP_DISABLE |
327 COH901318_CX_CTRL_TC_IRQ_DISABLE |
328 COH901318_CX_CTRL_HSP_ENABLE |
329 COH901318_CX_CTRL_HSS_DISABLE |
330 COH901318_CX_CTRL_DDMA_LEGACY |
331 COH901318_CX_CTRL_PRDD_SOURCE,
332 .param.ctrl_lli = 0 |
333 COH901318_CX_CTRL_TC_ENABLE |
334 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
335 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
336 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
337 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
338 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
339 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
340 COH901318_CX_CTRL_TCP_ENABLE |
341 COH901318_CX_CTRL_TC_IRQ_DISABLE |
342 COH901318_CX_CTRL_HSP_ENABLE |
343 COH901318_CX_CTRL_HSS_DISABLE |
344 COH901318_CX_CTRL_DDMA_LEGACY |
345 COH901318_CX_CTRL_PRDD_SOURCE,
346 .param.ctrl_lli_last = 0 |
347 COH901318_CX_CTRL_TC_ENABLE |
348 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
349 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
350 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
351 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
352 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
353 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
354 COH901318_CX_CTRL_TCP_ENABLE |
355 COH901318_CX_CTRL_TC_IRQ_ENABLE |
356 COH901318_CX_CTRL_HSP_ENABLE |
357 COH901318_CX_CTRL_HSS_DISABLE |
358 COH901318_CX_CTRL_DDMA_LEGACY |
359 COH901318_CX_CTRL_PRDD_SOURCE,
360 },
361 {
362 .number = U300_DMA_MSL_TX_2,
363 .name = "MSL TX 2",
364 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]365 .param.config = COH901318_CX_CFG_CH_DISABLE |
366 COH901318_CX_CFG_LCR_DISABLE |
367 COH901318_CX_CFG_TC_IRQ_ENABLE |
368 COH901318_CX_CFG_BE_IRQ_ENABLE,
369 .param.ctrl_lli_chained = 0 |
370 COH901318_CX_CTRL_TC_ENABLE |
371 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
372 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
373 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
374 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
375 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
376 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
377 COH901318_CX_CTRL_TCP_DISABLE |
378 COH901318_CX_CTRL_TC_IRQ_DISABLE |
379 COH901318_CX_CTRL_HSP_ENABLE |
380 COH901318_CX_CTRL_HSS_DISABLE |
381 COH901318_CX_CTRL_DDMA_LEGACY |
382 COH901318_CX_CTRL_PRDD_SOURCE,
383 .param.ctrl_lli = 0 |
384 COH901318_CX_CTRL_TC_ENABLE |
385 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
386 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
387 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
388 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
389 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
390 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
391 COH901318_CX_CTRL_TCP_ENABLE |
392 COH901318_CX_CTRL_TC_IRQ_DISABLE |
393 COH901318_CX_CTRL_HSP_ENABLE |
394 COH901318_CX_CTRL_HSS_DISABLE |
395 COH901318_CX_CTRL_DDMA_LEGACY |
396 COH901318_CX_CTRL_PRDD_SOURCE,
397 .param.ctrl_lli_last = 0 |
398 COH901318_CX_CTRL_TC_ENABLE |
399 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
400 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
401 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
402 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
403 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
404 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
405 COH901318_CX_CTRL_TCP_ENABLE |
406 COH901318_CX_CTRL_TC_IRQ_ENABLE |
407 COH901318_CX_CTRL_HSP_ENABLE |
408 COH901318_CX_CTRL_HSS_DISABLE |
409 COH901318_CX_CTRL_DDMA_LEGACY |
410 COH901318_CX_CTRL_PRDD_SOURCE,
411 .desc_nbr_max = 10,
412 },
413 {
414 .number = U300_DMA_MSL_TX_3,
415 .name = "MSL TX 3",
416 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]417 .param.config = COH901318_CX_CFG_CH_DISABLE |
418 COH901318_CX_CFG_LCR_DISABLE |
419 COH901318_CX_CFG_TC_IRQ_ENABLE |
420 COH901318_CX_CFG_BE_IRQ_ENABLE,
421 .param.ctrl_lli_chained = 0 |
422 COH901318_CX_CTRL_TC_ENABLE |
423 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
424 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
425 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
426 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
427 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
428 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
429 COH901318_CX_CTRL_TCP_DISABLE |
430 COH901318_CX_CTRL_TC_IRQ_DISABLE |
431 COH901318_CX_CTRL_HSP_ENABLE |
432 COH901318_CX_CTRL_HSS_DISABLE |
433 COH901318_CX_CTRL_DDMA_LEGACY |
434 COH901318_CX_CTRL_PRDD_SOURCE,
435 .param.ctrl_lli = 0 |
436 COH901318_CX_CTRL_TC_ENABLE |
437 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
438 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
439 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
440 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
441 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
442 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
443 COH901318_CX_CTRL_TCP_ENABLE |
444 COH901318_CX_CTRL_TC_IRQ_DISABLE |
445 COH901318_CX_CTRL_HSP_ENABLE |
446 COH901318_CX_CTRL_HSS_DISABLE |
447 COH901318_CX_CTRL_DDMA_LEGACY |
448 COH901318_CX_CTRL_PRDD_SOURCE,
449 .param.ctrl_lli_last = 0 |
450 COH901318_CX_CTRL_TC_ENABLE |
451 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
452 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
453 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
454 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
455 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
456 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
457 COH901318_CX_CTRL_TCP_ENABLE |
458 COH901318_CX_CTRL_TC_IRQ_ENABLE |
459 COH901318_CX_CTRL_HSP_ENABLE |
460 COH901318_CX_CTRL_HSS_DISABLE |
461 COH901318_CX_CTRL_DDMA_LEGACY |
462 COH901318_CX_CTRL_PRDD_SOURCE,
463 },
464 {
465 .number = U300_DMA_MSL_TX_4,
466 .name = "MSL TX 4",
467 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]468 .param.config = COH901318_CX_CFG_CH_DISABLE |
469 COH901318_CX_CFG_LCR_DISABLE |
470 COH901318_CX_CFG_TC_IRQ_ENABLE |
471 COH901318_CX_CFG_BE_IRQ_ENABLE,
472 .param.ctrl_lli_chained = 0 |
473 COH901318_CX_CTRL_TC_ENABLE |
474 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
475 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
476 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
477 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
478 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
479 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
480 COH901318_CX_CTRL_TCP_DISABLE |
481 COH901318_CX_CTRL_TC_IRQ_DISABLE |
482 COH901318_CX_CTRL_HSP_ENABLE |
483 COH901318_CX_CTRL_HSS_DISABLE |
484 COH901318_CX_CTRL_DDMA_LEGACY |
485 COH901318_CX_CTRL_PRDD_SOURCE,
486 .param.ctrl_lli = 0 |
487 COH901318_CX_CTRL_TC_ENABLE |
488 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
489 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
490 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
491 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
492 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
493 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
494 COH901318_CX_CTRL_TCP_ENABLE |
495 COH901318_CX_CTRL_TC_IRQ_DISABLE |
496 COH901318_CX_CTRL_HSP_ENABLE |
497 COH901318_CX_CTRL_HSS_DISABLE |
498 COH901318_CX_CTRL_DDMA_LEGACY |
499 COH901318_CX_CTRL_PRDD_SOURCE,
500 .param.ctrl_lli_last = 0 |
501 COH901318_CX_CTRL_TC_ENABLE |
502 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
503 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
504 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
505 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
506 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
507 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
508 COH901318_CX_CTRL_TCP_ENABLE |
509 COH901318_CX_CTRL_TC_IRQ_ENABLE |
510 COH901318_CX_CTRL_HSP_ENABLE |
511 COH901318_CX_CTRL_HSS_DISABLE |
512 COH901318_CX_CTRL_DDMA_LEGACY |
513 COH901318_CX_CTRL_PRDD_SOURCE,
514 },
515 {
516 .number = U300_DMA_MSL_TX_5,
517 .name = "MSL TX 5",
518 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]519 },
520 {
521 .number = U300_DMA_MSL_TX_6,
522 .name = "MSL TX 6",
523 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]524 },
525 {
526 .number = U300_DMA_MSL_RX_0,
527 .name = "MSL RX 0",
528 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]529 },
530 {
531 .number = U300_DMA_MSL_RX_1,
532 .name = "MSL RX 1",
533 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]534 .param.config = COH901318_CX_CFG_CH_DISABLE |
535 COH901318_CX_CFG_LCR_DISABLE |
536 COH901318_CX_CFG_TC_IRQ_ENABLE |
537 COH901318_CX_CFG_BE_IRQ_ENABLE,
538 .param.ctrl_lli_chained = 0 |
539 COH901318_CX_CTRL_TC_ENABLE |
540 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
541 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
542 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
543 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
544 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
545 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
546 COH901318_CX_CTRL_TCP_DISABLE |
547 COH901318_CX_CTRL_TC_IRQ_DISABLE |
548 COH901318_CX_CTRL_HSP_ENABLE |
549 COH901318_CX_CTRL_HSS_DISABLE |
550 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
551 COH901318_CX_CTRL_PRDD_DEST,
552 .param.ctrl_lli = 0,
553 .param.ctrl_lli_last = 0 |
554 COH901318_CX_CTRL_TC_ENABLE |
555 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
556 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
557 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
558 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
559 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
560 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
561 COH901318_CX_CTRL_TCP_DISABLE |
562 COH901318_CX_CTRL_TC_IRQ_ENABLE |
563 COH901318_CX_CTRL_HSP_ENABLE |
564 COH901318_CX_CTRL_HSS_DISABLE |
565 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
566 COH901318_CX_CTRL_PRDD_DEST,
567 },
568 {
569 .number = U300_DMA_MSL_RX_2,
570 .name = "MSL RX 2",
571 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]572 .param.config = COH901318_CX_CFG_CH_DISABLE |
573 COH901318_CX_CFG_LCR_DISABLE |
574 COH901318_CX_CFG_TC_IRQ_ENABLE |
575 COH901318_CX_CFG_BE_IRQ_ENABLE,
576 .param.ctrl_lli_chained = 0 |
577 COH901318_CX_CTRL_TC_ENABLE |
578 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
579 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
580 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
581 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
582 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
583 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
584 COH901318_CX_CTRL_TCP_DISABLE |
585 COH901318_CX_CTRL_TC_IRQ_DISABLE |
586 COH901318_CX_CTRL_HSP_ENABLE |
587 COH901318_CX_CTRL_HSS_DISABLE |
588 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
589 COH901318_CX_CTRL_PRDD_DEST,
590 .param.ctrl_lli = 0 |
591 COH901318_CX_CTRL_TC_ENABLE |
592 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
593 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
594 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
595 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
596 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
597 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
598 COH901318_CX_CTRL_TCP_DISABLE |
599 COH901318_CX_CTRL_TC_IRQ_ENABLE |
600 COH901318_CX_CTRL_HSP_ENABLE |
601 COH901318_CX_CTRL_HSS_DISABLE |
602 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
603 COH901318_CX_CTRL_PRDD_DEST,
604 .param.ctrl_lli_last = 0 |
605 COH901318_CX_CTRL_TC_ENABLE |
606 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
607 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
608 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
609 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
610 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
611 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
612 COH901318_CX_CTRL_TCP_DISABLE |
613 COH901318_CX_CTRL_TC_IRQ_ENABLE |
614 COH901318_CX_CTRL_HSP_ENABLE |
615 COH901318_CX_CTRL_HSS_DISABLE |
616 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
617 COH901318_CX_CTRL_PRDD_DEST,
618 },
619 {
620 .number = U300_DMA_MSL_RX_3,
621 .name = "MSL RX 3",
622 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]623 .param.config = COH901318_CX_CFG_CH_DISABLE |
624 COH901318_CX_CFG_LCR_DISABLE |
625 COH901318_CX_CFG_TC_IRQ_ENABLE |
626 COH901318_CX_CFG_BE_IRQ_ENABLE,
627 .param.ctrl_lli_chained = 0 |
628 COH901318_CX_CTRL_TC_ENABLE |
629 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
630 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
631 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
632 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
633 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
634 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
635 COH901318_CX_CTRL_TCP_DISABLE |
636 COH901318_CX_CTRL_TC_IRQ_DISABLE |
637 COH901318_CX_CTRL_HSP_ENABLE |
638 COH901318_CX_CTRL_HSS_DISABLE |
639 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
640 COH901318_CX_CTRL_PRDD_DEST,
641 .param.ctrl_lli = 0 |
642 COH901318_CX_CTRL_TC_ENABLE |
643 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
644 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
645 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
646 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
647 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
648 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
649 COH901318_CX_CTRL_TCP_DISABLE |
650 COH901318_CX_CTRL_TC_IRQ_ENABLE |
651 COH901318_CX_CTRL_HSP_ENABLE |
652 COH901318_CX_CTRL_HSS_DISABLE |
653 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
654 COH901318_CX_CTRL_PRDD_DEST,
655 .param.ctrl_lli_last = 0 |
656 COH901318_CX_CTRL_TC_ENABLE |
657 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
658 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
659 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
660 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
661 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
662 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
663 COH901318_CX_CTRL_TCP_DISABLE |
664 COH901318_CX_CTRL_TC_IRQ_ENABLE |
665 COH901318_CX_CTRL_HSP_ENABLE |
666 COH901318_CX_CTRL_HSS_DISABLE |
667 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
668 COH901318_CX_CTRL_PRDD_DEST,
669 },
670 {
671 .number = U300_DMA_MSL_RX_4,
672 .name = "MSL RX 4",
673 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]674 .param.config = COH901318_CX_CFG_CH_DISABLE |
675 COH901318_CX_CFG_LCR_DISABLE |
676 COH901318_CX_CFG_TC_IRQ_ENABLE |
677 COH901318_CX_CFG_BE_IRQ_ENABLE,
678 .param.ctrl_lli_chained = 0 |
679 COH901318_CX_CTRL_TC_ENABLE |
680 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
681 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
682 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
683 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
684 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
685 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
686 COH901318_CX_CTRL_TCP_DISABLE |
687 COH901318_CX_CTRL_TC_IRQ_DISABLE |
688 COH901318_CX_CTRL_HSP_ENABLE |
689 COH901318_CX_CTRL_HSS_DISABLE |
690 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
691 COH901318_CX_CTRL_PRDD_DEST,
692 .param.ctrl_lli = 0 |
693 COH901318_CX_CTRL_TC_ENABLE |
694 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
695 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
696 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
697 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
698 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
699 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
700 COH901318_CX_CTRL_TCP_DISABLE |
701 COH901318_CX_CTRL_TC_IRQ_ENABLE |
702 COH901318_CX_CTRL_HSP_ENABLE |
703 COH901318_CX_CTRL_HSS_DISABLE |
704 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
705 COH901318_CX_CTRL_PRDD_DEST,
706 .param.ctrl_lli_last = 0 |
707 COH901318_CX_CTRL_TC_ENABLE |
708 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
709 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
710 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
711 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
712 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
713 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
714 COH901318_CX_CTRL_TCP_DISABLE |
715 COH901318_CX_CTRL_TC_IRQ_ENABLE |
716 COH901318_CX_CTRL_HSP_ENABLE |
717 COH901318_CX_CTRL_HSS_DISABLE |
718 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
719 COH901318_CX_CTRL_PRDD_DEST,
720 },
721 {
722 .number = U300_DMA_MSL_RX_5,
723 .name = "MSL RX 5",
724 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]725 .param.config = COH901318_CX_CFG_CH_DISABLE |
726 COH901318_CX_CFG_LCR_DISABLE |
727 COH901318_CX_CFG_TC_IRQ_ENABLE |
728 COH901318_CX_CFG_BE_IRQ_ENABLE,
729 .param.ctrl_lli_chained = 0 |
730 COH901318_CX_CTRL_TC_ENABLE |
731 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
732 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
733 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
734 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
735 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
736 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
737 COH901318_CX_CTRL_TCP_DISABLE |
738 COH901318_CX_CTRL_TC_IRQ_DISABLE |
739 COH901318_CX_CTRL_HSP_ENABLE |
740 COH901318_CX_CTRL_HSS_DISABLE |
741 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
742 COH901318_CX_CTRL_PRDD_DEST,
743 .param.ctrl_lli = 0 |
744 COH901318_CX_CTRL_TC_ENABLE |
745 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
746 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
747 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
748 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
749 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
750 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
751 COH901318_CX_CTRL_TCP_DISABLE |
752 COH901318_CX_CTRL_TC_IRQ_ENABLE |
753 COH901318_CX_CTRL_HSP_ENABLE |
754 COH901318_CX_CTRL_HSS_DISABLE |
755 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
756 COH901318_CX_CTRL_PRDD_DEST,
757 .param.ctrl_lli_last = 0 |
758 COH901318_CX_CTRL_TC_ENABLE |
759 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
760 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
761 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
762 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
763 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
764 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
765 COH901318_CX_CTRL_TCP_DISABLE |
766 COH901318_CX_CTRL_TC_IRQ_ENABLE |
767 COH901318_CX_CTRL_HSP_ENABLE |
768 COH901318_CX_CTRL_HSS_DISABLE |
769 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
770 COH901318_CX_CTRL_PRDD_DEST,
771 },
772 {
773 .number = U300_DMA_MSL_RX_6,
774 .name = "MSL RX 6",
775 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]776 },
777 /*
778 * Don't set up device address, burst count or size of src
779 * or dst bus for this peripheral - handled by PrimeCell
780 * DMA extension.
781 */
782 {
783 .number = U300_DMA_MMCSD_RX_TX,
784 .name = "MMCSD RX TX",
785 .priority_high = 0,
786 .param.config = COH901318_CX_CFG_CH_DISABLE |
787 COH901318_CX_CFG_LCR_DISABLE |
788 COH901318_CX_CFG_TC_IRQ_ENABLE |
789 COH901318_CX_CFG_BE_IRQ_ENABLE,
790 .param.ctrl_lli_chained = 0 |
791 COH901318_CX_CTRL_TC_ENABLE |
792 COH901318_CX_CTRL_MASTER_MODE_M1RW |
793 COH901318_CX_CTRL_TCP_ENABLE |
794 COH901318_CX_CTRL_TC_IRQ_DISABLE |
795 COH901318_CX_CTRL_HSP_ENABLE |
796 COH901318_CX_CTRL_HSS_DISABLE |
797 COH901318_CX_CTRL_DDMA_LEGACY,
798 .param.ctrl_lli = 0 |
799 COH901318_CX_CTRL_TC_ENABLE |
800 COH901318_CX_CTRL_MASTER_MODE_M1RW |
801 COH901318_CX_CTRL_TCP_ENABLE |
802 COH901318_CX_CTRL_TC_IRQ_DISABLE |
803 COH901318_CX_CTRL_HSP_ENABLE |
804 COH901318_CX_CTRL_HSS_DISABLE |
805 COH901318_CX_CTRL_DDMA_LEGACY,
806 .param.ctrl_lli_last = 0 |
807 COH901318_CX_CTRL_TC_ENABLE |
808 COH901318_CX_CTRL_MASTER_MODE_M1RW |
809 COH901318_CX_CTRL_TCP_DISABLE |
810 COH901318_CX_CTRL_TC_IRQ_ENABLE |
811 COH901318_CX_CTRL_HSP_ENABLE |
812 COH901318_CX_CTRL_HSS_DISABLE |
813 COH901318_CX_CTRL_DDMA_LEGACY,
814
815 },
816 {
817 .number = U300_DMA_MSPRO_TX,
818 .name = "MSPRO TX",
819 .priority_high = 0,
820 },
821 {
822 .number = U300_DMA_MSPRO_RX,
823 .name = "MSPRO RX",
824 .priority_high = 0,
825 },
826 /*
827 * Don't set up device address, burst count or size of src
828 * or dst bus for this peripheral - handled by PrimeCell
829 * DMA extension.
830 */
831 {
832 .number = U300_DMA_UART0_TX,
833 .name = "UART0 TX",
834 .priority_high = 0,
835 .param.config = COH901318_CX_CFG_CH_DISABLE |
836 COH901318_CX_CFG_LCR_DISABLE |
837 COH901318_CX_CFG_TC_IRQ_ENABLE |
838 COH901318_CX_CFG_BE_IRQ_ENABLE,
839 .param.ctrl_lli_chained = 0 |
840 COH901318_CX_CTRL_TC_ENABLE |
841 COH901318_CX_CTRL_MASTER_MODE_M1RW |
842 COH901318_CX_CTRL_TCP_ENABLE |
843 COH901318_CX_CTRL_TC_IRQ_DISABLE |
844 COH901318_CX_CTRL_HSP_ENABLE |
845 COH901318_CX_CTRL_HSS_DISABLE |
846 COH901318_CX_CTRL_DDMA_LEGACY,
847 .param.ctrl_lli = 0 |
848 COH901318_CX_CTRL_TC_ENABLE |
849 COH901318_CX_CTRL_MASTER_MODE_M1RW |
850 COH901318_CX_CTRL_TCP_ENABLE |
851 COH901318_CX_CTRL_TC_IRQ_ENABLE |
852 COH901318_CX_CTRL_HSP_ENABLE |
853 COH901318_CX_CTRL_HSS_DISABLE |
854 COH901318_CX_CTRL_DDMA_LEGACY,
855 .param.ctrl_lli_last = 0 |
856 COH901318_CX_CTRL_TC_ENABLE |
857 COH901318_CX_CTRL_MASTER_MODE_M1RW |
858 COH901318_CX_CTRL_TCP_ENABLE |
859 COH901318_CX_CTRL_TC_IRQ_ENABLE |
860 COH901318_CX_CTRL_HSP_ENABLE |
861 COH901318_CX_CTRL_HSS_DISABLE |
862 COH901318_CX_CTRL_DDMA_LEGACY,
863 },
864 {
865 .number = U300_DMA_UART0_RX,
866 .name = "UART0 RX",
867 .priority_high = 0,
868 .param.config = COH901318_CX_CFG_CH_DISABLE |
869 COH901318_CX_CFG_LCR_DISABLE |
870 COH901318_CX_CFG_TC_IRQ_ENABLE |
871 COH901318_CX_CFG_BE_IRQ_ENABLE,
872 .param.ctrl_lli_chained = 0 |
873 COH901318_CX_CTRL_TC_ENABLE |
874 COH901318_CX_CTRL_MASTER_MODE_M1RW |
875 COH901318_CX_CTRL_TCP_ENABLE |
876 COH901318_CX_CTRL_TC_IRQ_DISABLE |
877 COH901318_CX_CTRL_HSP_ENABLE |
878 COH901318_CX_CTRL_HSS_DISABLE |
879 COH901318_CX_CTRL_DDMA_LEGACY,
880 .param.ctrl_lli = 0 |
881 COH901318_CX_CTRL_TC_ENABLE |
882 COH901318_CX_CTRL_MASTER_MODE_M1RW |
883 COH901318_CX_CTRL_TCP_ENABLE |
884 COH901318_CX_CTRL_TC_IRQ_ENABLE |
885 COH901318_CX_CTRL_HSP_ENABLE |
886 COH901318_CX_CTRL_HSS_DISABLE |
887 COH901318_CX_CTRL_DDMA_LEGACY,
888 .param.ctrl_lli_last = 0 |
889 COH901318_CX_CTRL_TC_ENABLE |
890 COH901318_CX_CTRL_MASTER_MODE_M1RW |
891 COH901318_CX_CTRL_TCP_ENABLE |
892 COH901318_CX_CTRL_TC_IRQ_ENABLE |
893 COH901318_CX_CTRL_HSP_ENABLE |
894 COH901318_CX_CTRL_HSS_DISABLE |
895 COH901318_CX_CTRL_DDMA_LEGACY,
896 },
897 {
898 .number = U300_DMA_APEX_TX,
899 .name = "APEX TX",
900 .priority_high = 0,
901 },
902 {
903 .number = U300_DMA_APEX_RX,
904 .name = "APEX RX",
905 .priority_high = 0,
906 },
907 {
908 .number = U300_DMA_PCM_I2S0_TX,
909 .name = "PCM I2S0 TX",
910 .priority_high = 1,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]911 .param.config = COH901318_CX_CFG_CH_DISABLE |
912 COH901318_CX_CFG_LCR_DISABLE |
913 COH901318_CX_CFG_TC_IRQ_ENABLE |
914 COH901318_CX_CFG_BE_IRQ_ENABLE,
915 .param.ctrl_lli_chained = 0 |
916 COH901318_CX_CTRL_TC_ENABLE |
917 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
918 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
919 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
920 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
921 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
922 COH901318_CX_CTRL_MASTER_MODE_M1RW |
923 COH901318_CX_CTRL_TCP_DISABLE |
924 COH901318_CX_CTRL_TC_IRQ_DISABLE |
925 COH901318_CX_CTRL_HSP_ENABLE |
926 COH901318_CX_CTRL_HSS_DISABLE |
927 COH901318_CX_CTRL_DDMA_LEGACY |
928 COH901318_CX_CTRL_PRDD_SOURCE,
929 .param.ctrl_lli = 0 |
930 COH901318_CX_CTRL_TC_ENABLE |
931 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
932 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
933 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
934 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
935 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
936 COH901318_CX_CTRL_MASTER_MODE_M1RW |
937 COH901318_CX_CTRL_TCP_ENABLE |
938 COH901318_CX_CTRL_TC_IRQ_DISABLE |
939 COH901318_CX_CTRL_HSP_ENABLE |
940 COH901318_CX_CTRL_HSS_DISABLE |
941 COH901318_CX_CTRL_DDMA_LEGACY |
942 COH901318_CX_CTRL_PRDD_SOURCE,
943 .param.ctrl_lli_last = 0 |
944 COH901318_CX_CTRL_TC_ENABLE |
945 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
946 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
947 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
948 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
949 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
950 COH901318_CX_CTRL_MASTER_MODE_M1RW |
951 COH901318_CX_CTRL_TCP_ENABLE |
952 COH901318_CX_CTRL_TC_IRQ_DISABLE |
953 COH901318_CX_CTRL_HSP_ENABLE |
954 COH901318_CX_CTRL_HSS_DISABLE |
955 COH901318_CX_CTRL_DDMA_LEGACY |
956 COH901318_CX_CTRL_PRDD_SOURCE,
957 },
958 {
959 .number = U300_DMA_PCM_I2S0_RX,
960 .name = "PCM I2S0 RX",
961 .priority_high = 1,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]962 .param.config = COH901318_CX_CFG_CH_DISABLE |
963 COH901318_CX_CFG_LCR_DISABLE |
964 COH901318_CX_CFG_TC_IRQ_ENABLE |
965 COH901318_CX_CFG_BE_IRQ_ENABLE,
966 .param.ctrl_lli_chained = 0 |
967 COH901318_CX_CTRL_TC_ENABLE |
968 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
969 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
970 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
971 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
972 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
973 COH901318_CX_CTRL_MASTER_MODE_M1RW |
974 COH901318_CX_CTRL_TCP_DISABLE |
975 COH901318_CX_CTRL_TC_IRQ_DISABLE |
976 COH901318_CX_CTRL_HSP_ENABLE |
977 COH901318_CX_CTRL_HSS_DISABLE |
978 COH901318_CX_CTRL_DDMA_LEGACY |
979 COH901318_CX_CTRL_PRDD_DEST,
980 .param.ctrl_lli = 0 |
981 COH901318_CX_CTRL_TC_ENABLE |
982 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
983 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
984 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
985 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
986 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
987 COH901318_CX_CTRL_MASTER_MODE_M1RW |
988 COH901318_CX_CTRL_TCP_ENABLE |
989 COH901318_CX_CTRL_TC_IRQ_DISABLE |
990 COH901318_CX_CTRL_HSP_ENABLE |
991 COH901318_CX_CTRL_HSS_DISABLE |
992 COH901318_CX_CTRL_DDMA_LEGACY |
993 COH901318_CX_CTRL_PRDD_DEST,
994 .param.ctrl_lli_last = 0 |
995 COH901318_CX_CTRL_TC_ENABLE |
996 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
997 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
998 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
999 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1000 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1001 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1002 COH901318_CX_CTRL_TCP_ENABLE |
1003 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1004 COH901318_CX_CTRL_HSP_ENABLE |
1005 COH901318_CX_CTRL_HSS_DISABLE |
1006 COH901318_CX_CTRL_DDMA_LEGACY |
1007 COH901318_CX_CTRL_PRDD_DEST,
1008 },
1009 {
1010 .number = U300_DMA_PCM_I2S1_TX,
1011 .name = "PCM I2S1 TX",
1012 .priority_high = 1,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]1013 .param.config = COH901318_CX_CFG_CH_DISABLE |
1014 COH901318_CX_CFG_LCR_DISABLE |
1015 COH901318_CX_CFG_TC_IRQ_ENABLE |
1016 COH901318_CX_CFG_BE_IRQ_ENABLE,
1017 .param.ctrl_lli_chained = 0 |
1018 COH901318_CX_CTRL_TC_ENABLE |
1019 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1020 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1021 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1022 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1023 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1024 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1025 COH901318_CX_CTRL_TCP_DISABLE |
1026 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1027 COH901318_CX_CTRL_HSP_ENABLE |
1028 COH901318_CX_CTRL_HSS_DISABLE |
1029 COH901318_CX_CTRL_DDMA_LEGACY |
1030 COH901318_CX_CTRL_PRDD_SOURCE,
1031 .param.ctrl_lli = 0 |
1032 COH901318_CX_CTRL_TC_ENABLE |
1033 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1034 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1035 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1036 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1037 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1038 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1039 COH901318_CX_CTRL_TCP_ENABLE |
1040 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1041 COH901318_CX_CTRL_HSP_ENABLE |
1042 COH901318_CX_CTRL_HSS_DISABLE |
1043 COH901318_CX_CTRL_DDMA_LEGACY |
1044 COH901318_CX_CTRL_PRDD_SOURCE,
1045 .param.ctrl_lli_last = 0 |
1046 COH901318_CX_CTRL_TC_ENABLE |
1047 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1048 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1049 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1050 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1051 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1052 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1053 COH901318_CX_CTRL_TCP_ENABLE |
1054 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1055 COH901318_CX_CTRL_HSP_ENABLE |
1056 COH901318_CX_CTRL_HSS_DISABLE |
1057 COH901318_CX_CTRL_DDMA_LEGACY |
1058 COH901318_CX_CTRL_PRDD_SOURCE,
1059 },
1060 {
1061 .number = U300_DMA_PCM_I2S1_RX,
1062 .name = "PCM I2S1 RX",
1063 .priority_high = 1,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]1064 .param.config = COH901318_CX_CFG_CH_DISABLE |
1065 COH901318_CX_CFG_LCR_DISABLE |
1066 COH901318_CX_CFG_TC_IRQ_ENABLE |
1067 COH901318_CX_CFG_BE_IRQ_ENABLE,
1068 .param.ctrl_lli_chained = 0 |
1069 COH901318_CX_CTRL_TC_ENABLE |
1070 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1071 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1072 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1073 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1074 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1075 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1076 COH901318_CX_CTRL_TCP_DISABLE |
1077 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1078 COH901318_CX_CTRL_HSP_ENABLE |
1079 COH901318_CX_CTRL_HSS_DISABLE |
1080 COH901318_CX_CTRL_DDMA_LEGACY |
1081 COH901318_CX_CTRL_PRDD_DEST,
1082 .param.ctrl_lli = 0 |
1083 COH901318_CX_CTRL_TC_ENABLE |
1084 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1085 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1086 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1087 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1088 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1089 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1090 COH901318_CX_CTRL_TCP_ENABLE |
1091 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1092 COH901318_CX_CTRL_HSP_ENABLE |
1093 COH901318_CX_CTRL_HSS_DISABLE |
1094 COH901318_CX_CTRL_DDMA_LEGACY |
1095 COH901318_CX_CTRL_PRDD_DEST,
1096 .param.ctrl_lli_last = 0 |
1097 COH901318_CX_CTRL_TC_ENABLE |
1098 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1099 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1100 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1101 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1102 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1103 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1104 COH901318_CX_CTRL_TCP_ENABLE |
1105 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1106 COH901318_CX_CTRL_HSP_ENABLE |
1107 COH901318_CX_CTRL_HSS_DISABLE |
1108 COH901318_CX_CTRL_DDMA_LEGACY |
1109 COH901318_CX_CTRL_PRDD_DEST,
1110 },
1111 {
1112 .number = U300_DMA_XGAM_CDI,
1113 .name = "XGAM CDI",
1114 .priority_high = 0,
1115 },
1116 {
1117 .number = U300_DMA_XGAM_PDI,
1118 .name = "XGAM PDI",
1119 .priority_high = 0,
1120 },
1121 /*
1122 * Don't set up device address, burst count or size of src
1123 * or dst bus for this peripheral - handled by PrimeCell
1124 * DMA extension.
1125 */
1126 {
1127 .number = U300_DMA_SPI_TX,
1128 .name = "SPI TX",
1129 .priority_high = 0,
1130 .param.config = COH901318_CX_CFG_CH_DISABLE |
1131 COH901318_CX_CFG_LCR_DISABLE |
1132 COH901318_CX_CFG_TC_IRQ_ENABLE |
1133 COH901318_CX_CFG_BE_IRQ_ENABLE,
1134 .param.ctrl_lli_chained = 0 |
1135 COH901318_CX_CTRL_TC_ENABLE |
1136 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1137 COH901318_CX_CTRL_TCP_DISABLE |
1138 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1139 COH901318_CX_CTRL_HSP_ENABLE |
1140 COH901318_CX_CTRL_HSS_DISABLE |
1141 COH901318_CX_CTRL_DDMA_LEGACY,
1142 .param.ctrl_lli = 0 |
1143 COH901318_CX_CTRL_TC_ENABLE |
1144 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1145 COH901318_CX_CTRL_TCP_DISABLE |
1146 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1147 COH901318_CX_CTRL_HSP_ENABLE |
1148 COH901318_CX_CTRL_HSS_DISABLE |
1149 COH901318_CX_CTRL_DDMA_LEGACY,
1150 .param.ctrl_lli_last = 0 |
1151 COH901318_CX_CTRL_TC_ENABLE |
1152 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1153 COH901318_CX_CTRL_TCP_DISABLE |
1154 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1155 COH901318_CX_CTRL_HSP_ENABLE |
1156 COH901318_CX_CTRL_HSS_DISABLE |
1157 COH901318_CX_CTRL_DDMA_LEGACY,
1158 },
1159 {
1160 .number = U300_DMA_SPI_RX,
1161 .name = "SPI RX",
1162 .priority_high = 0,
1163 .param.config = COH901318_CX_CFG_CH_DISABLE |
1164 COH901318_CX_CFG_LCR_DISABLE |
1165 COH901318_CX_CFG_TC_IRQ_ENABLE |
1166 COH901318_CX_CFG_BE_IRQ_ENABLE,
1167 .param.ctrl_lli_chained = 0 |
1168 COH901318_CX_CTRL_TC_ENABLE |
1169 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1170 COH901318_CX_CTRL_TCP_DISABLE |
1171 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1172 COH901318_CX_CTRL_HSP_ENABLE |
1173 COH901318_CX_CTRL_HSS_DISABLE |
1174 COH901318_CX_CTRL_DDMA_LEGACY,
1175 .param.ctrl_lli = 0 |
1176 COH901318_CX_CTRL_TC_ENABLE |
1177 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1178 COH901318_CX_CTRL_TCP_DISABLE |
1179 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1180 COH901318_CX_CTRL_HSP_ENABLE |
1181 COH901318_CX_CTRL_HSS_DISABLE |
1182 COH901318_CX_CTRL_DDMA_LEGACY,
1183 .param.ctrl_lli_last = 0 |
1184 COH901318_CX_CTRL_TC_ENABLE |
1185 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1186 COH901318_CX_CTRL_TCP_DISABLE |
1187 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1188 COH901318_CX_CTRL_HSP_ENABLE |
1189 COH901318_CX_CTRL_HSS_DISABLE |
1190 COH901318_CX_CTRL_DDMA_LEGACY,
1191
1192 },
1193 {
1194 .number = U300_DMA_GENERAL_PURPOSE_0,
1195 .name = "GENERAL 00",
1196 .priority_high = 0,
1197
1198 .param.config = flags_memcpy_config,
1199 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1200 .param.ctrl_lli = flags_memcpy_lli,
1201 .param.ctrl_lli_last = flags_memcpy_lli_last,
1202 },
1203 {
1204 .number = U300_DMA_GENERAL_PURPOSE_1,
1205 .name = "GENERAL 01",
1206 .priority_high = 0,
1207
1208 .param.config = flags_memcpy_config,
1209 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1210 .param.ctrl_lli = flags_memcpy_lli,
1211 .param.ctrl_lli_last = flags_memcpy_lli_last,
1212 },
1213 {
1214 .number = U300_DMA_GENERAL_PURPOSE_2,
1215 .name = "GENERAL 02",
1216 .priority_high = 0,
1217
1218 .param.config = flags_memcpy_config,
1219 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1220 .param.ctrl_lli = flags_memcpy_lli,
1221 .param.ctrl_lli_last = flags_memcpy_lli_last,
1222 },
1223 {
1224 .number = U300_DMA_GENERAL_PURPOSE_3,
1225 .name = "GENERAL 03",
1226 .priority_high = 0,
1227
1228 .param.config = flags_memcpy_config,
1229 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1230 .param.ctrl_lli = flags_memcpy_lli,
1231 .param.ctrl_lli_last = flags_memcpy_lli_last,
1232 },
1233 {
1234 .number = U300_DMA_GENERAL_PURPOSE_4,
1235 .name = "GENERAL 04",
1236 .priority_high = 0,
1237
1238 .param.config = flags_memcpy_config,
1239 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1240 .param.ctrl_lli = flags_memcpy_lli,
1241 .param.ctrl_lli_last = flags_memcpy_lli_last,
1242 },
1243 {
1244 .number = U300_DMA_GENERAL_PURPOSE_5,
1245 .name = "GENERAL 05",
1246 .priority_high = 0,
1247
1248 .param.config = flags_memcpy_config,
1249 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1250 .param.ctrl_lli = flags_memcpy_lli,
1251 .param.ctrl_lli_last = flags_memcpy_lli_last,
1252 },
1253 {
1254 .number = U300_DMA_GENERAL_PURPOSE_6,
1255 .name = "GENERAL 06",
1256 .priority_high = 0,
1257
1258 .param.config = flags_memcpy_config,
1259 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1260 .param.ctrl_lli = flags_memcpy_lli,
1261 .param.ctrl_lli_last = flags_memcpy_lli_last,
1262 },
1263 {
1264 .number = U300_DMA_GENERAL_PURPOSE_7,
1265 .name = "GENERAL 07",
1266 .priority_high = 0,
1267
1268 .param.config = flags_memcpy_config,
1269 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1270 .param.ctrl_lli = flags_memcpy_lli,
1271 .param.ctrl_lli_last = flags_memcpy_lli_last,
1272 },
1273 {
1274 .number = U300_DMA_GENERAL_PURPOSE_8,
1275 .name = "GENERAL 08",
1276 .priority_high = 0,
1277
1278 .param.config = flags_memcpy_config,
1279 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1280 .param.ctrl_lli = flags_memcpy_lli,
1281 .param.ctrl_lli_last = flags_memcpy_lli_last,
1282 },
1283 {
1284 .number = U300_DMA_UART1_TX,
1285 .name = "UART1 TX",
1286 .priority_high = 0,
1287 },
1288 {
1289 .number = U300_DMA_UART1_RX,
1290 .name = "UART1 RX",
1291 .priority_high = 0,
1292 }
1293};
1294
1295static struct coh901318_platform coh901318_platform = {
1296 .chans_slave = dma_slave_channels,
1297 .chans_memcpy = dma_memcpy_channels,
1298 .access_memory_state = coh901318_access_memory_state,
1299 .chan_conf = chan_config,
1300 .max_channels = U300_DMA_CHANNELS,
1301};
1302
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1303#define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
1304
1305#ifdef VERBOSE_DEBUG
1306#define COH_DBG(x) ({ if (1) x; 0; })
1307#else
1308#define COH_DBG(x) ({ if (0) x; 0; })
1309#endif
1310
1311struct coh901318_desc {
1312 struct dma_async_tx_descriptor desc;
1313 struct list_head node;
1314 struct scatterlist *sg;
1315 unsigned int sg_len;
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1316 struct coh901318_lli *lli;
Vinod Kouldb8196d2011-10-13 22:34:23 +0530[diff] [blame]1317 enum dma_transfer_direction dir;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1318 unsigned long flags;
Linus Walleijb89243d2011-07-01 16:47:28 +0200[diff] [blame]1319 u32 head_config;
1320 u32 head_ctrl;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1321};
1322
1323struct coh901318_base {
1324 struct device *dev;
1325 void __iomem *virtbase;
1326 struct coh901318_pool pool;
1327 struct powersave pm;
1328 struct dma_device dma_slave;
1329 struct dma_device dma_memcpy;
1330 struct coh901318_chan *chans;
1331 struct coh901318_platform *platform;
1332};
1333
1334struct coh901318_chan {
1335 spinlock_t lock;
1336 int allocated;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1337 int id;
1338 int stopped;
1339
1340 struct work_struct free_work;
1341 struct dma_chan chan;
1342
1343 struct tasklet_struct tasklet;
1344
1345 struct list_head active;
1346 struct list_head queue;
1347 struct list_head free;
1348
1349 unsigned long nbr_active_done;
1350 unsigned long busy;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1351
Linus Walleij9aab4d62013-01-04 13:50:49 +0100[diff] [blame]1352 u32 addr;
1353 u32 ctrl;
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]1354
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1355 struct coh901318_base *base;
1356};
1357
1358static void coh901318_list_print(struct coh901318_chan *cohc,
1359 struct coh901318_lli *lli)
1360{
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]1361 struct coh901318_lli *l = lli;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1362 int i = 0;
1363
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]1364 while (l) {
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1365 dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x"
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]1366 ", dst 0x%x, link 0x%x virt_link_addr 0x%p\n",
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1367 i, l, l->control, l->src_addr, l->dst_addr,
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]1368 l->link_addr, l->virt_link_addr);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1369 i++;
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]1370 l = l->virt_link_addr;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1371 }
1372}
1373
1374#ifdef CONFIG_DEBUG_FS
1375
1376#define COH901318_DEBUGFS_ASSIGN(x, y) (x = y)
1377
1378static struct coh901318_base *debugfs_dma_base;
1379static struct dentry *dma_dentry;
1380
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1381static int coh901318_debugfs_read(struct file *file, char __user *buf,
1382 size_t count, loff_t *f_pos)
1383{
1384 u64 started_channels = debugfs_dma_base->pm.started_channels;
1385 int pool_count = debugfs_dma_base->pool.debugfs_pool_counter;
1386 int i;
1387 int ret = 0;
1388 char *dev_buf;
1389 char *tmp;
1390 int dev_size;
1391
1392 dev_buf = kmalloc(4*1024, GFP_KERNEL);
1393 if (dev_buf == NULL)
1394 goto err_kmalloc;
1395 tmp = dev_buf;
1396
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]1397 tmp += sprintf(tmp, "DMA -- enabled dma channels\n");
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1398
1399 for (i = 0; i < debugfs_dma_base->platform->max_channels; i++)
1400 if (started_channels & (1 << i))
1401 tmp += sprintf(tmp, "channel %d\n", i);
1402
1403 tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count);
1404 dev_size = tmp - dev_buf;
1405
1406 /* No more to read if offset != 0 */
1407 if (*f_pos > dev_size)
1408 goto out;
1409
1410 if (count > dev_size - *f_pos)
1411 count = dev_size - *f_pos;
1412
1413 if (copy_to_user(buf, dev_buf + *f_pos, count))
1414 ret = -EINVAL;
1415 ret = count;
1416 *f_pos += count;
1417
1418 out:
1419 kfree(dev_buf);
1420 return ret;
1421
1422 err_kmalloc:
1423 return 0;
1424}
1425
1426static const struct file_operations coh901318_debugfs_status_operations = {
1427 .owner = THIS_MODULE,
Stephen Boyd234e3402012-04-05 14:25:11 -0700[diff] [blame]1428 .open = simple_open,
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1429 .read = coh901318_debugfs_read,
Arnd Bergmann6038f372010-08-15 18:52:59 +0200[diff] [blame]1430 .llseek = default_llseek,
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1431};
1432
1433
1434static int __init init_coh901318_debugfs(void)
1435{
1436
1437 dma_dentry = debugfs_create_dir("dma", NULL);
1438
1439 (void) debugfs_create_file("status",
1440 S_IFREG | S_IRUGO,
1441 dma_dentry, NULL,
1442 &coh901318_debugfs_status_operations);
1443 return 0;
1444}
1445
1446static void __exit exit_coh901318_debugfs(void)
1447{
1448 debugfs_remove_recursive(dma_dentry);
1449}
1450
1451module_init(init_coh901318_debugfs);
1452module_exit(exit_coh901318_debugfs);
1453#else
1454
1455#define COH901318_DEBUGFS_ASSIGN(x, y)
1456
1457#endif /* CONFIG_DEBUG_FS */
1458
1459static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
1460{
1461 return container_of(chan, struct coh901318_chan, chan);
1462}
1463
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1464static inline const struct coh901318_params *
1465cohc_chan_param(struct coh901318_chan *cohc)
1466{
1467 return &cohc->base->platform->chan_conf[cohc->id].param;
1468}
1469
1470static inline const struct coh_dma_channel *
1471cohc_chan_conf(struct coh901318_chan *cohc)
1472{
1473 return &cohc->base->platform->chan_conf[cohc->id];
1474}
1475
1476static void enable_powersave(struct coh901318_chan *cohc)
1477{
1478 unsigned long flags;
1479 struct powersave *pm = &cohc->base->pm;
1480
1481 spin_lock_irqsave(&pm->lock, flags);
1482
1483 pm->started_channels &= ~(1ULL << cohc->id);
1484
1485 if (!pm->started_channels) {
1486 /* DMA no longer intends to access memory */
1487 cohc->base->platform->access_memory_state(cohc->base->dev,
1488 false);
1489 }
1490
1491 spin_unlock_irqrestore(&pm->lock, flags);
1492}
1493static void disable_powersave(struct coh901318_chan *cohc)
1494{
1495 unsigned long flags;
1496 struct powersave *pm = &cohc->base->pm;
1497
1498 spin_lock_irqsave(&pm->lock, flags);
1499
1500 if (!pm->started_channels) {
1501 /* DMA intends to access memory */
1502 cohc->base->platform->access_memory_state(cohc->base->dev,
1503 true);
1504 }
1505
1506 pm->started_channels |= (1ULL << cohc->id);
1507
1508 spin_unlock_irqrestore(&pm->lock, flags);
1509}
1510
1511static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control)
1512{
1513 int channel = cohc->id;
1514 void __iomem *virtbase = cohc->base->virtbase;
1515
1516 writel(control,
1517 virtbase + COH901318_CX_CTRL +
1518 COH901318_CX_CTRL_SPACING * channel);
1519 return 0;
1520}
1521
1522static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf)
1523{
1524 int channel = cohc->id;
1525 void __iomem *virtbase = cohc->base->virtbase;
1526
1527 writel(conf,
1528 virtbase + COH901318_CX_CFG +
1529 COH901318_CX_CFG_SPACING*channel);
1530 return 0;
1531}
1532
1533
1534static int coh901318_start(struct coh901318_chan *cohc)
1535{
1536 u32 val;
1537 int channel = cohc->id;
1538 void __iomem *virtbase = cohc->base->virtbase;
1539
1540 disable_powersave(cohc);
1541
1542 val = readl(virtbase + COH901318_CX_CFG +
1543 COH901318_CX_CFG_SPACING * channel);
1544
1545 /* Enable channel */
1546 val |= COH901318_CX_CFG_CH_ENABLE;
1547 writel(val, virtbase + COH901318_CX_CFG +
1548 COH901318_CX_CFG_SPACING * channel);
1549
1550 return 0;
1551}
1552
1553static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1554 struct coh901318_lli *lli)
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1555{
1556 int channel = cohc->id;
1557 void __iomem *virtbase = cohc->base->virtbase;
1558
1559 BUG_ON(readl(virtbase + COH901318_CX_STAT +
1560 COH901318_CX_STAT_SPACING*channel) &
1561 COH901318_CX_STAT_ACTIVE);
1562
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1563 writel(lli->src_addr,
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1564 virtbase + COH901318_CX_SRC_ADDR +
1565 COH901318_CX_SRC_ADDR_SPACING * channel);
1566
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1567 writel(lli->dst_addr, virtbase +
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1568 COH901318_CX_DST_ADDR +
1569 COH901318_CX_DST_ADDR_SPACING * channel);
1570
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1571 writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR +
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1572 COH901318_CX_LNK_ADDR_SPACING * channel);
1573
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1574 writel(lli->control, virtbase + COH901318_CX_CTRL +
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1575 COH901318_CX_CTRL_SPACING * channel);
1576
1577 return 0;
1578}
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1579
1580static struct coh901318_desc *
1581coh901318_desc_get(struct coh901318_chan *cohc)
1582{
1583 struct coh901318_desc *desc;
1584
1585 if (list_empty(&cohc->free)) {
1586 /* alloc new desc because we're out of used ones
1587 * TODO: alloc a pile of descs instead of just one,
1588 * avoid many small allocations.
1589 */
Linus Walleijb87108a2010-03-02 14:17:20 -0700[diff] [blame]1590 desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1591 if (desc == NULL)
1592 goto out;
1593 INIT_LIST_HEAD(&desc->node);
Linus Walleijb87108a2010-03-02 14:17:20 -0700[diff] [blame]1594 dma_async_tx_descriptor_init(&desc->desc, &cohc->chan);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1595 } else {
1596 /* Reuse an old desc. */
1597 desc = list_first_entry(&cohc->free,
1598 struct coh901318_desc,
1599 node);
1600 list_del(&desc->node);
Linus Walleijb87108a2010-03-02 14:17:20 -0700[diff] [blame]1601 /* Initialize it a bit so it's not insane */
1602 desc->sg = NULL;
1603 desc->sg_len = 0;
1604 desc->desc.callback = NULL;
1605 desc->desc.callback_param = NULL;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1606 }
1607
1608 out:
1609 return desc;
1610}
1611
1612static void
1613coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd)
1614{
1615 list_add_tail(&cohd->node, &cohc->free);
1616}
1617
1618/* call with irq lock held */
1619static void
1620coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc)
1621{
1622 list_add_tail(&desc->node, &cohc->active);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1623}
1624
1625static struct coh901318_desc *
1626coh901318_first_active_get(struct coh901318_chan *cohc)
1627{
1628 struct coh901318_desc *d;
1629
1630 if (list_empty(&cohc->active))
1631 return NULL;
1632
1633 d = list_first_entry(&cohc->active,
1634 struct coh901318_desc,
1635 node);
1636 return d;
1637}
1638
1639static void
1640coh901318_desc_remove(struct coh901318_desc *cohd)
1641{
1642 list_del(&cohd->node);
1643}
1644
1645static void
1646coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc)
1647{
1648 list_add_tail(&desc->node, &cohc->queue);
1649}
1650
1651static struct coh901318_desc *
1652coh901318_first_queued(struct coh901318_chan *cohc)
1653{
1654 struct coh901318_desc *d;
1655
1656 if (list_empty(&cohc->queue))
1657 return NULL;
1658
1659 d = list_first_entry(&cohc->queue,
1660 struct coh901318_desc,
1661 node);
1662 return d;
1663}
1664
Linus Walleij84c84472010-03-04 14:40:30 +0100[diff] [blame]1665static inline u32 coh901318_get_bytes_in_lli(struct coh901318_lli *in_lli)
1666{
1667 struct coh901318_lli *lli = in_lli;
1668 u32 bytes = 0;
1669
1670 while (lli) {
1671 bytes += lli->control & COH901318_CX_CTRL_TC_VALUE_MASK;
1672 lli = lli->virt_link_addr;
1673 }
1674 return bytes;
1675}
1676
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1677/*
Linus Walleij84c84472010-03-04 14:40:30 +0100[diff] [blame]1678 * Get the number of bytes left to transfer on this channel,
1679 * it is unwise to call this before stopping the channel for
1680 * absolute measures, but for a rough guess you can still call
1681 * it.
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1682 */
Linus Walleij07934482010-03-26 16:50:49 -0700[diff] [blame]1683static u32 coh901318_get_bytes_left(struct dma_chan *chan)
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1684{
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1685 struct coh901318_chan *cohc = to_coh901318_chan(chan);
Linus Walleij84c84472010-03-04 14:40:30 +0100[diff] [blame]1686 struct coh901318_desc *cohd;
1687 struct list_head *pos;
1688 unsigned long flags;
1689 u32 left = 0;
1690 int i = 0;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1691
1692 spin_lock_irqsave(&cohc->lock, flags);
1693
Linus Walleij84c84472010-03-04 14:40:30 +0100[diff] [blame]1694 /*
1695 * If there are many queued jobs, we iterate and add the
1696 * size of them all. We take a special look on the first
1697 * job though, since it is probably active.
1698 */
1699 list_for_each(pos, &cohc->active) {
1700 /*
1701 * The first job in the list will be working on the
1702 * hardware. The job can be stopped but still active,
1703 * so that the transfer counter is somewhere inside
1704 * the buffer.
1705 */
1706 cohd = list_entry(pos, struct coh901318_desc, node);
1707
1708 if (i == 0) {
1709 struct coh901318_lli *lli;
1710 dma_addr_t ladd;
1711
1712 /* Read current transfer count value */
1713 left = readl(cohc->base->virtbase +
1714 COH901318_CX_CTRL +
1715 COH901318_CX_CTRL_SPACING * cohc->id) &
1716 COH901318_CX_CTRL_TC_VALUE_MASK;
1717
1718 /* See if the transfer is linked... */
1719 ladd = readl(cohc->base->virtbase +
1720 COH901318_CX_LNK_ADDR +
1721 COH901318_CX_LNK_ADDR_SPACING *
1722 cohc->id) &
1723 ~COH901318_CX_LNK_LINK_IMMEDIATE;
1724 /* Single transaction */
1725 if (!ladd)
1726 continue;
1727
1728 /*
1729 * Linked transaction, follow the lli, find the
1730 * currently processing lli, and proceed to the next
1731 */
1732 lli = cohd->lli;
1733 while (lli && lli->link_addr != ladd)
1734 lli = lli->virt_link_addr;
1735
1736 if (lli)
1737 lli = lli->virt_link_addr;
1738
1739 /*
1740 * Follow remaining lli links around to count the total
1741 * number of bytes left
1742 */
1743 left += coh901318_get_bytes_in_lli(lli);
1744 } else {
1745 left += coh901318_get_bytes_in_lli(cohd->lli);
1746 }
1747 i++;
1748 }
1749
1750 /* Also count bytes in the queued jobs */
1751 list_for_each(pos, &cohc->queue) {
1752 cohd = list_entry(pos, struct coh901318_desc, node);
1753 left += coh901318_get_bytes_in_lli(cohd->lli);
1754 }
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1755
1756 spin_unlock_irqrestore(&cohc->lock, flags);
1757
Linus Walleij84c84472010-03-04 14:40:30 +0100[diff] [blame]1758 return left;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1759}
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1760
Linus Walleijc3635c72010-03-26 16:44:01 -0700[diff] [blame]1761/*
1762 * Pauses a transfer without losing data. Enables power save.
1763 * Use this function in conjunction with coh901318_resume.
1764 */
1765static void coh901318_pause(struct dma_chan *chan)
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1766{
1767 u32 val;
1768 unsigned long flags;
1769 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1770 int channel = cohc->id;
1771 void __iomem *virtbase = cohc->base->virtbase;
1772
1773 spin_lock_irqsave(&cohc->lock, flags);
1774
1775 /* Disable channel in HW */
1776 val = readl(virtbase + COH901318_CX_CFG +
1777 COH901318_CX_CFG_SPACING * channel);
1778
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300[diff] [blame]1779 /* Stopping infinite transfer */
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1780 if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 &&
1781 (val & COH901318_CX_CFG_CH_ENABLE))
1782 cohc->stopped = 1;
1783
1784
1785 val &= ~COH901318_CX_CFG_CH_ENABLE;
1786 /* Enable twice, HW bug work around */
1787 writel(val, virtbase + COH901318_CX_CFG +
1788 COH901318_CX_CFG_SPACING * channel);
1789 writel(val, virtbase + COH901318_CX_CFG +
1790 COH901318_CX_CFG_SPACING * channel);
1791
1792 /* Spin-wait for it to actually go inactive */
1793 while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING *
1794 channel) & COH901318_CX_STAT_ACTIVE)
1795 cpu_relax();
1796
1797 /* Check if we stopped an active job */
1798 if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
1799 channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0)
1800 cohc->stopped = 1;
1801
1802 enable_powersave(cohc);
1803
1804 spin_unlock_irqrestore(&cohc->lock, flags);
1805}
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1806
Linus Walleijc3635c72010-03-26 16:44:01 -0700[diff] [blame]1807/* Resumes a transfer that has been stopped via 300_dma_stop(..).
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1808 Power save is handled.
1809*/
Linus Walleijc3635c72010-03-26 16:44:01 -0700[diff] [blame]1810static void coh901318_resume(struct dma_chan *chan)
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1811{
1812 u32 val;
1813 unsigned long flags;
1814 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1815 int channel = cohc->id;
1816
1817 spin_lock_irqsave(&cohc->lock, flags);
1818
1819 disable_powersave(cohc);
1820
1821 if (cohc->stopped) {
1822 /* Enable channel in HW */
1823 val = readl(cohc->base->virtbase + COH901318_CX_CFG +
1824 COH901318_CX_CFG_SPACING * channel);
1825
1826 val |= COH901318_CX_CFG_CH_ENABLE;
1827
1828 writel(val, cohc->base->virtbase + COH901318_CX_CFG +
1829 COH901318_CX_CFG_SPACING*channel);
1830
1831 cohc->stopped = 0;
1832 }
1833
1834 spin_unlock_irqrestore(&cohc->lock, flags);
1835}
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1836
1837bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
1838{
1839 unsigned int ch_nr = (unsigned int) chan_id;
1840
1841 if (ch_nr == to_coh901318_chan(chan)->id)
1842 return true;
1843
1844 return false;
1845}
1846EXPORT_SYMBOL(coh901318_filter_id);
1847
1848/*
1849 * DMA channel allocation
1850 */
1851static int coh901318_config(struct coh901318_chan *cohc,
1852 struct coh901318_params *param)
1853{
1854 unsigned long flags;
1855 const struct coh901318_params *p;
1856 int channel = cohc->id;
1857 void __iomem *virtbase = cohc->base->virtbase;
1858
1859 spin_lock_irqsave(&cohc->lock, flags);
1860
1861 if (param)
1862 p = param;
1863 else
1864 p = &cohc->base->platform->chan_conf[channel].param;
1865
1866 /* Clear any pending BE or TC interrupt */
1867 if (channel < 32) {
1868 writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1);
1869 writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1);
1870 } else {
1871 writel(1 << (channel - 32), virtbase +
1872 COH901318_BE_INT_CLEAR2);
1873 writel(1 << (channel - 32), virtbase +
1874 COH901318_TC_INT_CLEAR2);
1875 }
1876
1877 coh901318_set_conf(cohc, p->config);
1878 coh901318_set_ctrl(cohc, p->ctrl_lli_last);
1879
1880 spin_unlock_irqrestore(&cohc->lock, flags);
1881
1882 return 0;
1883}
1884
1885/* must lock when calling this function
1886 * start queued jobs, if any
1887 * TODO: start all queued jobs in one go
1888 *
1889 * Returns descriptor if queued job is started otherwise NULL.
1890 * If the queue is empty NULL is returned.
1891 */
1892static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc)
1893{
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1894 struct coh901318_desc *cohd;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1895
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1896 /*
1897 * start queued jobs, if any
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1898 * TODO: transmit all queued jobs in one go
1899 */
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1900 cohd = coh901318_first_queued(cohc);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1901
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1902 if (cohd != NULL) {
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1903 /* Remove from queue */
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1904 coh901318_desc_remove(cohd);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1905 /* initiate DMA job */
1906 cohc->busy = 1;
1907
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1908 coh901318_desc_submit(cohc, cohd);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1909
Linus Walleijb89243d2011-07-01 16:47:28 +0200[diff] [blame]1910 /* Program the transaction head */
1911 coh901318_set_conf(cohc, cohd->head_config);
1912 coh901318_set_ctrl(cohc, cohd->head_ctrl);
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1913 coh901318_prep_linked_list(cohc, cohd->lli);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1914
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1915 /* start dma job on this channel */
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1916 coh901318_start(cohc);
1917
1918 }
1919
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1920 return cohd;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1921}
1922
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]1923/*
1924 * This tasklet is called from the interrupt handler to
1925 * handle each descriptor (DMA job) that is sent to a channel.
1926 */
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1927static void dma_tasklet(unsigned long data)
1928{
1929 struct coh901318_chan *cohc = (struct coh901318_chan *) data;
1930 struct coh901318_desc *cohd_fin;
1931 unsigned long flags;
1932 dma_async_tx_callback callback;
1933 void *callback_param;
1934
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]1935 dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d"
1936 " nbr_active_done %ld\n", __func__,
1937 cohc->id, cohc->nbr_active_done);
1938
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1939 spin_lock_irqsave(&cohc->lock, flags);
1940
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]1941 /* get first active descriptor entry from list */
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1942 cohd_fin = coh901318_first_active_get(cohc);
1943
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1944 if (cohd_fin == NULL)
1945 goto err;
1946
Linus Walleij0b588282010-03-02 14:17:44 -0700[diff] [blame]1947 /* locate callback to client */
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1948 callback = cohd_fin->desc.callback;
1949 callback_param = cohd_fin->desc.callback_param;
1950
Linus Walleij0b588282010-03-02 14:17:44 -0700[diff] [blame]1951 /* sign this job as completed on the channel */
Russell King - ARM Linuxf7fbce02012-03-06 22:35:07 +0000[diff] [blame]1952 dma_cookie_complete(&cohd_fin->desc);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1953
Linus Walleij0b588282010-03-02 14:17:44 -0700[diff] [blame]1954 /* release the lli allocation and remove the descriptor */
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1955 coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
Linus Walleij0b588282010-03-02 14:17:44 -0700[diff] [blame]1956
1957 /* return desc to free-list */
1958 coh901318_desc_remove(cohd_fin);
1959 coh901318_desc_free(cohc, cohd_fin);
1960
1961 spin_unlock_irqrestore(&cohc->lock, flags);
1962
1963 /* Call the callback when we're done */
1964 if (callback)
1965 callback(callback_param);
1966
1967 spin_lock_irqsave(&cohc->lock, flags);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1968
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]1969 /*
1970 * If another interrupt fired while the tasklet was scheduling,
1971 * we don't get called twice, so we have this number of active
1972 * counter that keep track of the number of IRQs expected to
1973 * be handled for this channel. If there happen to be more than
1974 * one IRQ to be ack:ed, we simply schedule this tasklet again.
1975 */
Linus Walleij0b588282010-03-02 14:17:44 -0700[diff] [blame]1976 cohc->nbr_active_done--;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1977 if (cohc->nbr_active_done) {
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]1978 dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs "
1979 "came in while we were scheduling this tasklet\n");
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1980 if (cohc_chan_conf(cohc)->priority_high)
1981 tasklet_hi_schedule(&cohc->tasklet);
1982 else
1983 tasklet_schedule(&cohc->tasklet);
1984 }
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1985
Linus Walleij0b588282010-03-02 14:17:44 -0700[diff] [blame]1986 spin_unlock_irqrestore(&cohc->lock, flags);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1987
1988 return;
1989
1990 err:
1991 spin_unlock_irqrestore(&cohc->lock, flags);
1992 dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__);
1993}
1994
1995
1996/* called from interrupt context */
1997static void dma_tc_handle(struct coh901318_chan *cohc)
1998{
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1999 /*
2000 * If the channel is not allocated, then we shouldn't have
2001 * any TC interrupts on it.
2002 */
2003 if (!cohc->allocated) {
2004 dev_err(COHC_2_DEV(cohc), "spurious interrupt from "
2005 "unallocated channel\n");
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2006 return;
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2007 }
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2008
Linus Walleij0b588282010-03-02 14:17:44 -0700[diff] [blame]2009 spin_lock(&cohc->lock);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2010
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2011 /*
2012 * When we reach this point, at least one queue item
2013 * should have been moved over from cohc->queue to
2014 * cohc->active and run to completion, that is why we're
2015 * getting a terminal count interrupt is it not?
2016 * If you get this BUG() the most probable cause is that
2017 * the individual nodes in the lli chain have IRQ enabled,
2018 * so check your platform config for lli chain ctrl.
2019 */
2020 BUG_ON(list_empty(&cohc->active));
2021
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2022 cohc->nbr_active_done++;
2023
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2024 /*
2025 * This attempt to take a job from cohc->queue, put it
2026 * into cohc->active and start it.
2027 */
Linus Walleij0b588282010-03-02 14:17:44 -0700[diff] [blame]2028 if (coh901318_queue_start(cohc) == NULL)
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2029 cohc->busy = 0;
2030
Linus Walleij0b588282010-03-02 14:17:44 -0700[diff] [blame]2031 spin_unlock(&cohc->lock);
2032
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2033 /*
2034 * This tasklet will remove items from cohc->active
2035 * and thus terminates them.
2036 */
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2037 if (cohc_chan_conf(cohc)->priority_high)
2038 tasklet_hi_schedule(&cohc->tasklet);
2039 else
2040 tasklet_schedule(&cohc->tasklet);
2041}
2042
2043
2044static irqreturn_t dma_irq_handler(int irq, void *dev_id)
2045{
2046 u32 status1;
2047 u32 status2;
2048 int i;
2049 int ch;
2050 struct coh901318_base *base = dev_id;
2051 struct coh901318_chan *cohc;
2052 void __iomem *virtbase = base->virtbase;
2053
2054 status1 = readl(virtbase + COH901318_INT_STATUS1);
2055 status2 = readl(virtbase + COH901318_INT_STATUS2);
2056
2057 if (unlikely(status1 == 0 && status2 == 0)) {
2058 dev_warn(base->dev, "spurious DMA IRQ from no channel!\n");
2059 return IRQ_HANDLED;
2060 }
2061
2062 /* TODO: consider handle IRQ in tasklet here to
2063 * minimize interrupt latency */
2064
2065 /* Check the first 32 DMA channels for IRQ */
2066 while (status1) {
2067 /* Find first bit set, return as a number. */
2068 i = ffs(status1) - 1;
2069 ch = i;
2070
2071 cohc = &base->chans[ch];
2072 spin_lock(&cohc->lock);
2073
2074 /* Mask off this bit */
2075 status1 &= ~(1 << i);
2076 /* Check the individual channel bits */
2077 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) {
2078 dev_crit(COHC_2_DEV(cohc),
2079 "DMA bus error on channel %d!\n", ch);
2080 BUG_ON(1);
2081 /* Clear BE interrupt */
2082 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1);
2083 } else {
2084 /* Caused by TC, really? */
2085 if (unlikely(!test_bit(i, virtbase +
2086 COH901318_TC_INT_STATUS1))) {
2087 dev_warn(COHC_2_DEV(cohc),
2088 "ignoring interrupt not caused by terminal count on channel %d\n", ch);
2089 /* Clear TC interrupt */
2090 BUG_ON(1);
2091 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
2092 } else {
2093 /* Enable powersave if transfer has finished */
2094 if (!(readl(virtbase + COH901318_CX_STAT +
2095 COH901318_CX_STAT_SPACING*ch) &
2096 COH901318_CX_STAT_ENABLED)) {
2097 enable_powersave(cohc);
2098 }
2099
2100 /* Must clear TC interrupt before calling
2101 * dma_tc_handle
Justin P. Mattockbc0b44c2011-01-28 11:48:18 -0800[diff] [blame]2102 * in case tc_handle initiate a new dma job
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2103 */
2104 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
2105
2106 dma_tc_handle(cohc);
2107 }
2108 }
2109 spin_unlock(&cohc->lock);
2110 }
2111
2112 /* Check the remaining 32 DMA channels for IRQ */
2113 while (status2) {
2114 /* Find first bit set, return as a number. */
2115 i = ffs(status2) - 1;
2116 ch = i + 32;
2117 cohc = &base->chans[ch];
2118 spin_lock(&cohc->lock);
2119
2120 /* Mask off this bit */
2121 status2 &= ~(1 << i);
2122 /* Check the individual channel bits */
2123 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) {
2124 dev_crit(COHC_2_DEV(cohc),
2125 "DMA bus error on channel %d!\n", ch);
2126 /* Clear BE interrupt */
2127 BUG_ON(1);
2128 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2);
2129 } else {
2130 /* Caused by TC, really? */
2131 if (unlikely(!test_bit(i, virtbase +
2132 COH901318_TC_INT_STATUS2))) {
2133 dev_warn(COHC_2_DEV(cohc),
2134 "ignoring interrupt not caused by terminal count on channel %d\n", ch);
2135 /* Clear TC interrupt */
2136 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
2137 BUG_ON(1);
2138 } else {
2139 /* Enable powersave if transfer has finished */
2140 if (!(readl(virtbase + COH901318_CX_STAT +
2141 COH901318_CX_STAT_SPACING*ch) &
2142 COH901318_CX_STAT_ENABLED)) {
2143 enable_powersave(cohc);
2144 }
2145 /* Must clear TC interrupt before calling
2146 * dma_tc_handle
Justin P. Mattockbc0b44c2011-01-28 11:48:18 -0800[diff] [blame]2147 * in case tc_handle initiate a new dma job
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2148 */
2149 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
2150
2151 dma_tc_handle(cohc);
2152 }
2153 }
2154 spin_unlock(&cohc->lock);
2155 }
2156
2157 return IRQ_HANDLED;
2158}
2159
2160static int coh901318_alloc_chan_resources(struct dma_chan *chan)
2161{
2162 struct coh901318_chan *cohc = to_coh901318_chan(chan);
Linus Walleij84c84472010-03-04 14:40:30 +0100[diff] [blame]2163 unsigned long flags;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2164
2165 dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n",
2166 __func__, cohc->id);
2167
2168 if (chan->client_count > 1)
2169 return -EBUSY;
2170
Linus Walleij84c84472010-03-04 14:40:30 +0100[diff] [blame]2171 spin_lock_irqsave(&cohc->lock, flags);
2172
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2173 coh901318_config(cohc, NULL);
2174
2175 cohc->allocated = 1;
Russell King - ARM Linuxd3ee98cdc2012-03-06 22:35:47 +0000[diff] [blame]2176 dma_cookie_init(chan);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2177
Linus Walleij84c84472010-03-04 14:40:30 +0100[diff] [blame]2178 spin_unlock_irqrestore(&cohc->lock, flags);
2179
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2180 return 1;
2181}
2182
2183static void
2184coh901318_free_chan_resources(struct dma_chan *chan)
2185{
2186 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2187 int channel = cohc->id;
2188 unsigned long flags;
2189
2190 spin_lock_irqsave(&cohc->lock, flags);
2191
2192 /* Disable HW */
2193 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG +
2194 COH901318_CX_CFG_SPACING*channel);
2195 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL +
2196 COH901318_CX_CTRL_SPACING*channel);
2197
2198 cohc->allocated = 0;
2199
2200 spin_unlock_irqrestore(&cohc->lock, flags);
2201
Linus Walleij05827632010-05-17 16:30:42 -0700[diff] [blame]2202 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2203}
2204
2205
2206static dma_cookie_t
2207coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
2208{
2209 struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc,
2210 desc);
2211 struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
2212 unsigned long flags;
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000[diff] [blame]2213 dma_cookie_t cookie;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2214
2215 spin_lock_irqsave(&cohc->lock, flags);
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000[diff] [blame]2216 cookie = dma_cookie_assign(tx);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2217
2218 coh901318_desc_queue(cohc, cohd);
2219
2220 spin_unlock_irqrestore(&cohc->lock, flags);
2221
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000[diff] [blame]2222 return cookie;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2223}
2224
2225static struct dma_async_tx_descriptor *
2226coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
2227 size_t size, unsigned long flags)
2228{
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2229 struct coh901318_lli *lli;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2230 struct coh901318_desc *cohd;
2231 unsigned long flg;
2232 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2233 int lli_len;
2234 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
Linus Walleijb87108a2010-03-02 14:17:20 -0700[diff] [blame]2235 int ret;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2236
2237 spin_lock_irqsave(&cohc->lock, flg);
2238
2239 dev_vdbg(COHC_2_DEV(cohc),
2240 "[%s] channel %d src 0x%x dest 0x%x size %d\n",
2241 __func__, cohc->id, src, dest, size);
2242
2243 if (flags & DMA_PREP_INTERRUPT)
2244 /* Trigger interrupt after last lli */
2245 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
2246
2247 lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT;
2248 if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size)
2249 lli_len++;
2250
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2251 lli = coh901318_lli_alloc(&cohc->base->pool, lli_len);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2252
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2253 if (lli == NULL)
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2254 goto err;
2255
Linus Walleijb87108a2010-03-02 14:17:20 -0700[diff] [blame]2256 ret = coh901318_lli_fill_memcpy(
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2257 &cohc->base->pool, lli, src, size, dest,
Linus Walleijb87108a2010-03-02 14:17:20 -0700[diff] [blame]2258 cohc_chan_param(cohc)->ctrl_lli_chained,
2259 ctrl_last);
2260 if (ret)
2261 goto err;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2262
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2263 COH_DBG(coh901318_list_print(cohc, lli));
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2264
Linus Walleijb87108a2010-03-02 14:17:20 -0700[diff] [blame]2265 /* Pick a descriptor to handle this transfer */
2266 cohd = coh901318_desc_get(cohc);
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2267 cohd->lli = lli;
Linus Walleijb87108a2010-03-02 14:17:20 -0700[diff] [blame]2268 cohd->flags = flags;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2269 cohd->desc.tx_submit = coh901318_tx_submit;
2270
2271 spin_unlock_irqrestore(&cohc->lock, flg);
2272
2273 return &cohd->desc;
2274 err:
2275 spin_unlock_irqrestore(&cohc->lock, flg);
2276 return NULL;
2277}
2278
2279static struct dma_async_tx_descriptor *
2280coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
Vinod Kouldb8196d2011-10-13 22:34:23 +0530[diff] [blame]2281 unsigned int sg_len, enum dma_transfer_direction direction,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500[diff] [blame]2282 unsigned long flags, void *context)
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2283{
2284 struct coh901318_chan *cohc = to_coh901318_chan(chan);
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2285 struct coh901318_lli *lli;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2286 struct coh901318_desc *cohd;
Linus Walleij516fd432010-03-02 20:12:46 +0100[diff] [blame]2287 const struct coh901318_params *params;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2288 struct scatterlist *sg;
2289 int len = 0;
2290 int size;
2291 int i;
2292 u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained;
2293 u32 ctrl = cohc_chan_param(cohc)->ctrl_lli;
2294 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
Linus Walleij516fd432010-03-02 20:12:46 +0100[diff] [blame]2295 u32 config;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2296 unsigned long flg;
Linus Walleij0b588282010-03-02 14:17:44 -0700[diff] [blame]2297 int ret;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2298
2299 if (!sgl)
2300 goto out;
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200[diff] [blame]2301 if (sg_dma_len(sgl) == 0)
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2302 goto out;
2303
2304 spin_lock_irqsave(&cohc->lock, flg);
2305
2306 dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n",
2307 __func__, sg_len, direction);
2308
2309 if (flags & DMA_PREP_INTERRUPT)
2310 /* Trigger interrupt after last lli */
2311 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
2312
Linus Walleij516fd432010-03-02 20:12:46 +0100[diff] [blame]2313 params = cohc_chan_param(cohc);
2314 config = params->config;
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2315 /*
2316 * Add runtime-specific control on top, make
2317 * sure the bits you set per peripheral channel are
2318 * cleared in the default config from the platform.
2319 */
Linus Walleij9aab4d62013-01-04 13:50:49 +0100[diff] [blame]2320 ctrl_chained |= cohc->ctrl;
2321 ctrl_last |= cohc->ctrl;
2322 ctrl |= cohc->ctrl;
Linus Walleij516fd432010-03-02 20:12:46 +0100[diff] [blame]2323
Vinod Kouldb8196d2011-10-13 22:34:23 +0530[diff] [blame]2324 if (direction == DMA_MEM_TO_DEV) {
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2325 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
2326 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
2327
Linus Walleij516fd432010-03-02 20:12:46 +0100[diff] [blame]2328 config |= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2329 ctrl_chained |= tx_flags;
2330 ctrl_last |= tx_flags;
2331 ctrl |= tx_flags;
Vinod Kouldb8196d2011-10-13 22:34:23 +0530[diff] [blame]2332 } else if (direction == DMA_DEV_TO_MEM) {
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2333 u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
2334 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;
2335
Linus Walleij516fd432010-03-02 20:12:46 +0100[diff] [blame]2336 config |= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2337 ctrl_chained |= rx_flags;
2338 ctrl_last |= rx_flags;
2339 ctrl |= rx_flags;
2340 } else
2341 goto err_direction;
2342
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2343 /* The dma only supports transmitting packages up to
2344 * MAX_DMA_PACKET_SIZE. Calculate to total number of
2345 * dma elemts required to send the entire sg list
2346 */
2347 for_each_sg(sgl, sg, sg_len, i) {
2348 unsigned int factor;
2349 size = sg_dma_len(sg);
2350
2351 if (size <= MAX_DMA_PACKET_SIZE) {
2352 len++;
2353 continue;
2354 }
2355
2356 factor = size >> MAX_DMA_PACKET_SIZE_SHIFT;
2357 if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size)
2358 factor++;
2359
2360 len += factor;
2361 }
2362
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]2363 pr_debug("Allocate %d lli:s for this transfer\n", len);
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2364 lli = coh901318_lli_alloc(&cohc->base->pool, len);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2365
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2366 if (lli == NULL)
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2367 goto err_dma_alloc;
2368
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2369 /* initiate allocated lli list */
2370 ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
Linus Walleij9aab4d62013-01-04 13:50:49 +0100[diff] [blame]2371 cohc->addr,
Linus Walleij0b588282010-03-02 14:17:44 -0700[diff] [blame]2372 ctrl_chained,
2373 ctrl,
2374 ctrl_last,
2375 direction, COH901318_CX_CTRL_TC_IRQ_ENABLE);
2376 if (ret)
2377 goto err_lli_fill;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2378
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2379
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2380 COH_DBG(coh901318_list_print(cohc, lli));
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2381
Linus Walleijb87108a2010-03-02 14:17:20 -0700[diff] [blame]2382 /* Pick a descriptor to handle this transfer */
2383 cohd = coh901318_desc_get(cohc);
Linus Walleijb89243d2011-07-01 16:47:28 +0200[diff] [blame]2384 cohd->head_config = config;
2385 /*
2386 * Set the default head ctrl for the channel to the one from the
2387 * lli, things may have changed due to odd buffer alignment
2388 * etc.
2389 */
2390 cohd->head_ctrl = lli->control;
Linus Walleijb87108a2010-03-02 14:17:20 -0700[diff] [blame]2391 cohd->dir = direction;
2392 cohd->flags = flags;
2393 cohd->desc.tx_submit = coh901318_tx_submit;
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2394 cohd->lli = lli;
Linus Walleijb87108a2010-03-02 14:17:20 -0700[diff] [blame]2395
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2396 spin_unlock_irqrestore(&cohc->lock, flg);
2397
2398 return &cohd->desc;
Linus Walleij0b588282010-03-02 14:17:44 -0700[diff] [blame]2399 err_lli_fill:
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2400 err_dma_alloc:
2401 err_direction:
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2402 spin_unlock_irqrestore(&cohc->lock, flg);
2403 out:
2404 return NULL;
2405}
2406
2407static enum dma_status
Linus Walleij07934482010-03-26 16:50:49 -0700[diff] [blame]2408coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2409 struct dma_tx_state *txstate)
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2410{
2411 struct coh901318_chan *cohc = to_coh901318_chan(chan);
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000[diff] [blame]2412 enum dma_status ret;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2413
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000[diff] [blame]2414 ret = dma_cookie_status(chan, cookie, txstate);
2415 /* FIXME: should be conditional on ret != DMA_SUCCESS? */
2416 dma_set_residue(txstate, coh901318_get_bytes_left(chan));
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2417
Linus Walleij07934482010-03-26 16:50:49 -0700[diff] [blame]2418 if (ret == DMA_IN_PROGRESS && cohc->stopped)
2419 ret = DMA_PAUSED;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2420
2421 return ret;
2422}
2423
2424static void
2425coh901318_issue_pending(struct dma_chan *chan)
2426{
2427 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2428 unsigned long flags;
2429
2430 spin_lock_irqsave(&cohc->lock, flags);
2431
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2432 /*
2433 * Busy means that pending jobs are already being processed,
2434 * and then there is no point in starting the queue: the
2435 * terminal count interrupt on the channel will take the next
2436 * job on the queue and execute it anyway.
2437 */
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2438 if (!cohc->busy)
2439 coh901318_queue_start(cohc);
2440
2441 spin_unlock_irqrestore(&cohc->lock, flags);
2442}
2443
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2444/*
2445 * Here we wrap in the runtime dma control interface
2446 */
2447struct burst_table {
2448 int burst_8bit;
2449 int burst_16bit;
2450 int burst_32bit;
2451 u32 reg;
2452};
2453
2454static const struct burst_table burst_sizes[] = {
2455 {
2456 .burst_8bit = 64,
2457 .burst_16bit = 32,
2458 .burst_32bit = 16,
2459 .reg = COH901318_CX_CTRL_BURST_COUNT_64_BYTES,
2460 },
2461 {
2462 .burst_8bit = 48,
2463 .burst_16bit = 24,
2464 .burst_32bit = 12,
2465 .reg = COH901318_CX_CTRL_BURST_COUNT_48_BYTES,
2466 },
2467 {
2468 .burst_8bit = 32,
2469 .burst_16bit = 16,
2470 .burst_32bit = 8,
2471 .reg = COH901318_CX_CTRL_BURST_COUNT_32_BYTES,
2472 },
2473 {
2474 .burst_8bit = 16,
2475 .burst_16bit = 8,
2476 .burst_32bit = 4,
2477 .reg = COH901318_CX_CTRL_BURST_COUNT_16_BYTES,
2478 },
2479 {
2480 .burst_8bit = 8,
2481 .burst_16bit = 4,
2482 .burst_32bit = 2,
2483 .reg = COH901318_CX_CTRL_BURST_COUNT_8_BYTES,
2484 },
2485 {
2486 .burst_8bit = 4,
2487 .burst_16bit = 2,
2488 .burst_32bit = 1,
2489 .reg = COH901318_CX_CTRL_BURST_COUNT_4_BYTES,
2490 },
2491 {
2492 .burst_8bit = 2,
2493 .burst_16bit = 1,
2494 .burst_32bit = 0,
2495 .reg = COH901318_CX_CTRL_BURST_COUNT_2_BYTES,
2496 },
2497 {
2498 .burst_8bit = 1,
2499 .burst_16bit = 0,
2500 .burst_32bit = 0,
2501 .reg = COH901318_CX_CTRL_BURST_COUNT_1_BYTE,
2502 },
2503};
2504
2505static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
2506 struct dma_slave_config *config)
2507{
2508 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2509 dma_addr_t addr;
2510 enum dma_slave_buswidth addr_width;
2511 u32 maxburst;
Linus Walleij9aab4d62013-01-04 13:50:49 +0100[diff] [blame]2512 u32 ctrl = 0;
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2513 int i = 0;
2514
2515 /* We only support mem to per or per to mem transfers */
Vinod Kouldb8196d2011-10-13 22:34:23 +0530[diff] [blame]2516 if (config->direction == DMA_DEV_TO_MEM) {
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2517 addr = config->src_addr;
2518 addr_width = config->src_addr_width;
2519 maxburst = config->src_maxburst;
Vinod Kouldb8196d2011-10-13 22:34:23 +0530[diff] [blame]2520 } else if (config->direction == DMA_MEM_TO_DEV) {
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2521 addr = config->dst_addr;
2522 addr_width = config->dst_addr_width;
2523 maxburst = config->dst_maxburst;
2524 } else {
2525 dev_err(COHC_2_DEV(cohc), "illegal channel mode\n");
2526 return;
2527 }
2528
2529 dev_dbg(COHC_2_DEV(cohc), "configure channel for %d byte transfers\n",
2530 addr_width);
2531 switch (addr_width) {
2532 case DMA_SLAVE_BUSWIDTH_1_BYTE:
Linus Walleij9aab4d62013-01-04 13:50:49 +0100[diff] [blame]2533 ctrl |=
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2534 COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS |
2535 COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS;
2536
2537 while (i < ARRAY_SIZE(burst_sizes)) {
2538 if (burst_sizes[i].burst_8bit <= maxburst)
2539 break;
2540 i++;
2541 }
2542
2543 break;
2544 case DMA_SLAVE_BUSWIDTH_2_BYTES:
Linus Walleij9aab4d62013-01-04 13:50:49 +0100[diff] [blame]2545 ctrl |=
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2546 COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS |
2547 COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS;
2548
2549 while (i < ARRAY_SIZE(burst_sizes)) {
2550 if (burst_sizes[i].burst_16bit <= maxburst)
2551 break;
2552 i++;
2553 }
2554
2555 break;
2556 case DMA_SLAVE_BUSWIDTH_4_BYTES:
2557 /* Direction doesn't matter here, it's 32/32 bits */
Linus Walleij9aab4d62013-01-04 13:50:49 +0100[diff] [blame]2558 ctrl |=
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2559 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
2560 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS;
2561
2562 while (i < ARRAY_SIZE(burst_sizes)) {
2563 if (burst_sizes[i].burst_32bit <= maxburst)
2564 break;
2565 i++;
2566 }
2567
2568 break;
2569 default:
2570 dev_err(COHC_2_DEV(cohc),
2571 "bad runtimeconfig: alien address width\n");
2572 return;
2573 }
2574
Linus Walleij9aab4d62013-01-04 13:50:49 +0100[diff] [blame]2575 ctrl |= burst_sizes[i].reg;
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2576 dev_dbg(COHC_2_DEV(cohc),
2577 "selected burst size %d bytes for address width %d bytes, maxburst %d\n",
2578 burst_sizes[i].burst_8bit, addr_width, maxburst);
2579
Linus Walleij9aab4d62013-01-04 13:50:49 +0100[diff] [blame]2580 cohc->addr = addr;
2581 cohc->ctrl = ctrl;
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2582}
2583
Linus Walleijc3635c72010-03-26 16:44:01 -0700[diff] [blame]2584static int
Linus Walleij05827632010-05-17 16:30:42 -0700[diff] [blame]2585coh901318_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2586 unsigned long arg)
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2587{
2588 unsigned long flags;
2589 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2590 struct coh901318_desc *cohd;
2591 void __iomem *virtbase = cohc->base->virtbase;
2592
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2593 if (cmd == DMA_SLAVE_CONFIG) {
2594 struct dma_slave_config *config =
2595 (struct dma_slave_config *) arg;
2596
2597 coh901318_dma_set_runtimeconfig(chan, config);
2598 return 0;
2599 }
2600
Linus Walleijc3635c72010-03-26 16:44:01 -0700[diff] [blame]2601 if (cmd == DMA_PAUSE) {
2602 coh901318_pause(chan);
2603 return 0;
2604 }
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2605
Linus Walleijc3635c72010-03-26 16:44:01 -0700[diff] [blame]2606 if (cmd == DMA_RESUME) {
2607 coh901318_resume(chan);
2608 return 0;
2609 }
2610
2611 if (cmd != DMA_TERMINATE_ALL)
2612 return -ENXIO;
2613
2614 /* The remainder of this function terminates the transfer */
2615 coh901318_pause(chan);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2616 spin_lock_irqsave(&cohc->lock, flags);
2617
2618 /* Clear any pending BE or TC interrupt */
2619 if (cohc->id < 32) {
2620 writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
2621 writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
2622 } else {
2623 writel(1 << (cohc->id - 32), virtbase +
2624 COH901318_BE_INT_CLEAR2);
2625 writel(1 << (cohc->id - 32), virtbase +
2626 COH901318_TC_INT_CLEAR2);
2627 }
2628
2629 enable_powersave(cohc);
2630
2631 while ((cohd = coh901318_first_active_get(cohc))) {
2632 /* release the lli allocation*/
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2633 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2634
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2635 /* return desc to free-list */
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]2636 coh901318_desc_remove(cohd);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2637 coh901318_desc_free(cohc, cohd);
2638 }
2639
2640 while ((cohd = coh901318_first_queued(cohc))) {
2641 /* release the lli allocation*/
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2642 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2643
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2644 /* return desc to free-list */
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]2645 coh901318_desc_remove(cohd);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2646 coh901318_desc_free(cohc, cohd);
2647 }
2648
2649
2650 cohc->nbr_active_done = 0;
2651 cohc->busy = 0;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2652
2653 spin_unlock_irqrestore(&cohc->lock, flags);
Linus Walleijc3635c72010-03-26 16:44:01 -0700[diff] [blame]2654
2655 return 0;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2656}
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2657
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2658void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
2659 struct coh901318_base *base)
2660{
2661 int chans_i;
2662 int i = 0;
2663 struct coh901318_chan *cohc;
2664
2665 INIT_LIST_HEAD(&dma->channels);
2666
2667 for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
2668 for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
2669 cohc = &base->chans[i];
2670
2671 cohc->base = base;
2672 cohc->chan.device = dma;
2673 cohc->id = i;
2674
2675 /* TODO: do we really need this lock if only one
2676 * client is connected to each channel?
2677 */
2678
2679 spin_lock_init(&cohc->lock);
2680
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2681 cohc->nbr_active_done = 0;
2682 cohc->busy = 0;
2683 INIT_LIST_HEAD(&cohc->free);
2684 INIT_LIST_HEAD(&cohc->active);
2685 INIT_LIST_HEAD(&cohc->queue);
2686
2687 tasklet_init(&cohc->tasklet, dma_tasklet,
2688 (unsigned long) cohc);
2689
2690 list_add_tail(&cohc->chan.device_node,
2691 &dma->channels);
2692 }
2693 }
2694}
2695
2696static int __init coh901318_probe(struct platform_device *pdev)
2697{
2698 int err = 0;
2699 struct coh901318_platform *pdata;
2700 struct coh901318_base *base;
2701 int irq;
2702 struct resource *io;
2703
2704 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2705 if (!io)
Linus Walleijf7ceb362012-06-12 20:19:24 +0200[diff] [blame]2706 return -ENODEV;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2707
2708 /* Map DMA controller registers to virtual memory */
Linus Walleijf7ceb362012-06-12 20:19:24 +0200[diff] [blame]2709 if (devm_request_mem_region(&pdev->dev,
2710 io->start,
2711 resource_size(io),
2712 pdev->dev.driver->name) == NULL)
2713 return -ENOMEM;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2714
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]2715 pdata = &coh901318_platform,
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2716
Linus Walleijf7ceb362012-06-12 20:19:24 +0200[diff] [blame]2717 base = devm_kzalloc(&pdev->dev,
2718 ALIGN(sizeof(struct coh901318_base), 4) +
2719 pdata->max_channels *
2720 sizeof(struct coh901318_chan),
2721 GFP_KERNEL);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2722 if (!base)
Linus Walleijf7ceb362012-06-12 20:19:24 +0200[diff] [blame]2723 return -ENOMEM;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2724
2725 base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4);
2726
Linus Walleijf7ceb362012-06-12 20:19:24 +0200[diff] [blame]2727 base->virtbase = devm_ioremap(&pdev->dev, io->start, resource_size(io));
2728 if (!base->virtbase)
2729 return -ENOMEM;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2730
2731 base->dev = &pdev->dev;
2732 base->platform = pdata;
2733 spin_lock_init(&base->pm.lock);
2734 base->pm.started_channels = 0;
2735
2736 COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base);
2737
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2738 irq = platform_get_irq(pdev, 0);
2739 if (irq < 0)
Linus Walleijf7ceb362012-06-12 20:19:24 +0200[diff] [blame]2740 return irq;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2741
Linus Walleijf7ceb362012-06-12 20:19:24 +0200[diff] [blame]2742 err = devm_request_irq(&pdev->dev, irq, dma_irq_handler, IRQF_DISABLED,
2743 "coh901318", base);
2744 if (err)
2745 return err;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2746
2747 err = coh901318_pool_create(&base->pool, &pdev->dev,
2748 sizeof(struct coh901318_lli),
2749 32);
2750 if (err)
Linus Walleijf7ceb362012-06-12 20:19:24 +0200[diff] [blame]2751 return err;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2752
2753 /* init channels for device transfers */
2754 coh901318_base_init(&base->dma_slave, base->platform->chans_slave,
2755 base);
2756
2757 dma_cap_zero(base->dma_slave.cap_mask);
2758 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2759
2760 base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources;
2761 base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources;
2762 base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
Linus Walleij07934482010-03-26 16:50:49 -0700[diff] [blame]2763 base->dma_slave.device_tx_status = coh901318_tx_status;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2764 base->dma_slave.device_issue_pending = coh901318_issue_pending;
Linus Walleijc3635c72010-03-26 16:44:01 -0700[diff] [blame]2765 base->dma_slave.device_control = coh901318_control;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2766 base->dma_slave.dev = &pdev->dev;
2767
2768 err = dma_async_device_register(&base->dma_slave);
2769
2770 if (err)
2771 goto err_register_slave;
2772
2773 /* init channels for memcpy */
2774 coh901318_base_init(&base->dma_memcpy, base->platform->chans_memcpy,
2775 base);
2776
2777 dma_cap_zero(base->dma_memcpy.cap_mask);
2778 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
2779
2780 base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources;
2781 base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources;
2782 base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
Linus Walleij07934482010-03-26 16:50:49 -0700[diff] [blame]2783 base->dma_memcpy.device_tx_status = coh901318_tx_status;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2784 base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
Linus Walleijc3635c72010-03-26 16:44:01 -0700[diff] [blame]2785 base->dma_memcpy.device_control = coh901318_control;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2786 base->dma_memcpy.dev = &pdev->dev;
Linus Walleij516fd432010-03-02 20:12:46 +0100[diff] [blame]2787 /*
2788 * This controller can only access address at even 32bit boundaries,
2789 * i.e. 2^2
2790 */
2791 base->dma_memcpy.copy_align = 2;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2792 err = dma_async_device_register(&base->dma_memcpy);
2793
2794 if (err)
2795 goto err_register_memcpy;
2796
Linus Walleijf7ceb362012-06-12 20:19:24 +0200[diff] [blame]2797 platform_set_drvdata(pdev, base);
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]2798 dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2799 (u32) base->virtbase);
2800
2801 return err;
2802
2803 err_register_memcpy:
2804 dma_async_device_unregister(&base->dma_slave);
2805 err_register_slave:
2806 coh901318_pool_destroy(&base->pool);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2807 return err;
2808}
2809
2810static int __exit coh901318_remove(struct platform_device *pdev)
2811{
2812 struct coh901318_base *base = platform_get_drvdata(pdev);
2813
2814 dma_async_device_unregister(&base->dma_memcpy);
2815 dma_async_device_unregister(&base->dma_slave);
2816 coh901318_pool_destroy(&base->pool);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2817 return 0;
2818}
2819
2820
2821static struct platform_driver coh901318_driver = {
2822 .remove = __exit_p(coh901318_remove),
2823 .driver = {
2824 .name = "coh901318",
2825 },
2826};
2827
2828int __init coh901318_init(void)
2829{
2830 return platform_driver_probe(&coh901318_driver, coh901318_probe);
2831}
Linus Walleija0eb2212011-05-18 14:18:57 +0200[diff] [blame]2832subsys_initcall(coh901318_init);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2833
2834void __exit coh901318_exit(void)
2835{
2836 platform_driver_unregister(&coh901318_driver);
2837}
2838module_exit(coh901318_exit);
2839
2840MODULE_LICENSE("GPL");
2841MODULE_AUTHOR("Per Friden");