blob: 8920eea3452844dfb906fc3f9d6b67a01d37561f [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
4 *
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
6 *
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
9 *
10 * Module name: htab.c
11 *
12 * Description:
13 * PowerPC Hashed Page Table functions
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 */
20
21#undef DEBUG
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +110022#undef DEBUG_LOW
Linus Torvalds1da177e2005-04-16 15:20:36 -070023
Linus Torvalds1da177e2005-04-16 15:20:36 -070024#include <linux/spinlock.h>
25#include <linux/errno.h>
26#include <linux/sched.h>
27#include <linux/proc_fs.h>
28#include <linux/stat.h>
29#include <linux/sysctl.h>
30#include <linux/ctype.h>
31#include <linux/cache.h>
32#include <linux/init.h>
33#include <linux/signal.h>
David S. Millerd9b2b2a2008-02-13 16:56:49 -080034#include <linux/lmb.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070035
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#include <asm/processor.h>
37#include <asm/pgtable.h>
38#include <asm/mmu.h>
39#include <asm/mmu_context.h>
40#include <asm/page.h>
41#include <asm/types.h>
42#include <asm/system.h>
43#include <asm/uaccess.h>
44#include <asm/machdep.h>
David S. Millerd9b2b2a2008-02-13 16:56:49 -080045#include <asm/prom.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070046#include <asm/abs_addr.h>
47#include <asm/tlbflush.h>
48#include <asm/io.h>
49#include <asm/eeh.h>
50#include <asm/tlb.h>
51#include <asm/cacheflush.h>
52#include <asm/cputable.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070053#include <asm/sections.h>
Benjamin Herrenschmidtd0f13e32007-05-08 16:27:27 +100054#include <asm/spu.h>
will schmidtaa39be02007-10-30 06:24:19 +110055#include <asm/udbg.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070056
57#ifdef DEBUG
58#define DBG(fmt...) udbg_printf(fmt)
59#else
60#define DBG(fmt...)
61#endif
62
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +110063#ifdef DEBUG_LOW
64#define DBG_LOW(fmt...) udbg_printf(fmt)
65#else
66#define DBG_LOW(fmt...)
67#endif
68
69#define KB (1024)
70#define MB (1024*KB)
Jon Tollefson658013e2008-07-23 21:27:54 -070071#define GB (1024L*MB)
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +110072
Linus Torvalds1da177e2005-04-16 15:20:36 -070073/*
74 * Note: pte --> Linux PTE
75 * HPTE --> PowerPC Hashed Page Table Entry
76 *
77 * Execution context:
78 * htab_initialize is called with the MMU off (of course), but
79 * the kernel has been copied down to zero so it can directly
80 * reference global data. At this point it is very difficult
81 * to print debug info.
82 *
83 */
84
85#ifdef CONFIG_U3_DART
86extern unsigned long dart_tablebase;
87#endif /* CONFIG_U3_DART */
88
Paul Mackerras799d6042005-11-10 13:37:51 +110089static unsigned long _SDR1;
90struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
91
David Gibson8e561e72007-06-13 14:52:56 +100092struct hash_pte *htab_address;
Michael Ellerman337a7122006-02-21 17:22:55 +110093unsigned long htab_size_bytes;
David Gibson96e28442005-07-13 01:11:42 -070094unsigned long htab_hash_mask;
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +110095int mmu_linear_psize = MMU_PAGE_4K;
96int mmu_virtual_psize = MMU_PAGE_4K;
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +100097int mmu_vmalloc_psize = MMU_PAGE_4K;
Benjamin Herrenschmidtcec08e72008-04-30 15:41:48 +100098#ifdef CONFIG_SPARSEMEM_VMEMMAP
99int mmu_vmemmap_psize = MMU_PAGE_4K;
100#endif
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000101int mmu_io_psize = MMU_PAGE_4K;
Paul Mackerras1189be62007-10-11 20:37:10 +1000102int mmu_kernel_ssize = MMU_SEGSIZE_256M;
103int mmu_highuser_ssize = MMU_SEGSIZE_256M;
Michael Neuling584f8b72007-12-06 17:24:48 +1100104u16 mmu_slb_size = 64;
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100105#ifdef CONFIG_HUGETLB_PAGE
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100106unsigned int HPAGE_SHIFT;
107#endif
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000108#ifdef CONFIG_PPC_64K_PAGES
109int mmu_ci_restrictions;
110#endif
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000111#ifdef CONFIG_DEBUG_PAGEALLOC
112static u8 *linear_map_hash_slots;
113static unsigned long linear_map_hash_count;
Michael Ellermaned166692007-04-18 11:50:09 +1000114static DEFINE_SPINLOCK(linear_map_hash_lock);
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000115#endif /* CONFIG_DEBUG_PAGEALLOC */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700116
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100117/* There are definitions of page sizes arrays to be used when none
118 * is provided by the firmware.
119 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100121/* Pre-POWER4 CPUs (4k pages only)
122 */
Michael Ellerman09de9ff2008-05-08 14:27:07 +1000123static struct mmu_psize_def mmu_psize_defaults_old[] = {
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100124 [MMU_PAGE_4K] = {
125 .shift = 12,
126 .sllp = 0,
127 .penc = 0,
128 .avpnm = 0,
129 .tlbiel = 0,
130 },
131};
132
133/* POWER4, GPUL, POWER5
134 *
135 * Support for 16Mb large pages
136 */
Michael Ellerman09de9ff2008-05-08 14:27:07 +1000137static struct mmu_psize_def mmu_psize_defaults_gp[] = {
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100138 [MMU_PAGE_4K] = {
139 .shift = 12,
140 .sllp = 0,
141 .penc = 0,
142 .avpnm = 0,
143 .tlbiel = 1,
144 },
145 [MMU_PAGE_16M] = {
146 .shift = 24,
147 .sllp = SLB_VSID_L,
148 .penc = 0,
149 .avpnm = 0x1UL,
150 .tlbiel = 0,
151 },
152};
153
Benjamin Herrenschmidtbc033b62008-08-05 16:19:56 +1000154static unsigned long htab_convert_pte_flags(unsigned long pteflags)
155{
156 unsigned long rflags = pteflags & 0x1fa;
157
158 /* _PAGE_EXEC -> NOEXEC */
159 if ((pteflags & _PAGE_EXEC) == 0)
160 rflags |= HPTE_R_N;
161
162 /* PP bits. PAGE_USER is already PP bit 0x2, so we only
163 * need to add in 0x1 if it's a read-only user page
164 */
165 if ((pteflags & _PAGE_USER) && !((pteflags & _PAGE_RW) &&
166 (pteflags & _PAGE_DIRTY)))
167 rflags |= 1;
168
169 /* Always add C */
170 return rflags | HPTE_R_C;
171}
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100172
173int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
Benjamin Herrenschmidtbc033b62008-08-05 16:19:56 +1000174 unsigned long pstart, unsigned long prot,
Paul Mackerras1189be62007-10-11 20:37:10 +1000175 int psize, int ssize)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700176{
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100177 unsigned long vaddr, paddr;
178 unsigned int step, shift;
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100179 int ret = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100181 shift = mmu_psize_defs[psize].shift;
182 step = 1 << shift;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183
Benjamin Herrenschmidtbc033b62008-08-05 16:19:56 +1000184 prot = htab_convert_pte_flags(prot);
185
186 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
187 vstart, vend, pstart, prot, psize, ssize);
188
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100189 for (vaddr = vstart, paddr = pstart; vaddr < vend;
190 vaddr += step, paddr += step) {
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000191 unsigned long hash, hpteg;
Paul Mackerras1189be62007-10-11 20:37:10 +1000192 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
193 unsigned long va = hpt_va(vaddr, vsid, ssize);
Paul Mackerras9e88ba42008-08-30 11:26:27 +1000194 unsigned long tprot = prot;
195
196 /* Make kernel text executable */
197 if (in_kernel_text(vaddr))
198 tprot &= ~HPTE_R_N;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700199
Paul Mackerras1189be62007-10-11 20:37:10 +1000200 hash = hpt_hash(va, shift, ssize);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
202
Michael Ellermanc30a4df2006-06-23 18:16:39 +1000203 BUG_ON(!ppc_md.hpte_insert);
Paul Mackerras9e88ba42008-08-30 11:26:27 +1000204 ret = ppc_md.hpte_insert(hpteg, va, paddr, tprot,
Benjamin Herrenschmidtbc033b62008-08-05 16:19:56 +1000205 HPTE_V_BOLTED, psize, ssize);
Michael Ellermanc30a4df2006-06-23 18:16:39 +1000206
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100207 if (ret < 0)
208 break;
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000209#ifdef CONFIG_DEBUG_PAGEALLOC
210 if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
211 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
212#endif /* CONFIG_DEBUG_PAGEALLOC */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700213 }
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100214 return ret < 0 ? ret : 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215}
216
Stephen Rothwellae86f002008-03-27 16:08:57 +1100217#ifdef CONFIG_MEMORY_HOTPLUG
Badari Pulavarty52db9b42008-03-28 11:37:21 +1100218static int htab_remove_mapping(unsigned long vstart, unsigned long vend,
Badari Pulavartyf8c88032008-01-29 09:19:24 +1100219 int psize, int ssize)
220{
221 unsigned long vaddr;
222 unsigned int step, shift;
223
224 shift = mmu_psize_defs[psize].shift;
225 step = 1 << shift;
226
227 if (!ppc_md.hpte_removebolted) {
Badari Pulavarty52db9b42008-03-28 11:37:21 +1100228 printk(KERN_WARNING "Platform doesn't implement "
229 "hpte_removebolted\n");
230 return -EINVAL;
Badari Pulavartyf8c88032008-01-29 09:19:24 +1100231 }
232
233 for (vaddr = vstart; vaddr < vend; vaddr += step)
234 ppc_md.hpte_removebolted(vaddr, psize, ssize);
Badari Pulavarty52db9b42008-03-28 11:37:21 +1100235
236 return 0;
Badari Pulavartyf8c88032008-01-29 09:19:24 +1100237}
Stephen Rothwellae86f002008-03-27 16:08:57 +1100238#endif /* CONFIG_MEMORY_HOTPLUG */
Badari Pulavartyf8c88032008-01-29 09:19:24 +1100239
Paul Mackerras1189be62007-10-11 20:37:10 +1000240static int __init htab_dt_scan_seg_sizes(unsigned long node,
241 const char *uname, int depth,
242 void *data)
243{
244 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
245 u32 *prop;
246 unsigned long size = 0;
247
248 /* We are scanning "cpu" nodes only */
249 if (type == NULL || strcmp(type, "cpu") != 0)
250 return 0;
251
252 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes",
253 &size);
254 if (prop == NULL)
255 return 0;
256 for (; size >= 4; size -= 4, ++prop) {
257 if (prop[0] == 40) {
258 DBG("1T segment support detected\n");
259 cur_cpu_spec->cpu_features |= CPU_FTR_1T_SEGMENT;
Olof Johanssonf5534002007-10-12 16:44:55 +1000260 return 1;
Paul Mackerras1189be62007-10-11 20:37:10 +1000261 }
Paul Mackerras1189be62007-10-11 20:37:10 +1000262 }
Olof Johanssonf66bce52007-10-16 00:58:59 +1000263 cur_cpu_spec->cpu_features &= ~CPU_FTR_NO_SLBIE_B;
Paul Mackerras1189be62007-10-11 20:37:10 +1000264 return 0;
265}
266
267static void __init htab_init_seg_sizes(void)
268{
269 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
270}
271
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100272static int __init htab_dt_scan_page_sizes(unsigned long node,
273 const char *uname, int depth,
274 void *data)
275{
276 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
277 u32 *prop;
278 unsigned long size = 0;
279
280 /* We are scanning "cpu" nodes only */
281 if (type == NULL || strcmp(type, "cpu") != 0)
282 return 0;
283
284 prop = (u32 *)of_get_flat_dt_prop(node,
285 "ibm,segment-page-sizes", &size);
286 if (prop != NULL) {
287 DBG("Page sizes from device-tree:\n");
288 size /= 4;
289 cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE);
290 while(size > 0) {
291 unsigned int shift = prop[0];
292 unsigned int slbenc = prop[1];
293 unsigned int lpnum = prop[2];
294 unsigned int lpenc = 0;
295 struct mmu_psize_def *def;
296 int idx = -1;
297
298 size -= 3; prop += 3;
299 while(size > 0 && lpnum) {
300 if (prop[0] == shift)
301 lpenc = prop[1];
302 prop += 2; size -= 2;
303 lpnum--;
304 }
305 switch(shift) {
306 case 0xc:
307 idx = MMU_PAGE_4K;
308 break;
309 case 0x10:
310 idx = MMU_PAGE_64K;
311 break;
312 case 0x14:
313 idx = MMU_PAGE_1M;
314 break;
315 case 0x18:
316 idx = MMU_PAGE_16M;
317 cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE;
318 break;
319 case 0x22:
320 idx = MMU_PAGE_16G;
321 break;
322 }
323 if (idx < 0)
324 continue;
325 def = &mmu_psize_defs[idx];
326 def->shift = shift;
327 if (shift <= 23)
328 def->avpnm = 0;
329 else
330 def->avpnm = (1 << (shift - 23)) - 1;
331 def->sllp = slbenc;
332 def->penc = lpenc;
333 /* We don't know for sure what's up with tlbiel, so
334 * for now we only set it for 4K and 64K pages
335 */
336 if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)
337 def->tlbiel = 1;
338 else
339 def->tlbiel = 0;
340
341 DBG(" %d: shift=%02x, sllp=%04x, avpnm=%08x, "
342 "tlbiel=%d, penc=%d\n",
343 idx, shift, def->sllp, def->avpnm, def->tlbiel,
344 def->penc);
345 }
346 return 1;
347 }
348 return 0;
349}
350
Jon Tollefson658013e2008-07-23 21:27:54 -0700351/* Scan for 16G memory blocks that have been set aside for huge pages
352 * and reserve those blocks for 16G huge pages.
353 */
354static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
355 const char *uname, int depth,
356 void *data) {
357 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
358 unsigned long *addr_prop;
359 u32 *page_count_prop;
360 unsigned int expected_pages;
361 long unsigned int phys_addr;
362 long unsigned int block_size;
363
364 /* We are scanning "memory" nodes only */
365 if (type == NULL || strcmp(type, "memory") != 0)
366 return 0;
367
368 /* This property is the log base 2 of the number of virtual pages that
369 * will represent this memory block. */
370 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
371 if (page_count_prop == NULL)
372 return 0;
373 expected_pages = (1 << page_count_prop[0]);
374 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
375 if (addr_prop == NULL)
376 return 0;
377 phys_addr = addr_prop[0];
378 block_size = addr_prop[1];
379 if (block_size != (16 * GB))
380 return 0;
381 printk(KERN_INFO "Huge page(16GB) memory: "
382 "addr = 0x%lX size = 0x%lX pages = %d\n",
383 phys_addr, block_size, expected_pages);
384 lmb_reserve(phys_addr, block_size * expected_pages);
385 add_gpage(phys_addr, block_size, expected_pages);
386 return 0;
387}
388
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100389static void __init htab_init_page_sizes(void)
390{
391 int rc;
392
393 /* Default to 4K pages only */
394 memcpy(mmu_psize_defs, mmu_psize_defaults_old,
395 sizeof(mmu_psize_defaults_old));
396
397 /*
398 * Try to find the available page sizes in the device-tree
399 */
400 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
401 if (rc != 0) /* Found */
402 goto found;
403
404 /*
405 * Not in the device-tree, let's fallback on known size
406 * list for 16M capable GP & GR
407 */
Stephen Rothwell04704662006-11-30 11:46:22 +1100408 if (cpu_has_feature(CPU_FTR_16M_PAGE))
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100409 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
410 sizeof(mmu_psize_defaults_gp));
411 found:
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000412#ifndef CONFIG_DEBUG_PAGEALLOC
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100413 /*
414 * Pick a size for the linear mapping. Currently, we only support
415 * 16M, 1M and 4K which is the default
416 */
417 if (mmu_psize_defs[MMU_PAGE_16M].shift)
418 mmu_linear_psize = MMU_PAGE_16M;
419 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
420 mmu_linear_psize = MMU_PAGE_1M;
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000421#endif /* CONFIG_DEBUG_PAGEALLOC */
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100422
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000423#ifdef CONFIG_PPC_64K_PAGES
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100424 /*
425 * Pick a size for the ordinary pages. Default is 4K, we support
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000426 * 64K for user mappings and vmalloc if supported by the processor.
427 * We only use 64k for ioremap if the processor
428 * (and firmware) support cache-inhibited large pages.
429 * If not, we use 4k and set mmu_ci_restrictions so that
430 * hash_page knows to switch processes that use cache-inhibited
431 * mappings to 4k pages.
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100432 */
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000433 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100434 mmu_virtual_psize = MMU_PAGE_64K;
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000435 mmu_vmalloc_psize = MMU_PAGE_64K;
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000436 if (mmu_linear_psize == MMU_PAGE_4K)
437 mmu_linear_psize = MMU_PAGE_64K;
Paul Mackerrascfe666b2008-03-24 17:41:22 +1100438 if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE)) {
439 /*
440 * Don't use 64k pages for ioremap on pSeries, since
441 * that would stop us accessing the HEA ethernet.
442 */
443 if (!machine_is(pseries))
444 mmu_io_psize = MMU_PAGE_64K;
445 } else
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000446 mmu_ci_restrictions = 1;
447 }
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000448#endif /* CONFIG_PPC_64K_PAGES */
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100449
Benjamin Herrenschmidtcec08e72008-04-30 15:41:48 +1000450#ifdef CONFIG_SPARSEMEM_VMEMMAP
451 /* We try to use 16M pages for vmemmap if that is supported
452 * and we have at least 1G of RAM at boot
453 */
454 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
455 lmb_phys_mem_size() >= 0x40000000)
456 mmu_vmemmap_psize = MMU_PAGE_16M;
457 else if (mmu_psize_defs[MMU_PAGE_64K].shift)
458 mmu_vmemmap_psize = MMU_PAGE_64K;
459 else
460 mmu_vmemmap_psize = MMU_PAGE_4K;
461#endif /* CONFIG_SPARSEMEM_VMEMMAP */
462
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000463 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
Benjamin Herrenschmidtcec08e72008-04-30 15:41:48 +1000464 "virtual = %d, io = %d"
465#ifdef CONFIG_SPARSEMEM_VMEMMAP
466 ", vmemmap = %d"
467#endif
468 "\n",
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100469 mmu_psize_defs[mmu_linear_psize].shift,
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000470 mmu_psize_defs[mmu_virtual_psize].shift,
Benjamin Herrenschmidtcec08e72008-04-30 15:41:48 +1000471 mmu_psize_defs[mmu_io_psize].shift
472#ifdef CONFIG_SPARSEMEM_VMEMMAP
473 ,mmu_psize_defs[mmu_vmemmap_psize].shift
474#endif
475 );
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100476
477#ifdef CONFIG_HUGETLB_PAGE
Jon Tollefson658013e2008-07-23 21:27:54 -0700478 /* Reserve 16G huge page memory sections for huge pages */
479 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
480
Jon Tollefson0d9ea752008-07-23 21:27:56 -0700481/* Set default large page size. Currently, we pick 16M or 1M depending
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100482 * on what is available
483 */
484 if (mmu_psize_defs[MMU_PAGE_16M].shift)
Jon Tollefson0d9ea752008-07-23 21:27:56 -0700485 HPAGE_SHIFT = mmu_psize_defs[MMU_PAGE_16M].shift;
David Gibson7d24f0b2005-11-07 00:57:52 -0800486 /* With 4k/4level pagetables, we can't (for now) cope with a
487 * huge page size < PMD_SIZE */
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100488 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
Jon Tollefson0d9ea752008-07-23 21:27:56 -0700489 HPAGE_SHIFT = mmu_psize_defs[MMU_PAGE_1M].shift;
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100490#endif /* CONFIG_HUGETLB_PAGE */
491}
492
493static int __init htab_dt_scan_pftsize(unsigned long node,
494 const char *uname, int depth,
495 void *data)
496{
497 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
498 u32 *prop;
499
500 /* We are scanning "cpu" nodes only */
501 if (type == NULL || strcmp(type, "cpu") != 0)
502 return 0;
503
504 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
505 if (prop != NULL) {
506 /* pft_size[0] is the NUMA CEC cookie */
507 ppc64_pft_size = prop[1];
508 return 1;
509 }
510 return 0;
511}
512
513static unsigned long __init htab_get_table_size(void)
Paul Mackerras3eac8c62005-10-12 16:58:53 +1000514{
Paul Mackerras799d6042005-11-10 13:37:51 +1100515 unsigned long mem_size, rnd_mem_size, pteg_count;
Paul Mackerras3eac8c62005-10-12 16:58:53 +1000516
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100517 /* If hash size isn't already provided by the platform, we try to
Adrian Bunk943ffb52006-01-10 00:10:13 +0100518 * retrieve it from the device-tree. If it's not there neither, we
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100519 * calculate it now based on the total RAM size
Paul Mackerras3eac8c62005-10-12 16:58:53 +1000520 */
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100521 if (ppc64_pft_size == 0)
522 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
Paul Mackerras3eac8c62005-10-12 16:58:53 +1000523 if (ppc64_pft_size)
524 return 1UL << ppc64_pft_size;
525
526 /* round mem_size up to next power of 2 */
Paul Mackerras799d6042005-11-10 13:37:51 +1100527 mem_size = lmb_phys_mem_size();
528 rnd_mem_size = 1UL << __ilog2(mem_size);
529 if (rnd_mem_size < mem_size)
Paul Mackerras3eac8c62005-10-12 16:58:53 +1000530 rnd_mem_size <<= 1;
531
532 /* # pages / 2 */
533 pteg_count = max(rnd_mem_size >> (12 + 1), 1UL << 11);
534
535 return pteg_count << 7;
536}
537
Mike Kravetz54b79242005-11-07 16:25:48 -0800538#ifdef CONFIG_MEMORY_HOTPLUG
539void create_section_mapping(unsigned long start, unsigned long end)
540{
Benjamin Herrenschmidtbc033b62008-08-05 16:19:56 +1000541 BUG_ON(htab_bolt_mapping(start, end, __pa(start),
542 PAGE_KERNEL, mmu_linear_psize,
543 mmu_kernel_ssize));
Mike Kravetz54b79242005-11-07 16:25:48 -0800544}
Badari Pulavartyf8c88032008-01-29 09:19:24 +1100545
Badari Pulavarty52db9b42008-03-28 11:37:21 +1100546int remove_section_mapping(unsigned long start, unsigned long end)
Badari Pulavartyf8c88032008-01-29 09:19:24 +1100547{
Badari Pulavarty52db9b42008-03-28 11:37:21 +1100548 return htab_remove_mapping(start, end, mmu_linear_psize,
549 mmu_kernel_ssize);
Badari Pulavartyf8c88032008-01-29 09:19:24 +1100550}
Mike Kravetz54b79242005-11-07 16:25:48 -0800551#endif /* CONFIG_MEMORY_HOTPLUG */
552
Michael Ellerman7d0daae2006-06-23 18:16:38 +1000553static inline void make_bl(unsigned int *insn_addr, void *func)
554{
555 unsigned long funcp = *((unsigned long *)func);
556 int offset = funcp - (unsigned long)insn_addr;
557
558 *insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc));
559 flush_icache_range((unsigned long)insn_addr, 4+
560 (unsigned long)insn_addr);
561}
562
563static void __init htab_finish_init(void)
564{
565 extern unsigned int *htab_call_hpte_insert1;
566 extern unsigned int *htab_call_hpte_insert2;
567 extern unsigned int *htab_call_hpte_remove;
568 extern unsigned int *htab_call_hpte_updatepp;
569
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +1000570#ifdef CONFIG_PPC_HAS_HASH_64K
Michael Ellerman7d0daae2006-06-23 18:16:38 +1000571 extern unsigned int *ht64_call_hpte_insert1;
572 extern unsigned int *ht64_call_hpte_insert2;
573 extern unsigned int *ht64_call_hpte_remove;
574 extern unsigned int *ht64_call_hpte_updatepp;
575
576 make_bl(ht64_call_hpte_insert1, ppc_md.hpte_insert);
577 make_bl(ht64_call_hpte_insert2, ppc_md.hpte_insert);
578 make_bl(ht64_call_hpte_remove, ppc_md.hpte_remove);
579 make_bl(ht64_call_hpte_updatepp, ppc_md.hpte_updatepp);
Jon Tollefson5b825832007-05-17 04:43:02 +1000580#endif /* CONFIG_PPC_HAS_HASH_64K */
Michael Ellerman7d0daae2006-06-23 18:16:38 +1000581
582 make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert);
583 make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert);
584 make_bl(htab_call_hpte_remove, ppc_md.hpte_remove);
585 make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp);
586}
587
Linus Torvalds1da177e2005-04-16 15:20:36 -0700588void __init htab_initialize(void)
589{
Michael Ellerman337a7122006-02-21 17:22:55 +1100590 unsigned long table;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700591 unsigned long pteg_count;
Paul Mackerras9e88ba42008-08-30 11:26:27 +1000592 unsigned long prot;
Michael Ellerman41d824b2008-01-30 01:13:59 +1100593 unsigned long base = 0, size = 0, limit;
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100594 int i;
595
Linus Torvalds1da177e2005-04-16 15:20:36 -0700596 DBG(" -> htab_initialize()\n");
597
Paul Mackerras1189be62007-10-11 20:37:10 +1000598 /* Initialize segment sizes */
599 htab_init_seg_sizes();
600
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100601 /* Initialize page sizes */
602 htab_init_page_sizes();
603
Paul Mackerras1189be62007-10-11 20:37:10 +1000604 if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) {
605 mmu_kernel_ssize = MMU_SEGSIZE_1T;
606 mmu_highuser_ssize = MMU_SEGSIZE_1T;
607 printk(KERN_INFO "Using 1TB segments\n");
608 }
609
Linus Torvalds1da177e2005-04-16 15:20:36 -0700610 /*
611 * Calculate the required size of the htab. We want the number of
612 * PTEGs to equal one half the number of real pages.
613 */
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100614 htab_size_bytes = htab_get_table_size();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700615 pteg_count = htab_size_bytes >> 7;
616
Linus Torvalds1da177e2005-04-16 15:20:36 -0700617 htab_hash_mask = pteg_count - 1;
618
Michael Ellerman57cfb812006-03-21 20:45:59 +1100619 if (firmware_has_feature(FW_FEATURE_LPAR)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700620 /* Using a hypervisor which owns the htab */
621 htab_address = NULL;
622 _SDR1 = 0;
623 } else {
624 /* Find storage for the HPT. Must be contiguous in
Michael Ellerman41d824b2008-01-30 01:13:59 +1100625 * the absolute address space. On cell we want it to be
Michael Ellerman31bf1112008-03-12 18:03:24 +1100626 * in the first 2 Gig so we can use it for IOMMU hacks.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627 */
Michael Ellerman41d824b2008-01-30 01:13:59 +1100628 if (machine_is(cell))
Michael Ellerman31bf1112008-03-12 18:03:24 +1100629 limit = 0x80000000;
Michael Ellerman41d824b2008-01-30 01:13:59 +1100630 else
631 limit = 0;
632
633 table = lmb_alloc_base(htab_size_bytes, htab_size_bytes, limit);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700634
635 DBG("Hash table allocated at %lx, size: %lx\n", table,
636 htab_size_bytes);
637
Linus Torvalds1da177e2005-04-16 15:20:36 -0700638 htab_address = abs_to_virt(table);
639
640 /* htab absolute addr + encoded htabsize */
641 _SDR1 = table + __ilog2(pteg_count) - 11;
642
643 /* Initialize the HPT with no entries */
644 memset((void *)table, 0, htab_size_bytes);
Paul Mackerras799d6042005-11-10 13:37:51 +1100645
646 /* Set SDR1 */
647 mtspr(SPRN_SDR1, _SDR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700648 }
649
Benjamin Herrenschmidtbc033b62008-08-05 16:19:56 +1000650 prot = PAGE_KERNEL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700651
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +1000652#ifdef CONFIG_DEBUG_PAGEALLOC
653 linear_map_hash_count = lmb_end_of_DRAM() >> PAGE_SHIFT;
654 linear_map_hash_slots = __va(lmb_alloc_base(linear_map_hash_count,
655 1, lmb.rmo_size));
656 memset(linear_map_hash_slots, 0, linear_map_hash_count);
657#endif /* CONFIG_DEBUG_PAGEALLOC */
658
Linus Torvalds1da177e2005-04-16 15:20:36 -0700659 /* On U3 based machines, we need to reserve the DART area and
660 * _NOT_ map it to avoid cache paradoxes as it's remapped non
661 * cacheable later on
662 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700663
664 /* create bolted the linear mapping in the hash table */
665 for (i=0; i < lmb.memory.cnt; i++) {
Michael Ellermanb5666f72005-12-05 10:24:33 -0600666 base = (unsigned long)__va(lmb.memory.region[i].base);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700667 size = lmb.memory.region[i].size;
668
Benjamin Herrenschmidtbc033b62008-08-05 16:19:56 +1000669 DBG("creating mapping for region: %lx..%lx (prot: %x)\n",
Paul Mackerras9e88ba42008-08-30 11:26:27 +1000670 base, size, prot);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700671
672#ifdef CONFIG_U3_DART
673 /* Do not map the DART space. Fortunately, it will be aligned
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100674 * in such a way that it will not cross two lmb regions and
675 * will fit within a single 16Mb page.
676 * The DART space is assumed to be a full 16Mb region even if
677 * we only use 2Mb of that space. We will use more of it later
678 * for AGP GART. We have to use a full 16Mb large page.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700679 */
680 DBG("DART base: %lx\n", dart_tablebase);
681
682 if (dart_tablebase != 0 && dart_tablebase >= base
683 && dart_tablebase < (base + size)) {
Michael Ellermancaf80e52006-03-21 20:45:51 +1100684 unsigned long dart_table_end = dart_tablebase + 16 * MB;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700685 if (base != dart_tablebase)
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100686 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
Paul Mackerras9e88ba42008-08-30 11:26:27 +1000687 __pa(base), prot,
Paul Mackerras1189be62007-10-11 20:37:10 +1000688 mmu_linear_psize,
689 mmu_kernel_ssize));
Michael Ellermancaf80e52006-03-21 20:45:51 +1100690 if ((base + size) > dart_table_end)
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100691 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
Michael Ellermancaf80e52006-03-21 20:45:51 +1100692 base + size,
693 __pa(dart_table_end),
Paul Mackerras9e88ba42008-08-30 11:26:27 +1000694 prot,
Paul Mackerras1189be62007-10-11 20:37:10 +1000695 mmu_linear_psize,
696 mmu_kernel_ssize));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700697 continue;
698 }
699#endif /* CONFIG_U3_DART */
Michael Ellermancaf80e52006-03-21 20:45:51 +1100700 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
Paul Mackerras9e88ba42008-08-30 11:26:27 +1000701 prot, mmu_linear_psize, mmu_kernel_ssize));
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100702 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700703
704 /*
705 * If we have a memory_limit and we've allocated TCEs then we need to
706 * explicitly map the TCE area at the top of RAM. We also cope with the
707 * case that the TCEs start below memory_limit.
708 * tce_alloc_start/end are 16MB aligned so the mapping should work
709 * for either 4K or 16MB pages.
710 */
711 if (tce_alloc_start) {
Michael Ellermanb5666f72005-12-05 10:24:33 -0600712 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
713 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700714
715 if (base + size >= tce_alloc_start)
716 tce_alloc_start = base + size + 1;
717
Michael Ellermancaf80e52006-03-21 20:45:51 +1100718 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
Benjamin Herrenschmidtbc033b62008-08-05 16:19:56 +1000719 __pa(tce_alloc_start), prot,
Paul Mackerras1189be62007-10-11 20:37:10 +1000720 mmu_linear_psize, mmu_kernel_ssize));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700721 }
722
Michael Ellerman7d0daae2006-06-23 18:16:38 +1000723 htab_finish_init();
724
Linus Torvalds1da177e2005-04-16 15:20:36 -0700725 DBG(" <- htab_initialize()\n");
726}
727#undef KB
728#undef MB
Linus Torvalds1da177e2005-04-16 15:20:36 -0700729
Anton Blancharde597cb322005-12-29 10:46:29 +1100730void htab_initialize_secondary(void)
Paul Mackerras799d6042005-11-10 13:37:51 +1100731{
Michael Ellerman57cfb812006-03-21 20:45:59 +1100732 if (!firmware_has_feature(FW_FEATURE_LPAR))
Paul Mackerras799d6042005-11-10 13:37:51 +1100733 mtspr(SPRN_SDR1, _SDR1);
734}
735
Linus Torvalds1da177e2005-04-16 15:20:36 -0700736/*
737 * Called by asm hashtable.S for doing lazy icache flush
738 */
739unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
740{
741 struct page *page;
742
Benjamin Herrenschmidt76c8e252005-11-08 11:21:05 +1100743 if (!pfn_valid(pte_pfn(pte)))
744 return pp;
745
Linus Torvalds1da177e2005-04-16 15:20:36 -0700746 page = pte_page(pte);
747
748 /* page is dirty */
749 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
750 if (trap == 0x400) {
751 __flush_dcache_icache(page_address(page));
752 set_bit(PG_arch_1, &page->flags);
753 } else
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100754 pp |= HPTE_R_N;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700755 }
756 return pp;
757}
758
Paul Mackerras3a8247c2008-06-18 15:29:12 +1000759#ifdef CONFIG_PPC_MM_SLICES
760unsigned int get_paca_psize(unsigned long addr)
761{
762 unsigned long index, slices;
763
764 if (addr < SLICE_LOW_TOP) {
765 slices = get_paca()->context.low_slices_psize;
766 index = GET_LOW_SLICE_INDEX(addr);
767 } else {
768 slices = get_paca()->context.high_slices_psize;
769 index = GET_HIGH_SLICE_INDEX(addr);
770 }
771 return (slices >> (index * 4)) & 0xF;
772}
773
774#else
775unsigned int get_paca_psize(unsigned long addr)
776{
777 return get_paca()->context.user_psize;
778}
779#endif
780
Paul Mackerras721151d2007-04-03 21:24:02 +1000781/*
782 * Demote a segment to using 4k pages.
783 * For now this makes the whole process use 4k pages.
784 */
Paul Mackerras721151d2007-04-03 21:24:02 +1000785#ifdef CONFIG_PPC_64K_PAGES
Paul Mackerrasfa282372008-01-24 08:35:13 +1100786void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
Benjamin Herrenschmidt16f1c742007-05-08 16:27:27 +1000787{
Paul Mackerras3a8247c2008-06-18 15:29:12 +1000788 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
Paul Mackerras721151d2007-04-03 21:24:02 +1000789 return;
Paul Mackerras3a8247c2008-06-18 15:29:12 +1000790 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
Geert Uytterhoeven1e57ba82007-07-17 02:35:38 +1000791#ifdef CONFIG_SPU_BASE
Paul Mackerras721151d2007-04-03 21:24:02 +1000792 spu_flush_all_slbs(mm);
793#endif
Paul Mackerras3a8247c2008-06-18 15:29:12 +1000794 if (get_paca_psize(addr) != MMU_PAGE_4K) {
Paul Mackerrasfa282372008-01-24 08:35:13 +1100795 get_paca()->context = mm->context;
796 slb_flush_and_rebolt();
797 }
Paul Mackerras721151d2007-04-03 21:24:02 +1000798}
Benjamin Herrenschmidt16f1c742007-05-08 16:27:27 +1000799#endif /* CONFIG_PPC_64K_PAGES */
Paul Mackerras721151d2007-04-03 21:24:02 +1000800
Paul Mackerrasfa282372008-01-24 08:35:13 +1100801#ifdef CONFIG_PPC_SUBPAGE_PROT
802/*
803 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
804 * Userspace sets the subpage permissions using the subpage_prot system call.
805 *
806 * Result is 0: full permissions, _PAGE_RW: read-only,
807 * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
808 */
809static int subpage_protection(pgd_t *pgdir, unsigned long ea)
810{
811 struct subpage_prot_table *spt = pgd_subpage_prot(pgdir);
812 u32 spp = 0;
813 u32 **sbpm, *sbpp;
814
815 if (ea >= spt->maxaddr)
816 return 0;
817 if (ea < 0x100000000) {
818 /* addresses below 4GB use spt->low_prot */
819 sbpm = spt->low_prot;
820 } else {
821 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
822 if (!sbpm)
823 return 0;
824 }
825 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
826 if (!sbpp)
827 return 0;
828 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
829
830 /* extract 2-bit bitfield for this 4k subpage */
831 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
832
833 /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
834 spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0);
835 return spp;
836}
837
838#else /* CONFIG_PPC_SUBPAGE_PROT */
839static inline int subpage_protection(pgd_t *pgdir, unsigned long ea)
840{
841 return 0;
842}
843#endif
844
Linus Torvalds1da177e2005-04-16 15:20:36 -0700845/* Result code is:
846 * 0 - handled
847 * 1 - normal page fault
848 * -1 - critical hash insertion error
Paul Mackerrasfa282372008-01-24 08:35:13 +1100849 * -2 - access not permitted by subpage protection mechanism
Linus Torvalds1da177e2005-04-16 15:20:36 -0700850 */
851int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
852{
853 void *pgdir;
854 unsigned long vsid;
855 struct mm_struct *mm;
856 pte_t *ptep;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700857 cpumask_t tmp;
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100858 int rc, user_region = 0, local = 0;
Paul Mackerras1189be62007-10-11 20:37:10 +1000859 int psize, ssize;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700860
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100861 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
862 ea, access, trap);
David Gibson1f8d4192005-05-05 16:15:13 -0700863
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100864 if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) {
865 DBG_LOW(" out of pgtable range !\n");
866 return 1;
867 }
868
869 /* Get region & vsid */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700870 switch (REGION_ID(ea)) {
871 case USER_REGION_ID:
872 user_region = 1;
873 mm = current->mm;
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100874 if (! mm) {
875 DBG_LOW(" user region with no mm !\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876 return 1;
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100877 }
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +1000878 psize = get_slice_psize(mm, ea);
Paul Mackerras1189be62007-10-11 20:37:10 +1000879 ssize = user_segment_size(ea);
880 vsid = get_vsid(mm->context.id, ea, ssize);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700881 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700882 case VMALLOC_REGION_ID:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700883 mm = &init_mm;
Paul Mackerras1189be62007-10-11 20:37:10 +1000884 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000885 if (ea < VMALLOC_END)
886 psize = mmu_vmalloc_psize;
887 else
888 psize = mmu_io_psize;
Paul Mackerras1189be62007-10-11 20:37:10 +1000889 ssize = mmu_kernel_ssize;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700890 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700891 default:
892 /* Not a valid range
893 * Send the problem up to do_page_fault
894 */
895 return 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700896 }
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100897 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700898
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100899 /* Get pgdir */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700900 pgdir = mm->pgd;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700901 if (pgdir == NULL)
902 return 1;
903
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100904 /* Check CPU locality */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700905 tmp = cpumask_of_cpu(smp_processor_id());
906 if (user_region && cpus_equal(mm->cpu_vm_mask, tmp))
907 local = 1;
908
Benjamin Herrenschmidtd0f13e32007-05-08 16:27:27 +1000909#ifdef CONFIG_HUGETLB_PAGE
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100910 /* Handle hugepage regions */
Jon Tollefson0d9ea752008-07-23 21:27:56 -0700911 if (HPAGE_SHIFT && mmu_huge_psizes[psize]) {
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100912 DBG_LOW(" -> huge page !\n");
David Gibsoncbf52af2005-12-09 14:20:52 +1100913 return hash_huge_page(mm, access, ea, vsid, local, trap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700914 }
Benjamin Herrenschmidtd0f13e32007-05-08 16:27:27 +1000915#endif /* CONFIG_HUGETLB_PAGE */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700916
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +1000917#ifndef CONFIG_PPC_64K_PAGES
918 /* If we use 4K pages and our psize is not 4K, then we are hitting
919 * a special driver mapping, we need to align the address before
920 * we fetch the PTE
921 */
922 if (psize != MMU_PAGE_4K)
923 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
924#endif /* CONFIG_PPC_64K_PAGES */
925
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100926 /* Get PTE and page size from page tables */
927 ptep = find_linux_pte(pgdir, ea);
928 if (ptep == NULL || !pte_present(*ptep)) {
929 DBG_LOW(" no PTE !\n");
930 return 1;
931 }
932
933#ifndef CONFIG_PPC_64K_PAGES
934 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
935#else
936 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
937 pte_val(*(ptep + PTRS_PER_PTE)));
938#endif
939 /* Pre-check access permissions (will be re-checked atomically
940 * in __hash_page_XX but this pre-check is a fast path
941 */
942 if (access & ~pte_val(*ptep)) {
943 DBG_LOW(" no access !\n");
944 return 1;
945 }
946
947 /* Do actual hashing */
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +1000948#ifdef CONFIG_PPC_64K_PAGES
Paul Mackerras721151d2007-04-03 21:24:02 +1000949 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
Paul Mackerras3a8247c2008-06-18 15:29:12 +1000950 if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
Paul Mackerras721151d2007-04-03 21:24:02 +1000951 demote_segment_4k(mm, ea);
952 psize = MMU_PAGE_4K;
953 }
954
Benjamin Herrenschmidt16f1c742007-05-08 16:27:27 +1000955 /* If this PTE is non-cacheable and we have restrictions on
956 * using non cacheable large pages, then we switch to 4k
957 */
958 if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
959 (pte_val(*ptep) & _PAGE_NO_CACHE)) {
960 if (user_region) {
961 demote_segment_4k(mm, ea);
962 psize = MMU_PAGE_4K;
963 } else if (ea < VMALLOC_END) {
964 /*
965 * some driver did a non-cacheable mapping
966 * in vmalloc space, so switch vmalloc
967 * to 4k pages
968 */
969 printk(KERN_ALERT "Reducing vmalloc segment "
970 "to 4kB pages because of "
971 "non-cacheable mapping\n");
972 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
Geert Uytterhoeven1e57ba82007-07-17 02:35:38 +1000973#ifdef CONFIG_SPU_BASE
Benjamin Herrenschmidt94b2a432007-03-10 00:05:37 +0100974 spu_flush_all_slbs(mm);
975#endif
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000976 }
Benjamin Herrenschmidt16f1c742007-05-08 16:27:27 +1000977 }
978 if (user_region) {
Paul Mackerras3a8247c2008-06-18 15:29:12 +1000979 if (psize != get_paca_psize(ea)) {
Benjamin Herrenschmidtf6ab0b92007-10-29 12:05:18 +1100980 get_paca()->context = mm->context;
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000981 slb_flush_and_rebolt();
982 }
Benjamin Herrenschmidt16f1c742007-05-08 16:27:27 +1000983 } else if (get_paca()->vmalloc_sllp !=
984 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
985 get_paca()->vmalloc_sllp =
986 mmu_psize_defs[mmu_vmalloc_psize].sllp;
Michael Neuling67439b72007-08-03 11:55:39 +1000987 slb_vmalloc_update();
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000988 }
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +1000989#endif /* CONFIG_PPC_64K_PAGES */
Benjamin Herrenschmidt16f1c742007-05-08 16:27:27 +1000990
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +1000991#ifdef CONFIG_PPC_HAS_HASH_64K
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +1000992 if (psize == MMU_PAGE_64K)
Paul Mackerras1189be62007-10-11 20:37:10 +1000993 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100994 else
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +1000995#endif /* CONFIG_PPC_HAS_HASH_64K */
Paul Mackerrasfa282372008-01-24 08:35:13 +1100996 {
997 int spp = subpage_protection(pgdir, ea);
998 if (access & spp)
999 rc = -2;
1000 else
1001 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1002 local, ssize, spp);
1003 }
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001004
1005#ifndef CONFIG_PPC_64K_PAGES
1006 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1007#else
1008 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1009 pte_val(*(ptep + PTRS_PER_PTE)));
1010#endif
1011 DBG_LOW(" -> rc=%d\n", rc);
1012 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001013}
Arnd Bergmann67207b92005-11-15 15:53:48 -05001014EXPORT_SYMBOL_GPL(hash_page);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001015
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001016void hash_preload(struct mm_struct *mm, unsigned long ea,
1017 unsigned long access, unsigned long trap)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001018{
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001019 unsigned long vsid;
1020 void *pgdir;
1021 pte_t *ptep;
1022 cpumask_t mask;
1023 unsigned long flags;
1024 int local = 0;
Paul Mackerras1189be62007-10-11 20:37:10 +10001025 int ssize;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001026
Benjamin Herrenschmidtd0f13e32007-05-08 16:27:27 +10001027 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1028
1029#ifdef CONFIG_PPC_MM_SLICES
1030 /* We only prefault standard pages for now */
Ilpo Järvinen2b02d132007-08-16 08:03:35 +10001031 if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001032 return;
Benjamin Herrenschmidtd0f13e32007-05-08 16:27:27 +10001033#endif
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001034
1035 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1036 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1037
Benjamin Herrenschmidt16f1c742007-05-08 16:27:27 +10001038 /* Get Linux PTE if available */
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001039 pgdir = mm->pgd;
1040 if (pgdir == NULL)
1041 return;
1042 ptep = find_linux_pte(pgdir, ea);
1043 if (!ptep)
1044 return;
Benjamin Herrenschmidt16f1c742007-05-08 16:27:27 +10001045
1046#ifdef CONFIG_PPC_64K_PAGES
1047 /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
1048 * a 64K kernel), then we don't preload, hash_page() will take
1049 * care of it once we actually try to access the page.
1050 * That way we don't have to duplicate all of the logic for segment
1051 * page size demotion here
1052 */
1053 if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
1054 return;
1055#endif /* CONFIG_PPC_64K_PAGES */
1056
1057 /* Get VSID */
Paul Mackerras1189be62007-10-11 20:37:10 +10001058 ssize = user_segment_size(ea);
1059 vsid = get_vsid(mm->context.id, ea, ssize);
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001060
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +10001061 /* Hash doesn't like irqs */
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001062 local_irq_save(flags);
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +10001063
1064 /* Is that local to this CPU ? */
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001065 mask = cpumask_of_cpu(smp_processor_id());
1066 if (cpus_equal(mm->cpu_vm_mask, mask))
1067 local = 1;
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +10001068
1069 /* Hash it in */
1070#ifdef CONFIG_PPC_HAS_HASH_64K
Paul Mackerrasbf72aeb2006-06-15 10:45:18 +10001071 if (mm->context.user_psize == MMU_PAGE_64K)
Paul Mackerras1189be62007-10-11 20:37:10 +10001072 __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001073 else
Jon Tollefson5b825832007-05-17 04:43:02 +10001074#endif /* CONFIG_PPC_HAS_HASH_64K */
Paul Mackerrasfa282372008-01-24 08:35:13 +11001075 __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
1076 subpage_protection(pgdir, ea));
Benjamin Herrenschmidt16c2d472007-05-08 16:27:28 +10001077
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001078 local_irq_restore(flags);
1079}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001080
Benjamin Herrenschmidtf6ab0b92007-10-29 12:05:18 +11001081/* WARNING: This is called from hash_low_64.S, if you change this prototype,
1082 * do not forget to update the assembly call site !
1083 */
Paul Mackerras1189be62007-10-11 20:37:10 +10001084void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
1085 int local)
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001086{
1087 unsigned long hash, index, shift, hidx, slot;
1088
1089 DBG_LOW("flush_hash_page(va=%016x)\n", va);
1090 pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
Paul Mackerras1189be62007-10-11 20:37:10 +10001091 hash = hpt_hash(va, shift, ssize);
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001092 hidx = __rpte_to_hidx(pte, index);
1093 if (hidx & _PTEIDX_SECONDARY)
1094 hash = ~hash;
1095 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1096 slot += hidx & _PTEIDX_GROUP_IX;
1097 DBG_LOW(" sub %d: hash=%x, hidx=%x\n", index, slot, hidx);
Paul Mackerras1189be62007-10-11 20:37:10 +10001098 ppc_md.hpte_invalidate(slot, va, psize, ssize, local);
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001099 } pte_iterate_hashed_end();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001100}
1101
Benjamin Herrenschmidt61b1a942005-09-20 13:52:50 +10001102void flush_hash_range(unsigned long number, int local)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001103{
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001104 if (ppc_md.flush_hash_range)
Benjamin Herrenschmidt61b1a942005-09-20 13:52:50 +10001105 ppc_md.flush_hash_range(number, local);
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001106 else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001107 int i;
Benjamin Herrenschmidt61b1a942005-09-20 13:52:50 +10001108 struct ppc64_tlb_batch *batch =
1109 &__get_cpu_var(ppc64_tlb_batch);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001110
1111 for (i = 0; i < number; i++)
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +11001112 flush_hash_page(batch->vaddr[i], batch->pte[i],
Paul Mackerras1189be62007-10-11 20:37:10 +10001113 batch->psize, batch->ssize, local);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001114 }
1115}
1116
Linus Torvalds1da177e2005-04-16 15:20:36 -07001117/*
1118 * low_hash_fault is called when we the low level hash code failed
1119 * to instert a PTE due to an hypervisor error
1120 */
Paul Mackerrasfa282372008-01-24 08:35:13 +11001121void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001122{
1123 if (user_mode(regs)) {
Paul Mackerrasfa282372008-01-24 08:35:13 +11001124#ifdef CONFIG_PPC_SUBPAGE_PROT
1125 if (rc == -2)
1126 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1127 else
1128#endif
1129 _exception(SIGBUS, regs, BUS_ADRERR, address);
1130 } else
1131 bad_page_fault(regs, address, SIGBUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001132}
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +10001133
1134#ifdef CONFIG_DEBUG_PAGEALLOC
1135static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1136{
Paul Mackerras1189be62007-10-11 20:37:10 +10001137 unsigned long hash, hpteg;
1138 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1139 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
Benjamin Herrenschmidtbc033b62008-08-05 16:19:56 +10001140 unsigned long mode = htab_convert_pte_flags(PAGE_KERNEL);
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +10001141 int ret;
1142
Paul Mackerras1189be62007-10-11 20:37:10 +10001143 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +10001144 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
1145
1146 ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr),
Paul Mackerras1189be62007-10-11 20:37:10 +10001147 mode, HPTE_V_BOLTED,
1148 mmu_linear_psize, mmu_kernel_ssize);
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +10001149 BUG_ON (ret < 0);
1150 spin_lock(&linear_map_hash_lock);
1151 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1152 linear_map_hash_slots[lmi] = ret | 0x80;
1153 spin_unlock(&linear_map_hash_lock);
1154}
1155
1156static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1157{
Paul Mackerras1189be62007-10-11 20:37:10 +10001158 unsigned long hash, hidx, slot;
1159 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1160 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +10001161
Paul Mackerras1189be62007-10-11 20:37:10 +10001162 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +10001163 spin_lock(&linear_map_hash_lock);
1164 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1165 hidx = linear_map_hash_slots[lmi] & 0x7f;
1166 linear_map_hash_slots[lmi] = 0;
1167 spin_unlock(&linear_map_hash_lock);
1168 if (hidx & _PTEIDX_SECONDARY)
1169 hash = ~hash;
1170 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1171 slot += hidx & _PTEIDX_GROUP_IX;
Paul Mackerras1189be62007-10-11 20:37:10 +10001172 ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0);
Benjamin Herrenschmidt370a9082007-04-12 15:30:23 +10001173}
1174
1175void kernel_map_pages(struct page *page, int numpages, int enable)
1176{
1177 unsigned long flags, vaddr, lmi;
1178 int i;
1179
1180 local_irq_save(flags);
1181 for (i = 0; i < numpages; i++, page++) {
1182 vaddr = (unsigned long)page_address(page);
1183 lmi = __pa(vaddr) >> PAGE_SHIFT;
1184 if (lmi >= linear_map_hash_count)
1185 continue;
1186 if (enable)
1187 kernel_map_linear_page(vaddr, lmi);
1188 else
1189 kernel_unmap_linear_page(vaddr, lmi);
1190 }
1191 local_irq_restore(flags);
1192}
1193#endif /* CONFIG_DEBUG_PAGEALLOC */