blob: 7da861755f4f6b5840a78c38f3fe280fff8479d4 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
Ralf Baechle010b8532006-01-29 18:42:08 +00005 * Copyright (C) 1994 - 2006 Ralf Baechle
Ralf Baechle41943182005-05-05 16:45:59 +00006 * Copyright (C) 2003, 2004 Maciej W. Rozycki
Ralf Baechle41943182005-05-05 16:45:59 +00007 * Copyright (C) 2001, 2004 MIPS Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
Ralf Baechle631330f2009-06-19 14:05:26 +010017#include <linux/smp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070018#include <linux/stddef.h>
Wu Zhangjinf8ede0f2009-11-17 01:32:59 +080019#include <linux/module.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020
Ralf Baechle57599062007-02-18 19:07:31 +000021#include <asm/bugs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <asm/cpu.h>
23#include <asm/fpu.h>
24#include <asm/mipsregs.h>
25#include <asm/system.h>
David Daney654f57b2008-09-23 00:07:16 -070026#include <asm/watch.h>
Chris Dearmana074f0e2009-07-10 01:51:27 -070027#include <asm/spram.h>
David Daney949e51b2010-10-14 11:32:33 -070028#include <asm/uaccess.h>
29
Linus Torvalds1da177e2005-04-16 15:20:36 -070030/*
31 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
32 * the implementation of the "wait" feature differs between CPU families. This
33 * points to the function that implements CPU specific wait.
34 * The wait instruction stops the pipeline and reduces the power consumption of
35 * the CPU very much.
36 */
Ralf Baechle982f6ff2009-09-17 02:25:07 +020037void (*cpu_wait)(void);
Wu Zhangjinf8ede0f2009-11-17 01:32:59 +080038EXPORT_SYMBOL(cpu_wait);
Linus Torvalds1da177e2005-04-16 15:20:36 -070039
40static void r3081_wait(void)
41{
42 unsigned long cfg = read_c0_conf();
43 write_c0_conf(cfg | R30XX_CONF_HALT);
44}
45
46static void r39xx_wait(void)
47{
Atsushi Nemoto60a6c372006-06-08 01:09:01 +090048 local_irq_disable();
49 if (!need_resched())
50 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
51 local_irq_enable();
Linus Torvalds1da177e2005-04-16 15:20:36 -070052}
53
Atsushi Nemotoc65a5482007-11-12 02:05:18 +090054extern void r4k_wait(void);
Atsushi Nemoto60a6c372006-06-08 01:09:01 +090055
56/*
57 * This variant is preferable as it allows testing need_resched and going to
58 * sleep depending on the outcome atomically. Unfortunately the "It is
59 * implementation-dependent whether the pipeline restarts when a non-enabled
60 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
61 * using this version a gamble.
62 */
Kevin D. Kissell8531a352008-09-09 21:48:52 +020063void r4k_wait_irqoff(void)
Atsushi Nemoto60a6c372006-06-08 01:09:01 +090064{
65 local_irq_disable();
66 if (!need_resched())
Kevin D. Kissell8531a352008-09-09 21:48:52 +020067 __asm__(" .set push \n"
68 " .set mips3 \n"
Atsushi Nemoto60a6c372006-06-08 01:09:01 +090069 " wait \n"
Kevin D. Kissell8531a352008-09-09 21:48:52 +020070 " .set pop \n");
Atsushi Nemoto60a6c372006-06-08 01:09:01 +090071 local_irq_enable();
Kevin D. Kissell8531a352008-09-09 21:48:52 +020072 __asm__(" .globl __pastwait \n"
73 "__pastwait: \n");
74 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -070075}
76
Ralf Baechle5a812992007-07-17 18:49:48 +010077/*
78 * The RM7000 variant has to handle erratum 38. The workaround is to not
79 * have any pending stores when the WAIT instruction is executed.
80 */
81static void rm7k_wait_irqoff(void)
82{
83 local_irq_disable();
84 if (!need_resched())
85 __asm__(
86 " .set push \n"
87 " .set mips3 \n"
88 " .set noat \n"
89 " mfc0 $1, $12 \n"
90 " sync \n"
91 " mtc0 $1, $12 # stalls until W stage \n"
92 " wait \n"
93 " mtc0 $1, $12 # stalls until W stage \n"
94 " .set pop \n");
95 local_irq_enable();
96}
97
Manuel Lauss2882b0c2009-08-22 18:09:27 +020098/*
99 * The Au1xxx wait is available only if using 32khz counter or
100 * external timer source, but specifically not CP0 Counter.
101 * alchemy/common/time.c may override cpu_wait!
102 */
Pete Popov494900a2005-04-07 00:42:10 +0000103static void au1k_wait(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104{
Atsushi Nemoto60a6c372006-06-08 01:09:01 +0900105 __asm__(" .set mips3 \n"
106 " cache 0x14, 0(%0) \n"
107 " cache 0x14, 32(%0) \n"
108 " sync \n"
109 " nop \n"
110 " wait \n"
111 " nop \n"
112 " nop \n"
113 " nop \n"
114 " nop \n"
115 " .set mips0 \n"
Ralf Baechle10f650d2005-05-25 13:32:49 +0000116 : : "r" (au1k_wait));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117}
118
Ralf Baechle982f6ff2009-09-17 02:25:07 +0200119static int __initdata nowait;
Ralf Baechle55d04df2005-07-13 19:22:45 +0000120
Atsushi Nemotof49a7472007-02-18 01:02:14 +0900121static int __init wait_disable(char *s)
Ralf Baechle55d04df2005-07-13 19:22:45 +0000122{
123 nowait = 1;
124
125 return 1;
126}
127
128__setup("nowait", wait_disable);
129
Kevin Cernekee0103d232010-05-02 14:43:52 -0700130static int __cpuinitdata mips_fpu_disabled;
131
132static int __init fpu_disable(char *s)
133{
134 cpu_data[0].options &= ~MIPS_CPU_FPU;
135 mips_fpu_disabled = 1;
136
137 return 1;
138}
139
140__setup("nofpu", fpu_disable);
141
142int __cpuinitdata mips_dsp_disabled;
143
144static int __init dsp_disable(char *s)
145{
146 cpu_data[0].ases &= ~MIPS_ASE_DSP;
147 mips_dsp_disabled = 1;
148
149 return 1;
150}
151
152__setup("nodsp", dsp_disable);
153
Atsushi Nemotoc65a5482007-11-12 02:05:18 +0900154void __init check_wait(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700155{
156 struct cpuinfo_mips *c = &current_cpu_data;
157
Ralf Baechle55d04df2005-07-13 19:22:45 +0000158 if (nowait) {
Ralf Baechlec2379232006-11-30 01:14:44 +0000159 printk("Wait instruction disabled.\n");
Ralf Baechle55d04df2005-07-13 19:22:45 +0000160 return;
161 }
162
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163 switch (c->cputype) {
164 case CPU_R3081:
165 case CPU_R3081E:
166 cpu_wait = r3081_wait;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700167 break;
168 case CPU_TX3927:
169 cpu_wait = r39xx_wait;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700170 break;
171 case CPU_R4200:
172/* case CPU_R4300: */
173 case CPU_R4600:
174 case CPU_R4640:
175 case CPU_R4650:
176 case CPU_R4700:
177 case CPU_R5000:
Shinya Kuribayashia644b272009-03-03 18:05:51 +0900178 case CPU_R5500:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700179 case CPU_NEVADA:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180 case CPU_4KC:
181 case CPU_4KEC:
182 case CPU_4KSC:
183 case CPU_5KC:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700184 case CPU_25KF:
Ralf Baechle4b3e9752007-06-21 00:22:34 +0100185 case CPU_PR4450:
Kevin Cernekee602977b2010-10-16 14:22:30 -0700186 case CPU_BMIPS3300:
187 case CPU_BMIPS4350:
188 case CPU_BMIPS4380:
189 case CPU_BMIPS5000:
David Daney0dd47812008-12-11 15:33:26 -0800190 case CPU_CAVIUM_OCTEON:
David Daney6f329462010-02-10 15:12:48 -0800191 case CPU_CAVIUM_OCTEON_PLUS:
David Daney0e56b382010-10-07 16:03:45 -0700192 case CPU_CAVIUM_OCTEON2:
Lars-Peter Clausen83ccf692010-07-17 11:07:51 +0000193 case CPU_JZRISC:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700194 cpu_wait = r4k_wait;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700195 break;
Ralf Baechle4b3e9752007-06-21 00:22:34 +0100196
Ralf Baechle5a812992007-07-17 18:49:48 +0100197 case CPU_RM7000:
198 cpu_wait = rm7k_wait_irqoff;
199 break;
200
Ralf Baechle4b3e9752007-06-21 00:22:34 +0100201 case CPU_24K:
202 case CPU_34K:
Ralf Baechle39b8d522008-04-28 17:14:26 +0100203 case CPU_1004K:
Ralf Baechle4b3e9752007-06-21 00:22:34 +0100204 cpu_wait = r4k_wait;
205 if (read_c0_config7() & MIPS_CONF7_WII)
206 cpu_wait = r4k_wait_irqoff;
207 break;
208
209 case CPU_74K:
210 cpu_wait = r4k_wait;
211 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
212 cpu_wait = r4k_wait_irqoff;
213 break;
214
Atsushi Nemoto60a6c372006-06-08 01:09:01 +0900215 case CPU_TX49XX:
216 cpu_wait = r4k_wait_irqoff;
Atsushi Nemoto60a6c372006-06-08 01:09:01 +0900217 break;
Manuel Lauss270717a2009-03-25 17:49:28 +0100218 case CPU_ALCHEMY:
Manuel Lauss0c694de2008-12-21 09:26:23 +0100219 cpu_wait = au1k_wait;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220 break;
Ralf Baechlec8eae712007-06-12 13:04:09 +0100221 case CPU_20KC:
222 /*
223 * WAIT on Rev1.0 has E1, E2, E3 and E16.
224 * WAIT on Rev2.0 and Rev3.0 has E16.
225 * Rev3.1 WAIT is nop, why bother
226 */
227 if ((c->processor_id & 0xff) <= 0x64)
228 break;
229
Ralf Baechle50da4692007-09-14 19:08:43 +0100230 /*
231 * Another rev is incremeting c0_count at a reduced clock
232 * rate while in WAIT mode. So we basically have the choice
233 * between using the cp0 timer as clocksource or avoiding
234 * the WAIT instruction. Until more details are known,
235 * disable the use of WAIT for 20Kc entirely.
236 cpu_wait = r4k_wait;
237 */
Ralf Baechlec8eae712007-06-12 13:04:09 +0100238 break;
Ralf Baechle441ee342006-06-02 11:48:11 +0100239 case CPU_RM9000:
Ralf Baechlec2379232006-11-30 01:14:44 +0000240 if ((c->processor_id & 0x00ff) >= 0x40)
Ralf Baechle441ee342006-06-02 11:48:11 +0100241 cpu_wait = r4k_wait;
Ralf Baechle441ee342006-06-02 11:48:11 +0100242 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700243 default:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700244 break;
245 }
246}
247
Marc St-Jean9267a302007-06-14 15:55:31 -0600248static inline void check_errata(void)
249{
250 struct cpuinfo_mips *c = &current_cpu_data;
251
252 switch (c->cputype) {
253 case CPU_34K:
254 /*
255 * Erratum "RPS May Cause Incorrect Instruction Execution"
256 * This code only handles VPE0, any SMP/SMTC/RTOS code
257 * making use of VPE1 will be responsable for that VPE.
258 */
259 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
260 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
261 break;
262 default:
263 break;
264 }
265}
266
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267void __init check_bugs32(void)
268{
Marc St-Jean9267a302007-06-14 15:55:31 -0600269 check_errata();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700270}
271
272/*
273 * Probe whether cpu has config register by trying to play with
274 * alternate cache bit and see whether it matters.
275 * It's used by cpu_probe to distinguish between R3000A and R3081.
276 */
277static inline int cpu_has_confreg(void)
278{
279#ifdef CONFIG_CPU_R3000
280 extern unsigned long r3k_cache_size(unsigned long);
281 unsigned long size1, size2;
282 unsigned long cfg = read_c0_conf();
283
284 size1 = r3k_cache_size(ST0_ISC);
285 write_c0_conf(cfg ^ R30XX_CONF_AC);
286 size2 = r3k_cache_size(ST0_ISC);
287 write_c0_conf(cfg);
288 return size1 != size2;
289#else
290 return 0;
291#endif
292}
293
Robert Millanc094c992011-04-18 11:37:55 -0700294static inline void set_elf_platform(int cpu, const char *plat)
295{
296 if (cpu == 0)
297 __elf_platform = plat;
298}
299
Linus Torvalds1da177e2005-04-16 15:20:36 -0700300/*
301 * Get the FPU Implementation/Revision.
302 */
303static inline unsigned long cpu_get_fpu_id(void)
304{
305 unsigned long tmp, fpu_id;
306
307 tmp = read_c0_status();
308 __enable_fpu();
309 fpu_id = read_32bit_cp1_register(CP1_REVISION);
310 write_c0_status(tmp);
311 return fpu_id;
312}
313
314/*
315 * Check the CPU has an FPU the official way.
316 */
317static inline int __cpu_has_fpu(void)
318{
319 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
320}
321
Guenter Roeck91dfc422010-02-02 08:52:20 -0800322static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
323{
324#ifdef __NEED_VMBITS_PROBE
David Daney5b7efa82010-02-08 12:27:00 -0800325 write_c0_entryhi(0x3fffffffffffe000ULL);
Guenter Roeck91dfc422010-02-02 08:52:20 -0800326 back_to_back_c0_hazard();
David Daney5b7efa82010-02-08 12:27:00 -0800327 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
Guenter Roeck91dfc422010-02-02 08:52:20 -0800328#endif
329}
330
Ralf Baechle02cf2112005-10-01 13:06:32 +0100331#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700332 | MIPS_CPU_COUNTER)
333
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000334static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700335{
336 switch (c->processor_id & 0xff00) {
337 case PRID_IMP_R2000:
338 c->cputype = CPU_R2000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000339 __cpu_name[cpu] = "R2000";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340 c->isa_level = MIPS_CPU_ISA_I;
Ralf Baechle02cf2112005-10-01 13:06:32 +0100341 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
342 MIPS_CPU_NOFPUEX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343 if (__cpu_has_fpu())
344 c->options |= MIPS_CPU_FPU;
345 c->tlbsize = 64;
346 break;
347 case PRID_IMP_R3000:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000348 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
349 if (cpu_has_confreg()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700350 c->cputype = CPU_R3081E;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000351 __cpu_name[cpu] = "R3081";
352 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353 c->cputype = CPU_R3000A;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000354 __cpu_name[cpu] = "R3000A";
355 }
356 break;
357 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358 c->cputype = CPU_R3000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000359 __cpu_name[cpu] = "R3000";
360 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700361 c->isa_level = MIPS_CPU_ISA_I;
Ralf Baechle02cf2112005-10-01 13:06:32 +0100362 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
363 MIPS_CPU_NOFPUEX;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700364 if (__cpu_has_fpu())
365 c->options |= MIPS_CPU_FPU;
366 c->tlbsize = 64;
367 break;
368 case PRID_IMP_R4000:
369 if (read_c0_config() & CONF_SC) {
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000370 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700371 c->cputype = CPU_R4400PC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000372 __cpu_name[cpu] = "R4400PC";
373 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700374 c->cputype = CPU_R4000PC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000375 __cpu_name[cpu] = "R4000PC";
376 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700377 } else {
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000378 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700379 c->cputype = CPU_R4400SC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000380 __cpu_name[cpu] = "R4400SC";
381 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700382 c->cputype = CPU_R4000SC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000383 __cpu_name[cpu] = "R4000SC";
384 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700385 }
386
387 c->isa_level = MIPS_CPU_ISA_III;
388 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
389 MIPS_CPU_WATCH | MIPS_CPU_VCE |
390 MIPS_CPU_LLSC;
391 c->tlbsize = 48;
392 break;
393 case PRID_IMP_VR41XX:
394 switch (c->processor_id & 0xf0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700395 case PRID_REV_VR4111:
396 c->cputype = CPU_VR4111;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000397 __cpu_name[cpu] = "NEC VR4111";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700398 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700399 case PRID_REV_VR4121:
400 c->cputype = CPU_VR4121;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000401 __cpu_name[cpu] = "NEC VR4121";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700402 break;
403 case PRID_REV_VR4122:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000404 if ((c->processor_id & 0xf) < 0x3) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700405 c->cputype = CPU_VR4122;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000406 __cpu_name[cpu] = "NEC VR4122";
407 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700408 c->cputype = CPU_VR4181A;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000409 __cpu_name[cpu] = "NEC VR4181A";
410 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700411 break;
412 case PRID_REV_VR4130:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000413 if ((c->processor_id & 0xf) < 0x4) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700414 c->cputype = CPU_VR4131;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000415 __cpu_name[cpu] = "NEC VR4131";
416 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700417 c->cputype = CPU_VR4133;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000418 __cpu_name[cpu] = "NEC VR4133";
419 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420 break;
421 default:
422 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
423 c->cputype = CPU_VR41XX;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000424 __cpu_name[cpu] = "NEC Vr41xx";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700425 break;
426 }
427 c->isa_level = MIPS_CPU_ISA_III;
428 c->options = R4K_OPTS;
429 c->tlbsize = 32;
430 break;
431 case PRID_IMP_R4300:
432 c->cputype = CPU_R4300;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000433 __cpu_name[cpu] = "R4300";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700434 c->isa_level = MIPS_CPU_ISA_III;
435 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
436 MIPS_CPU_LLSC;
437 c->tlbsize = 32;
438 break;
439 case PRID_IMP_R4600:
440 c->cputype = CPU_R4600;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000441 __cpu_name[cpu] = "R4600";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700442 c->isa_level = MIPS_CPU_ISA_III;
Thiemo Seufer075e7502005-07-27 21:48:12 +0000443 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
444 MIPS_CPU_LLSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700445 c->tlbsize = 48;
446 break;
447 #if 0
448 case PRID_IMP_R4650:
449 /*
450 * This processor doesn't have an MMU, so it's not
451 * "real easy" to run Linux on it. It is left purely
452 * for documentation. Commented out because it shares
453 * it's c0_prid id number with the TX3900.
454 */
Ralf Baechlea3dddd52006-03-11 08:18:41 +0000455 c->cputype = CPU_R4650;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000456 __cpu_name[cpu] = "R4650";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700457 c->isa_level = MIPS_CPU_ISA_III;
458 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
459 c->tlbsize = 48;
460 break;
461 #endif
462 case PRID_IMP_TX39:
463 c->isa_level = MIPS_CPU_ISA_I;
Ralf Baechle02cf2112005-10-01 13:06:32 +0100464 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700465
466 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
467 c->cputype = CPU_TX3927;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000468 __cpu_name[cpu] = "TX3927";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700469 c->tlbsize = 64;
470 } else {
471 switch (c->processor_id & 0xff) {
472 case PRID_REV_TX3912:
473 c->cputype = CPU_TX3912;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000474 __cpu_name[cpu] = "TX3912";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700475 c->tlbsize = 32;
476 break;
477 case PRID_REV_TX3922:
478 c->cputype = CPU_TX3922;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000479 __cpu_name[cpu] = "TX3922";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700480 c->tlbsize = 64;
481 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700482 }
483 }
484 break;
485 case PRID_IMP_R4700:
486 c->cputype = CPU_R4700;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000487 __cpu_name[cpu] = "R4700";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488 c->isa_level = MIPS_CPU_ISA_III;
489 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
490 MIPS_CPU_LLSC;
491 c->tlbsize = 48;
492 break;
493 case PRID_IMP_TX49:
494 c->cputype = CPU_TX49XX;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000495 __cpu_name[cpu] = "R49XX";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700496 c->isa_level = MIPS_CPU_ISA_III;
497 c->options = R4K_OPTS | MIPS_CPU_LLSC;
498 if (!(c->processor_id & 0x08))
499 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
500 c->tlbsize = 48;
501 break;
502 case PRID_IMP_R5000:
503 c->cputype = CPU_R5000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000504 __cpu_name[cpu] = "R5000";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700505 c->isa_level = MIPS_CPU_ISA_IV;
506 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
507 MIPS_CPU_LLSC;
508 c->tlbsize = 48;
509 break;
510 case PRID_IMP_R5432:
511 c->cputype = CPU_R5432;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000512 __cpu_name[cpu] = "R5432";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700513 c->isa_level = MIPS_CPU_ISA_IV;
514 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
515 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
516 c->tlbsize = 48;
517 break;
518 case PRID_IMP_R5500:
519 c->cputype = CPU_R5500;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000520 __cpu_name[cpu] = "R5500";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700521 c->isa_level = MIPS_CPU_ISA_IV;
522 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
523 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
524 c->tlbsize = 48;
525 break;
526 case PRID_IMP_NEVADA:
527 c->cputype = CPU_NEVADA;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000528 __cpu_name[cpu] = "Nevada";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700529 c->isa_level = MIPS_CPU_ISA_IV;
530 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
531 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
532 c->tlbsize = 48;
533 break;
534 case PRID_IMP_R6000:
535 c->cputype = CPU_R6000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000536 __cpu_name[cpu] = "R6000";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700537 c->isa_level = MIPS_CPU_ISA_II;
538 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
539 MIPS_CPU_LLSC;
540 c->tlbsize = 32;
541 break;
542 case PRID_IMP_R6000A:
543 c->cputype = CPU_R6000A;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000544 __cpu_name[cpu] = "R6000A";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700545 c->isa_level = MIPS_CPU_ISA_II;
546 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
547 MIPS_CPU_LLSC;
548 c->tlbsize = 32;
549 break;
550 case PRID_IMP_RM7000:
551 c->cputype = CPU_RM7000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000552 __cpu_name[cpu] = "RM7000";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700553 c->isa_level = MIPS_CPU_ISA_IV;
554 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
555 MIPS_CPU_LLSC;
556 /*
557 * Undocumented RM7000: Bit 29 in the info register of
558 * the RM7000 v2.0 indicates if the TLB has 48 or 64
559 * entries.
560 *
561 * 29 1 => 64 entry JTLB
562 * 0 => 48 entry JTLB
563 */
564 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
565 break;
566 case PRID_IMP_RM9000:
567 c->cputype = CPU_RM9000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000568 __cpu_name[cpu] = "RM9000";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700569 c->isa_level = MIPS_CPU_ISA_IV;
570 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
571 MIPS_CPU_LLSC;
572 /*
573 * Bit 29 in the info register of the RM9000
574 * indicates if the TLB has 48 or 64 entries.
575 *
576 * 29 1 => 64 entry JTLB
577 * 0 => 48 entry JTLB
578 */
579 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
580 break;
581 case PRID_IMP_R8000:
582 c->cputype = CPU_R8000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000583 __cpu_name[cpu] = "RM8000";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700584 c->isa_level = MIPS_CPU_ISA_IV;
585 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
586 MIPS_CPU_FPU | MIPS_CPU_32FPR |
587 MIPS_CPU_LLSC;
588 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
589 break;
590 case PRID_IMP_R10000:
591 c->cputype = CPU_R10000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000592 __cpu_name[cpu] = "R10000";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700593 c->isa_level = MIPS_CPU_ISA_IV;
Ralf Baechle8b366122005-11-22 17:53:59 +0000594 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
Linus Torvalds1da177e2005-04-16 15:20:36 -0700595 MIPS_CPU_FPU | MIPS_CPU_32FPR |
596 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
597 MIPS_CPU_LLSC;
598 c->tlbsize = 64;
599 break;
600 case PRID_IMP_R12000:
601 c->cputype = CPU_R12000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000602 __cpu_name[cpu] = "R12000";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700603 c->isa_level = MIPS_CPU_ISA_IV;
Ralf Baechle8b366122005-11-22 17:53:59 +0000604 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
Linus Torvalds1da177e2005-04-16 15:20:36 -0700605 MIPS_CPU_FPU | MIPS_CPU_32FPR |
606 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
607 MIPS_CPU_LLSC;
608 c->tlbsize = 64;
609 break;
Kumba44d921b2006-05-16 22:23:59 -0400610 case PRID_IMP_R14000:
611 c->cputype = CPU_R14000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000612 __cpu_name[cpu] = "R14000";
Kumba44d921b2006-05-16 22:23:59 -0400613 c->isa_level = MIPS_CPU_ISA_IV;
614 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
615 MIPS_CPU_FPU | MIPS_CPU_32FPR |
616 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
617 MIPS_CPU_LLSC;
618 c->tlbsize = 64;
619 break;
Fuxin Zhang2a21c732007-06-06 14:52:43 +0800620 case PRID_IMP_LOONGSON2:
621 c->cputype = CPU_LOONGSON2;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000622 __cpu_name[cpu] = "ICT Loongson-2";
Fuxin Zhang2a21c732007-06-06 14:52:43 +0800623 c->isa_level = MIPS_CPU_ISA_III;
624 c->options = R4K_OPTS |
625 MIPS_CPU_FPU | MIPS_CPU_LLSC |
626 MIPS_CPU_32FPR;
627 c->tlbsize = 64;
628 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700629 }
630}
631
Ralf Baechle234fcd12008-03-08 09:56:28 +0000632static char unknown_isa[] __cpuinitdata = KERN_ERR \
Ralf Baechleb4672d32005-12-08 14:04:24 +0000633 "Unsupported ISA type, c0.config0: %d.";
634
Ralf Baechle41943182005-05-05 16:45:59 +0000635static inline unsigned int decode_config0(struct cpuinfo_mips *c)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700636{
Ralf Baechle41943182005-05-05 16:45:59 +0000637 unsigned int config0;
638 int isa;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700639
Ralf Baechle41943182005-05-05 16:45:59 +0000640 config0 = read_c0_config();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641
Ralf Baechle41943182005-05-05 16:45:59 +0000642 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
Ralf Baechle02cf2112005-10-01 13:06:32 +0100643 c->options |= MIPS_CPU_TLB;
Ralf Baechle41943182005-05-05 16:45:59 +0000644 isa = (config0 & MIPS_CONF_AT) >> 13;
645 switch (isa) {
646 case 0:
Thiemo Seufer3a01c492006-07-03 13:30:01 +0100647 switch ((config0 & MIPS_CONF_AR) >> 10) {
Ralf Baechleb4672d32005-12-08 14:04:24 +0000648 case 0:
649 c->isa_level = MIPS_CPU_ISA_M32R1;
650 break;
651 case 1:
652 c->isa_level = MIPS_CPU_ISA_M32R2;
653 break;
654 default:
655 goto unknown;
656 }
Ralf Baechle41943182005-05-05 16:45:59 +0000657 break;
658 case 2:
Thiemo Seufer3a01c492006-07-03 13:30:01 +0100659 switch ((config0 & MIPS_CONF_AR) >> 10) {
Ralf Baechleb4672d32005-12-08 14:04:24 +0000660 case 0:
661 c->isa_level = MIPS_CPU_ISA_M64R1;
662 break;
663 case 1:
664 c->isa_level = MIPS_CPU_ISA_M64R2;
665 break;
666 default:
667 goto unknown;
668 }
Ralf Baechle41943182005-05-05 16:45:59 +0000669 break;
670 default:
Ralf Baechleb4672d32005-12-08 14:04:24 +0000671 goto unknown;
Ralf Baechle41943182005-05-05 16:45:59 +0000672 }
673
674 return config0 & MIPS_CONF_M;
Ralf Baechleb4672d32005-12-08 14:04:24 +0000675
676unknown:
677 panic(unknown_isa, config0);
Ralf Baechle41943182005-05-05 16:45:59 +0000678}
679
680static inline unsigned int decode_config1(struct cpuinfo_mips *c)
681{
682 unsigned int config1;
683
Linus Torvalds1da177e2005-04-16 15:20:36 -0700684 config1 = read_c0_config1();
Ralf Baechle41943182005-05-05 16:45:59 +0000685
686 if (config1 & MIPS_CONF1_MD)
687 c->ases |= MIPS_ASE_MDMX;
688 if (config1 & MIPS_CONF1_WR)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700689 c->options |= MIPS_CPU_WATCH;
Ralf Baechle41943182005-05-05 16:45:59 +0000690 if (config1 & MIPS_CONF1_CA)
691 c->ases |= MIPS_ASE_MIPS16;
692 if (config1 & MIPS_CONF1_EP)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700693 c->options |= MIPS_CPU_EJTAG;
Ralf Baechle41943182005-05-05 16:45:59 +0000694 if (config1 & MIPS_CONF1_FP) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700695 c->options |= MIPS_CPU_FPU;
696 c->options |= MIPS_CPU_32FPR;
697 }
Ralf Baechle41943182005-05-05 16:45:59 +0000698 if (cpu_has_tlb)
699 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
700
701 return config1 & MIPS_CONF_M;
702}
703
704static inline unsigned int decode_config2(struct cpuinfo_mips *c)
705{
706 unsigned int config2;
707
708 config2 = read_c0_config2();
709
710 if (config2 & MIPS_CONF2_SL)
711 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
712
713 return config2 & MIPS_CONF_M;
714}
715
716static inline unsigned int decode_config3(struct cpuinfo_mips *c)
717{
718 unsigned int config3;
719
720 config3 = read_c0_config3();
721
722 if (config3 & MIPS_CONF3_SM)
723 c->ases |= MIPS_ASE_SMARTMIPS;
Ralf Baechlee50c0a82005-05-31 11:49:19 +0000724 if (config3 & MIPS_CONF3_DSP)
725 c->ases |= MIPS_ASE_DSP;
Ralf Baechle8f406112005-07-14 07:34:18 +0000726 if (config3 & MIPS_CONF3_VINT)
727 c->options |= MIPS_CPU_VINT;
728 if (config3 & MIPS_CONF3_VEIC)
729 c->options |= MIPS_CPU_VEIC;
730 if (config3 & MIPS_CONF3_MT)
Ralf Baechlee0daad42007-02-05 00:10:11 +0000731 c->ases |= MIPS_ASE_MIPSMT;
Ralf Baechlea3692022007-07-10 17:33:02 +0100732 if (config3 & MIPS_CONF3_ULRI)
733 c->options |= MIPS_CPU_ULRI;
Ralf Baechle41943182005-05-05 16:45:59 +0000734
735 return config3 & MIPS_CONF_M;
736}
737
David Daney1b362e32010-01-22 14:41:15 -0800738static inline unsigned int decode_config4(struct cpuinfo_mips *c)
739{
740 unsigned int config4;
741
742 config4 = read_c0_config4();
743
744 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
745 && cpu_has_tlb)
746 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
747
David Daneye77c32f2010-12-21 14:19:09 -0800748 c->kscratch_mask = (config4 >> 16) & 0xff;
749
David Daney1b362e32010-01-22 14:41:15 -0800750 return config4 & MIPS_CONF_M;
751}
752
Ralf Baechle234fcd12008-03-08 09:56:28 +0000753static void __cpuinit decode_configs(struct cpuinfo_mips *c)
Ralf Baechle41943182005-05-05 16:45:59 +0000754{
Ralf Baechle558ce122008-10-29 12:33:34 +0000755 int ok;
756
Ralf Baechle41943182005-05-05 16:45:59 +0000757 /* MIPS32 or MIPS64 compliant CPU. */
Ralf Baechle02cf2112005-10-01 13:06:32 +0100758 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
759 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
Ralf Baechle41943182005-05-05 16:45:59 +0000760
Linus Torvalds1da177e2005-04-16 15:20:36 -0700761 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
762
Ralf Baechle558ce122008-10-29 12:33:34 +0000763 ok = decode_config0(c); /* Read Config registers. */
764 BUG_ON(!ok); /* Arch spec violation! */
765 if (ok)
766 ok = decode_config1(c);
767 if (ok)
768 ok = decode_config2(c);
769 if (ok)
770 ok = decode_config3(c);
David Daney1b362e32010-01-22 14:41:15 -0800771 if (ok)
772 ok = decode_config4(c);
Ralf Baechle558ce122008-10-29 12:33:34 +0000773
774 mips_probe_watch_registers(c);
David Daney0c2f4552010-07-26 14:29:37 -0700775
776 if (cpu_has_mips_r2)
777 c->core = read_c0_ebase() & 0x3ff;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700778}
779
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000780static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700781{
Ralf Baechle41943182005-05-05 16:45:59 +0000782 decode_configs(c);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700783 switch (c->processor_id & 0xff00) {
784 case PRID_IMP_4KC:
785 c->cputype = CPU_4KC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000786 __cpu_name[cpu] = "MIPS 4Kc";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700787 break;
788 case PRID_IMP_4KEC:
Ralf Baechle2b07bd02005-04-08 20:36:05 +0000789 case PRID_IMP_4KECR2:
790 c->cputype = CPU_4KEC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000791 __cpu_name[cpu] = "MIPS 4KEc";
Ralf Baechle2b07bd02005-04-08 20:36:05 +0000792 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700793 case PRID_IMP_4KSC:
Ralf Baechle8afcb5d2005-10-04 15:01:26 +0100794 case PRID_IMP_4KSD:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700795 c->cputype = CPU_4KSC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000796 __cpu_name[cpu] = "MIPS 4KSc";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700797 break;
798 case PRID_IMP_5KC:
799 c->cputype = CPU_5KC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000800 __cpu_name[cpu] = "MIPS 5Kc";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700801 break;
802 case PRID_IMP_20KC:
803 c->cputype = CPU_20KC;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000804 __cpu_name[cpu] = "MIPS 20Kc";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700805 break;
806 case PRID_IMP_24K:
Ralf Baechlee50c0a82005-05-31 11:49:19 +0000807 case PRID_IMP_24KE:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700808 c->cputype = CPU_24K;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000809 __cpu_name[cpu] = "MIPS 24Kc";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700810 break;
811 case PRID_IMP_25KF:
812 c->cputype = CPU_25KF;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000813 __cpu_name[cpu] = "MIPS 25Kc";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814 break;
Ralf Baechlebbc7f222005-07-12 16:12:05 +0000815 case PRID_IMP_34K:
816 c->cputype = CPU_34K;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000817 __cpu_name[cpu] = "MIPS 34Kc";
Ralf Baechlebbc7f222005-07-12 16:12:05 +0000818 break;
Chris Dearmanc6209532006-05-02 14:08:46 +0100819 case PRID_IMP_74K:
820 c->cputype = CPU_74K;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000821 __cpu_name[cpu] = "MIPS 74Kc";
Chris Dearmanc6209532006-05-02 14:08:46 +0100822 break;
Ralf Baechle39b8d522008-04-28 17:14:26 +0100823 case PRID_IMP_1004K:
824 c->cputype = CPU_1004K;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000825 __cpu_name[cpu] = "MIPS 1004Kc";
Ralf Baechle39b8d522008-04-28 17:14:26 +0100826 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700827 }
Chris Dearman0b6d4972007-09-13 12:32:02 +0100828
829 spram_config();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700830}
831
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000832static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700833{
Ralf Baechle41943182005-05-05 16:45:59 +0000834 decode_configs(c);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700835 switch (c->processor_id & 0xff00) {
836 case PRID_IMP_AU1_REV1:
837 case PRID_IMP_AU1_REV2:
Manuel Lauss270717a2009-03-25 17:49:28 +0100838 c->cputype = CPU_ALCHEMY;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700839 switch ((c->processor_id >> 24) & 0xff) {
840 case 0:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000841 __cpu_name[cpu] = "Au1000";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700842 break;
843 case 1:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000844 __cpu_name[cpu] = "Au1500";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700845 break;
846 case 2:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000847 __cpu_name[cpu] = "Au1100";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700848 break;
849 case 3:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000850 __cpu_name[cpu] = "Au1550";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700851 break;
Pete Popove3ad1c22005-03-01 06:33:16 +0000852 case 4:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000853 __cpu_name[cpu] = "Au1200";
Manuel Lauss270717a2009-03-25 17:49:28 +0100854 if ((c->processor_id & 0xff) == 2)
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000855 __cpu_name[cpu] = "Au1250";
Manuel Lauss237cfee2007-12-06 09:07:55 +0100856 break;
857 case 5:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000858 __cpu_name[cpu] = "Au1210";
Pete Popove3ad1c22005-03-01 06:33:16 +0000859 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700860 default:
Manuel Lauss270717a2009-03-25 17:49:28 +0100861 __cpu_name[cpu] = "Au1xxx";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700862 break;
863 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700864 break;
865 }
866}
867
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000868static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700869{
Ralf Baechle41943182005-05-05 16:45:59 +0000870 decode_configs(c);
Ralf Baechle02cf2112005-10-01 13:06:32 +0100871
Linus Torvalds1da177e2005-04-16 15:20:36 -0700872 switch (c->processor_id & 0xff00) {
873 case PRID_IMP_SB1:
874 c->cputype = CPU_SB1;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000875 __cpu_name[cpu] = "SiByte SB1";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876 /* FPU in pass1 is known to have issues. */
Ralf Baechleaa323742006-05-29 00:02:12 +0100877 if ((c->processor_id & 0xff) < 0x02)
Ralf Baechle010b8532006-01-29 18:42:08 +0000878 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700879 break;
Andrew Isaacson93ce2f522005-10-19 23:56:20 -0700880 case PRID_IMP_SB1A:
881 c->cputype = CPU_SB1A;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000882 __cpu_name[cpu] = "SiByte SB1A";
Andrew Isaacson93ce2f522005-10-19 23:56:20 -0700883 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700884 }
885}
886
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000887static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700888{
Ralf Baechle41943182005-05-05 16:45:59 +0000889 decode_configs(c);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700890 switch (c->processor_id & 0xff00) {
891 case PRID_IMP_SR71000:
892 c->cputype = CPU_SR71000;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000893 __cpu_name[cpu] = "Sandcraft SR71000";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700894 c->scache.ways = 8;
895 c->tlbsize = 64;
896 break;
897 }
898}
899
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000900static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
Pete Popovbdf21b12005-07-14 17:47:57 +0000901{
902 decode_configs(c);
903 switch (c->processor_id & 0xff00) {
904 case PRID_IMP_PR4450:
905 c->cputype = CPU_PR4450;
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000906 __cpu_name[cpu] = "Philips PR4450";
Ralf Baechlee7958bb2005-12-08 13:00:20 +0000907 c->isa_level = MIPS_CPU_ISA_M32R1;
Pete Popovbdf21b12005-07-14 17:47:57 +0000908 break;
Pete Popovbdf21b12005-07-14 17:47:57 +0000909 }
910}
911
Ralf Baechlecea7e2d2008-10-30 13:38:45 +0000912static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +0200913{
914 decode_configs(c);
915 switch (c->processor_id & 0xff00) {
Kevin Cernekee190fca32010-11-23 10:26:45 -0800916 case PRID_IMP_BMIPS32_REV4:
917 case PRID_IMP_BMIPS32_REV8:
Kevin Cernekee602977b2010-10-16 14:22:30 -0700918 c->cputype = CPU_BMIPS32;
919 __cpu_name[cpu] = "Broadcom BMIPS32";
Kevin Cernekee06785df2011-04-16 11:29:28 -0700920 set_elf_platform(cpu, "bmips32");
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +0200921 break;
Kevin Cernekee602977b2010-10-16 14:22:30 -0700922 case PRID_IMP_BMIPS3300:
923 case PRID_IMP_BMIPS3300_ALT:
924 case PRID_IMP_BMIPS3300_BUG:
925 c->cputype = CPU_BMIPS3300;
926 __cpu_name[cpu] = "Broadcom BMIPS3300";
Kevin Cernekee06785df2011-04-16 11:29:28 -0700927 set_elf_platform(cpu, "bmips3300");
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +0200928 break;
Kevin Cernekee602977b2010-10-16 14:22:30 -0700929 case PRID_IMP_BMIPS43XX: {
930 int rev = c->processor_id & 0xff;
931
932 if (rev >= PRID_REV_BMIPS4380_LO &&
933 rev <= PRID_REV_BMIPS4380_HI) {
934 c->cputype = CPU_BMIPS4380;
935 __cpu_name[cpu] = "Broadcom BMIPS4380";
Kevin Cernekee06785df2011-04-16 11:29:28 -0700936 set_elf_platform(cpu, "bmips4380");
Kevin Cernekee602977b2010-10-16 14:22:30 -0700937 } else {
938 c->cputype = CPU_BMIPS4350;
939 __cpu_name[cpu] = "Broadcom BMIPS4350";
Kevin Cernekee06785df2011-04-16 11:29:28 -0700940 set_elf_platform(cpu, "bmips4350");
Maxime Bizon0de663e2009-08-18 13:23:37 +0100941 }
942 break;
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +0200943 }
Kevin Cernekee602977b2010-10-16 14:22:30 -0700944 case PRID_IMP_BMIPS5000:
945 c->cputype = CPU_BMIPS5000;
946 __cpu_name[cpu] = "Broadcom BMIPS5000";
Kevin Cernekee06785df2011-04-16 11:29:28 -0700947 set_elf_platform(cpu, "bmips5000");
Kevin Cernekee602977b2010-10-16 14:22:30 -0700948 c->options |= MIPS_CPU_ULRI;
949 break;
Kevin Cernekee602977b2010-10-16 14:22:30 -0700950 }
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +0200951}
952
David Daney0dd47812008-12-11 15:33:26 -0800953static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
954{
955 decode_configs(c);
956 switch (c->processor_id & 0xff00) {
957 case PRID_IMP_CAVIUM_CN38XX:
958 case PRID_IMP_CAVIUM_CN31XX:
959 case PRID_IMP_CAVIUM_CN30XX:
David Daney6f329462010-02-10 15:12:48 -0800960 c->cputype = CPU_CAVIUM_OCTEON;
961 __cpu_name[cpu] = "Cavium Octeon";
962 goto platform;
David Daney0dd47812008-12-11 15:33:26 -0800963 case PRID_IMP_CAVIUM_CN58XX:
964 case PRID_IMP_CAVIUM_CN56XX:
965 case PRID_IMP_CAVIUM_CN50XX:
966 case PRID_IMP_CAVIUM_CN52XX:
David Daney6f329462010-02-10 15:12:48 -0800967 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
968 __cpu_name[cpu] = "Cavium Octeon+";
969platform:
Robert Millanc094c992011-04-18 11:37:55 -0700970 set_elf_platform(cpu, "octeon");
David Daney0dd47812008-12-11 15:33:26 -0800971 break;
David Daney0e56b382010-10-07 16:03:45 -0700972 case PRID_IMP_CAVIUM_CN63XX:
973 c->cputype = CPU_CAVIUM_OCTEON2;
974 __cpu_name[cpu] = "Cavium Octeon II";
Robert Millanc094c992011-04-18 11:37:55 -0700975 set_elf_platform(cpu, "octeon2");
David Daney0e56b382010-10-07 16:03:45 -0700976 break;
David Daney0dd47812008-12-11 15:33:26 -0800977 default:
978 printk(KERN_INFO "Unknown Octeon chip!\n");
979 c->cputype = CPU_UNKNOWN;
980 break;
981 }
982}
983
Lars-Peter Clausen83ccf692010-07-17 11:07:51 +0000984static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
985{
986 decode_configs(c);
987 /* JZRISC does not implement the CP0 counter. */
988 c->options &= ~MIPS_CPU_COUNTER;
989 switch (c->processor_id & 0xff00) {
990 case PRID_IMP_JZRISC:
991 c->cputype = CPU_JZRISC;
992 __cpu_name[cpu] = "Ingenic JZRISC";
993 break;
994 default:
995 panic("Unknown Ingenic Processor ID!");
996 break;
997 }
998}
999
Jayachandran Ca7117c62011-05-11 12:04:58 +05301000static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1001{
1002 decode_configs(c);
1003
1004 c->options = (MIPS_CPU_TLB |
1005 MIPS_CPU_4KEX |
1006 MIPS_CPU_COUNTER |
1007 MIPS_CPU_DIVEC |
1008 MIPS_CPU_WATCH |
1009 MIPS_CPU_EJTAG |
1010 MIPS_CPU_LLSC);
1011
1012 switch (c->processor_id & 0xff00) {
1013 case PRID_IMP_NETLOGIC_XLR732:
1014 case PRID_IMP_NETLOGIC_XLR716:
1015 case PRID_IMP_NETLOGIC_XLR532:
1016 case PRID_IMP_NETLOGIC_XLR308:
1017 case PRID_IMP_NETLOGIC_XLR532C:
1018 case PRID_IMP_NETLOGIC_XLR516C:
1019 case PRID_IMP_NETLOGIC_XLR508C:
1020 case PRID_IMP_NETLOGIC_XLR308C:
1021 c->cputype = CPU_XLR;
1022 __cpu_name[cpu] = "Netlogic XLR";
1023 break;
1024
1025 case PRID_IMP_NETLOGIC_XLS608:
1026 case PRID_IMP_NETLOGIC_XLS408:
1027 case PRID_IMP_NETLOGIC_XLS404:
1028 case PRID_IMP_NETLOGIC_XLS208:
1029 case PRID_IMP_NETLOGIC_XLS204:
1030 case PRID_IMP_NETLOGIC_XLS108:
1031 case PRID_IMP_NETLOGIC_XLS104:
1032 case PRID_IMP_NETLOGIC_XLS616B:
1033 case PRID_IMP_NETLOGIC_XLS608B:
1034 case PRID_IMP_NETLOGIC_XLS416B:
1035 case PRID_IMP_NETLOGIC_XLS412B:
1036 case PRID_IMP_NETLOGIC_XLS408B:
1037 case PRID_IMP_NETLOGIC_XLS404B:
1038 c->cputype = CPU_XLR;
1039 __cpu_name[cpu] = "Netlogic XLS";
1040 break;
1041
1042 default:
1043 printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n",
1044 c->processor_id);
1045 c->cputype = CPU_XLR;
1046 break;
1047 }
1048
1049 c->isa_level = MIPS_CPU_ISA_M64R1;
1050 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1051}
1052
David Daney949e51b2010-10-14 11:32:33 -07001053#ifdef CONFIG_64BIT
1054/* For use by uaccess.h */
1055u64 __ua_limit;
1056EXPORT_SYMBOL(__ua_limit);
1057#endif
1058
Ralf Baechle9966db252007-10-11 23:46:17 +01001059const char *__cpu_name[NR_CPUS];
David Daney874fd3b2010-01-28 16:52:12 -08001060const char *__elf_platform;
Ralf Baechle9966db252007-10-11 23:46:17 +01001061
Ralf Baechle234fcd12008-03-08 09:56:28 +00001062__cpuinit void cpu_probe(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001063{
1064 struct cpuinfo_mips *c = &current_cpu_data;
Ralf Baechle9966db252007-10-11 23:46:17 +01001065 unsigned int cpu = smp_processor_id();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001066
1067 c->processor_id = PRID_IMP_UNKNOWN;
1068 c->fpu_id = FPIR_IMP_NONE;
1069 c->cputype = CPU_UNKNOWN;
1070
1071 c->processor_id = read_c0_prid();
1072 switch (c->processor_id & 0xff0000) {
1073 case PRID_COMP_LEGACY:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001074 cpu_probe_legacy(c, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001075 break;
1076 case PRID_COMP_MIPS:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001077 cpu_probe_mips(c, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001078 break;
1079 case PRID_COMP_ALCHEMY:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001080 cpu_probe_alchemy(c, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001081 break;
1082 case PRID_COMP_SIBYTE:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001083 cpu_probe_sibyte(c, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001084 break;
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +02001085 case PRID_COMP_BROADCOM:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001086 cpu_probe_broadcom(c, cpu);
Aurelien Jarno1c0c13e2007-09-25 15:40:12 +02001087 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001088 case PRID_COMP_SANDCRAFT:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001089 cpu_probe_sandcraft(c, cpu);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001090 break;
Daniel Lairda92b0582008-03-06 09:07:18 +00001091 case PRID_COMP_NXP:
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001092 cpu_probe_nxp(c, cpu);
Ralf Baechlea3dddd52006-03-11 08:18:41 +00001093 break;
David Daney0dd47812008-12-11 15:33:26 -08001094 case PRID_COMP_CAVIUM:
1095 cpu_probe_cavium(c, cpu);
1096 break;
Lars-Peter Clausen83ccf692010-07-17 11:07:51 +00001097 case PRID_COMP_INGENIC:
1098 cpu_probe_ingenic(c, cpu);
1099 break;
Jayachandran Ca7117c62011-05-11 12:04:58 +05301100 case PRID_COMP_NETLOGIC:
1101 cpu_probe_netlogic(c, cpu);
1102 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001103 }
Franck Bui-Huudec8b1c2007-10-08 16:11:51 +02001104
Ralf Baechlecea7e2d2008-10-30 13:38:45 +00001105 BUG_ON(!__cpu_name[cpu]);
1106 BUG_ON(c->cputype == CPU_UNKNOWN);
1107
Franck Bui-Huudec8b1c2007-10-08 16:11:51 +02001108 /*
1109 * Platform code can force the cpu type to optimize code
1110 * generation. In that case be sure the cpu type is correctly
1111 * manually setup otherwise it could trigger some nasty bugs.
1112 */
1113 BUG_ON(current_cpu_type() != c->cputype);
1114
Kevin Cernekee0103d232010-05-02 14:43:52 -07001115 if (mips_fpu_disabled)
1116 c->options &= ~MIPS_CPU_FPU;
1117
1118 if (mips_dsp_disabled)
1119 c->ases &= ~MIPS_ASE_DSP;
1120
Ralf Baechle41943182005-05-05 16:45:59 +00001121 if (c->options & MIPS_CPU_FPU) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001122 c->fpu_id = cpu_get_fpu_id();
Ralf Baechle41943182005-05-05 16:45:59 +00001123
Ralf Baechlee7958bb2005-12-08 13:00:20 +00001124 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
Ralf Baechleb4672d32005-12-08 14:04:24 +00001125 c->isa_level == MIPS_CPU_ISA_M32R2 ||
1126 c->isa_level == MIPS_CPU_ISA_M64R1 ||
1127 c->isa_level == MIPS_CPU_ISA_M64R2) {
Ralf Baechle41943182005-05-05 16:45:59 +00001128 if (c->fpu_id & MIPS_FPIR_3D)
1129 c->ases |= MIPS_ASE_MIPS3D;
1130 }
1131 }
Ralf Baechle9966db252007-10-11 23:46:17 +01001132
Ralf Baechlef6771db2007-11-08 18:02:29 +00001133 if (cpu_has_mips_r2)
1134 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1135 else
1136 c->srsets = 1;
Guenter Roeck91dfc422010-02-02 08:52:20 -08001137
1138 cpu_probe_vmbits(c);
David Daney949e51b2010-10-14 11:32:33 -07001139
1140#ifdef CONFIG_64BIT
1141 if (cpu == 0)
1142 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1143#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001144}
1145
Ralf Baechle234fcd12008-03-08 09:56:28 +00001146__cpuinit void cpu_report(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001147{
1148 struct cpuinfo_mips *c = &current_cpu_data;
1149
Ralf Baechle9966db252007-10-11 23:46:17 +01001150 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1151 c->processor_id, cpu_name_string());
Linus Torvalds1da177e2005-04-16 15:20:36 -07001152 if (c->options & MIPS_CPU_FPU)
Ralf Baechle9966db252007-10-11 23:46:17 +01001153 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001154}