Paul Gortmaker | 69c60c8 | 2011-05-26 12:22:53 -0400 | [diff] [blame] | 1 | #include <linux/export.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | #include <linux/bitops.h> |
Stephen Rothwell | 5cdd174 | 2011-08-10 11:49:56 +1000 | [diff] [blame] | 3 | #include <linux/elf.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | #include <linux/mm.h> |
Yinghai Lu | 8d71a2e | 2008-09-07 17:58:53 -0700 | [diff] [blame] | 5 | |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 6 | #include <linux/io.h> |
Borislav Petkov | c98fdea | 2012-02-07 13:08:52 +0100 | [diff] [blame] | 7 | #include <linux/sched.h> |
Hector Marco-Gisbert | 4e26d11f | 2015-03-27 12:38:21 +0100 | [diff] [blame] | 8 | #include <linux/random.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | #include <asm/processor.h> |
Andi Kleen | d3f7eae | 2007-08-10 22:31:07 +0200 | [diff] [blame] | 10 | #include <asm/apic.h> |
Yinghai Lu | 1f442d7 | 2009-03-07 23:46:26 -0800 | [diff] [blame] | 11 | #include <asm/cpu.h> |
Borislav Petkov | 26bfa5f | 2014-06-24 13:25:04 +0200 | [diff] [blame] | 12 | #include <asm/smp.h> |
Andreas Herrmann | 42937e8 | 2009-06-08 15:55:09 +0200 | [diff] [blame] | 13 | #include <asm/pci-direct.h> |
Huang Rui | b466bdb | 2015-08-10 12:19:54 +0200 | [diff] [blame] | 14 | #include <asm/delay.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15 | |
Yinghai Lu | 8d71a2e | 2008-09-07 17:58:53 -0700 | [diff] [blame] | 16 | #ifdef CONFIG_X86_64 |
Yinghai Lu | 8d71a2e | 2008-09-07 17:58:53 -0700 | [diff] [blame] | 17 | # include <asm/mmconfig.h> |
| 18 | # include <asm/cacheflush.h> |
| 19 | #endif |
| 20 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | #include "cpu.h" |
| 22 | |
Thomas Gleixner | bd7e769 | 2016-12-09 19:29:09 +0100 | [diff] [blame] | 23 | static const int amd_erratum_383[]; |
| 24 | static const int amd_erratum_400[]; |
| 25 | static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); |
| 26 | |
Aravind Gopalakrishnan | cc2749e | 2015-06-15 10:28:15 +0200 | [diff] [blame] | 27 | /* |
| 28 | * nodes_per_socket: Stores the number of nodes per socket. |
| 29 | * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX |
| 30 | * Node Identifiers[10:8] |
| 31 | */ |
| 32 | static u32 nodes_per_socket = 1; |
| 33 | |
Borislav Petkov | 2c929ce | 2012-06-01 16:52:38 +0200 | [diff] [blame] | 34 | static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) |
| 35 | { |
Borislav Petkov | 2c929ce | 2012-06-01 16:52:38 +0200 | [diff] [blame] | 36 | u32 gprs[8] = { 0 }; |
| 37 | int err; |
| 38 | |
Borislav Petkov | 682469a | 2013-04-08 17:57:45 +0200 | [diff] [blame] | 39 | WARN_ONCE((boot_cpu_data.x86 != 0xf), |
| 40 | "%s should only be used on K8!\n", __func__); |
Borislav Petkov | 2c929ce | 2012-06-01 16:52:38 +0200 | [diff] [blame] | 41 | |
| 42 | gprs[1] = msr; |
| 43 | gprs[7] = 0x9c5a203a; |
| 44 | |
| 45 | err = rdmsr_safe_regs(gprs); |
| 46 | |
| 47 | *p = gprs[0] | ((u64)gprs[2] << 32); |
| 48 | |
| 49 | return err; |
| 50 | } |
| 51 | |
| 52 | static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) |
| 53 | { |
Borislav Petkov | 2c929ce | 2012-06-01 16:52:38 +0200 | [diff] [blame] | 54 | u32 gprs[8] = { 0 }; |
| 55 | |
Borislav Petkov | 682469a | 2013-04-08 17:57:45 +0200 | [diff] [blame] | 56 | WARN_ONCE((boot_cpu_data.x86 != 0xf), |
| 57 | "%s should only be used on K8!\n", __func__); |
Borislav Petkov | 2c929ce | 2012-06-01 16:52:38 +0200 | [diff] [blame] | 58 | |
| 59 | gprs[0] = (u32)val; |
| 60 | gprs[1] = msr; |
| 61 | gprs[2] = val >> 32; |
| 62 | gprs[7] = 0x9c5a203a; |
| 63 | |
| 64 | return wrmsr_safe_regs(gprs); |
| 65 | } |
| 66 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 67 | /* |
| 68 | * B step AMD K6 before B 9730xxxx have hardware bugs that can cause |
| 69 | * misexecution of code under Linux. Owners of such processors should |
| 70 | * contact AMD for precise details and a CPU swap. |
| 71 | * |
| 72 | * See http://www.multimania.com/poulot/k6bug.html |
Andreas Herrmann | d7de864 | 2012-04-11 17:12:38 +0200 | [diff] [blame] | 73 | * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" |
| 74 | * (Publication # 21266 Issue Date: August 1998) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 75 | * |
| 76 | * The following test is erm.. interesting. AMD neglected to up |
| 77 | * the chip setting when fixing the bug but they also tweaked some |
| 78 | * performance at the same time.. |
| 79 | */ |
Paolo Ciarrocchi | fb87a29 | 2008-02-22 23:10:33 +0100 | [diff] [blame] | 80 | |
Andi Kleen | 277d5b4 | 2013-08-05 15:02:43 -0700 | [diff] [blame] | 81 | extern __visible void vide(void); |
Josh Poimboeuf | de642fa | 2016-01-21 16:49:14 -0600 | [diff] [blame] | 82 | __asm__(".globl vide\n" |
| 83 | ".type vide, @function\n" |
| 84 | ".align 4\n" |
| 85 | "vide: ret\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 86 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 87 | static void init_amd_k5(struct cpuinfo_x86 *c) |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 88 | { |
Borislav Petkov | 26bfa5f | 2014-06-24 13:25:04 +0200 | [diff] [blame] | 89 | #ifdef CONFIG_X86_32 |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 90 | /* |
| 91 | * General Systems BIOSen alias the cpu frequency registers |
Adam Buchbinder | 6a6256f | 2016-02-23 15:34:30 -0800 | [diff] [blame] | 92 | * of the Elan at 0x000df000. Unfortunately, one of the Linux |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 93 | * drivers subsequently pokes it, and changes the CPU speed. |
| 94 | * Workaround : Remove the unneeded alias. |
| 95 | */ |
| 96 | #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ |
| 97 | #define CBAR_ENB (0x80000000) |
| 98 | #define CBAR_KEY (0X000000CB) |
| 99 | if (c->x86_model == 9 || c->x86_model == 10) { |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 100 | if (inl(CBAR) & CBAR_ENB) |
| 101 | outl(0 | CBAR_KEY, CBAR); |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 102 | } |
Borislav Petkov | 26bfa5f | 2014-06-24 13:25:04 +0200 | [diff] [blame] | 103 | #endif |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 104 | } |
| 105 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 106 | static void init_amd_k6(struct cpuinfo_x86 *c) |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 107 | { |
Borislav Petkov | 26bfa5f | 2014-06-24 13:25:04 +0200 | [diff] [blame] | 108 | #ifdef CONFIG_X86_32 |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 109 | u32 l, h; |
Jiang Liu | 46a8413 | 2013-07-03 15:04:19 -0700 | [diff] [blame] | 110 | int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 111 | |
| 112 | if (c->x86_model < 6) { |
| 113 | /* Based on AMD doc 20734R - June 2000 */ |
| 114 | if (c->x86_model == 0) { |
| 115 | clear_cpu_cap(c, X86_FEATURE_APIC); |
| 116 | set_cpu_cap(c, X86_FEATURE_PGE); |
| 117 | } |
| 118 | return; |
| 119 | } |
| 120 | |
Jia Zhang | 06be007 | 2018-01-01 09:52:10 +0800 | [diff] [blame^] | 121 | if (c->x86_model == 6 && c->x86_stepping == 1) { |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 122 | const int K6_BUG_LOOP = 1000000; |
| 123 | int n; |
| 124 | void (*f_vide)(void); |
Andy Lutomirski | 3796366 | 2015-06-25 18:44:01 +0200 | [diff] [blame] | 125 | u64 d, d2; |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 126 | |
Chen Yucong | 1b74dde | 2016-02-02 11:45:02 +0800 | [diff] [blame] | 127 | pr_info("AMD K6 stepping B detected - "); |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 128 | |
| 129 | /* |
| 130 | * It looks like AMD fixed the 2.6.2 bug and improved indirect |
| 131 | * calls at the same time. |
| 132 | */ |
| 133 | |
| 134 | n = K6_BUG_LOOP; |
| 135 | f_vide = vide; |
Andy Lutomirski | 4ea1636 | 2015-06-25 18:44:07 +0200 | [diff] [blame] | 136 | d = rdtsc(); |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 137 | while (n--) |
| 138 | f_vide(); |
Andy Lutomirski | 4ea1636 | 2015-06-25 18:44:07 +0200 | [diff] [blame] | 139 | d2 = rdtsc(); |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 140 | d = d2-d; |
| 141 | |
| 142 | if (d > 20*K6_BUG_LOOP) |
Chen Yucong | 1b74dde | 2016-02-02 11:45:02 +0800 | [diff] [blame] | 143 | pr_cont("system stability may be impaired when more than 32 MB are used.\n"); |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 144 | else |
Chen Yucong | 1b74dde | 2016-02-02 11:45:02 +0800 | [diff] [blame] | 145 | pr_cont("probably OK (after B9730xxxx).\n"); |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 146 | } |
| 147 | |
| 148 | /* K6 with old style WHCR */ |
| 149 | if (c->x86_model < 8 || |
Jia Zhang | 06be007 | 2018-01-01 09:52:10 +0800 | [diff] [blame^] | 150 | (c->x86_model == 8 && c->x86_stepping < 8)) { |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 151 | /* We can only write allocate on the low 508Mb */ |
| 152 | if (mbytes > 508) |
| 153 | mbytes = 508; |
| 154 | |
| 155 | rdmsr(MSR_K6_WHCR, l, h); |
| 156 | if ((l&0x0000FFFF) == 0) { |
| 157 | unsigned long flags; |
| 158 | l = (1<<0)|((mbytes/4)<<1); |
| 159 | local_irq_save(flags); |
| 160 | wbinvd(); |
| 161 | wrmsr(MSR_K6_WHCR, l, h); |
| 162 | local_irq_restore(flags); |
Chen Yucong | 1b74dde | 2016-02-02 11:45:02 +0800 | [diff] [blame] | 163 | pr_info("Enabling old style K6 write allocation for %d Mb\n", |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 164 | mbytes); |
| 165 | } |
| 166 | return; |
| 167 | } |
| 168 | |
Jia Zhang | 06be007 | 2018-01-01 09:52:10 +0800 | [diff] [blame^] | 169 | if ((c->x86_model == 8 && c->x86_stepping > 7) || |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 170 | c->x86_model == 9 || c->x86_model == 13) { |
| 171 | /* The more serious chips .. */ |
| 172 | |
| 173 | if (mbytes > 4092) |
| 174 | mbytes = 4092; |
| 175 | |
| 176 | rdmsr(MSR_K6_WHCR, l, h); |
| 177 | if ((l&0xFFFF0000) == 0) { |
| 178 | unsigned long flags; |
| 179 | l = ((mbytes>>2)<<22)|(1<<16); |
| 180 | local_irq_save(flags); |
| 181 | wbinvd(); |
| 182 | wrmsr(MSR_K6_WHCR, l, h); |
| 183 | local_irq_restore(flags); |
Chen Yucong | 1b74dde | 2016-02-02 11:45:02 +0800 | [diff] [blame] | 184 | pr_info("Enabling new style K6 write allocation for %d Mb\n", |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 185 | mbytes); |
| 186 | } |
| 187 | |
| 188 | return; |
| 189 | } |
| 190 | |
| 191 | if (c->x86_model == 10) { |
| 192 | /* AMD Geode LX is model 10 */ |
| 193 | /* placeholder for any needed mods */ |
| 194 | return; |
| 195 | } |
Borislav Petkov | 26bfa5f | 2014-06-24 13:25:04 +0200 | [diff] [blame] | 196 | #endif |
Yinghai Lu | 1f442d7 | 2009-03-07 23:46:26 -0800 | [diff] [blame] | 197 | } |
| 198 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 199 | static void init_amd_k7(struct cpuinfo_x86 *c) |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 200 | { |
Borislav Petkov | 26bfa5f | 2014-06-24 13:25:04 +0200 | [diff] [blame] | 201 | #ifdef CONFIG_X86_32 |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 202 | u32 l, h; |
| 203 | |
| 204 | /* |
| 205 | * Bit 15 of Athlon specific MSR 15, needs to be 0 |
| 206 | * to enable SSE on Palomino/Morgan/Barton CPU's. |
| 207 | * If the BIOS didn't enable it already, enable it here. |
| 208 | */ |
| 209 | if (c->x86_model >= 6 && c->x86_model <= 10) { |
| 210 | if (!cpu_has(c, X86_FEATURE_XMM)) { |
Chen Yucong | 1b74dde | 2016-02-02 11:45:02 +0800 | [diff] [blame] | 211 | pr_info("Enabling disabled K7/SSE Support.\n"); |
Borislav Petkov | 8f86a73 | 2014-03-09 18:05:24 +0100 | [diff] [blame] | 212 | msr_clear_bit(MSR_K7_HWCR, 15); |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 213 | set_cpu_cap(c, X86_FEATURE_XMM); |
| 214 | } |
| 215 | } |
| 216 | |
| 217 | /* |
| 218 | * It's been determined by AMD that Athlons since model 8 stepping 1 |
| 219 | * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx |
| 220 | * As per AMD technical note 27212 0.2 |
| 221 | */ |
Jia Zhang | 06be007 | 2018-01-01 09:52:10 +0800 | [diff] [blame^] | 222 | if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) { |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 223 | rdmsr(MSR_K7_CLK_CTL, l, h); |
| 224 | if ((l & 0xfff00000) != 0x20000000) { |
Chen Yucong | 1b74dde | 2016-02-02 11:45:02 +0800 | [diff] [blame] | 225 | pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", |
| 226 | l, ((l & 0x000fffff)|0x20000000)); |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 227 | wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); |
| 228 | } |
| 229 | } |
| 230 | |
| 231 | set_cpu_cap(c, X86_FEATURE_K7); |
Yinghai Lu | 1f442d7 | 2009-03-07 23:46:26 -0800 | [diff] [blame] | 232 | |
Borislav Petkov | 26bfa5f | 2014-06-24 13:25:04 +0200 | [diff] [blame] | 233 | /* calling is from identify_secondary_cpu() ? */ |
| 234 | if (!c->cpu_index) |
| 235 | return; |
| 236 | |
| 237 | /* |
| 238 | * Certain Athlons might work (for various values of 'work') in SMP |
| 239 | * but they are not certified as MP capable. |
| 240 | */ |
| 241 | /* Athlon 660/661 is valid. */ |
Jia Zhang | 06be007 | 2018-01-01 09:52:10 +0800 | [diff] [blame^] | 242 | if ((c->x86_model == 6) && ((c->x86_stepping == 0) || |
| 243 | (c->x86_stepping == 1))) |
Borislav Petkov | 26bfa5f | 2014-06-24 13:25:04 +0200 | [diff] [blame] | 244 | return; |
| 245 | |
| 246 | /* Duron 670 is valid */ |
Jia Zhang | 06be007 | 2018-01-01 09:52:10 +0800 | [diff] [blame^] | 247 | if ((c->x86_model == 7) && (c->x86_stepping == 0)) |
Borislav Petkov | 26bfa5f | 2014-06-24 13:25:04 +0200 | [diff] [blame] | 248 | return; |
| 249 | |
| 250 | /* |
| 251 | * Athlon 662, Duron 671, and Athlon >model 7 have capability |
| 252 | * bit. It's worth noting that the A5 stepping (662) of some |
| 253 | * Athlon XP's have the MP bit set. |
| 254 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for |
| 255 | * more. |
| 256 | */ |
Jia Zhang | 06be007 | 2018-01-01 09:52:10 +0800 | [diff] [blame^] | 257 | if (((c->x86_model == 6) && (c->x86_stepping >= 2)) || |
| 258 | ((c->x86_model == 7) && (c->x86_stepping >= 1)) || |
Borislav Petkov | 26bfa5f | 2014-06-24 13:25:04 +0200 | [diff] [blame] | 259 | (c->x86_model > 7)) |
| 260 | if (cpu_has(c, X86_FEATURE_MP)) |
| 261 | return; |
| 262 | |
| 263 | /* If we get here, not a certified SMP capable AMD system. */ |
| 264 | |
| 265 | /* |
| 266 | * Don't taint if we are running SMP kernel on a single non-MP |
| 267 | * approved Athlon |
| 268 | */ |
| 269 | WARN_ONCE(1, "WARNING: This combination of AMD" |
| 270 | " processors is not suitable for SMP.\n"); |
| 271 | add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 272 | #endif |
Borislav Petkov | 26bfa5f | 2014-06-24 13:25:04 +0200 | [diff] [blame] | 273 | } |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 274 | |
Tejun Heo | 645a791 | 2011-01-23 14:37:40 +0100 | [diff] [blame] | 275 | #ifdef CONFIG_NUMA |
Tejun Heo | bbc9e2f | 2011-01-23 14:37:39 +0100 | [diff] [blame] | 276 | /* |
| 277 | * To workaround broken NUMA config. Read the comment in |
| 278 | * srat_detect_node(). |
| 279 | */ |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 280 | static int nearby_node(int apicid) |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 281 | { |
| 282 | int i, node; |
| 283 | |
| 284 | for (i = apicid - 1; i >= 0; i--) { |
Tejun Heo | bbc9e2f | 2011-01-23 14:37:39 +0100 | [diff] [blame] | 285 | node = __apicid_to_node[i]; |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 286 | if (node != NUMA_NO_NODE && node_online(node)) |
| 287 | return node; |
| 288 | } |
| 289 | for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { |
Tejun Heo | bbc9e2f | 2011-01-23 14:37:39 +0100 | [diff] [blame] | 290 | node = __apicid_to_node[i]; |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 291 | if (node != NUMA_NO_NODE && node_online(node)) |
| 292 | return node; |
| 293 | } |
| 294 | return first_node(node_online_map); /* Shouldn't happen */ |
| 295 | } |
| 296 | #endif |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 297 | |
| 298 | /* |
Andreas Herrmann | 23588c3 | 2010-09-30 14:36:28 +0200 | [diff] [blame] | 299 | * Fixup core topology information for |
| 300 | * (1) AMD multi-node processors |
| 301 | * Assumption: Number of cores in each internal node is the same. |
Andreas Herrmann | 6057b4d | 2010-09-30 14:38:57 +0200 | [diff] [blame] | 302 | * (2) AMD processors supporting compute units |
Andreas Herrmann | 4a376ec | 2009-09-03 09:40:21 +0200 | [diff] [blame] | 303 | */ |
Borislav Petkov | c8e56d2 | 2015-06-04 18:55:25 +0200 | [diff] [blame] | 304 | #ifdef CONFIG_SMP |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 305 | static void amd_get_topology(struct cpuinfo_x86 *c) |
Andreas Herrmann | 4a376ec | 2009-09-03 09:40:21 +0200 | [diff] [blame] | 306 | { |
Andreas Herrmann | 23588c3 | 2010-09-30 14:36:28 +0200 | [diff] [blame] | 307 | u8 node_id; |
Andreas Herrmann | 4a376ec | 2009-09-03 09:40:21 +0200 | [diff] [blame] | 308 | int cpu = smp_processor_id(); |
| 309 | |
Andreas Herrmann | 23588c3 | 2010-09-30 14:36:28 +0200 | [diff] [blame] | 310 | /* get information required for multi-node processors */ |
Borislav Petkov | 362f924 | 2015-12-07 10:39:41 +0100 | [diff] [blame] | 311 | if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { |
Borislav Petkov | 6e306c5 | 2017-02-05 11:50:21 +0100 | [diff] [blame] | 312 | u32 eax, ebx, ecx, edx; |
Andreas Herrmann | 6057b4d | 2010-09-30 14:38:57 +0200 | [diff] [blame] | 313 | |
Borislav Petkov | 6e306c5 | 2017-02-05 11:50:21 +0100 | [diff] [blame] | 314 | cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); |
| 315 | |
| 316 | node_id = ecx & 0xff; |
| 317 | smp_num_siblings = ((ebx >> 8) & 0xff) + 1; |
| 318 | |
| 319 | if (c->x86 == 0x15) |
| 320 | c->cu_id = ebx & 0xff; |
Yazen Ghannam | e2d9ad2 | 2016-11-08 16:30:54 +0100 | [diff] [blame] | 321 | |
Yazen Ghannam | c8cbc21 | 2017-02-05 11:50:22 +0100 | [diff] [blame] | 322 | if (c->x86 >= 0x17) { |
| 323 | c->cpu_core_id = ebx & 0xff; |
| 324 | |
| 325 | if (smp_num_siblings > 1) |
| 326 | c->x86_max_cores /= smp_num_siblings; |
| 327 | } |
| 328 | |
Yazen Ghannam | e2d9ad2 | 2016-11-08 16:30:54 +0100 | [diff] [blame] | 329 | /* |
| 330 | * We may have multiple LLCs if L3 caches exist, so check if we |
| 331 | * have an L3 cache by looking at the L3 cache CPUID leaf. |
| 332 | */ |
| 333 | if (cpuid_edx(0x80000006)) { |
| 334 | if (c->x86 == 0x17) { |
| 335 | /* |
| 336 | * LLC is at the core complex level. |
| 337 | * Core complex id is ApicId[3]. |
| 338 | */ |
| 339 | per_cpu(cpu_llc_id, cpu) = c->apicid >> 3; |
| 340 | } else { |
| 341 | /* LLC is at the node level. */ |
| 342 | per_cpu(cpu_llc_id, cpu) = node_id; |
| 343 | } |
| 344 | } |
Andreas Herrmann | 23588c3 | 2010-09-30 14:36:28 +0200 | [diff] [blame] | 345 | } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { |
Andreas Herrmann | 6057b4d | 2010-09-30 14:38:57 +0200 | [diff] [blame] | 346 | u64 value; |
| 347 | |
Andreas Herrmann | 23588c3 | 2010-09-30 14:36:28 +0200 | [diff] [blame] | 348 | rdmsrl(MSR_FAM10H_NODE_ID, value); |
Andreas Herrmann | 23588c3 | 2010-09-30 14:36:28 +0200 | [diff] [blame] | 349 | node_id = value & 7; |
Yazen Ghannam | e2d9ad2 | 2016-11-08 16:30:54 +0100 | [diff] [blame] | 350 | |
| 351 | per_cpu(cpu_llc_id, cpu) = node_id; |
Andreas Herrmann | 23588c3 | 2010-09-30 14:36:28 +0200 | [diff] [blame] | 352 | } else |
Andreas Herrmann | 9d260eb | 2009-12-16 15:43:55 +0100 | [diff] [blame] | 353 | return; |
| 354 | |
Andreas Herrmann | 23588c3 | 2010-09-30 14:36:28 +0200 | [diff] [blame] | 355 | /* fixup multi-node processor information */ |
Aravind Gopalakrishnan | cc2749e | 2015-06-15 10:28:15 +0200 | [diff] [blame] | 356 | if (nodes_per_socket > 1) { |
Andreas Herrmann | d518573 | 2011-01-24 16:05:40 +0100 | [diff] [blame] | 357 | u32 cus_per_node; |
Andreas Herrmann | 6057b4d | 2010-09-30 14:38:57 +0200 | [diff] [blame] | 358 | |
Andreas Herrmann | 23588c3 | 2010-09-30 14:36:28 +0200 | [diff] [blame] | 359 | set_cpu_cap(c, X86_FEATURE_AMD_DCM); |
Peter Zijlstra | ee6825c | 2016-03-25 15:52:34 +0100 | [diff] [blame] | 360 | cus_per_node = c->x86_max_cores / nodes_per_socket; |
Andreas Herrmann | 4a376ec | 2009-09-03 09:40:21 +0200 | [diff] [blame] | 361 | |
Borislav Petkov | 9e81509 | 2011-02-14 18:14:51 +0100 | [diff] [blame] | 362 | /* core id has to be in the [0 .. cores_per_node - 1] range */ |
Borislav Petkov | 8196dab | 2016-03-25 15:52:36 +0100 | [diff] [blame] | 363 | c->cpu_core_id %= cus_per_node; |
Andreas Herrmann | 23588c3 | 2010-09-30 14:36:28 +0200 | [diff] [blame] | 364 | } |
Andreas Herrmann | 4a376ec | 2009-09-03 09:40:21 +0200 | [diff] [blame] | 365 | } |
| 366 | #endif |
| 367 | |
| 368 | /* |
Michael Opdenacker | aa5e5dc | 2013-09-18 06:00:43 +0200 | [diff] [blame] | 369 | * On a AMD dual core setup the lower bits of the APIC id distinguish the cores. |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 370 | * Assumes number of cores is a power of two. |
| 371 | */ |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 372 | static void amd_detect_cmp(struct cpuinfo_x86 *c) |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 373 | { |
Borislav Petkov | c8e56d2 | 2015-06-04 18:55:25 +0200 | [diff] [blame] | 374 | #ifdef CONFIG_SMP |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 375 | unsigned bits; |
Andreas Herrmann | 99bd0c0 | 2009-06-19 10:59:09 +0200 | [diff] [blame] | 376 | int cpu = smp_processor_id(); |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 377 | |
| 378 | bits = c->x86_coreid_bits; |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 379 | /* Low order bits define the core id (index of core in socket) */ |
| 380 | c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); |
| 381 | /* Convert the initial APIC ID into the socket ID */ |
| 382 | c->phys_proc_id = c->initial_apicid >> bits; |
Andreas Herrmann | 99bd0c0 | 2009-06-19 10:59:09 +0200 | [diff] [blame] | 383 | /* use socket ID also for last level cache */ |
| 384 | per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; |
Andreas Herrmann | 23588c3 | 2010-09-30 14:36:28 +0200 | [diff] [blame] | 385 | amd_get_topology(c); |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 386 | #endif |
| 387 | } |
| 388 | |
Daniel J Blueman | 8b84c8d | 2012-11-27 14:32:10 +0800 | [diff] [blame] | 389 | u16 amd_get_nb_id(int cpu) |
Andreas Herrmann | 6a81269 | 2009-09-16 11:33:40 +0200 | [diff] [blame] | 390 | { |
Daniel J Blueman | 8b84c8d | 2012-11-27 14:32:10 +0800 | [diff] [blame] | 391 | u16 id = 0; |
Andreas Herrmann | 6a81269 | 2009-09-16 11:33:40 +0200 | [diff] [blame] | 392 | #ifdef CONFIG_SMP |
| 393 | id = per_cpu(cpu_llc_id, cpu); |
| 394 | #endif |
| 395 | return id; |
| 396 | } |
| 397 | EXPORT_SYMBOL_GPL(amd_get_nb_id); |
| 398 | |
Aravind Gopalakrishnan | cc2749e | 2015-06-15 10:28:15 +0200 | [diff] [blame] | 399 | u32 amd_get_nodes_per_socket(void) |
| 400 | { |
| 401 | return nodes_per_socket; |
| 402 | } |
| 403 | EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket); |
| 404 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 405 | static void srat_detect_node(struct cpuinfo_x86 *c) |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 406 | { |
Tejun Heo | 645a791 | 2011-01-23 14:37:40 +0100 | [diff] [blame] | 407 | #ifdef CONFIG_NUMA |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 408 | int cpu = smp_processor_id(); |
| 409 | int node; |
Yinghai Lu | 0d96b9f | 2009-08-29 13:17:14 -0700 | [diff] [blame] | 410 | unsigned apicid = c->apicid; |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 411 | |
Tejun Heo | bbc9e2f | 2011-01-23 14:37:39 +0100 | [diff] [blame] | 412 | node = numa_cpu_node(cpu); |
| 413 | if (node == NUMA_NO_NODE) |
| 414 | node = per_cpu(cpu_llc_id, cpu); |
Andreas Herrmann | 4a376ec | 2009-09-03 09:40:21 +0200 | [diff] [blame] | 415 | |
Daniel J Blueman | 64be4c1 | 2011-12-05 16:20:37 +0800 | [diff] [blame] | 416 | /* |
Andreas Herrmann | 6889463 | 2012-04-02 18:06:48 +0200 | [diff] [blame] | 417 | * On multi-fabric platform (e.g. Numascale NumaChip) a |
| 418 | * platform-specific handler needs to be called to fixup some |
| 419 | * IDs of the CPU. |
Daniel J Blueman | 64be4c1 | 2011-12-05 16:20:37 +0800 | [diff] [blame] | 420 | */ |
Andreas Herrmann | 6889463 | 2012-04-02 18:06:48 +0200 | [diff] [blame] | 421 | if (x86_cpuinit.fixup_cpu_id) |
Daniel J Blueman | 64be4c1 | 2011-12-05 16:20:37 +0800 | [diff] [blame] | 422 | x86_cpuinit.fixup_cpu_id(c, node); |
| 423 | |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 424 | if (!node_online(node)) { |
Tejun Heo | bbc9e2f | 2011-01-23 14:37:39 +0100 | [diff] [blame] | 425 | /* |
| 426 | * Two possibilities here: |
| 427 | * |
| 428 | * - The CPU is missing memory and no node was created. In |
| 429 | * that case try picking one from a nearby CPU. |
| 430 | * |
| 431 | * - The APIC IDs differ from the HyperTransport node IDs |
| 432 | * which the K8 northbridge parsing fills in. Assume |
| 433 | * they are all increased by a constant offset, but in |
| 434 | * the same order as the HT nodeids. If that doesn't |
| 435 | * result in a usable node fall back to the path for the |
| 436 | * previous case. |
| 437 | * |
| 438 | * This workaround operates directly on the mapping between |
| 439 | * APIC ID and NUMA node, assuming certain relationship |
| 440 | * between APIC ID, HT node ID and NUMA topology. As going |
| 441 | * through CPU mapping may alter the outcome, directly |
| 442 | * access __apicid_to_node[]. |
| 443 | */ |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 444 | int ht_nodeid = c->initial_apicid; |
| 445 | |
Dan Carpenter | 7030a7e | 2016-01-13 15:39:40 +0300 | [diff] [blame] | 446 | if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) |
Tejun Heo | bbc9e2f | 2011-01-23 14:37:39 +0100 | [diff] [blame] | 447 | node = __apicid_to_node[ht_nodeid]; |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 448 | /* Pick a nearby node */ |
| 449 | if (!node_online(node)) |
| 450 | node = nearby_node(apicid); |
| 451 | } |
| 452 | numa_set_node(cpu, node); |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 453 | #endif |
| 454 | } |
| 455 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 456 | static void early_init_amd_mc(struct cpuinfo_x86 *c) |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 457 | { |
Borislav Petkov | c8e56d2 | 2015-06-04 18:55:25 +0200 | [diff] [blame] | 458 | #ifdef CONFIG_SMP |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 459 | unsigned bits, ecx; |
| 460 | |
| 461 | /* Multi core CPU? */ |
| 462 | if (c->extended_cpuid_level < 0x80000008) |
| 463 | return; |
| 464 | |
| 465 | ecx = cpuid_ecx(0x80000008); |
| 466 | |
| 467 | c->x86_max_cores = (ecx & 0xff) + 1; |
| 468 | |
| 469 | /* CPU telling us the core id bits shift? */ |
| 470 | bits = (ecx >> 12) & 0xF; |
| 471 | |
| 472 | /* Otherwise recompute */ |
| 473 | if (bits == 0) { |
| 474 | while ((1 << bits) < c->x86_max_cores) |
| 475 | bits++; |
| 476 | } |
| 477 | |
| 478 | c->x86_coreid_bits = bits; |
| 479 | #endif |
| 480 | } |
| 481 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 482 | static void bsp_init_amd(struct cpuinfo_x86 *c) |
Borislav Petkov | 8fa8b03 | 2011-08-05 20:04:09 +0200 | [diff] [blame] | 483 | { |
Borislav Petkov | 26bfa5f | 2014-06-24 13:25:04 +0200 | [diff] [blame] | 484 | |
| 485 | #ifdef CONFIG_X86_64 |
| 486 | if (c->x86 >= 0xf) { |
| 487 | unsigned long long tseg; |
| 488 | |
| 489 | /* |
| 490 | * Split up direct mapping around the TSEG SMM area. |
| 491 | * Don't do it for gbpages because there seems very little |
| 492 | * benefit in doing so. |
| 493 | */ |
| 494 | if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { |
| 495 | unsigned long pfn = tseg >> PAGE_SHIFT; |
| 496 | |
Chen Yucong | 1b74dde | 2016-02-02 11:45:02 +0800 | [diff] [blame] | 497 | pr_debug("tseg: %010llx\n", tseg); |
Borislav Petkov | 26bfa5f | 2014-06-24 13:25:04 +0200 | [diff] [blame] | 498 | if (pfn_range_is_mapped(pfn, pfn + 1)) |
| 499 | set_memory_4k((unsigned long)__va(tseg), 1); |
| 500 | } |
| 501 | } |
| 502 | #endif |
| 503 | |
Borislav Petkov | 8fa8b03 | 2011-08-05 20:04:09 +0200 | [diff] [blame] | 504 | if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { |
| 505 | |
| 506 | if (c->x86 > 0x10 || |
| 507 | (c->x86 == 0x10 && c->x86_model >= 0x2)) { |
| 508 | u64 val; |
| 509 | |
| 510 | rdmsrl(MSR_K7_HWCR, val); |
| 511 | if (!(val & BIT(24))) |
Chen Yucong | 1b74dde | 2016-02-02 11:45:02 +0800 | [diff] [blame] | 512 | pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); |
Borislav Petkov | 8fa8b03 | 2011-08-05 20:04:09 +0200 | [diff] [blame] | 513 | } |
| 514 | } |
| 515 | |
| 516 | if (c->x86 == 0x15) { |
| 517 | unsigned long upperbit; |
| 518 | u32 cpuid, assoc; |
| 519 | |
| 520 | cpuid = cpuid_edx(0x80000005); |
| 521 | assoc = cpuid >> 16 & 0xff; |
| 522 | upperbit = ((cpuid >> 24) << 10) / assoc; |
| 523 | |
| 524 | va_align.mask = (upperbit - 1) & PAGE_MASK; |
| 525 | va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; |
Hector Marco-Gisbert | 4e26d11f | 2015-03-27 12:38:21 +0100 | [diff] [blame] | 526 | |
| 527 | /* A random value per boot for bit slice [12:upper_bit) */ |
| 528 | va_align.bits = get_random_int() & va_align.mask; |
Borislav Petkov | 8fa8b03 | 2011-08-05 20:04:09 +0200 | [diff] [blame] | 529 | } |
Huang Rui | b466bdb | 2015-08-10 12:19:54 +0200 | [diff] [blame] | 530 | |
| 531 | if (cpu_has(c, X86_FEATURE_MWAITX)) |
| 532 | use_mwaitx_delay(); |
Huang Rui | 8dfeae0 | 2016-01-14 10:50:04 +0800 | [diff] [blame] | 533 | |
| 534 | if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { |
| 535 | u32 ecx; |
| 536 | |
| 537 | ecx = cpuid_ecx(0x8000001e); |
| 538 | nodes_per_socket = ((ecx >> 8) & 7) + 1; |
| 539 | } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { |
| 540 | u64 value; |
| 541 | |
| 542 | rdmsrl(MSR_FAM10H_NODE_ID, value); |
| 543 | nodes_per_socket = ((value >> 3) & 7) + 1; |
| 544 | } |
Borislav Petkov | 8fa8b03 | 2011-08-05 20:04:09 +0200 | [diff] [blame] | 545 | } |
| 546 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 547 | static void early_init_amd(struct cpuinfo_x86 *c) |
Andi Kleen | 2b16a23 | 2008-01-30 13:32:40 +0100 | [diff] [blame] | 548 | { |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 549 | early_init_amd_mc(c); |
| 550 | |
Venki Pallipadi | 40fb171 | 2008-11-17 16:11:37 -0800 | [diff] [blame] | 551 | /* |
| 552 | * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate |
| 553 | * with P/T states and does not stop in deep C-states |
| 554 | */ |
| 555 | if (c->x86_power & (1 << 8)) { |
Yinghai Lu | e322423 | 2008-09-06 01:52:28 -0700 | [diff] [blame] | 556 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); |
Venki Pallipadi | 40fb171 | 2008-11-17 16:11:37 -0800 | [diff] [blame] | 557 | set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); |
Borislav Petkov | c98fdea | 2012-02-07 13:08:52 +0100 | [diff] [blame] | 558 | if (!check_tsc_unstable()) |
Peter Zijlstra | 35af99e | 2013-11-28 19:38:42 +0100 | [diff] [blame] | 559 | set_sched_clock_stable(); |
Venki Pallipadi | 40fb171 | 2008-11-17 16:11:37 -0800 | [diff] [blame] | 560 | } |
Yinghai Lu | 5fef55f | 2008-09-04 21:09:43 +0200 | [diff] [blame] | 561 | |
Huang Rui | 01fe03f | 2016-01-14 10:50:06 +0800 | [diff] [blame] | 562 | /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ |
| 563 | if (c->x86_power & BIT(12)) |
| 564 | set_cpu_cap(c, X86_FEATURE_ACC_POWER); |
| 565 | |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 566 | #ifdef CONFIG_X86_64 |
| 567 | set_cpu_cap(c, X86_FEATURE_SYSCALL32); |
| 568 | #else |
Yinghai Lu | 5fef55f | 2008-09-04 21:09:43 +0200 | [diff] [blame] | 569 | /* Set MTRR capability flag if appropriate */ |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 570 | if (c->x86 == 5) |
| 571 | if (c->x86_model == 13 || c->x86_model == 9 || |
Jia Zhang | 06be007 | 2018-01-01 09:52:10 +0800 | [diff] [blame^] | 572 | (c->x86_model == 8 && c->x86_stepping >= 8)) |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 573 | set_cpu_cap(c, X86_FEATURE_K6_MTRR); |
| 574 | #endif |
Andreas Herrmann | 42937e8 | 2009-06-08 15:55:09 +0200 | [diff] [blame] | 575 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) |
Aravind Gopalakrishnan | b9d16a2 | 2015-04-27 10:25:51 -0500 | [diff] [blame] | 576 | /* |
| 577 | * ApicID can always be treated as an 8-bit value for AMD APIC versions |
| 578 | * >= 0x10, but even old K8s came out of reset with version 0x10. So, we |
| 579 | * can safely set X86_FEATURE_EXTD_APICID unconditionally for families |
| 580 | * after 16h. |
| 581 | */ |
Borislav Petkov | 425d8c2 | 2016-04-05 08:29:51 +0200 | [diff] [blame] | 582 | if (boot_cpu_has(X86_FEATURE_APIC)) { |
| 583 | if (c->x86 > 0x16) |
Andreas Herrmann | 42937e8 | 2009-06-08 15:55:09 +0200 | [diff] [blame] | 584 | set_cpu_cap(c, X86_FEATURE_EXTD_APICID); |
Borislav Petkov | 425d8c2 | 2016-04-05 08:29:51 +0200 | [diff] [blame] | 585 | else if (c->x86 >= 0xf) { |
| 586 | /* check CPU config space for extended APIC ID */ |
| 587 | unsigned int val; |
| 588 | |
| 589 | val = read_pci_config(0, 24, 0, 0x68); |
| 590 | if ((val >> 17 & 0x3) == 0x3) |
| 591 | set_cpu_cap(c, X86_FEATURE_EXTD_APICID); |
| 592 | } |
Andreas Herrmann | 42937e8 | 2009-06-08 15:55:09 +0200 | [diff] [blame] | 593 | } |
| 594 | #endif |
Borislav Petkov | 3b56496 | 2014-01-15 00:07:11 +0100 | [diff] [blame] | 595 | |
Paolo Bonzini | c1118b3 | 2014-09-22 13:17:48 +0200 | [diff] [blame] | 596 | /* |
| 597 | * This is only needed to tell the kernel whether to use VMCALL |
| 598 | * and VMMCALL. VMMCALL is never executed except under virt, so |
| 599 | * we can set it unconditionally. |
| 600 | */ |
| 601 | set_cpu_cap(c, X86_FEATURE_VMMCALL); |
| 602 | |
Borislav Petkov | 3b56496 | 2014-01-15 00:07:11 +0100 | [diff] [blame] | 603 | /* F16h erratum 793, CVE-2013-6885 */ |
Borislav Petkov | 8f86a73 | 2014-03-09 18:05:24 +0100 | [diff] [blame] | 604 | if (c->x86 == 0x16 && c->x86_model <= 0xf) |
| 605 | msr_set_bit(MSR_AMD64_LS_CFG, 15); |
Andi Kleen | 2b16a23 | 2008-01-30 13:32:40 +0100 | [diff] [blame] | 606 | |
Thomas Gleixner | bd7e769 | 2016-12-09 19:29:09 +0100 | [diff] [blame] | 607 | /* |
| 608 | * Check whether the machine is affected by erratum 400. This is |
| 609 | * used to select the proper idle routine and to enable the check |
| 610 | * whether the machine is affected in arch_post_acpi_init(), which |
| 611 | * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. |
| 612 | */ |
| 613 | if (cpu_has_amd_erratum(c, amd_erratum_400)) |
| 614 | set_cpu_bug(c, X86_BUG_AMD_E400); |
| 615 | } |
Borislav Petkov | e6ee94d | 2013-03-20 15:07:27 +0100 | [diff] [blame] | 616 | |
Borislav Petkov | 26bfa5f | 2014-06-24 13:25:04 +0200 | [diff] [blame] | 617 | static void init_amd_k8(struct cpuinfo_x86 *c) |
| 618 | { |
| 619 | u32 level; |
| 620 | u64 value; |
| 621 | |
| 622 | /* On C+ stepping K8 rep microcode works well for copy/memset */ |
| 623 | level = cpuid_eax(1); |
| 624 | if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) |
| 625 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
| 626 | |
| 627 | /* |
| 628 | * Some BIOSes incorrectly force this feature, but only K8 revision D |
| 629 | * (model = 0x14) and later actually support it. |
| 630 | * (AMD Erratum #110, docId: 25759). |
| 631 | */ |
| 632 | if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { |
| 633 | clear_cpu_cap(c, X86_FEATURE_LAHF_LM); |
| 634 | if (!rdmsrl_amd_safe(0xc001100d, &value)) { |
| 635 | value &= ~BIT_64(32); |
| 636 | wrmsrl_amd_safe(0xc001100d, value); |
| 637 | } |
| 638 | } |
| 639 | |
| 640 | if (!c->x86_model_id[0]) |
| 641 | strcpy(c->x86_model_id, "Hammer"); |
Borislav Petkov | 6f9b63a | 2014-07-29 17:41:23 +0200 | [diff] [blame] | 642 | |
| 643 | #ifdef CONFIG_SMP |
| 644 | /* |
| 645 | * Disable TLB flush filter by setting HWCR.FFDIS on K8 |
| 646 | * bit 6 of msr C001_0015 |
| 647 | * |
| 648 | * Errata 63 for SH-B3 steppings |
| 649 | * Errata 122 for all steppings (F+ have it disabled by default) |
| 650 | */ |
| 651 | msr_set_bit(MSR_K7_HWCR, 6); |
| 652 | #endif |
Borislav Petkov | 96e5d28 | 2016-04-07 17:31:49 -0700 | [diff] [blame] | 653 | set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); |
Borislav Petkov | 26bfa5f | 2014-06-24 13:25:04 +0200 | [diff] [blame] | 654 | } |
| 655 | |
| 656 | static void init_amd_gh(struct cpuinfo_x86 *c) |
| 657 | { |
| 658 | #ifdef CONFIG_X86_64 |
| 659 | /* do this for boot cpu */ |
| 660 | if (c == &boot_cpu_data) |
| 661 | check_enable_amd_mmconf_dmi(); |
| 662 | |
| 663 | fam10h_check_enable_mmcfg(); |
| 664 | #endif |
| 665 | |
| 666 | /* |
| 667 | * Disable GART TLB Walk Errors on Fam10h. We do this here because this |
| 668 | * is always needed when GART is enabled, even in a kernel which has no |
| 669 | * MCE support built in. BIOS should disable GartTlbWlk Errors already. |
| 670 | * If it doesn't, we do it here as suggested by the BKDG. |
| 671 | * |
| 672 | * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 |
| 673 | */ |
| 674 | msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); |
| 675 | |
| 676 | /* |
| 677 | * On family 10h BIOS may not have properly enabled WC+ support, causing |
| 678 | * it to be converted to CD memtype. This may result in performance |
| 679 | * degradation for certain nested-paging guests. Prevent this conversion |
| 680 | * by clearing bit 24 in MSR_AMD64_BU_CFG2. |
| 681 | * |
| 682 | * NOTE: we want to use the _safe accessors so as not to #GP kvm |
| 683 | * guests on older kvm hosts. |
| 684 | */ |
| 685 | msr_clear_bit(MSR_AMD64_BU_CFG2, 24); |
| 686 | |
| 687 | if (cpu_has_amd_erratum(c, amd_erratum_383)) |
| 688 | set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); |
| 689 | } |
| 690 | |
Emanuel Czirai | d199299 | 2016-09-02 07:35:50 +0200 | [diff] [blame] | 691 | #define MSR_AMD64_DE_CFG 0xC0011029 |
| 692 | |
| 693 | static void init_amd_ln(struct cpuinfo_x86 *c) |
| 694 | { |
| 695 | /* |
| 696 | * Apply erratum 665 fix unconditionally so machines without a BIOS |
| 697 | * fix work. |
| 698 | */ |
| 699 | msr_set_bit(MSR_AMD64_DE_CFG, 31); |
| 700 | } |
| 701 | |
Borislav Petkov | 26bfa5f | 2014-06-24 13:25:04 +0200 | [diff] [blame] | 702 | static void init_amd_bd(struct cpuinfo_x86 *c) |
| 703 | { |
| 704 | u64 value; |
| 705 | |
| 706 | /* re-enable TopologyExtensions if switched off by BIOS */ |
Borislav Petkov | 96685a5 | 2016-06-01 12:04:28 +0200 | [diff] [blame] | 707 | if ((c->x86_model >= 0x10) && (c->x86_model <= 0x6f) && |
Borislav Petkov | 26bfa5f | 2014-06-24 13:25:04 +0200 | [diff] [blame] | 708 | !cpu_has(c, X86_FEATURE_TOPOEXT)) { |
| 709 | |
| 710 | if (msr_set_bit(0xc0011005, 54) > 0) { |
| 711 | rdmsrl(0xc0011005, value); |
| 712 | if (value & BIT_64(54)) { |
| 713 | set_cpu_cap(c, X86_FEATURE_TOPOEXT); |
Borislav Petkov | 96685a5 | 2016-06-01 12:04:28 +0200 | [diff] [blame] | 714 | pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n"); |
Borislav Petkov | 26bfa5f | 2014-06-24 13:25:04 +0200 | [diff] [blame] | 715 | } |
| 716 | } |
| 717 | } |
| 718 | |
| 719 | /* |
| 720 | * The way access filter has a performance penalty on some workloads. |
| 721 | * Disable it on the affected CPUs. |
| 722 | */ |
| 723 | if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { |
Borislav Petkov | ae8b787 | 2015-11-23 11:12:23 +0100 | [diff] [blame] | 724 | if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { |
Borislav Petkov | 26bfa5f | 2014-06-24 13:25:04 +0200 | [diff] [blame] | 725 | value |= 0x1E; |
Borislav Petkov | ae8b787 | 2015-11-23 11:12:23 +0100 | [diff] [blame] | 726 | wrmsrl_safe(MSR_F15H_IC_CFG, value); |
Borislav Petkov | 26bfa5f | 2014-06-24 13:25:04 +0200 | [diff] [blame] | 727 | } |
| 728 | } |
| 729 | } |
| 730 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 731 | static void init_amd(struct cpuinfo_x86 *c) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 732 | { |
Linus Torvalds | 8e8da02 | 2011-12-04 11:57:09 -0800 | [diff] [blame] | 733 | u32 dummy; |
Andi Kleen | 7d318d7 | 2005-09-29 22:05:55 +0200 | [diff] [blame] | 734 | |
Andi Kleen | 2b16a23 | 2008-01-30 13:32:40 +0100 | [diff] [blame] | 735 | early_init_amd(c); |
| 736 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 737 | /* |
Paolo Ciarrocchi | fb87a29 | 2008-02-22 23:10:33 +0100 | [diff] [blame] | 738 | * Bit 31 in normal CPUID used for nonstandard 3DNow ID; |
Ingo Molnar | 16282a8 | 2008-02-26 08:49:57 +0100 | [diff] [blame] | 739 | * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway |
Paolo Ciarrocchi | fb87a29 | 2008-02-22 23:10:33 +0100 | [diff] [blame] | 740 | */ |
Ingo Molnar | 16282a8 | 2008-02-26 08:49:57 +0100 | [diff] [blame] | 741 | clear_cpu_cap(c, 0*32+31); |
Paolo Ciarrocchi | fb87a29 | 2008-02-22 23:10:33 +0100 | [diff] [blame] | 742 | |
Borislav Petkov | 12d8a96 | 2010-06-02 20:29:21 +0200 | [diff] [blame] | 743 | if (c->x86 >= 0x10) |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 744 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
Yinghai Lu | 0d96b9f | 2009-08-29 13:17:14 -0700 | [diff] [blame] | 745 | |
| 746 | /* get apicid instead of initial apic id from cpuid */ |
| 747 | c->apicid = hard_smp_processor_id(); |
Andi Kleen | 3556ddf | 2007-04-02 12:14:12 +0200 | [diff] [blame] | 748 | |
Andi Kleen | c12ceb7 | 2007-05-21 14:31:47 +0200 | [diff] [blame] | 749 | /* K6s reports MCEs but don't actually have all the MSRs */ |
| 750 | if (c->x86 < 6) |
Ingo Molnar | 16282a8 | 2008-02-26 08:49:57 +0100 | [diff] [blame] | 751 | clear_cpu_cap(c, X86_FEATURE_MCE); |
Borislav Petkov | 26bfa5f | 2014-06-24 13:25:04 +0200 | [diff] [blame] | 752 | |
| 753 | switch (c->x86) { |
| 754 | case 4: init_amd_k5(c); break; |
| 755 | case 5: init_amd_k6(c); break; |
| 756 | case 6: init_amd_k7(c); break; |
| 757 | case 0xf: init_amd_k8(c); break; |
| 758 | case 0x10: init_amd_gh(c); break; |
Emanuel Czirai | d199299 | 2016-09-02 07:35:50 +0200 | [diff] [blame] | 759 | case 0x12: init_amd_ln(c); break; |
Borislav Petkov | 26bfa5f | 2014-06-24 13:25:04 +0200 | [diff] [blame] | 760 | case 0x15: init_amd_bd(c); break; |
| 761 | } |
Andi Kleen | de42186 | 2008-01-30 13:32:37 +0100 | [diff] [blame] | 762 | |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 763 | /* Enable workaround for FXSAVE leak */ |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 764 | if (c->x86 >= 6) |
Borislav Petkov | 9b13a93 | 2014-06-18 00:06:23 +0200 | [diff] [blame] | 765 | set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 766 | |
Borislav Petkov | 27c13ec | 2009-11-21 14:01:45 +0100 | [diff] [blame] | 767 | cpu_detect_cache_sizes(c); |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 768 | |
| 769 | /* Multi core CPU? */ |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 770 | if (c->extended_cpuid_level >= 0x80000008) { |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 771 | amd_detect_cmp(c); |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 772 | srat_detect_node(c); |
| 773 | } |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 774 | |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 775 | #ifdef CONFIG_X86_32 |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 776 | detect_ht(c); |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 777 | #endif |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 778 | |
Andreas Herrmann | 04a1541 | 2012-10-19 10:59:33 +0200 | [diff] [blame] | 779 | init_amd_cacheinfo(c); |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 780 | |
Borislav Petkov | 12d8a96 | 2010-06-02 20:29:21 +0200 | [diff] [blame] | 781 | if (c->x86 >= 0xf) |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 782 | set_cpu_cap(c, X86_FEATURE_K8); |
| 783 | |
Borislav Petkov | 054efb6 | 2016-03-29 17:42:00 +0200 | [diff] [blame] | 784 | if (cpu_has(c, X86_FEATURE_XMM2)) { |
Tom Lendacky | 9c5e750 | 2018-01-08 16:09:32 -0600 | [diff] [blame] | 785 | unsigned long long val; |
| 786 | int ret; |
| 787 | |
Tom Lendacky | abcc3e5 | 2018-01-08 16:09:21 -0600 | [diff] [blame] | 788 | /* |
| 789 | * A serializing LFENCE has less overhead than MFENCE, so |
| 790 | * use it for execution serialization. On families which |
| 791 | * don't have that MSR, LFENCE is already serializing. |
| 792 | * msr_set_bit() uses the safe accessors, too, even if the MSR |
| 793 | * is not present. |
| 794 | */ |
| 795 | msr_set_bit(MSR_F10H_DECFG, |
| 796 | MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT); |
| 797 | |
Tom Lendacky | 9c5e750 | 2018-01-08 16:09:32 -0600 | [diff] [blame] | 798 | /* |
| 799 | * Verify that the MSR write was successful (could be running |
| 800 | * under a hypervisor) and only then assume that LFENCE is |
| 801 | * serializing. |
| 802 | */ |
| 803 | ret = rdmsrl_safe(MSR_F10H_DECFG, &val); |
| 804 | if (!ret && (val & MSR_F10H_DECFG_LFENCE_SERIALIZE)) { |
| 805 | /* A serializing LFENCE stops RDTSC speculation */ |
| 806 | set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); |
| 807 | } else { |
| 808 | /* MFENCE stops RDTSC speculation */ |
| 809 | set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); |
| 810 | } |
Yinghai Lu | 11fdd25 | 2008-09-07 17:58:50 -0700 | [diff] [blame] | 811 | } |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 812 | |
Boris Ostrovsky | e9cdd34 | 2011-05-26 11:19:52 -0400 | [diff] [blame] | 813 | /* |
| 814 | * Family 0x12 and above processors have APIC timer |
| 815 | * running in deep C states. |
| 816 | */ |
| 817 | if (c->x86 > 0x11) |
Boris Ostrovsky | b87cf80 | 2011-03-15 12:13:44 -0400 | [diff] [blame] | 818 | set_cpu_cap(c, X86_FEATURE_ARAT); |
Joerg Roedel | 5bbc097 | 2011-04-15 14:47:40 +0200 | [diff] [blame] | 819 | |
Linus Torvalds | 8e8da02 | 2011-12-04 11:57:09 -0800 | [diff] [blame] | 820 | rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); |
Borislav Petkov | a930dc4 | 2015-01-18 17:48:18 +0100 | [diff] [blame] | 821 | |
| 822 | /* 3DNow or LM implies PREFETCHW */ |
| 823 | if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) |
| 824 | if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) |
| 825 | set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); |
Andy Lutomirski | 61f01dd | 2015-04-26 16:47:59 -0700 | [diff] [blame] | 826 | |
| 827 | /* AMD CPUs don't reset SS attributes on SYSRET */ |
| 828 | set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 829 | } |
| 830 | |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 831 | #ifdef CONFIG_X86_32 |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 832 | static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 833 | { |
| 834 | /* AMD errata T13 (order #21922) */ |
| 835 | if ((c->x86 == 6)) { |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 836 | /* Duron Rev A0 */ |
Jia Zhang | 06be007 | 2018-01-01 09:52:10 +0800 | [diff] [blame^] | 837 | if (c->x86_model == 3 && c->x86_stepping == 0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 838 | size = 64; |
Alan Cox | 8bdbd96 | 2009-07-04 00:35:45 +0100 | [diff] [blame] | 839 | /* Tbird rev A1/A2 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 840 | if (c->x86_model == 4 && |
Jia Zhang | 06be007 | 2018-01-01 09:52:10 +0800 | [diff] [blame^] | 841 | (c->x86_stepping == 0 || c->x86_stepping == 1)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 842 | size = 256; |
| 843 | } |
| 844 | return size; |
| 845 | } |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 846 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 847 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 848 | static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) |
Borislav Petkov | b46882e | 2012-08-06 19:00:38 +0200 | [diff] [blame] | 849 | { |
| 850 | u32 ebx, eax, ecx, edx; |
| 851 | u16 mask = 0xfff; |
| 852 | |
| 853 | if (c->x86 < 0xf) |
| 854 | return; |
| 855 | |
| 856 | if (c->extended_cpuid_level < 0x80000006) |
| 857 | return; |
| 858 | |
| 859 | cpuid(0x80000006, &eax, &ebx, &ecx, &edx); |
| 860 | |
| 861 | tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; |
| 862 | tlb_lli_4k[ENTRIES] = ebx & mask; |
| 863 | |
| 864 | /* |
| 865 | * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB |
| 866 | * characteristics from the CPUID function 0x80000005 instead. |
| 867 | */ |
| 868 | if (c->x86 == 0xf) { |
| 869 | cpuid(0x80000005, &eax, &ebx, &ecx, &edx); |
| 870 | mask = 0xff; |
| 871 | } |
| 872 | |
| 873 | /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ |
Borislav Petkov | d139336 | 2014-01-15 12:52:15 +0100 | [diff] [blame] | 874 | if (!((eax >> 16) & mask)) |
| 875 | tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; |
| 876 | else |
Borislav Petkov | b46882e | 2012-08-06 19:00:38 +0200 | [diff] [blame] | 877 | tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; |
Borislav Petkov | b46882e | 2012-08-06 19:00:38 +0200 | [diff] [blame] | 878 | |
| 879 | /* a 4M entry uses two 2M entries */ |
| 880 | tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; |
| 881 | |
| 882 | /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ |
| 883 | if (!(eax & mask)) { |
| 884 | /* Erratum 658 */ |
| 885 | if (c->x86 == 0x15 && c->x86_model <= 0x1f) { |
| 886 | tlb_lli_2m[ENTRIES] = 1024; |
| 887 | } else { |
| 888 | cpuid(0x80000005, &eax, &ebx, &ecx, &edx); |
| 889 | tlb_lli_2m[ENTRIES] = eax & 0xff; |
| 890 | } |
| 891 | } else |
| 892 | tlb_lli_2m[ENTRIES] = eax & mask; |
| 893 | |
| 894 | tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; |
| 895 | } |
| 896 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 897 | static const struct cpu_dev amd_cpu_dev = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 898 | .c_vendor = "AMD", |
Paolo Ciarrocchi | fb87a29 | 2008-02-22 23:10:33 +0100 | [diff] [blame] | 899 | .c_ident = { "AuthenticAMD" }, |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 900 | #ifdef CONFIG_X86_32 |
Jan Beulich | 09dc68d | 2013-10-21 09:35:20 +0100 | [diff] [blame] | 901 | .legacy_models = { |
| 902 | { .family = 4, .model_names = |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 903 | { |
| 904 | [3] = "486 DX/2", |
| 905 | [7] = "486 DX/2-WB", |
Paolo Ciarrocchi | fb87a29 | 2008-02-22 23:10:33 +0100 | [diff] [blame] | 906 | [8] = "486 DX/4", |
| 907 | [9] = "486 DX/4-WB", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 908 | [14] = "Am5x86-WT", |
Paolo Ciarrocchi | fb87a29 | 2008-02-22 23:10:33 +0100 | [diff] [blame] | 909 | [15] = "Am5x86-WB" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 910 | } |
| 911 | }, |
| 912 | }, |
Jan Beulich | 09dc68d | 2013-10-21 09:35:20 +0100 | [diff] [blame] | 913 | .legacy_cache_size = amd_size_cache, |
Yinghai Lu | 6c62aa4 | 2008-09-07 17:58:54 -0700 | [diff] [blame] | 914 | #endif |
Thomas Petazzoni | 03ae576 | 2008-02-15 12:00:23 +0100 | [diff] [blame] | 915 | .c_early_init = early_init_amd, |
Borislav Petkov | b46882e | 2012-08-06 19:00:38 +0200 | [diff] [blame] | 916 | .c_detect_tlb = cpu_detect_tlb_amd, |
Borislav Petkov | 8fa8b03 | 2011-08-05 20:04:09 +0200 | [diff] [blame] | 917 | .c_bsp_init = bsp_init_amd, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 918 | .c_init = init_amd, |
Yinghai Lu | 10a434f | 2008-09-04 21:09:45 +0200 | [diff] [blame] | 919 | .c_x86_vendor = X86_VENDOR_AMD, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 920 | }; |
| 921 | |
Yinghai Lu | 10a434f | 2008-09-04 21:09:45 +0200 | [diff] [blame] | 922 | cpu_dev_register(amd_cpu_dev); |
Hans Rosenfeld | d78d671 | 2010-07-28 19:09:30 +0200 | [diff] [blame] | 923 | |
| 924 | /* |
| 925 | * AMD errata checking |
| 926 | * |
| 927 | * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or |
| 928 | * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that |
| 929 | * have an OSVW id assigned, which it takes as first argument. Both take a |
| 930 | * variable number of family-specific model-stepping ranges created by |
Borislav Petkov | 7d7dc11 | 2013-03-20 15:07:28 +0100 | [diff] [blame] | 931 | * AMD_MODEL_RANGE(). |
Hans Rosenfeld | d78d671 | 2010-07-28 19:09:30 +0200 | [diff] [blame] | 932 | * |
| 933 | * Example: |
| 934 | * |
| 935 | * const int amd_erratum_319[] = |
| 936 | * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), |
| 937 | * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), |
| 938 | * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); |
| 939 | */ |
| 940 | |
Borislav Petkov | 7d7dc11 | 2013-03-20 15:07:28 +0100 | [diff] [blame] | 941 | #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } |
| 942 | #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } |
| 943 | #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ |
| 944 | ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) |
| 945 | #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) |
| 946 | #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) |
| 947 | #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) |
| 948 | |
| 949 | static const int amd_erratum_400[] = |
Borislav Petkov | 328935e | 2011-05-17 14:55:18 +0200 | [diff] [blame] | 950 | AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), |
Hans Rosenfeld | 9d8888c | 2010-07-28 19:09:31 +0200 | [diff] [blame] | 951 | AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); |
| 952 | |
Borislav Petkov | e6ee94d | 2013-03-20 15:07:27 +0100 | [diff] [blame] | 953 | static const int amd_erratum_383[] = |
Hans Rosenfeld | 1be85a6 | 2010-07-28 19:09:32 +0200 | [diff] [blame] | 954 | AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); |
Hans Rosenfeld | 9d8888c | 2010-07-28 19:09:31 +0200 | [diff] [blame] | 955 | |
Torsten Kaiser | 8c6b79b | 2013-07-23 19:40:49 +0200 | [diff] [blame] | 956 | |
| 957 | static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) |
Hans Rosenfeld | d78d671 | 2010-07-28 19:09:30 +0200 | [diff] [blame] | 958 | { |
Hans Rosenfeld | d78d671 | 2010-07-28 19:09:30 +0200 | [diff] [blame] | 959 | int osvw_id = *erratum++; |
| 960 | u32 range; |
| 961 | u32 ms; |
| 962 | |
Hans Rosenfeld | d78d671 | 2010-07-28 19:09:30 +0200 | [diff] [blame] | 963 | if (osvw_id >= 0 && osvw_id < 65536 && |
| 964 | cpu_has(cpu, X86_FEATURE_OSVW)) { |
| 965 | u64 osvw_len; |
| 966 | |
| 967 | rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); |
| 968 | if (osvw_id < osvw_len) { |
| 969 | u64 osvw_bits; |
| 970 | |
| 971 | rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), |
| 972 | osvw_bits); |
| 973 | return osvw_bits & (1ULL << (osvw_id & 0x3f)); |
| 974 | } |
| 975 | } |
| 976 | |
| 977 | /* OSVW unavailable or ID unknown, match family-model-stepping range */ |
Jia Zhang | 06be007 | 2018-01-01 09:52:10 +0800 | [diff] [blame^] | 978 | ms = (cpu->x86_model << 4) | cpu->x86_stepping; |
Hans Rosenfeld | d78d671 | 2010-07-28 19:09:30 +0200 | [diff] [blame] | 979 | while ((range = *erratum++)) |
| 980 | if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && |
| 981 | (ms >= AMD_MODEL_RANGE_START(range)) && |
| 982 | (ms <= AMD_MODEL_RANGE_END(range))) |
| 983 | return true; |
| 984 | |
| 985 | return false; |
| 986 | } |
Jacob Shin | d6d55f0 | 2014-05-29 17:26:50 +0200 | [diff] [blame] | 987 | |
| 988 | void set_dr_addr_mask(unsigned long mask, int dr) |
| 989 | { |
Borislav Petkov | 362f924 | 2015-12-07 10:39:41 +0100 | [diff] [blame] | 990 | if (!boot_cpu_has(X86_FEATURE_BPEXT)) |
Jacob Shin | d6d55f0 | 2014-05-29 17:26:50 +0200 | [diff] [blame] | 991 | return; |
| 992 | |
| 993 | switch (dr) { |
| 994 | case 0: |
| 995 | wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); |
| 996 | break; |
| 997 | case 1: |
| 998 | case 2: |
| 999 | case 3: |
| 1000 | wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); |
| 1001 | break; |
| 1002 | default: |
| 1003 | break; |
| 1004 | } |
| 1005 | } |