blob: 55b08e84ac8df5d08912bf61d10eb511f0bf9ec0 [file] [log] [blame]
Chris Leechc13c8262006-05-23 17:18:44 -07001/*
2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
20 */
21#ifndef DMAENGINE_H
22#define DMAENGINE_H
David Woodhouse1c0f16e2006-06-27 02:53:56 -070023
Chris Leechc13c8262006-05-23 17:18:44 -070024#include <linux/device.h>
25#include <linux/uio.h>
Dan Williams7405f742007-01-02 11:10:43 -070026#include <linux/dma-mapping.h>
Chris Leechc13c8262006-05-23 17:18:44 -070027
28/**
Randy Dunlapfe4ada22006-07-03 19:44:51 -070029 * typedef dma_cookie_t - an opaque DMA cookie
Chris Leechc13c8262006-05-23 17:18:44 -070030 *
31 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
32 */
33typedef s32 dma_cookie_t;
Steven J. Magnani76bd0612010-02-28 22:18:16 -070034#define DMA_MIN_COOKIE 1
35#define DMA_MAX_COOKIE INT_MAX
Chris Leechc13c8262006-05-23 17:18:44 -070036
37#define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
38
39/**
40 * enum dma_status - DMA transaction status
41 * @DMA_SUCCESS: transaction completed successfully
42 * @DMA_IN_PROGRESS: transaction not yet processed
Linus Walleij07934482010-03-26 16:50:49 -070043 * @DMA_PAUSED: transaction is paused
Chris Leechc13c8262006-05-23 17:18:44 -070044 * @DMA_ERROR: transaction failed
45 */
46enum dma_status {
47 DMA_SUCCESS,
48 DMA_IN_PROGRESS,
Linus Walleij07934482010-03-26 16:50:49 -070049 DMA_PAUSED,
Chris Leechc13c8262006-05-23 17:18:44 -070050 DMA_ERROR,
51};
52
53/**
Dan Williams7405f742007-01-02 11:10:43 -070054 * enum dma_transaction_type - DMA transaction types/indexes
Dan Williams138f4c32009-09-08 17:42:51 -070055 *
56 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
57 * automatically set as dma devices are registered.
Dan Williams7405f742007-01-02 11:10:43 -070058 */
59enum dma_transaction_type {
60 DMA_MEMCPY,
61 DMA_XOR,
Dan Williamsb2f46fd2009-07-14 12:20:36 -070062 DMA_PQ,
Dan Williams099f53c2009-04-08 14:28:37 -070063 DMA_XOR_VAL,
64 DMA_PQ_VAL,
Dan Williams7405f742007-01-02 11:10:43 -070065 DMA_MEMSET,
Dan Williams7405f742007-01-02 11:10:43 -070066 DMA_INTERRUPT,
Dan Williams59b5ec22009-01-06 11:38:15 -070067 DMA_PRIVATE,
Dan Williams138f4c32009-09-08 17:42:51 -070068 DMA_ASYNC_TX,
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -070069 DMA_SLAVE,
Dan Williams7405f742007-01-02 11:10:43 -070070};
71
72/* last transaction type for creation of the capabilities mask */
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -070073#define DMA_TX_TYPE_END (DMA_SLAVE + 1)
74
Dan Williams7405f742007-01-02 11:10:43 -070075
76/**
Dan Williams636bdea2008-04-17 20:17:26 -070077 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
Dan Williamsb2f46fd2009-07-14 12:20:36 -070078 * control completion, and communicate status.
Dan Williamsd4c56f92008-02-02 19:49:58 -070079 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
Dan Williamsb2f46fd2009-07-14 12:20:36 -070080 * this transaction
Guennadi Liakhovetskia88f6662009-12-10 18:35:15 +010081 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
Dan Williamsb2f46fd2009-07-14 12:20:36 -070082 * acknowledges receipt, i.e. has has a chance to establish any dependency
83 * chains
Dan Williamse1d181e2008-07-04 00:13:40 -070084 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
85 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
Maciej Sosnowski4f005db2009-04-23 12:31:51 +020086 * @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single
87 * (if not set, do the source dma-unmapping as page)
88 * @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single
89 * (if not set, do the destination dma-unmapping as page)
Dan Williamsb2f46fd2009-07-14 12:20:36 -070090 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
91 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
92 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
93 * sources that were the result of a previous operation, in the case of a PQ
94 * operation it continues the calculation with new sources
Dan Williams0403e382009-09-08 17:42:50 -070095 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
96 * on the result of this operation
Dan Williamsd4c56f92008-02-02 19:49:58 -070097 */
Dan Williams636bdea2008-04-17 20:17:26 -070098enum dma_ctrl_flags {
Dan Williamsd4c56f92008-02-02 19:49:58 -070099 DMA_PREP_INTERRUPT = (1 << 0),
Dan Williams636bdea2008-04-17 20:17:26 -0700100 DMA_CTRL_ACK = (1 << 1),
Dan Williamse1d181e2008-07-04 00:13:40 -0700101 DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
102 DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
Maciej Sosnowski4f005db2009-04-23 12:31:51 +0200103 DMA_COMPL_SRC_UNMAP_SINGLE = (1 << 4),
104 DMA_COMPL_DEST_UNMAP_SINGLE = (1 << 5),
Dan Williamsf9dd2132009-09-08 17:42:29 -0700105 DMA_PREP_PQ_DISABLE_P = (1 << 6),
106 DMA_PREP_PQ_DISABLE_Q = (1 << 7),
107 DMA_PREP_CONTINUE = (1 << 8),
Dan Williams0403e382009-09-08 17:42:50 -0700108 DMA_PREP_FENCE = (1 << 9),
Dan Williamsd4c56f92008-02-02 19:49:58 -0700109};
110
111/**
Linus Walleijc3635c72010-03-26 16:44:01 -0700112 * enum dma_ctrl_cmd - DMA operations that can optionally be exercised
113 * on a running channel.
114 * @DMA_TERMINATE_ALL: terminate all ongoing transfers
115 * @DMA_PAUSE: pause ongoing transfers
116 * @DMA_RESUME: resume paused transfer
117 */
118enum dma_ctrl_cmd {
119 DMA_TERMINATE_ALL,
120 DMA_PAUSE,
121 DMA_RESUME,
122};
123
124/**
Dan Williamsad283ea2009-08-29 19:09:26 -0700125 * enum sum_check_bits - bit position of pq_check_flags
126 */
127enum sum_check_bits {
128 SUM_CHECK_P = 0,
129 SUM_CHECK_Q = 1,
130};
131
132/**
133 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
134 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
135 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
136 */
137enum sum_check_flags {
138 SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
139 SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
140};
141
142
143/**
Dan Williams7405f742007-01-02 11:10:43 -0700144 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
145 * See linux/cpumask.h
146 */
147typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
148
149/**
Chris Leechc13c8262006-05-23 17:18:44 -0700150 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
Chris Leechc13c8262006-05-23 17:18:44 -0700151 * @memcpy_count: transaction counter
152 * @bytes_transferred: byte counter
153 */
154
155struct dma_chan_percpu {
Chris Leechc13c8262006-05-23 17:18:44 -0700156 /* stats */
157 unsigned long memcpy_count;
158 unsigned long bytes_transferred;
159};
160
161/**
162 * struct dma_chan - devices supply DMA channels, clients use them
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700163 * @device: ptr to the dma device who supplies this channel, always !%NULL
Chris Leechc13c8262006-05-23 17:18:44 -0700164 * @cookie: last cookie value returned to client
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700165 * @chan_id: channel ID for sysfs
Dan Williams41d5e592009-01-06 11:38:21 -0700166 * @dev: class device for sysfs
Chris Leechc13c8262006-05-23 17:18:44 -0700167 * @device_node: used to add this to the device chan list
168 * @local: per-cpu pointer to a struct dma_chan_percpu
Dan Williams7cc5bf92008-07-08 11:58:21 -0700169 * @client-count: how many clients are using this channel
Dan Williamsbec08512009-01-06 11:38:14 -0700170 * @table_count: number of appearances in the mem-to-mem allocation table
Dan Williams287d8592009-02-18 14:48:26 -0800171 * @private: private data for certain client-channel associations
Chris Leechc13c8262006-05-23 17:18:44 -0700172 */
173struct dma_chan {
Chris Leechc13c8262006-05-23 17:18:44 -0700174 struct dma_device *device;
175 dma_cookie_t cookie;
176
177 /* sysfs */
178 int chan_id;
Dan Williams41d5e592009-01-06 11:38:21 -0700179 struct dma_chan_dev *dev;
Chris Leechc13c8262006-05-23 17:18:44 -0700180
Chris Leechc13c8262006-05-23 17:18:44 -0700181 struct list_head device_node;
Tejun Heoa29d8b82010-02-02 14:39:15 +0900182 struct dma_chan_percpu __percpu *local;
Dan Williams7cc5bf92008-07-08 11:58:21 -0700183 int client_count;
Dan Williamsbec08512009-01-06 11:38:14 -0700184 int table_count;
Dan Williams287d8592009-02-18 14:48:26 -0800185 void *private;
Chris Leechc13c8262006-05-23 17:18:44 -0700186};
187
Dan Williams41d5e592009-01-06 11:38:21 -0700188/**
189 * struct dma_chan_dev - relate sysfs device node to backing channel device
190 * @chan - driver channel device
191 * @device - sysfs device
Dan Williams864498a2009-01-06 11:38:21 -0700192 * @dev_id - parent dma_device dev_id
193 * @idr_ref - reference count to gate release of dma_device dev_id
Dan Williams41d5e592009-01-06 11:38:21 -0700194 */
195struct dma_chan_dev {
196 struct dma_chan *chan;
197 struct device device;
Dan Williams864498a2009-01-06 11:38:21 -0700198 int dev_id;
199 atomic_t *idr_ref;
Dan Williams41d5e592009-01-06 11:38:21 -0700200};
201
202static inline const char *dma_chan_name(struct dma_chan *chan)
203{
204 return dev_name(&chan->dev->device);
205}
Dan Williamsd379b012007-07-09 11:56:42 -0700206
Chris Leechc13c8262006-05-23 17:18:44 -0700207void dma_chan_cleanup(struct kref *kref);
208
Chris Leechc13c8262006-05-23 17:18:44 -0700209/**
Dan Williams59b5ec22009-01-06 11:38:15 -0700210 * typedef dma_filter_fn - callback filter for dma_request_channel
211 * @chan: channel to be reviewed
212 * @filter_param: opaque parameter passed through dma_request_channel
213 *
214 * When this optional parameter is specified in a call to dma_request_channel a
215 * suitable channel is passed to this routine for further dispositioning before
216 * being returned. Where 'suitable' indicates a non-busy channel that
Dan Williams7dd60252009-01-06 11:38:19 -0700217 * satisfies the given capability mask. It returns 'true' to indicate that the
218 * channel is suitable.
Dan Williams59b5ec22009-01-06 11:38:15 -0700219 */
Dan Williams7dd60252009-01-06 11:38:19 -0700220typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
Dan Williams59b5ec22009-01-06 11:38:15 -0700221
Dan Williams7405f742007-01-02 11:10:43 -0700222typedef void (*dma_async_tx_callback)(void *dma_async_param);
223/**
224 * struct dma_async_tx_descriptor - async transaction descriptor
225 * ---dma generic offload fields---
226 * @cookie: tracking cookie for this transaction, set to -EBUSY if
227 * this tx is sitting on a dependency list
Dan Williams636bdea2008-04-17 20:17:26 -0700228 * @flags: flags to augment operation preparation, control completion, and
229 * communicate status
Dan Williams7405f742007-01-02 11:10:43 -0700230 * @phys: physical address of the descriptor
Dan Williams7405f742007-01-02 11:10:43 -0700231 * @chan: target channel for this operation
232 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
Dan Williams7405f742007-01-02 11:10:43 -0700233 * @callback: routine to call after this operation is complete
234 * @callback_param: general parameter to pass to the callback routine
235 * ---async_tx api specific fields---
Dan Williams19242d72008-04-17 20:17:25 -0700236 * @next: at completion submit this descriptor
Dan Williams7405f742007-01-02 11:10:43 -0700237 * @parent: pointer to the next level up in the dependency chain
Dan Williams19242d72008-04-17 20:17:25 -0700238 * @lock: protect the parent and next pointers
Dan Williams7405f742007-01-02 11:10:43 -0700239 */
240struct dma_async_tx_descriptor {
241 dma_cookie_t cookie;
Dan Williams636bdea2008-04-17 20:17:26 -0700242 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
Dan Williams7405f742007-01-02 11:10:43 -0700243 dma_addr_t phys;
Dan Williams7405f742007-01-02 11:10:43 -0700244 struct dma_chan *chan;
245 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
Dan Williams7405f742007-01-02 11:10:43 -0700246 dma_async_tx_callback callback;
247 void *callback_param;
Dan Williams19242d72008-04-17 20:17:25 -0700248 struct dma_async_tx_descriptor *next;
Dan Williams7405f742007-01-02 11:10:43 -0700249 struct dma_async_tx_descriptor *parent;
250 spinlock_t lock;
251};
252
Chris Leechc13c8262006-05-23 17:18:44 -0700253/**
Linus Walleij07934482010-03-26 16:50:49 -0700254 * struct dma_tx_state - filled in to report the status of
255 * a transfer.
256 * @last: last completed DMA cookie
257 * @used: last issued DMA cookie (i.e. the one in progress)
258 * @residue: the remaining number of bytes left to transmit
259 * on the selected transfer for states DMA_IN_PROGRESS and
260 * DMA_PAUSED if this is implemented in the driver, else 0
261 */
262struct dma_tx_state {
263 dma_cookie_t last;
264 dma_cookie_t used;
265 u32 residue;
266};
267
268/**
Chris Leechc13c8262006-05-23 17:18:44 -0700269 * struct dma_device - info on the entity supplying DMA services
270 * @chancnt: how many DMA channels are supported
Atsushi Nemoto0f571512009-03-06 20:07:14 +0900271 * @privatecnt: how many DMA channels are requested by dma_request_channel
Chris Leechc13c8262006-05-23 17:18:44 -0700272 * @channels: the list of struct dma_chan
273 * @global_node: list_head for global dma_device_list
Dan Williams7405f742007-01-02 11:10:43 -0700274 * @cap_mask: one or more dma_capability flags
275 * @max_xor: maximum number of xor sources, 0 if no capability
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700276 * @max_pq: maximum number of PQ sources and PQ-continue capability
Dan Williams83544ae2009-09-08 17:42:53 -0700277 * @copy_align: alignment shift for memcpy operations
278 * @xor_align: alignment shift for xor operations
279 * @pq_align: alignment shift for pq operations
280 * @fill_align: alignment shift for memset operations
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700281 * @dev_id: unique device ID
Dan Williams7405f742007-01-02 11:10:43 -0700282 * @dev: struct device reference for dma mapping api
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700283 * @device_alloc_chan_resources: allocate resources and return the
284 * number of allocated descriptors
285 * @device_free_chan_resources: release DMA channel's resources
Dan Williams7405f742007-01-02 11:10:43 -0700286 * @device_prep_dma_memcpy: prepares a memcpy operation
287 * @device_prep_dma_xor: prepares a xor operation
Dan Williams099f53c2009-04-08 14:28:37 -0700288 * @device_prep_dma_xor_val: prepares a xor validation operation
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700289 * @device_prep_dma_pq: prepares a pq operation
290 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
Dan Williams7405f742007-01-02 11:10:43 -0700291 * @device_prep_dma_memset: prepares a memset operation
292 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -0700293 * @device_prep_slave_sg: prepares a slave dma operation
Linus Walleijc3635c72010-03-26 16:44:01 -0700294 * @device_control: manipulate all pending operations on a channel, returns
295 * zero or error code
Linus Walleij07934482010-03-26 16:50:49 -0700296 * @device_tx_status: poll for transaction completion, the optional
297 * txstate parameter can be supplied with a pointer to get a
298 * struct with auxilary transfer status information, otherwise the call
299 * will just return a simple status code
Dan Williams7405f742007-01-02 11:10:43 -0700300 * @device_issue_pending: push pending transactions to hardware
Chris Leechc13c8262006-05-23 17:18:44 -0700301 */
302struct dma_device {
303
304 unsigned int chancnt;
Atsushi Nemoto0f571512009-03-06 20:07:14 +0900305 unsigned int privatecnt;
Chris Leechc13c8262006-05-23 17:18:44 -0700306 struct list_head channels;
307 struct list_head global_node;
Dan Williams7405f742007-01-02 11:10:43 -0700308 dma_cap_mask_t cap_mask;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700309 unsigned short max_xor;
310 unsigned short max_pq;
Dan Williams83544ae2009-09-08 17:42:53 -0700311 u8 copy_align;
312 u8 xor_align;
313 u8 pq_align;
314 u8 fill_align;
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700315 #define DMA_HAS_PQ_CONTINUE (1 << 15)
Chris Leechc13c8262006-05-23 17:18:44 -0700316
Chris Leechc13c8262006-05-23 17:18:44 -0700317 int dev_id;
Dan Williams7405f742007-01-02 11:10:43 -0700318 struct device *dev;
Chris Leechc13c8262006-05-23 17:18:44 -0700319
Dan Williamsaa1e6f12009-01-06 11:38:17 -0700320 int (*device_alloc_chan_resources)(struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700321 void (*device_free_chan_resources)(struct dma_chan *chan);
Dan Williams7405f742007-01-02 11:10:43 -0700322
323 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
Dan Williams00367312008-02-02 19:49:57 -0700324 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700325 size_t len, unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700326 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
Dan Williams00367312008-02-02 19:49:57 -0700327 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700328 unsigned int src_cnt, size_t len, unsigned long flags);
Dan Williams099f53c2009-04-08 14:28:37 -0700329 struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
Dan Williams00367312008-02-02 19:49:57 -0700330 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
Dan Williamsad283ea2009-08-29 19:09:26 -0700331 size_t len, enum sum_check_flags *result, unsigned long flags);
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700332 struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
333 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
334 unsigned int src_cnt, const unsigned char *scf,
335 size_t len, unsigned long flags);
336 struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
337 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
338 unsigned int src_cnt, const unsigned char *scf, size_t len,
339 enum sum_check_flags *pqres, unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700340 struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
Dan Williams00367312008-02-02 19:49:57 -0700341 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700342 unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700343 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
Dan Williams636bdea2008-04-17 20:17:26 -0700344 struct dma_chan *chan, unsigned long flags);
Dan Williams7405f742007-01-02 11:10:43 -0700345
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -0700346 struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
347 struct dma_chan *chan, struct scatterlist *sgl,
348 unsigned int sg_len, enum dma_data_direction direction,
349 unsigned long flags);
Linus Walleijc3635c72010-03-26 16:44:01 -0700350 int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd);
Haavard Skinnemoendc0ee6432008-07-08 11:59:35 -0700351
Linus Walleij07934482010-03-26 16:50:49 -0700352 enum dma_status (*device_tx_status)(struct dma_chan *chan,
353 dma_cookie_t cookie,
354 struct dma_tx_state *txstate);
Dan Williams7405f742007-01-02 11:10:43 -0700355 void (*device_issue_pending)(struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700356};
357
Dan Williams83544ae2009-09-08 17:42:53 -0700358static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len)
359{
360 size_t mask;
361
362 if (!align)
363 return true;
364 mask = (1 << align) - 1;
365 if (mask & (off1 | off2 | len))
366 return false;
367 return true;
368}
369
370static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
371 size_t off2, size_t len)
372{
373 return dmaengine_check_align(dev->copy_align, off1, off2, len);
374}
375
376static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
377 size_t off2, size_t len)
378{
379 return dmaengine_check_align(dev->xor_align, off1, off2, len);
380}
381
382static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
383 size_t off2, size_t len)
384{
385 return dmaengine_check_align(dev->pq_align, off1, off2, len);
386}
387
388static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
389 size_t off2, size_t len)
390{
391 return dmaengine_check_align(dev->fill_align, off1, off2, len);
392}
393
Dan Williamsb2f46fd2009-07-14 12:20:36 -0700394static inline void
395dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
396{
397 dma->max_pq = maxpq;
398 if (has_pq_continue)
399 dma->max_pq |= DMA_HAS_PQ_CONTINUE;
400}
401
402static inline bool dmaf_continue(enum dma_ctrl_flags flags)
403{
404 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
405}
406
407static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
408{
409 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
410
411 return (flags & mask) == mask;
412}
413
414static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
415{
416 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
417}
418
419static unsigned short dma_dev_to_maxpq(struct dma_device *dma)
420{
421 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
422}
423
424/* dma_maxpq - reduce maxpq in the face of continued operations
425 * @dma - dma device with PQ capability
426 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
427 *
428 * When an engine does not support native continuation we need 3 extra
429 * source slots to reuse P and Q with the following coefficients:
430 * 1/ {00} * P : remove P from Q', but use it as a source for P'
431 * 2/ {01} * Q : use Q to continue Q' calculation
432 * 3/ {00} * Q : subtract Q from P' to cancel (2)
433 *
434 * In the case where P is disabled we only need 1 extra source:
435 * 1/ {01} * Q : use Q to continue Q' calculation
436 */
437static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
438{
439 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
440 return dma_dev_to_maxpq(dma);
441 else if (dmaf_p_disabled_continue(flags))
442 return dma_dev_to_maxpq(dma) - 1;
443 else if (dmaf_continue(flags))
444 return dma_dev_to_maxpq(dma) - 3;
445 BUG();
446}
447
Chris Leechc13c8262006-05-23 17:18:44 -0700448/* --- public DMA engine API --- */
449
Dan Williams649274d2009-01-11 00:20:39 -0800450#ifdef CONFIG_DMA_ENGINE
Dan Williams209b84a2009-01-06 11:38:17 -0700451void dmaengine_get(void);
452void dmaengine_put(void);
Dan Williams649274d2009-01-11 00:20:39 -0800453#else
454static inline void dmaengine_get(void)
455{
456}
457static inline void dmaengine_put(void)
458{
459}
460#endif
461
David S. Millerb4bd07c2009-02-06 22:06:43 -0800462#ifdef CONFIG_NET_DMA
463#define net_dmaengine_get() dmaengine_get()
464#define net_dmaengine_put() dmaengine_put()
465#else
466static inline void net_dmaengine_get(void)
467{
468}
469static inline void net_dmaengine_put(void)
470{
471}
472#endif
473
Dan Williams729b5d12009-03-25 09:13:25 -0700474#ifdef CONFIG_ASYNC_TX_DMA
475#define async_dmaengine_get() dmaengine_get()
476#define async_dmaengine_put() dmaengine_put()
Dan Williams138f4c32009-09-08 17:42:51 -0700477#ifdef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH
478#define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
479#else
Dan Williams729b5d12009-03-25 09:13:25 -0700480#define async_dma_find_channel(type) dma_find_channel(type)
Dan Williams138f4c32009-09-08 17:42:51 -0700481#endif /* CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH */
Dan Williams729b5d12009-03-25 09:13:25 -0700482#else
483static inline void async_dmaengine_get(void)
484{
485}
486static inline void async_dmaengine_put(void)
487{
488}
489static inline struct dma_chan *
490async_dma_find_channel(enum dma_transaction_type type)
491{
492 return NULL;
493}
Dan Williams138f4c32009-09-08 17:42:51 -0700494#endif /* CONFIG_ASYNC_TX_DMA */
Dan Williams729b5d12009-03-25 09:13:25 -0700495
Dan Williams7405f742007-01-02 11:10:43 -0700496dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
497 void *dest, void *src, size_t len);
498dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
499 struct page *page, unsigned int offset, void *kdata, size_t len);
500dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
Chris Leechc13c8262006-05-23 17:18:44 -0700501 struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
Dan Williams7405f742007-01-02 11:10:43 -0700502 unsigned int src_off, size_t len);
503void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
504 struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700505
Dan Williams08398752008-07-17 17:59:56 -0700506static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
Dan Williams7405f742007-01-02 11:10:43 -0700507{
Dan Williams636bdea2008-04-17 20:17:26 -0700508 tx->flags |= DMA_CTRL_ACK;
509}
510
Guennadi Liakhovetskief560682009-01-19 15:36:21 -0700511static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
512{
513 tx->flags &= ~DMA_CTRL_ACK;
514}
515
Dan Williams08398752008-07-17 17:59:56 -0700516static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
Dan Williams636bdea2008-04-17 20:17:26 -0700517{
Dan Williams08398752008-07-17 17:59:56 -0700518 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
Chris Leechc13c8262006-05-23 17:18:44 -0700519}
520
Dan Williams7405f742007-01-02 11:10:43 -0700521#define first_dma_cap(mask) __first_dma_cap(&(mask))
522static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
523{
524 return min_t(int, DMA_TX_TYPE_END,
525 find_first_bit(srcp->bits, DMA_TX_TYPE_END));
526}
527
528#define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
529static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
530{
531 return min_t(int, DMA_TX_TYPE_END,
532 find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
533}
534
535#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
536static inline void
537__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
538{
539 set_bit(tx_type, dstp->bits);
540}
541
Atsushi Nemoto0f571512009-03-06 20:07:14 +0900542#define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
543static inline void
544__dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
545{
546 clear_bit(tx_type, dstp->bits);
547}
548
Dan Williams33df8ca2009-01-06 11:38:15 -0700549#define dma_cap_zero(mask) __dma_cap_zero(&(mask))
550static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
551{
552 bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
553}
554
Dan Williams7405f742007-01-02 11:10:43 -0700555#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
556static inline int
557__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
558{
559 return test_bit(tx_type, srcp->bits);
560}
561
562#define for_each_dma_cap_mask(cap, mask) \
563 for ((cap) = first_dma_cap(mask); \
564 (cap) < DMA_TX_TYPE_END; \
565 (cap) = next_dma_cap((cap), (mask)))
566
Chris Leechc13c8262006-05-23 17:18:44 -0700567/**
Dan Williams7405f742007-01-02 11:10:43 -0700568 * dma_async_issue_pending - flush pending transactions to HW
Randy Dunlapfe4ada22006-07-03 19:44:51 -0700569 * @chan: target DMA channel
Chris Leechc13c8262006-05-23 17:18:44 -0700570 *
571 * This allows drivers to push copies to HW in batches,
572 * reducing MMIO writes where possible.
573 */
Dan Williams7405f742007-01-02 11:10:43 -0700574static inline void dma_async_issue_pending(struct dma_chan *chan)
Chris Leechc13c8262006-05-23 17:18:44 -0700575{
Dan Williamsec8670f2008-03-01 07:51:29 -0700576 chan->device->device_issue_pending(chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700577}
578
Dan Williams7405f742007-01-02 11:10:43 -0700579#define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
580
Chris Leechc13c8262006-05-23 17:18:44 -0700581/**
Dan Williams7405f742007-01-02 11:10:43 -0700582 * dma_async_is_tx_complete - poll for transaction completion
Chris Leechc13c8262006-05-23 17:18:44 -0700583 * @chan: DMA channel
584 * @cookie: transaction identifier to check status of
585 * @last: returns last completed cookie, can be NULL
586 * @used: returns last issued cookie, can be NULL
587 *
588 * If @last and @used are passed in, upon return they reflect the driver
589 * internal state and can be used with dma_async_is_complete() to check
590 * the status of multiple cookies without re-checking hardware state.
591 */
Dan Williams7405f742007-01-02 11:10:43 -0700592static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
Chris Leechc13c8262006-05-23 17:18:44 -0700593 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
594{
Linus Walleij07934482010-03-26 16:50:49 -0700595 struct dma_tx_state state;
596 enum dma_status status;
597
598 status = chan->device->device_tx_status(chan, cookie, &state);
599 if (last)
600 *last = state.last;
601 if (used)
602 *used = state.used;
603 return status;
Chris Leechc13c8262006-05-23 17:18:44 -0700604}
605
Dan Williams7405f742007-01-02 11:10:43 -0700606#define dma_async_memcpy_complete(chan, cookie, last, used)\
607 dma_async_is_tx_complete(chan, cookie, last, used)
608
Chris Leechc13c8262006-05-23 17:18:44 -0700609/**
610 * dma_async_is_complete - test a cookie against chan state
611 * @cookie: transaction identifier to test status of
612 * @last_complete: last know completed transaction
613 * @last_used: last cookie value handed out
614 *
615 * dma_async_is_complete() is used in dma_async_memcpy_complete()
Sebastian Siewior8a5703f2008-04-21 22:38:45 +0000616 * the test logic is separated for lightweight testing of multiple cookies
Chris Leechc13c8262006-05-23 17:18:44 -0700617 */
618static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
619 dma_cookie_t last_complete, dma_cookie_t last_used)
620{
621 if (last_complete <= last_used) {
622 if ((cookie <= last_complete) || (cookie > last_used))
623 return DMA_SUCCESS;
624 } else {
625 if ((cookie <= last_complete) && (cookie > last_used))
626 return DMA_SUCCESS;
627 }
628 return DMA_IN_PROGRESS;
629}
630
Dan Williams7405f742007-01-02 11:10:43 -0700631enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
Dan Williams07f22112009-01-05 17:14:31 -0700632#ifdef CONFIG_DMA_ENGINE
633enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
Dan Williamsc50331e2009-01-19 15:33:14 -0700634void dma_issue_pending_all(void);
Dan Williams07f22112009-01-05 17:14:31 -0700635#else
636static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
637{
638 return DMA_SUCCESS;
639}
Dan Williamsc50331e2009-01-19 15:33:14 -0700640static inline void dma_issue_pending_all(void)
641{
642 do { } while (0);
643}
Dan Williams07f22112009-01-05 17:14:31 -0700644#endif
Chris Leechc13c8262006-05-23 17:18:44 -0700645
646/* --- DMA device --- */
647
648int dma_async_device_register(struct dma_device *device);
649void dma_async_device_unregister(struct dma_device *device);
Dan Williams07f22112009-01-05 17:14:31 -0700650void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
Dan Williamsbec08512009-01-06 11:38:14 -0700651struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
Dan Williams59b5ec22009-01-06 11:38:15 -0700652#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
653struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param);
654void dma_release_channel(struct dma_chan *chan);
Chris Leechc13c8262006-05-23 17:18:44 -0700655
Chris Leechde5506e2006-05-23 17:50:37 -0700656/* --- Helper iov-locking functions --- */
657
658struct dma_page_list {
Al Virob2ddb902008-03-29 03:09:38 +0000659 char __user *base_address;
Chris Leechde5506e2006-05-23 17:50:37 -0700660 int nr_pages;
661 struct page **pages;
662};
663
664struct dma_pinned_list {
665 int nr_iovecs;
666 struct dma_page_list page_list[0];
667};
668
669struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
670void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
671
672dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
673 struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
674dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
675 struct dma_pinned_list *pinned_list, struct page *page,
676 unsigned int offset, size_t len);
677
Chris Leechc13c8262006-05-23 17:18:44 -0700678#endif /* DMAENGINE_H */