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gerrit-public.fairphone.software / kernel / msm-4.9 / 08ff924e7fa7b826396f5ef1cb15656db7fb6545 / . / drivers / scsi / mpt3sas / mpi / mpi2.h
blob: ec27ad2d186f9b6b8a25d795284822f75f09e667 [file] [log] [blame]
Sreekanth Reddyf92363d2012-11-30 07:44:21 +0530[diff] [blame]1/*
Sreekanth Reddya4ffce02014-09-12 15:35:29 +0530[diff] [blame]2 * Copyright (c) 2000-2014 LSI Corporation.
Sreekanth Reddyf92363d2012-11-30 07:44:21 +0530[diff] [blame]3 *
4 *
5 * Name: mpi2.h
6 * Title: MPI Message independent structures and definitions
7 * including System Interface Register Set and
8 * scatter/gather formats.
9 * Creation Date: June 21, 2006
10 *
Sreekanth Reddya6f84002015-06-30 12:24:59 +0530[diff] [blame]11 * mpi2.h Version: 02.00.35
Sreekanth Reddyf92363d2012-11-30 07:44:21 +0530[diff] [blame]12 *
13 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
14 * prefix are for use only on MPI v2.5 products, and must not be used
15 * with MPI v2.0 products. Unless otherwise noted, names beginning with
16 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
17 *
18 * Version History
19 * ---------------
20 *
21 * Date Version Description
22 * -------- -------- ------------------------------------------------------
23 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
24 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
25 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
26 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
27 * Moved ReplyPostHostIndex register to offset 0x6C of the
28 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
29 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
30 * Added union of request descriptors.
31 * Added union of reply descriptors.
32 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
33 * Added define for MPI2_VERSION_02_00.
34 * Fixed the size of the FunctionDependent5 field in the
35 * MPI2_DEFAULT_REPLY structure.
36 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
37 * Removed the MPI-defined Fault Codes and extended the
38 * product specific codes up to 0xEFFF.
39 * Added a sixth key value for the WriteSequence register
40 * and changed the flush value to 0x0.
41 * Added message function codes for Diagnostic Buffer Post
42 * and Diagnsotic Release.
43 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
44 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
45 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
46 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
47 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
48 * Added #defines for marking a reply descriptor as unused.
49 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
50 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
51 * Moved LUN field defines from mpi2_init.h.
52 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
53 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
54 * In all request and reply descriptors, replaced VF_ID
55 * field with MSIxIndex field.
56 * Removed DevHandle field from
57 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
58 * bytes reserved.
59 * Added RAID Accelerator functionality.
60 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
61 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT.
62 * Added MSI-x index mask and shift for Reply Post Host
63 * Index register.
64 * Added function code for Host Based Discovery Action.
65 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT.
66 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
67 * Added defines for product-specific range of message
68 * function codes, 0xF0 to 0xFF.
69 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT.
70 * Added alternative defines for the SGE Direction bit.
71 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT.
72 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT.
73 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
74 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT.
75 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE.
76 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT.
77 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT.
78 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT.
79 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT.
80 * Incorporating additions for MPI v2.5.
81 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT.
82 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT.
83 * Added Hard Reset delay timings.
84 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT.
Sreekanth Reddy17263e72013-06-29 03:54:07 +0530[diff] [blame]85 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT.
86 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT.
87 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT.
88 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET.
Sreekanth Reddy861ff732014-09-12 15:35:25 +0530[diff] [blame]89 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT.
90 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT.
Sreekanth Reddya94bea32015-06-30 12:24:51 +0530[diff] [blame]91 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT.
92 * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT.
Sreekanth Reddy35c319b2015-06-30 12:24:55 +0530[diff] [blame]93 * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT
Sreekanth Reddya6f84002015-06-30 12:24:59 +0530[diff] [blame]94 * 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT.
Sreekanth Reddyf92363d2012-11-30 07:44:21 +0530[diff] [blame]95 * --------------------------------------------------------------------------
96 */
97
98#ifndef MPI2_H
99#define MPI2_H
100
101/*****************************************************************************
102*
103* MPI Version Definitions
104*
105*****************************************************************************/
106
107#define MPI2_VERSION_MAJOR_MASK (0xFF00)
108#define MPI2_VERSION_MAJOR_SHIFT (8)
109#define MPI2_VERSION_MINOR_MASK (0x00FF)
110#define MPI2_VERSION_MINOR_SHIFT (0)
111
112/*major version for all MPI v2.x */
113#define MPI2_VERSION_MAJOR (0x02)
114
115/*minor version for MPI v2.0 compatible products */
116#define MPI2_VERSION_MINOR (0x00)
117#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
118 MPI2_VERSION_MINOR)
119#define MPI2_VERSION_02_00 (0x0200)
120
121/*minor version for MPI v2.5 compatible products */
122#define MPI25_VERSION_MINOR (0x05)
123#define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
124 MPI25_VERSION_MINOR)
125#define MPI2_VERSION_02_05 (0x0205)
126
127/*Unit and Dev versioning for this MPI header set */
Sreekanth Reddya6f84002015-06-30 12:24:59 +0530[diff] [blame]128#define MPI2_HEADER_VERSION_UNIT (0x23)
Sreekanth Reddyf92363d2012-11-30 07:44:21 +0530[diff] [blame]129#define MPI2_HEADER_VERSION_DEV (0x00)
130#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
131#define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
132#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
133#define MPI2_HEADER_VERSION_DEV_SHIFT (0)
134#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
135 MPI2_HEADER_VERSION_DEV)
136
137/*****************************************************************************
138*
139* IOC State Definitions
140*
141*****************************************************************************/
142
143#define MPI2_IOC_STATE_RESET (0x00000000)
144#define MPI2_IOC_STATE_READY (0x10000000)
145#define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
146#define MPI2_IOC_STATE_FAULT (0x40000000)
147
148#define MPI2_IOC_STATE_MASK (0xF0000000)
149#define MPI2_IOC_STATE_SHIFT (28)
150
151/*Fault state range for prodcut specific codes */
152#define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
153#define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
154
155/*****************************************************************************
156*
157* System Interface Register Definitions
158*
159*****************************************************************************/
160
161typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS {
162 U32 Doorbell; /*0x00 */
163 U32 WriteSequence; /*0x04 */
164 U32 HostDiagnostic; /*0x08 */
165 U32 Reserved1; /*0x0C */
166 U32 DiagRWData; /*0x10 */
167 U32 DiagRWAddressLow; /*0x14 */
168 U32 DiagRWAddressHigh; /*0x18 */
169 U32 Reserved2[5]; /*0x1C */
170 U32 HostInterruptStatus; /*0x30 */
171 U32 HostInterruptMask; /*0x34 */
172 U32 DCRData; /*0x38 */
173 U32 DCRAddress; /*0x3C */
174 U32 Reserved3[2]; /*0x40 */
175 U32 ReplyFreeHostIndex; /*0x48 */
176 U32 Reserved4[8]; /*0x4C */
177 U32 ReplyPostHostIndex; /*0x6C */
178 U32 Reserved5; /*0x70 */
179 U32 HCBSize; /*0x74 */
180 U32 HCBAddressLow; /*0x78 */
181 U32 HCBAddressHigh; /*0x7C */
182 U32 Reserved6[16]; /*0x80 */
183 U32 RequestDescriptorPostLow; /*0xC0 */
184 U32 RequestDescriptorPostHigh; /*0xC4 */
185 U32 Reserved7[14]; /*0xC8 */
186} MPI2_SYSTEM_INTERFACE_REGS,
187 *PTR_MPI2_SYSTEM_INTERFACE_REGS,
188 Mpi2SystemInterfaceRegs_t,
189 *pMpi2SystemInterfaceRegs_t;
190
191/*
192 *Defines for working with the Doorbell register.
193 */
194#define MPI2_DOORBELL_OFFSET (0x00000000)
195
196/*IOC --> System values */
197#define MPI2_DOORBELL_USED (0x08000000)
198#define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
199#define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
200#define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
201#define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
202
203/*System --> IOC values */
204#define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
205#define MPI2_DOORBELL_FUNCTION_SHIFT (24)
206#define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
207#define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
208
209/*
210 *Defines for the WriteSequence register
211 */
212#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
213#define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
214#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
215#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
216#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
217#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
218#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
219#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
220#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
221
222/*
223 *Defines for the HostDiagnostic register
224 */
225#define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
226
227#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
228#define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
229#define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
230
231#define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
232#define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
233#define MPI2_DIAG_HCB_MODE (0x00000100)
234#define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
235#define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
236#define MPI2_DIAG_RESET_HISTORY (0x00000020)
237#define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
238#define MPI2_DIAG_RESET_ADAPTER (0x00000004)
239#define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
240
241/*
242 *Offsets for DiagRWData and address
243 */
244#define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
245#define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
246#define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
247
248/*
249 *Defines for the HostInterruptStatus register
250 */
251#define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
252#define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
253#define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
254#define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
255#define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
256#define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
257#define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
258
259/*
260 *Defines for the HostInterruptMask register
261 */
262#define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
263#define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
264#define MPI2_HIM_REPLY_INT_MASK (0x00000008)
265#define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
266#define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
267#define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
268
269/*
270 *Offsets for DCRData and address
271 */
272#define MPI2_DCR_DATA_OFFSET (0x00000038)
273#define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
274
275/*
276 *Offset for the Reply Free Queue
277 */
278#define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
279
280/*
281 *Defines for the Reply Descriptor Post Queue
282 */
283#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
284#define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
285#define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
286#define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
Sreekanth Reddy17263e72013-06-29 03:54:07 +0530[diff] [blame]287#define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /*MPI v2.5 only*/
288
Sreekanth Reddyf92363d2012-11-30 07:44:21 +0530[diff] [blame]289
290/*
291 *Defines for the HCBSize and address
292 */
293#define MPI2_HCB_SIZE_OFFSET (0x00000074)
294#define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
295#define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
296
297#define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
298#define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
299
300/*
301 *Offsets for the Request Queue
302 */
303#define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
304#define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
305
306/*Hard Reset delay timings */
307#define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000)
308#define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000)
309#define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000)
310
311/*****************************************************************************
312*
313* Message Descriptors
314*
315*****************************************************************************/
316
317/*Request Descriptors */
318
319/*Default Request Descriptor */
320typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR {
321 U8 RequestFlags; /*0x00 */
322 U8 MSIxIndex; /*0x01 */
323 U16 SMID; /*0x02 */
324 U16 LMID; /*0x04 */
325 U16 DescriptorTypeDependent; /*0x06 */
326} MPI2_DEFAULT_REQUEST_DESCRIPTOR,
327 *PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
328 Mpi2DefaultRequestDescriptor_t,
329 *pMpi2DefaultRequestDescriptor_t;
330
331/*defines for the RequestFlags field */
332#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
333#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
334#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
335#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
336#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
337#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
338#define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C)
339
340#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
341
342/*High Priority Request Descriptor */
343typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
344 U8 RequestFlags; /*0x00 */
345 U8 MSIxIndex; /*0x01 */
346 U16 SMID; /*0x02 */
347 U16 LMID; /*0x04 */
348 U16 Reserved1; /*0x06 */
349} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
350 *PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
351 Mpi2HighPriorityRequestDescriptor_t,
352 *pMpi2HighPriorityRequestDescriptor_t;
353
354/*SCSI IO Request Descriptor */
355typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
356 U8 RequestFlags; /*0x00 */
357 U8 MSIxIndex; /*0x01 */
358 U16 SMID; /*0x02 */
359 U16 LMID; /*0x04 */
360 U16 DevHandle; /*0x06 */
361} MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
362 *PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
363 Mpi2SCSIIORequestDescriptor_t,
364 *pMpi2SCSIIORequestDescriptor_t;
365
366/*SCSI Target Request Descriptor */
367typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
368 U8 RequestFlags; /*0x00 */
369 U8 MSIxIndex; /*0x01 */
370 U16 SMID; /*0x02 */
371 U16 LMID; /*0x04 */
372 U16 IoIndex; /*0x06 */
373} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
374 *PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
375 Mpi2SCSITargetRequestDescriptor_t,
376 *pMpi2SCSITargetRequestDescriptor_t;
377
378/*RAID Accelerator Request Descriptor */
379typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
380 U8 RequestFlags; /*0x00 */
381 U8 MSIxIndex; /*0x01 */
382 U16 SMID; /*0x02 */
383 U16 LMID; /*0x04 */
384 U16 Reserved; /*0x06 */
385} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
386 *PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
387 Mpi2RAIDAcceleratorRequestDescriptor_t,
388 *pMpi2RAIDAcceleratorRequestDescriptor_t;
389
390/*Fast Path SCSI IO Request Descriptor */
391typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
392 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
393 *PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
394 Mpi25FastPathSCSIIORequestDescriptor_t,
395 *pMpi25FastPathSCSIIORequestDescriptor_t;
396
397/*union of Request Descriptors */
398typedef union _MPI2_REQUEST_DESCRIPTOR_UNION {
399 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
400 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
401 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
402 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
403 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
404 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO;
405 U64 Words;
406} MPI2_REQUEST_DESCRIPTOR_UNION,
407 *PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
408 Mpi2RequestDescriptorUnion_t,
409 *pMpi2RequestDescriptorUnion_t;
410
411/*Reply Descriptors */
412
413/*Default Reply Descriptor */
414typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR {
415 U8 ReplyFlags; /*0x00 */
416 U8 MSIxIndex; /*0x01 */
417 U16 DescriptorTypeDependent1; /*0x02 */
418 U32 DescriptorTypeDependent2; /*0x04 */
419} MPI2_DEFAULT_REPLY_DESCRIPTOR,
420 *PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
421 Mpi2DefaultReplyDescriptor_t,
422 *pMpi2DefaultReplyDescriptor_t;
423
424/*defines for the ReplyFlags field */
425#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
426#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
427#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
428#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
429#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
430#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
431#define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06)
432#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
433
434/*values for marking a reply descriptor as unused */
435#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
436#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
437
438/*Address Reply Descriptor */
439typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR {
440 U8 ReplyFlags; /*0x00 */
441 U8 MSIxIndex; /*0x01 */
442 U16 SMID; /*0x02 */
443 U32 ReplyFrameAddress; /*0x04 */
444} MPI2_ADDRESS_REPLY_DESCRIPTOR,
445 *PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
446 Mpi2AddressReplyDescriptor_t,
447 *pMpi2AddressReplyDescriptor_t;
448
449#define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
450
451/*SCSI IO Success Reply Descriptor */
452typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
453 U8 ReplyFlags; /*0x00 */
454 U8 MSIxIndex; /*0x01 */
455 U16 SMID; /*0x02 */
456 U16 TaskTag; /*0x04 */
457 U16 Reserved1; /*0x06 */
458} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
459 *PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
460 Mpi2SCSIIOSuccessReplyDescriptor_t,
461 *pMpi2SCSIIOSuccessReplyDescriptor_t;
462
463/*TargetAssist Success Reply Descriptor */
464typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
465 U8 ReplyFlags; /*0x00 */
466 U8 MSIxIndex; /*0x01 */
467 U16 SMID; /*0x02 */
468 U8 SequenceNumber; /*0x04 */
469 U8 Reserved1; /*0x05 */
470 U16 IoIndex; /*0x06 */
471} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
472 *PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
473 Mpi2TargetAssistSuccessReplyDescriptor_t,
474 *pMpi2TargetAssistSuccessReplyDescriptor_t;
475
476/*Target Command Buffer Reply Descriptor */
477typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
478 U8 ReplyFlags; /*0x00 */
479 U8 MSIxIndex; /*0x01 */
480 U8 VP_ID; /*0x02 */
481 U8 Flags; /*0x03 */
482 U16 InitiatorDevHandle; /*0x04 */
483 U16 IoIndex; /*0x06 */
484} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
485 *PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
486 Mpi2TargetCommandBufferReplyDescriptor_t,
487 *pMpi2TargetCommandBufferReplyDescriptor_t;
488
489/*defines for Flags field */
490#define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
491
492/*RAID Accelerator Success Reply Descriptor */
493typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
494 U8 ReplyFlags; /*0x00 */
495 U8 MSIxIndex; /*0x01 */
496 U16 SMID; /*0x02 */
497 U32 Reserved; /*0x04 */
498} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
499 *PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
500 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
501 *pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
502
503/*Fast Path SCSI IO Success Reply Descriptor */
504typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
505 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
506 *PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
507 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t,
508 *pMpi25FastPathSCSIIOSuccessReplyDescriptor_t;
509
510/*union of Reply Descriptors */
511typedef union _MPI2_REPLY_DESCRIPTORS_UNION {
512 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
513 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
514 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
515 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
516 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
517 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
518 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess;
519 U64 Words;
520} MPI2_REPLY_DESCRIPTORS_UNION,
521 *PTR_MPI2_REPLY_DESCRIPTORS_UNION,
522 Mpi2ReplyDescriptorsUnion_t,
523 *pMpi2ReplyDescriptorsUnion_t;
524
525/*****************************************************************************
526*
527* Message Functions
528*
529*****************************************************************************/
530
531#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00)
532#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01)
533#define MPI2_FUNCTION_IOC_INIT (0x02)
534#define MPI2_FUNCTION_IOC_FACTS (0x03)
535#define MPI2_FUNCTION_CONFIG (0x04)
536#define MPI2_FUNCTION_PORT_FACTS (0x05)
537#define MPI2_FUNCTION_PORT_ENABLE (0x06)
538#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07)
539#define MPI2_FUNCTION_EVENT_ACK (0x08)
540#define MPI2_FUNCTION_FW_DOWNLOAD (0x09)
541#define MPI2_FUNCTION_TARGET_ASSIST (0x0B)
542#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C)
543#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D)
544#define MPI2_FUNCTION_FW_UPLOAD (0x12)
545#define MPI2_FUNCTION_RAID_ACTION (0x15)
546#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16)
547#define MPI2_FUNCTION_TOOLBOX (0x17)
548#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18)
549#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A)
550#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B)
551#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C)
552#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D)
553#define MPI2_FUNCTION_DIAG_RELEASE (0x1E)
554#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24)
555#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25)
556#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C)
557#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F)
558#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30)
559#define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31)
560#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0)
561#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF)
562
563/*Doorbell functions */
564#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
565#define MPI2_FUNCTION_HANDSHAKE (0x42)
566
567/*****************************************************************************
568*
569* IOC Status Values
570*
571*****************************************************************************/
572
573/*mask for IOCStatus status value */
574#define MPI2_IOCSTATUS_MASK (0x7FFF)
575
576/****************************************************************************
577* Common IOCStatus values for all replies
578****************************************************************************/
579
580#define MPI2_IOCSTATUS_SUCCESS (0x0000)
581#define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
582#define MPI2_IOCSTATUS_BUSY (0x0002)
583#define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
584#define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
585#define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
586#define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
587#define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
588#define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
589#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
590
591/****************************************************************************
592* Config IOCStatus values
593****************************************************************************/
594
595#define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
596#define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
597#define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
598#define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
599#define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
600#define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
601
602/****************************************************************************
603* SCSI IO Reply
604****************************************************************************/
605
606#define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
607#define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
608#define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
609#define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
610#define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
611#define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
612#define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
613#define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
614#define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
615#define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
616#define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
617#define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
618
619/****************************************************************************
620* For use by SCSI Initiator and SCSI Target end-to-end data protection
621****************************************************************************/
622
623#define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
624#define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
625#define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
626
627/****************************************************************************
628* SCSI Target values
629****************************************************************************/
630
631#define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
632#define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
633#define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
634#define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
635#define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
636#define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
637#define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
638#define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
639#define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
640#define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
641
642/****************************************************************************
643* Serial Attached SCSI values
644****************************************************************************/
645
646#define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
647#define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
648
649/****************************************************************************
650* Diagnostic Buffer Post / Diagnostic Release values
651****************************************************************************/
652
653#define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
654
655/****************************************************************************
656* RAID Accelerator values
657****************************************************************************/
658
659#define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
660
661/****************************************************************************
662* IOCStatus flag to indicate that log info is available
663****************************************************************************/
664
665#define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
666
667/****************************************************************************
668* IOCLogInfo Types
669****************************************************************************/
670
671#define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
672#define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
673#define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
674#define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
675#define MPI2_IOCLOGINFO_TYPE_FC (0x2)
676#define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
677#define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
678#define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
679
680/*****************************************************************************
681*
682* Standard Message Structures
683*
684*****************************************************************************/
685
686/****************************************************************************
687*Request Message Header for all request messages
688****************************************************************************/
689
690typedef struct _MPI2_REQUEST_HEADER {
691 U16 FunctionDependent1; /*0x00 */
692 U8 ChainOffset; /*0x02 */
693 U8 Function; /*0x03 */
694 U16 FunctionDependent2; /*0x04 */
695 U8 FunctionDependent3; /*0x06 */
696 U8 MsgFlags; /*0x07 */
697 U8 VP_ID; /*0x08 */
698 U8 VF_ID; /*0x09 */
699 U16 Reserved1; /*0x0A */
700} MPI2_REQUEST_HEADER, *PTR_MPI2_REQUEST_HEADER,
701 MPI2RequestHeader_t, *pMPI2RequestHeader_t;
702
703/****************************************************************************
704* Default Reply
705****************************************************************************/
706
707typedef struct _MPI2_DEFAULT_REPLY {
708 U16 FunctionDependent1; /*0x00 */
709 U8 MsgLength; /*0x02 */
710 U8 Function; /*0x03 */
711 U16 FunctionDependent2; /*0x04 */
712 U8 FunctionDependent3; /*0x06 */
713 U8 MsgFlags; /*0x07 */
714 U8 VP_ID; /*0x08 */
715 U8 VF_ID; /*0x09 */
716 U16 Reserved1; /*0x0A */
717 U16 FunctionDependent5; /*0x0C */
718 U16 IOCStatus; /*0x0E */
719 U32 IOCLogInfo; /*0x10 */
720} MPI2_DEFAULT_REPLY, *PTR_MPI2_DEFAULT_REPLY,
721 MPI2DefaultReply_t, *pMPI2DefaultReply_t;
722
723/*common version structure/union used in messages and configuration pages */
724
725typedef struct _MPI2_VERSION_STRUCT {
726 U8 Dev; /*0x00 */
727 U8 Unit; /*0x01 */
728 U8 Minor; /*0x02 */
729 U8 Major; /*0x03 */
730} MPI2_VERSION_STRUCT;
731
732typedef union _MPI2_VERSION_UNION {
733 MPI2_VERSION_STRUCT Struct;
734 U32 Word;
735} MPI2_VERSION_UNION;
736
737/*LUN field defines, common to many structures */
738#define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
739#define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
740#define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
741#define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
742#define MPI2_LUN_LEVEL_1_WORD (0xFF00)
743#define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
744
745/*****************************************************************************
746*
747* Fusion-MPT MPI Scatter Gather Elements
748*
749*****************************************************************************/
750
751/****************************************************************************
752* MPI Simple Element structures
753****************************************************************************/
754
755typedef struct _MPI2_SGE_SIMPLE32 {
756 U32 FlagsLength;
757 U32 Address;
758} MPI2_SGE_SIMPLE32, *PTR_MPI2_SGE_SIMPLE32,
759 Mpi2SGESimple32_t, *pMpi2SGESimple32_t;
760
761typedef struct _MPI2_SGE_SIMPLE64 {
762 U32 FlagsLength;
763 U64 Address;
764} MPI2_SGE_SIMPLE64, *PTR_MPI2_SGE_SIMPLE64,
765 Mpi2SGESimple64_t, *pMpi2SGESimple64_t;
766
767typedef struct _MPI2_SGE_SIMPLE_UNION {
768 U32 FlagsLength;
769 union {
770 U32 Address32;
771 U64 Address64;
772 } u;
773} MPI2_SGE_SIMPLE_UNION,
774 *PTR_MPI2_SGE_SIMPLE_UNION,
775 Mpi2SGESimpleUnion_t,
776 *pMpi2SGESimpleUnion_t;
777
778/****************************************************************************
779* MPI Chain Element structures - for MPI v2.0 products only
780****************************************************************************/
781
782typedef struct _MPI2_SGE_CHAIN32 {
783 U16 Length;
784 U8 NextChainOffset;
785 U8 Flags;
786 U32 Address;
787} MPI2_SGE_CHAIN32, *PTR_MPI2_SGE_CHAIN32,
788 Mpi2SGEChain32_t, *pMpi2SGEChain32_t;
789
790typedef struct _MPI2_SGE_CHAIN64 {
791 U16 Length;
792 U8 NextChainOffset;
793 U8 Flags;
794 U64 Address;
795} MPI2_SGE_CHAIN64, *PTR_MPI2_SGE_CHAIN64,
796 Mpi2SGEChain64_t, *pMpi2SGEChain64_t;
797
798typedef struct _MPI2_SGE_CHAIN_UNION {
799 U16 Length;
800 U8 NextChainOffset;
801 U8 Flags;
802 union {
803 U32 Address32;
804 U64 Address64;
805 } u;
806} MPI2_SGE_CHAIN_UNION,
807 *PTR_MPI2_SGE_CHAIN_UNION,
808 Mpi2SGEChainUnion_t,
809 *pMpi2SGEChainUnion_t;
810
811/****************************************************************************
812* MPI Transaction Context Element structures - for MPI v2.0 products only
813****************************************************************************/
814
815typedef struct _MPI2_SGE_TRANSACTION32 {
816 U8 Reserved;
817 U8 ContextSize;
818 U8 DetailsLength;
819 U8 Flags;
820 U32 TransactionContext[1];
821 U32 TransactionDetails[1];
822} MPI2_SGE_TRANSACTION32,
823 *PTR_MPI2_SGE_TRANSACTION32,
824 Mpi2SGETransaction32_t,
825 *pMpi2SGETransaction32_t;
826
827typedef struct _MPI2_SGE_TRANSACTION64 {
828 U8 Reserved;
829 U8 ContextSize;
830 U8 DetailsLength;
831 U8 Flags;
832 U32 TransactionContext[2];
833 U32 TransactionDetails[1];
834} MPI2_SGE_TRANSACTION64,
835 *PTR_MPI2_SGE_TRANSACTION64,
836 Mpi2SGETransaction64_t,
837 *pMpi2SGETransaction64_t;
838
839typedef struct _MPI2_SGE_TRANSACTION96 {
840 U8 Reserved;
841 U8 ContextSize;
842 U8 DetailsLength;
843 U8 Flags;
844 U32 TransactionContext[3];
845 U32 TransactionDetails[1];
846} MPI2_SGE_TRANSACTION96, *PTR_MPI2_SGE_TRANSACTION96,
847 Mpi2SGETransaction96_t, *pMpi2SGETransaction96_t;
848
849typedef struct _MPI2_SGE_TRANSACTION128 {
850 U8 Reserved;
851 U8 ContextSize;
852 U8 DetailsLength;
853 U8 Flags;
854 U32 TransactionContext[4];
855 U32 TransactionDetails[1];
856} MPI2_SGE_TRANSACTION128, *PTR_MPI2_SGE_TRANSACTION128,
857 Mpi2SGETransaction_t128, *pMpi2SGETransaction_t128;
858
859typedef struct _MPI2_SGE_TRANSACTION_UNION {
860 U8 Reserved;
861 U8 ContextSize;
862 U8 DetailsLength;
863 U8 Flags;
864 union {
865 U32 TransactionContext32[1];
866 U32 TransactionContext64[2];
867 U32 TransactionContext96[3];
868 U32 TransactionContext128[4];
869 } u;
870 U32 TransactionDetails[1];
871} MPI2_SGE_TRANSACTION_UNION,
872 *PTR_MPI2_SGE_TRANSACTION_UNION,
873 Mpi2SGETransactionUnion_t,
874 *pMpi2SGETransactionUnion_t;
875
876/****************************************************************************
877* MPI SGE union for IO SGL's - for MPI v2.0 products only
878****************************************************************************/
879
880typedef struct _MPI2_MPI_SGE_IO_UNION {
881 union {
882 MPI2_SGE_SIMPLE_UNION Simple;
883 MPI2_SGE_CHAIN_UNION Chain;
884 } u;
885} MPI2_MPI_SGE_IO_UNION, *PTR_MPI2_MPI_SGE_IO_UNION,
886 Mpi2MpiSGEIOUnion_t, *pMpi2MpiSGEIOUnion_t;
887
888/****************************************************************************
889* MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only
890****************************************************************************/
891
892typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION {
893 union {
894 MPI2_SGE_SIMPLE_UNION Simple;
895 MPI2_SGE_TRANSACTION_UNION Transaction;
896 } u;
897} MPI2_SGE_TRANS_SIMPLE_UNION,
898 *PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
899 Mpi2SGETransSimpleUnion_t,
900 *pMpi2SGETransSimpleUnion_t;
901
902/****************************************************************************
903* All MPI SGE types union
904****************************************************************************/
905
906typedef struct _MPI2_MPI_SGE_UNION {
907 union {
908 MPI2_SGE_SIMPLE_UNION Simple;
909 MPI2_SGE_CHAIN_UNION Chain;
910 MPI2_SGE_TRANSACTION_UNION Transaction;
911 } u;
912} MPI2_MPI_SGE_UNION, *PTR_MPI2_MPI_SGE_UNION,
913 Mpi2MpiSgeUnion_t, *pMpi2MpiSgeUnion_t;
914
915/****************************************************************************
916* MPI SGE field definition and masks
917****************************************************************************/
918
919/*Flags field bit definitions */
920
921#define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
922#define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
923#define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
924#define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
925#define MPI2_SGE_FLAGS_DIRECTION (0x04)
926#define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
927#define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
928
929#define MPI2_SGE_FLAGS_SHIFT (24)
930
931#define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
932#define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
933
934/*Element Type */
935
936#define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
937#define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
938#define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
939#define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
940
941/*Address location */
942
943#define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
944
945/*Direction */
946
947#define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
948#define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
949
950#define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST)
951#define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC)
952
953/*Address Size */
954
955#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
956#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
957
958/*Context Size */
959
960#define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
961#define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
962#define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
963#define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
964
965#define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
966#define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
967
968/****************************************************************************
969* MPI SGE operation Macros
970****************************************************************************/
971
972/*SIMPLE FlagsLength manipulations... */
973#define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
974#define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> \
975 MPI2_SGE_FLAGS_SHIFT)
976#define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
977#define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
978
979#define MPI2_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_SGE_SET_FLAGS(f) | \
980 MPI2_SGE_LENGTH(l))
981
982#define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
983#define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
984#define MPI2_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \
985 MPI2_SGE_SET_FLAGS_LENGTH(f, l))
986
987/*CAUTION - The following are READ-MODIFY-WRITE! */
988#define MPI2_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \
989 MPI2_SGE_SET_FLAGS(f))
990#define MPI2_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \
991 MPI2_SGE_LENGTH(l))
992
993#define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> \
994 MPI2_SGE_CHAIN_OFFSET_SHIFT)
995
996/*****************************************************************************
997*
998* Fusion-MPT IEEE Scatter Gather Elements
999*
1000*****************************************************************************/
1001
1002/****************************************************************************
1003* IEEE Simple Element structures
1004****************************************************************************/
1005
1006/*MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */
1007typedef struct _MPI2_IEEE_SGE_SIMPLE32 {
1008 U32 Address;
1009 U32 FlagsLength;
1010} MPI2_IEEE_SGE_SIMPLE32, *PTR_MPI2_IEEE_SGE_SIMPLE32,
1011 Mpi2IeeeSgeSimple32_t, *pMpi2IeeeSgeSimple32_t;
1012
1013typedef struct _MPI2_IEEE_SGE_SIMPLE64 {
1014 U64 Address;
1015 U32 Length;
1016 U16 Reserved1;
1017 U8 Reserved2;
1018 U8 Flags;
1019} MPI2_IEEE_SGE_SIMPLE64, *PTR_MPI2_IEEE_SGE_SIMPLE64,
1020 Mpi2IeeeSgeSimple64_t, *pMpi2IeeeSgeSimple64_t;
1021
1022typedef union _MPI2_IEEE_SGE_SIMPLE_UNION {
1023 MPI2_IEEE_SGE_SIMPLE32 Simple32;
1024 MPI2_IEEE_SGE_SIMPLE64 Simple64;
1025} MPI2_IEEE_SGE_SIMPLE_UNION,
1026 *PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1027 Mpi2IeeeSgeSimpleUnion_t,
1028 *pMpi2IeeeSgeSimpleUnion_t;
1029
1030/****************************************************************************
1031* IEEE Chain Element structures
1032****************************************************************************/
1033
1034/*MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */
1035typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1036
1037/*MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */
1038typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1039
1040typedef union _MPI2_IEEE_SGE_CHAIN_UNION {
1041 MPI2_IEEE_SGE_CHAIN32 Chain32;
1042 MPI2_IEEE_SGE_CHAIN64 Chain64;
1043} MPI2_IEEE_SGE_CHAIN_UNION,
1044 *PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1045 Mpi2IeeeSgeChainUnion_t,
1046 *pMpi2IeeeSgeChainUnion_t;
1047
1048/*MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 products only */
1049typedef struct _MPI25_IEEE_SGE_CHAIN64 {
1050 U64 Address;
1051 U32 Length;
1052 U16 Reserved1;
1053 U8 NextChainOffset;
1054 U8 Flags;
1055} MPI25_IEEE_SGE_CHAIN64,
1056 *PTR_MPI25_IEEE_SGE_CHAIN64,
1057 Mpi25IeeeSgeChain64_t,
1058 *pMpi25IeeeSgeChain64_t;
1059
1060/****************************************************************************
1061* All IEEE SGE types union
1062****************************************************************************/
1063
1064/*MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */
1065typedef struct _MPI2_IEEE_SGE_UNION {
1066 union {
1067 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1068 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1069 } u;
1070} MPI2_IEEE_SGE_UNION, *PTR_MPI2_IEEE_SGE_UNION,
1071 Mpi2IeeeSgeUnion_t, *pMpi2IeeeSgeUnion_t;
1072
1073/****************************************************************************
1074* IEEE SGE union for IO SGL's
1075****************************************************************************/
1076
1077typedef union _MPI25_SGE_IO_UNION {
1078 MPI2_IEEE_SGE_SIMPLE64 IeeeSimple;
1079 MPI25_IEEE_SGE_CHAIN64 IeeeChain;
1080} MPI25_SGE_IO_UNION, *PTR_MPI25_SGE_IO_UNION,
1081 Mpi25SGEIOUnion_t, *pMpi25SGEIOUnion_t;
1082
1083/****************************************************************************
1084* IEEE SGE field definitions and masks
1085****************************************************************************/
1086
1087/*Flags field bit definitions */
1088
1089#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1090#define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1091
1092#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1093
1094#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1095
1096/*Element Type */
1097
1098#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1099#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1100
1101/*Data Location Address Space */
1102
1103#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1104#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1105#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1106#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1107#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1108#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03)
1109#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \
1110 (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR)
1111
1112/****************************************************************************
1113* IEEE SGE operation Macros
1114****************************************************************************/
1115
1116/*SIMPLE FlagsLength manipulations... */
1117#define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1118#define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) \
1119 >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1120#define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1121
1122#define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) |\
1123 MPI2_IEEE32_SGE_LENGTH(l))
1124
1125#define MPI2_IEEE32_pSGE_GET_FLAGS(psg) \
1126 MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1127#define MPI2_IEEE32_pSGE_GET_LENGTH(psg) \
1128 MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1129#define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \
1130 MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l))
1131
1132/*CAUTION - The following are READ-MODIFY-WRITE! */
1133#define MPI2_IEEE32_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \
1134 MPI2_IEEE32_SGE_SET_FLAGS(f))
1135#define MPI2_IEEE32_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \
1136 MPI2_IEEE32_SGE_LENGTH(l))
1137
1138/*****************************************************************************
1139*
1140* Fusion-MPT MPI/IEEE Scatter Gather Unions
1141*
1142*****************************************************************************/
1143
1144typedef union _MPI2_SIMPLE_SGE_UNION {
1145 MPI2_SGE_SIMPLE_UNION MpiSimple;
1146 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1147} MPI2_SIMPLE_SGE_UNION, *PTR_MPI2_SIMPLE_SGE_UNION,
1148 Mpi2SimpleSgeUntion_t, *pMpi2SimpleSgeUntion_t;
1149
1150typedef union _MPI2_SGE_IO_UNION {
1151 MPI2_SGE_SIMPLE_UNION MpiSimple;
1152 MPI2_SGE_CHAIN_UNION MpiChain;
1153 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1154 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1155} MPI2_SGE_IO_UNION, *PTR_MPI2_SGE_IO_UNION,
1156 Mpi2SGEIOUnion_t, *pMpi2SGEIOUnion_t;
1157
1158/****************************************************************************
1159*
1160* Values for SGLFlags field, used in many request messages with an SGL
1161*
1162****************************************************************************/
1163
1164/*values for MPI SGL Data Location Address Space subfield */
1165#define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1166#define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1167#define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1168#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1169#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1170/*values for SGL Type subfield */
1171#define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1172#define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1173#define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1174#define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)
1175
1176#endif