Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 1 | #ifndef LINUX_MSI_H |
| 2 | #define LINUX_MSI_H |
| 3 | |
Neil Horman | b50cac5 | 2011-10-06 14:08:18 -0400 | [diff] [blame] | 4 | #include <linux/kobject.h> |
Michael Ellerman | 4aa9bc9 | 2007-04-05 17:19:10 +1000 | [diff] [blame] | 5 | #include <linux/list.h> |
| 6 | |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 7 | struct msi_msg { |
| 8 | u32 address_lo; /* low 32 bits of msi message address */ |
| 9 | u32 address_hi; /* high 32 bits of msi message address */ |
| 10 | u32 data; /* 16 bits of msi message data */ |
| 11 | }; |
| 12 | |
Yijing Wang | 38737d8 | 2014-10-27 10:44:36 +0800 | [diff] [blame] | 13 | extern int pci_msi_ignore_mask; |
Satoru Takeuchi | c54c187 | 2007-01-18 13:50:05 +0900 | [diff] [blame] | 14 | /* Helper functions */ |
Thomas Gleixner | 1c9db52 | 2010-09-28 16:46:51 +0200 | [diff] [blame] | 15 | struct irq_data; |
Thomas Gleixner | 39431ac | 2010-09-28 19:09:51 +0200 | [diff] [blame] | 16 | struct msi_desc; |
Jiang Liu | 25a98bd | 2015-07-09 16:00:45 +0800 | [diff] [blame] | 17 | struct pci_dev; |
Marc Zyngier | c09fcc4b | 2015-07-28 14:46:16 +0100 | [diff] [blame] | 18 | struct platform_msi_priv_data; |
Bjorn Helgaas | 2366d06 | 2013-04-18 10:55:46 -0600 | [diff] [blame] | 19 | void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg); |
Bjorn Helgaas | 2366d06 | 2013-04-18 10:55:46 -0600 | [diff] [blame] | 20 | void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg); |
Jiang Liu | 891d4a4 | 2014-11-09 23:10:33 +0800 | [diff] [blame] | 21 | |
Marc Zyngier | c09fcc4b | 2015-07-28 14:46:16 +0100 | [diff] [blame] | 22 | typedef void (*irq_write_msi_msg_t)(struct msi_desc *desc, |
| 23 | struct msi_msg *msg); |
| 24 | |
| 25 | /** |
| 26 | * platform_msi_desc - Platform device specific msi descriptor data |
| 27 | * @msi_priv_data: Pointer to platform private data |
| 28 | * @msi_index: The index of the MSI descriptor for multi MSI |
| 29 | */ |
| 30 | struct platform_msi_desc { |
| 31 | struct platform_msi_priv_data *msi_priv_data; |
| 32 | u16 msi_index; |
| 33 | }; |
| 34 | |
Jiang Liu | fc88419 | 2015-07-09 16:00:46 +0800 | [diff] [blame] | 35 | /** |
| 36 | * struct msi_desc - Descriptor structure for MSI based interrupts |
| 37 | * @list: List head for management |
| 38 | * @irq: The base interrupt number |
| 39 | * @nvec_used: The number of vectors used |
| 40 | * @dev: Pointer to the device which uses this descriptor |
| 41 | * @msg: The last set MSI message cached for reuse |
| 42 | * |
| 43 | * @masked: [PCI MSI/X] Mask bits |
| 44 | * @is_msix: [PCI MSI/X] True if MSI-X |
| 45 | * @multiple: [PCI MSI/X] log2 num of messages allocated |
| 46 | * @multi_cap: [PCI MSI/X] log2 num of messages supported |
| 47 | * @maskbit: [PCI MSI/X] Mask-Pending bit supported? |
| 48 | * @is_64: [PCI MSI/X] Address size: 0=32bit 1=64bit |
| 49 | * @entry_nr: [PCI MSI/X] Entry which is described by this descriptor |
| 50 | * @default_irq:[PCI MSI/X] The default pre-assigned non-MSI irq |
| 51 | * @mask_pos: [PCI MSI] Mask register position |
| 52 | * @mask_base: [PCI MSI-X] Mask register base address |
Marc Zyngier | c09fcc4b | 2015-07-28 14:46:16 +0100 | [diff] [blame] | 53 | * @platform: [platform] Platform device specific msi descriptor data |
Jiang Liu | fc88419 | 2015-07-09 16:00:46 +0800 | [diff] [blame] | 54 | */ |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 55 | struct msi_desc { |
Jiang Liu | fc88419 | 2015-07-09 16:00:46 +0800 | [diff] [blame] | 56 | /* Shared device/bus type independent data */ |
| 57 | struct list_head list; |
| 58 | unsigned int irq; |
| 59 | unsigned int nvec_used; |
| 60 | struct device *dev; |
| 61 | struct msi_msg msg; |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 62 | |
Matthew Wilcox | 264d9ca | 2009-03-17 08:54:08 -0400 | [diff] [blame] | 63 | union { |
Jiang Liu | fc88419 | 2015-07-09 16:00:46 +0800 | [diff] [blame] | 64 | /* PCI MSI/X specific data */ |
| 65 | struct { |
| 66 | u32 masked; |
| 67 | struct { |
| 68 | __u8 is_msix : 1; |
| 69 | __u8 multiple : 3; |
| 70 | __u8 multi_cap : 3; |
| 71 | __u8 maskbit : 1; |
| 72 | __u8 is_64 : 1; |
| 73 | __u16 entry_nr; |
| 74 | unsigned default_irq; |
| 75 | } msi_attrib; |
| 76 | union { |
| 77 | u8 mask_pos; |
| 78 | void __iomem *mask_base; |
| 79 | }; |
| 80 | }; |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 81 | |
Jiang Liu | fc88419 | 2015-07-09 16:00:46 +0800 | [diff] [blame] | 82 | /* |
| 83 | * Non PCI variants add their data structure here. New |
| 84 | * entries need to use a named structure. We want |
| 85 | * proper name spaces for this. The PCI part is |
| 86 | * anonymous for now as it would require an immediate |
| 87 | * tree wide cleanup. |
| 88 | */ |
Marc Zyngier | c09fcc4b | 2015-07-28 14:46:16 +0100 | [diff] [blame] | 89 | struct platform_msi_desc platform; |
Jiang Liu | fc88419 | 2015-07-09 16:00:46 +0800 | [diff] [blame] | 90 | }; |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 91 | }; |
| 92 | |
Jiang Liu | d31eb34 | 2014-11-15 22:24:03 +0800 | [diff] [blame] | 93 | /* Helpers to hide struct msi_desc implementation details */ |
Jiang Liu | 25a98bd | 2015-07-09 16:00:45 +0800 | [diff] [blame] | 94 | #define msi_desc_to_dev(desc) ((desc)->dev) |
Jiang Liu | 4a7cc83 | 2015-07-09 16:00:44 +0800 | [diff] [blame] | 95 | #define dev_to_msi_list(dev) (&(dev)->msi_list) |
Jiang Liu | d31eb34 | 2014-11-15 22:24:03 +0800 | [diff] [blame] | 96 | #define first_msi_entry(dev) \ |
| 97 | list_first_entry(dev_to_msi_list((dev)), struct msi_desc, list) |
| 98 | #define for_each_msi_entry(desc, dev) \ |
| 99 | list_for_each_entry((desc), dev_to_msi_list((dev)), list) |
| 100 | |
| 101 | #ifdef CONFIG_PCI_MSI |
| 102 | #define first_pci_msi_entry(pdev) first_msi_entry(&(pdev)->dev) |
| 103 | #define for_each_pci_msi_entry(desc, pdev) \ |
| 104 | for_each_msi_entry((desc), &(pdev)->dev) |
| 105 | |
Jiang Liu | 25a98bd | 2015-07-09 16:00:45 +0800 | [diff] [blame] | 106 | struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc); |
Jiang Liu | c179c9b | 2015-07-09 16:00:36 +0800 | [diff] [blame] | 107 | void *msi_desc_to_pci_sysdata(struct msi_desc *desc); |
| 108 | #else /* CONFIG_PCI_MSI */ |
| 109 | static inline void *msi_desc_to_pci_sysdata(struct msi_desc *desc) |
| 110 | { |
| 111 | return NULL; |
| 112 | } |
Jiang Liu | d31eb34 | 2014-11-15 22:24:03 +0800 | [diff] [blame] | 113 | #endif /* CONFIG_PCI_MSI */ |
| 114 | |
Jiang Liu | aa48b6f | 2015-07-09 16:00:47 +0800 | [diff] [blame] | 115 | struct msi_desc *alloc_msi_entry(struct device *dev); |
| 116 | void free_msi_entry(struct msi_desc *entry); |
Jiang Liu | 891d4a4 | 2014-11-09 23:10:33 +0800 | [diff] [blame] | 117 | void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg); |
Jiang Liu | 83a1891 | 2014-11-09 23:10:34 +0800 | [diff] [blame] | 118 | void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg); |
| 119 | void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg); |
| 120 | |
Thomas Gleixner | 23ed8d5 | 2014-11-23 11:55:58 +0100 | [diff] [blame] | 121 | u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag); |
| 122 | u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag); |
| 123 | void pci_msi_mask_irq(struct irq_data *data); |
| 124 | void pci_msi_unmask_irq(struct irq_data *data); |
| 125 | |
Jiang Liu | 83a1891 | 2014-11-09 23:10:34 +0800 | [diff] [blame] | 126 | /* Conversion helpers. Should be removed after merging */ |
| 127 | static inline void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
| 128 | { |
| 129 | __pci_write_msi_msg(entry, msg); |
| 130 | } |
| 131 | static inline void write_msi_msg(int irq, struct msi_msg *msg) |
| 132 | { |
| 133 | pci_write_msi_msg(irq, msg); |
| 134 | } |
Thomas Gleixner | 23ed8d5 | 2014-11-23 11:55:58 +0100 | [diff] [blame] | 135 | static inline void mask_msi_irq(struct irq_data *data) |
| 136 | { |
| 137 | pci_msi_mask_irq(data); |
| 138 | } |
| 139 | static inline void unmask_msi_irq(struct irq_data *data) |
| 140 | { |
| 141 | pci_msi_unmask_irq(data); |
| 142 | } |
Jiang Liu | 891d4a4 | 2014-11-09 23:10:33 +0800 | [diff] [blame] | 143 | |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 144 | /* |
Thomas Petazzoni | 4287d82 | 2013-08-09 22:27:06 +0200 | [diff] [blame] | 145 | * The arch hooks to setup up msi irqs. Those functions are |
| 146 | * implemented as weak symbols so that they /can/ be overriden by |
| 147 | * architecture specific code if needed. |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 148 | */ |
Eric W. Biederman | f7feaca | 2007-01-28 12:56:37 -0700 | [diff] [blame] | 149 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc); |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 150 | void arch_teardown_msi_irq(unsigned int irq); |
Bjorn Helgaas | 2366d06 | 2013-04-18 10:55:46 -0600 | [diff] [blame] | 151 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type); |
| 152 | void arch_teardown_msi_irqs(struct pci_dev *dev); |
DuanZhenzhong | ac8344c | 2013-12-04 13:09:16 +0800 | [diff] [blame] | 153 | void arch_restore_msi_irqs(struct pci_dev *dev); |
Thomas Petazzoni | 4287d82 | 2013-08-09 22:27:06 +0200 | [diff] [blame] | 154 | |
| 155 | void default_teardown_msi_irqs(struct pci_dev *dev); |
DuanZhenzhong | ac8344c | 2013-12-04 13:09:16 +0800 | [diff] [blame] | 156 | void default_restore_msi_irqs(struct pci_dev *dev); |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 157 | |
Yijing Wang | c2791b8 | 2014-11-11 17:45:45 -0700 | [diff] [blame] | 158 | struct msi_controller { |
Thierry Reding | 0cbdcfc | 2013-08-09 22:27:08 +0200 | [diff] [blame] | 159 | struct module *owner; |
| 160 | struct device *dev; |
Thomas Petazzoni | 0d5a6db | 2013-08-09 22:27:09 +0200 | [diff] [blame] | 161 | struct device_node *of_node; |
| 162 | struct list_head list; |
Thierry Reding | 0cbdcfc | 2013-08-09 22:27:08 +0200 | [diff] [blame] | 163 | |
Yijing Wang | c2791b8 | 2014-11-11 17:45:45 -0700 | [diff] [blame] | 164 | int (*setup_irq)(struct msi_controller *chip, struct pci_dev *dev, |
Thierry Reding | 0cbdcfc | 2013-08-09 22:27:08 +0200 | [diff] [blame] | 165 | struct msi_desc *desc); |
Yijing Wang | c2791b8 | 2014-11-11 17:45:45 -0700 | [diff] [blame] | 166 | void (*teardown_irq)(struct msi_controller *chip, unsigned int irq); |
Thierry Reding | 0cbdcfc | 2013-08-09 22:27:08 +0200 | [diff] [blame] | 167 | }; |
| 168 | |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 169 | #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN |
Jiang Liu | d910969 | 2014-11-15 22:24:04 +0800 | [diff] [blame] | 170 | |
Jiang Liu | aeeb596 | 2014-11-15 22:24:05 +0800 | [diff] [blame] | 171 | #include <linux/irqhandler.h> |
Jiang Liu | d910969 | 2014-11-15 22:24:04 +0800 | [diff] [blame] | 172 | #include <asm/msi.h> |
| 173 | |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 174 | struct irq_domain; |
| 175 | struct irq_chip; |
| 176 | struct device_node; |
| 177 | struct msi_domain_info; |
| 178 | |
| 179 | /** |
| 180 | * struct msi_domain_ops - MSI interrupt domain callbacks |
| 181 | * @get_hwirq: Retrieve the resulting hw irq number |
| 182 | * @msi_init: Domain specific init function for MSI interrupts |
| 183 | * @msi_free: Domain specific function to free a MSI interrupts |
Jiang Liu | d910969 | 2014-11-15 22:24:04 +0800 | [diff] [blame] | 184 | * @msi_check: Callback for verification of the domain/info/dev data |
| 185 | * @msi_prepare: Prepare the allocation of the interrupts in the domain |
| 186 | * @msi_finish: Optional callbacl to finalize the allocation |
| 187 | * @set_desc: Set the msi descriptor for an interrupt |
| 188 | * @handle_error: Optional error handler if the allocation fails |
| 189 | * |
| 190 | * @get_hwirq, @msi_init and @msi_free are callbacks used by |
| 191 | * msi_create_irq_domain() and related interfaces |
| 192 | * |
| 193 | * @msi_check, @msi_prepare, @msi_finish, @set_desc and @handle_error |
| 194 | * are callbacks used by msi_irq_domain_alloc_irqs() and related |
| 195 | * interfaces which are based on msi_desc. |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 196 | */ |
| 197 | struct msi_domain_ops { |
Jiang Liu | aeeb596 | 2014-11-15 22:24:05 +0800 | [diff] [blame] | 198 | irq_hw_number_t (*get_hwirq)(struct msi_domain_info *info, |
| 199 | msi_alloc_info_t *arg); |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 200 | int (*msi_init)(struct irq_domain *domain, |
| 201 | struct msi_domain_info *info, |
| 202 | unsigned int virq, irq_hw_number_t hwirq, |
Jiang Liu | aeeb596 | 2014-11-15 22:24:05 +0800 | [diff] [blame] | 203 | msi_alloc_info_t *arg); |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 204 | void (*msi_free)(struct irq_domain *domain, |
| 205 | struct msi_domain_info *info, |
| 206 | unsigned int virq); |
Jiang Liu | d910969 | 2014-11-15 22:24:04 +0800 | [diff] [blame] | 207 | int (*msi_check)(struct irq_domain *domain, |
| 208 | struct msi_domain_info *info, |
| 209 | struct device *dev); |
| 210 | int (*msi_prepare)(struct irq_domain *domain, |
| 211 | struct device *dev, int nvec, |
| 212 | msi_alloc_info_t *arg); |
| 213 | void (*msi_finish)(msi_alloc_info_t *arg, int retval); |
| 214 | void (*set_desc)(msi_alloc_info_t *arg, |
| 215 | struct msi_desc *desc); |
| 216 | int (*handle_error)(struct irq_domain *domain, |
| 217 | struct msi_desc *desc, int error); |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 218 | }; |
| 219 | |
| 220 | /** |
| 221 | * struct msi_domain_info - MSI interrupt domain data |
Jiang Liu | aeeb596 | 2014-11-15 22:24:05 +0800 | [diff] [blame] | 222 | * @flags: Flags to decribe features and capabilities |
| 223 | * @ops: The callback data structure |
| 224 | * @chip: Optional: associated interrupt chip |
| 225 | * @chip_data: Optional: associated interrupt chip data |
| 226 | * @handler: Optional: associated interrupt flow handler |
| 227 | * @handler_data: Optional: associated interrupt flow handler data |
| 228 | * @handler_name: Optional: associated interrupt flow handler name |
| 229 | * @data: Optional: domain specific data |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 230 | */ |
| 231 | struct msi_domain_info { |
Jiang Liu | aeeb596 | 2014-11-15 22:24:05 +0800 | [diff] [blame] | 232 | u32 flags; |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 233 | struct msi_domain_ops *ops; |
| 234 | struct irq_chip *chip; |
Jiang Liu | aeeb596 | 2014-11-15 22:24:05 +0800 | [diff] [blame] | 235 | void *chip_data; |
| 236 | irq_flow_handler_t handler; |
| 237 | void *handler_data; |
| 238 | const char *handler_name; |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 239 | void *data; |
| 240 | }; |
| 241 | |
Jiang Liu | aeeb596 | 2014-11-15 22:24:05 +0800 | [diff] [blame] | 242 | /* Flags for msi_domain_info */ |
| 243 | enum { |
| 244 | /* |
| 245 | * Init non implemented ops callbacks with default MSI domain |
| 246 | * callbacks. |
| 247 | */ |
| 248 | MSI_FLAG_USE_DEF_DOM_OPS = (1 << 0), |
| 249 | /* |
| 250 | * Init non implemented chip callbacks with default MSI chip |
| 251 | * callbacks. |
| 252 | */ |
| 253 | MSI_FLAG_USE_DEF_CHIP_OPS = (1 << 1), |
| 254 | /* Build identity map between hwirq and irq */ |
| 255 | MSI_FLAG_IDENTITY_MAP = (1 << 2), |
| 256 | /* Support multiple PCI MSI interrupts */ |
| 257 | MSI_FLAG_MULTI_PCI_MSI = (1 << 3), |
| 258 | /* Support PCI MSIX interrupts */ |
| 259 | MSI_FLAG_PCI_MSIX = (1 << 4), |
| 260 | }; |
| 261 | |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 262 | int msi_domain_set_affinity(struct irq_data *data, const struct cpumask *mask, |
| 263 | bool force); |
| 264 | |
| 265 | struct irq_domain *msi_create_irq_domain(struct device_node *of_node, |
| 266 | struct msi_domain_info *info, |
| 267 | struct irq_domain *parent); |
Jiang Liu | d910969 | 2014-11-15 22:24:04 +0800 | [diff] [blame] | 268 | int msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev, |
| 269 | int nvec); |
| 270 | void msi_domain_free_irqs(struct irq_domain *domain, struct device *dev); |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 271 | struct msi_domain_info *msi_get_domain_info(struct irq_domain *domain); |
| 272 | |
Marc Zyngier | c09fcc4b | 2015-07-28 14:46:16 +0100 | [diff] [blame] | 273 | struct irq_domain *platform_msi_create_irq_domain(struct device_node *np, |
| 274 | struct msi_domain_info *info, |
| 275 | struct irq_domain *parent); |
| 276 | int platform_msi_domain_alloc_irqs(struct device *dev, unsigned int nvec, |
| 277 | irq_write_msi_msg_t write_msi_msg); |
| 278 | void platform_msi_domain_free_irqs(struct device *dev); |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 279 | #endif /* CONFIG_GENERIC_MSI_IRQ_DOMAIN */ |
| 280 | |
Jiang Liu | 3878eae | 2014-11-11 21:02:18 +0800 | [diff] [blame] | 281 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
| 282 | void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg); |
| 283 | struct irq_domain *pci_msi_create_irq_domain(struct device_node *node, |
| 284 | struct msi_domain_info *info, |
| 285 | struct irq_domain *parent); |
| 286 | int pci_msi_domain_alloc_irqs(struct irq_domain *domain, struct pci_dev *dev, |
| 287 | int nvec, int type); |
| 288 | void pci_msi_domain_free_irqs(struct irq_domain *domain, struct pci_dev *dev); |
Jiang Liu | 8e047ad | 2014-11-15 22:24:07 +0800 | [diff] [blame] | 289 | struct irq_domain *pci_msi_create_default_irq_domain(struct device_node *node, |
| 290 | struct msi_domain_info *info, struct irq_domain *parent); |
| 291 | |
Jiang Liu | 3878eae | 2014-11-11 21:02:18 +0800 | [diff] [blame] | 292 | irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev, |
| 293 | struct msi_desc *desc); |
| 294 | int pci_msi_domain_check_cap(struct irq_domain *domain, |
| 295 | struct msi_domain_info *info, struct device *dev); |
| 296 | #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */ |
| 297 | |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 298 | #endif /* LINUX_MSI_H */ |