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Russell King7bedaa52012-04-13 12:10:24 +01001/*
2 * OMAP DMAengine support
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
Russell Kingfa3ad862013-11-02 17:07:09 +00008#include <linux/delay.h>
Russell King7bedaa52012-04-13 12:10:24 +01009#include <linux/dmaengine.h>
10#include <linux/dma-mapping.h>
11#include <linux/err.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/list.h>
15#include <linux/module.h>
16#include <linux/omap-dma.h>
17#include <linux/platform_device.h>
18#include <linux/slab.h>
19#include <linux/spinlock.h>
Jon Hunter8d306622013-02-26 12:27:24 -060020#include <linux/of_dma.h>
21#include <linux/of_device.h>
Russell King7bedaa52012-04-13 12:10:24 +010022
23#include "virt-dma.h"
Tony Lindgren7d7e1eb2012-08-27 17:43:01 -070024
Peter Ujfalusi341ce712015-04-09 12:35:50 +030025#define OMAP_SDMA_REQUESTS 127
26#define OMAP_SDMA_CHANNELS 32
27
Russell King7bedaa52012-04-13 12:10:24 +010028struct omap_dmadev {
29 struct dma_device ddev;
30 spinlock_t lock;
Russell King596c4712013-12-10 11:08:01 +000031 void __iomem *base;
32 const struct omap_dma_reg *reg_map;
Russell King1b416c42013-11-02 13:00:03 +000033 struct omap_system_dma_plat_info *plat;
Russell King6ddeb6d2013-12-10 19:05:50 +000034 bool legacy;
Peter Ujfaluside506082015-04-09 12:35:51 +030035 unsigned dma_requests;
Russell King6ddeb6d2013-12-10 19:05:50 +000036 spinlock_t irq_lock;
37 uint32_t irq_enable_mask;
Peter Ujfalusi341ce712015-04-09 12:35:50 +030038 struct omap_chan *lch_map[OMAP_SDMA_CHANNELS];
Russell King7bedaa52012-04-13 12:10:24 +010039};
40
41struct omap_chan {
42 struct virt_dma_chan vc;
Russell King596c4712013-12-10 11:08:01 +000043 void __iomem *channel_base;
44 const struct omap_dma_reg *reg_map;
Russell Kingaa4c5b92014-01-14 23:58:10 +000045 uint32_t ccr;
Russell King7bedaa52012-04-13 12:10:24 +010046
47 struct dma_slave_config cfg;
48 unsigned dma_sig;
Russell King3a774ea2012-06-21 10:40:15 +010049 bool cyclic;
Peter Ujfalusi2dcdf572012-09-14 15:05:45 +030050 bool paused;
Russell King7bedaa52012-04-13 12:10:24 +010051
52 int dma_ch;
53 struct omap_desc *desc;
54 unsigned sgidx;
55};
56
57struct omap_sg {
58 dma_addr_t addr;
59 uint32_t en; /* number of elements (24-bit) */
60 uint32_t fn; /* number of frames (16-bit) */
61};
62
63struct omap_desc {
64 struct virt_dma_desc vd;
65 enum dma_transfer_direction dir;
66 dma_addr_t dev_addr;
67
Russell King7c836bc2012-06-18 16:45:19 +010068 int16_t fi; /* for OMAP_DMA_SYNC_PACKET */
Russell King90438262013-11-02 19:57:06 +000069 uint8_t es; /* CSDP_DATA_TYPE_xxx */
Russell King3ed4d182013-11-02 19:16:09 +000070 uint32_t ccr; /* CCR value */
Russell King965aeb4d2013-11-06 17:12:30 +000071 uint16_t clnk_ctrl; /* CLNK_CTRL value */
Russell Kingfa3ad862013-11-02 17:07:09 +000072 uint16_t cicr; /* CICR value */
Russell King2f0d13b2013-11-02 18:51:53 +000073 uint32_t csdp; /* CSDP value */
Russell King7bedaa52012-04-13 12:10:24 +010074
75 unsigned sglen;
76 struct omap_sg sg[0];
77};
78
Russell King90438262013-11-02 19:57:06 +000079enum {
80 CCR_FS = BIT(5),
81 CCR_READ_PRIORITY = BIT(6),
82 CCR_ENABLE = BIT(7),
83 CCR_AUTO_INIT = BIT(8), /* OMAP1 only */
84 CCR_REPEAT = BIT(9), /* OMAP1 only */
85 CCR_OMAP31_DISABLE = BIT(10), /* OMAP1 only */
86 CCR_SUSPEND_SENSITIVE = BIT(8), /* OMAP2+ only */
87 CCR_RD_ACTIVE = BIT(9), /* OMAP2+ only */
88 CCR_WR_ACTIVE = BIT(10), /* OMAP2+ only */
89 CCR_SRC_AMODE_CONSTANT = 0 << 12,
90 CCR_SRC_AMODE_POSTINC = 1 << 12,
91 CCR_SRC_AMODE_SGLIDX = 2 << 12,
92 CCR_SRC_AMODE_DBLIDX = 3 << 12,
93 CCR_DST_AMODE_CONSTANT = 0 << 14,
94 CCR_DST_AMODE_POSTINC = 1 << 14,
95 CCR_DST_AMODE_SGLIDX = 2 << 14,
96 CCR_DST_AMODE_DBLIDX = 3 << 14,
97 CCR_CONSTANT_FILL = BIT(16),
98 CCR_TRANSPARENT_COPY = BIT(17),
99 CCR_BS = BIT(18),
100 CCR_SUPERVISOR = BIT(22),
101 CCR_PREFETCH = BIT(23),
102 CCR_TRIGGER_SRC = BIT(24),
103 CCR_BUFFERING_DISABLE = BIT(25),
104 CCR_WRITE_PRIORITY = BIT(26),
105 CCR_SYNC_ELEMENT = 0,
106 CCR_SYNC_FRAME = CCR_FS,
107 CCR_SYNC_BLOCK = CCR_BS,
108 CCR_SYNC_PACKET = CCR_BS | CCR_FS,
109
110 CSDP_DATA_TYPE_8 = 0,
111 CSDP_DATA_TYPE_16 = 1,
112 CSDP_DATA_TYPE_32 = 2,
113 CSDP_SRC_PORT_EMIFF = 0 << 2, /* OMAP1 only */
114 CSDP_SRC_PORT_EMIFS = 1 << 2, /* OMAP1 only */
115 CSDP_SRC_PORT_OCP_T1 = 2 << 2, /* OMAP1 only */
116 CSDP_SRC_PORT_TIPB = 3 << 2, /* OMAP1 only */
117 CSDP_SRC_PORT_OCP_T2 = 4 << 2, /* OMAP1 only */
118 CSDP_SRC_PORT_MPUI = 5 << 2, /* OMAP1 only */
119 CSDP_SRC_PACKED = BIT(6),
120 CSDP_SRC_BURST_1 = 0 << 7,
121 CSDP_SRC_BURST_16 = 1 << 7,
122 CSDP_SRC_BURST_32 = 2 << 7,
123 CSDP_SRC_BURST_64 = 3 << 7,
124 CSDP_DST_PORT_EMIFF = 0 << 9, /* OMAP1 only */
125 CSDP_DST_PORT_EMIFS = 1 << 9, /* OMAP1 only */
126 CSDP_DST_PORT_OCP_T1 = 2 << 9, /* OMAP1 only */
127 CSDP_DST_PORT_TIPB = 3 << 9, /* OMAP1 only */
128 CSDP_DST_PORT_OCP_T2 = 4 << 9, /* OMAP1 only */
129 CSDP_DST_PORT_MPUI = 5 << 9, /* OMAP1 only */
130 CSDP_DST_PACKED = BIT(13),
131 CSDP_DST_BURST_1 = 0 << 14,
132 CSDP_DST_BURST_16 = 1 << 14,
133 CSDP_DST_BURST_32 = 2 << 14,
134 CSDP_DST_BURST_64 = 3 << 14,
135
136 CICR_TOUT_IE = BIT(0), /* OMAP1 only */
137 CICR_DROP_IE = BIT(1),
138 CICR_HALF_IE = BIT(2),
139 CICR_FRAME_IE = BIT(3),
140 CICR_LAST_IE = BIT(4),
141 CICR_BLOCK_IE = BIT(5),
142 CICR_PKT_IE = BIT(7), /* OMAP2+ only */
143 CICR_TRANS_ERR_IE = BIT(8), /* OMAP2+ only */
144 CICR_SUPERVISOR_ERR_IE = BIT(10), /* OMAP2+ only */
145 CICR_MISALIGNED_ERR_IE = BIT(11), /* OMAP2+ only */
146 CICR_DRAIN_IE = BIT(12), /* OMAP2+ only */
147 CICR_SUPER_BLOCK_IE = BIT(14), /* OMAP2+ only */
148
149 CLNK_CTRL_ENABLE_LNK = BIT(15),
150};
151
Russell King7bedaa52012-04-13 12:10:24 +0100152static const unsigned es_bytes[] = {
Russell King90438262013-11-02 19:57:06 +0000153 [CSDP_DATA_TYPE_8] = 1,
154 [CSDP_DATA_TYPE_16] = 2,
155 [CSDP_DATA_TYPE_32] = 4,
Russell King7bedaa52012-04-13 12:10:24 +0100156};
157
Jon Hunter8d306622013-02-26 12:27:24 -0600158static struct of_dma_filter_info omap_dma_info = {
159 .filter_fn = omap_dma_filter_fn,
160};
161
Russell King7bedaa52012-04-13 12:10:24 +0100162static inline struct omap_dmadev *to_omap_dma_dev(struct dma_device *d)
163{
164 return container_of(d, struct omap_dmadev, ddev);
165}
166
167static inline struct omap_chan *to_omap_dma_chan(struct dma_chan *c)
168{
169 return container_of(c, struct omap_chan, vc.chan);
170}
171
172static inline struct omap_desc *to_omap_dma_desc(struct dma_async_tx_descriptor *t)
173{
174 return container_of(t, struct omap_desc, vd.tx);
175}
176
177static void omap_dma_desc_free(struct virt_dma_desc *vd)
178{
179 kfree(container_of(vd, struct omap_desc, vd));
180}
181
Russell King596c4712013-12-10 11:08:01 +0000182static void omap_dma_write(uint32_t val, unsigned type, void __iomem *addr)
183{
184 switch (type) {
185 case OMAP_DMA_REG_16BIT:
186 writew_relaxed(val, addr);
187 break;
188 case OMAP_DMA_REG_2X16BIT:
189 writew_relaxed(val, addr);
190 writew_relaxed(val >> 16, addr + 2);
191 break;
192 case OMAP_DMA_REG_32BIT:
193 writel_relaxed(val, addr);
194 break;
195 default:
196 WARN_ON(1);
197 }
198}
199
200static unsigned omap_dma_read(unsigned type, void __iomem *addr)
201{
202 unsigned val;
203
204 switch (type) {
205 case OMAP_DMA_REG_16BIT:
206 val = readw_relaxed(addr);
207 break;
208 case OMAP_DMA_REG_2X16BIT:
209 val = readw_relaxed(addr);
210 val |= readw_relaxed(addr + 2) << 16;
211 break;
212 case OMAP_DMA_REG_32BIT:
213 val = readl_relaxed(addr);
214 break;
215 default:
216 WARN_ON(1);
217 val = 0;
218 }
219
220 return val;
221}
222
Russell Kingc5ed98b2013-11-06 17:33:09 +0000223static void omap_dma_glbl_write(struct omap_dmadev *od, unsigned reg, unsigned val)
224{
Russell King596c4712013-12-10 11:08:01 +0000225 const struct omap_dma_reg *r = od->reg_map + reg;
226
227 WARN_ON(r->stride);
228
229 omap_dma_write(val, r->type, od->base + r->offset);
Russell Kingc5ed98b2013-11-06 17:33:09 +0000230}
231
232static unsigned omap_dma_glbl_read(struct omap_dmadev *od, unsigned reg)
233{
Russell King596c4712013-12-10 11:08:01 +0000234 const struct omap_dma_reg *r = od->reg_map + reg;
235
236 WARN_ON(r->stride);
237
238 return omap_dma_read(r->type, od->base + r->offset);
Russell Kingc5ed98b2013-11-06 17:33:09 +0000239}
240
241static void omap_dma_chan_write(struct omap_chan *c, unsigned reg, unsigned val)
242{
Russell King596c4712013-12-10 11:08:01 +0000243 const struct omap_dma_reg *r = c->reg_map + reg;
244
245 omap_dma_write(val, r->type, c->channel_base + r->offset);
Russell Kingc5ed98b2013-11-06 17:33:09 +0000246}
247
248static unsigned omap_dma_chan_read(struct omap_chan *c, unsigned reg)
249{
Russell King596c4712013-12-10 11:08:01 +0000250 const struct omap_dma_reg *r = c->reg_map + reg;
251
252 return omap_dma_read(r->type, c->channel_base + r->offset);
Russell Kingc5ed98b2013-11-06 17:33:09 +0000253}
254
Russell King470b23f2013-11-02 21:23:06 +0000255static void omap_dma_clear_csr(struct omap_chan *c)
256{
257 if (dma_omap1())
Russell Kingc5ed98b2013-11-06 17:33:09 +0000258 omap_dma_chan_read(c, CSR);
Russell King470b23f2013-11-02 21:23:06 +0000259 else
Russell Kingc5ed98b2013-11-06 17:33:09 +0000260 omap_dma_chan_write(c, CSR, ~0);
Russell King470b23f2013-11-02 21:23:06 +0000261}
262
Russell King6ddeb6d2013-12-10 19:05:50 +0000263static unsigned omap_dma_get_csr(struct omap_chan *c)
264{
265 unsigned val = omap_dma_chan_read(c, CSR);
266
267 if (!dma_omap1())
268 omap_dma_chan_write(c, CSR, val);
269
270 return val;
271}
272
Russell King596c4712013-12-10 11:08:01 +0000273static void omap_dma_assign(struct omap_dmadev *od, struct omap_chan *c,
274 unsigned lch)
275{
276 c->channel_base = od->base + od->plat->channel_stride * lch;
Russell King6ddeb6d2013-12-10 19:05:50 +0000277
278 od->lch_map[lch] = c;
Russell King596c4712013-12-10 11:08:01 +0000279}
280
Russell Kingfa3ad862013-11-02 17:07:09 +0000281static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
282{
283 struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
Russell Kingfa3ad862013-11-02 17:07:09 +0000284
285 if (__dma_omap15xx(od->plat->dma_attr))
Russell Kingc5ed98b2013-11-06 17:33:09 +0000286 omap_dma_chan_write(c, CPC, 0);
Russell Kingfa3ad862013-11-02 17:07:09 +0000287 else
Russell Kingc5ed98b2013-11-06 17:33:09 +0000288 omap_dma_chan_write(c, CDAC, 0);
Russell Kingfa3ad862013-11-02 17:07:09 +0000289
Russell King470b23f2013-11-02 21:23:06 +0000290 omap_dma_clear_csr(c);
Russell Kingfa3ad862013-11-02 17:07:09 +0000291
292 /* Enable interrupts */
Russell Kingc5ed98b2013-11-06 17:33:09 +0000293 omap_dma_chan_write(c, CICR, d->cicr);
Russell Kingfa3ad862013-11-02 17:07:09 +0000294
Russell King45da7b02013-11-06 17:18:42 +0000295 /* Enable channel */
Russell Kingc5ed98b2013-11-06 17:33:09 +0000296 omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE);
Russell Kingfa3ad862013-11-02 17:07:09 +0000297}
298
299static void omap_dma_stop(struct omap_chan *c)
300{
301 struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
302 uint32_t val;
303
304 /* disable irq */
Russell Kingc5ed98b2013-11-06 17:33:09 +0000305 omap_dma_chan_write(c, CICR, 0);
Russell Kingfa3ad862013-11-02 17:07:09 +0000306
Russell King470b23f2013-11-02 21:23:06 +0000307 omap_dma_clear_csr(c);
Russell Kingfa3ad862013-11-02 17:07:09 +0000308
Russell Kingc5ed98b2013-11-06 17:33:09 +0000309 val = omap_dma_chan_read(c, CCR);
Russell King90438262013-11-02 19:57:06 +0000310 if (od->plat->errata & DMA_ERRATA_i541 && val & CCR_TRIGGER_SRC) {
Russell Kingfa3ad862013-11-02 17:07:09 +0000311 uint32_t sysconfig;
312 unsigned i;
313
Russell Kingc5ed98b2013-11-06 17:33:09 +0000314 sysconfig = omap_dma_glbl_read(od, OCP_SYSCONFIG);
Russell Kingfa3ad862013-11-02 17:07:09 +0000315 val = sysconfig & ~DMA_SYSCONFIG_MIDLEMODE_MASK;
316 val |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
Russell Kingc5ed98b2013-11-06 17:33:09 +0000317 omap_dma_glbl_write(od, OCP_SYSCONFIG, val);
Russell Kingfa3ad862013-11-02 17:07:09 +0000318
Russell Kingc5ed98b2013-11-06 17:33:09 +0000319 val = omap_dma_chan_read(c, CCR);
Russell King90438262013-11-02 19:57:06 +0000320 val &= ~CCR_ENABLE;
Russell Kingc5ed98b2013-11-06 17:33:09 +0000321 omap_dma_chan_write(c, CCR, val);
Russell Kingfa3ad862013-11-02 17:07:09 +0000322
323 /* Wait for sDMA FIFO to drain */
324 for (i = 0; ; i++) {
Russell Kingc5ed98b2013-11-06 17:33:09 +0000325 val = omap_dma_chan_read(c, CCR);
Russell King90438262013-11-02 19:57:06 +0000326 if (!(val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE)))
Russell Kingfa3ad862013-11-02 17:07:09 +0000327 break;
328
329 if (i > 100)
330 break;
331
332 udelay(5);
333 }
334
Russell King90438262013-11-02 19:57:06 +0000335 if (val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE))
Russell Kingfa3ad862013-11-02 17:07:09 +0000336 dev_err(c->vc.chan.device->dev,
337 "DMA drain did not complete on lch %d\n",
338 c->dma_ch);
339
Russell Kingc5ed98b2013-11-06 17:33:09 +0000340 omap_dma_glbl_write(od, OCP_SYSCONFIG, sysconfig);
Russell Kingfa3ad862013-11-02 17:07:09 +0000341 } else {
Russell King90438262013-11-02 19:57:06 +0000342 val &= ~CCR_ENABLE;
Russell Kingc5ed98b2013-11-06 17:33:09 +0000343 omap_dma_chan_write(c, CCR, val);
Russell Kingfa3ad862013-11-02 17:07:09 +0000344 }
345
346 mb();
347
348 if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) {
Russell Kingc5ed98b2013-11-06 17:33:09 +0000349 val = omap_dma_chan_read(c, CLNK_CTRL);
Russell Kingfa3ad862013-11-02 17:07:09 +0000350
351 if (dma_omap1())
352 val |= 1 << 14; /* set the STOP_LNK bit */
353 else
Russell King90438262013-11-02 19:57:06 +0000354 val &= ~CLNK_CTRL_ENABLE_LNK;
Russell Kingfa3ad862013-11-02 17:07:09 +0000355
Russell Kingc5ed98b2013-11-06 17:33:09 +0000356 omap_dma_chan_write(c, CLNK_CTRL, val);
Russell Kingfa3ad862013-11-02 17:07:09 +0000357 }
358}
359
Russell King7bedaa52012-04-13 12:10:24 +0100360static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
361 unsigned idx)
362{
363 struct omap_sg *sg = d->sg + idx;
Russell King893e63e2013-11-03 11:17:11 +0000364 unsigned cxsa, cxei, cxfi;
Russell King7bedaa52012-04-13 12:10:24 +0100365
Peter Ujfalusi4ce98c02015-04-22 10:34:29 +0300366 if (d->dir == DMA_DEV_TO_MEM || d->dir == DMA_MEM_TO_MEM) {
Russell King893e63e2013-11-03 11:17:11 +0000367 cxsa = CDSA;
368 cxei = CDEI;
369 cxfi = CDFI;
Russell Kingb9e97822013-11-02 13:26:57 +0000370 } else {
Russell King893e63e2013-11-03 11:17:11 +0000371 cxsa = CSSA;
372 cxei = CSEI;
373 cxfi = CSFI;
Russell Kingb9e97822013-11-02 13:26:57 +0000374 }
375
Russell Kingc5ed98b2013-11-06 17:33:09 +0000376 omap_dma_chan_write(c, cxsa, sg->addr);
377 omap_dma_chan_write(c, cxei, 0);
378 omap_dma_chan_write(c, cxfi, 0);
379 omap_dma_chan_write(c, CEN, sg->en);
380 omap_dma_chan_write(c, CFN, sg->fn);
Russell King7bedaa52012-04-13 12:10:24 +0100381
Russell Kingfa3ad862013-11-02 17:07:09 +0000382 omap_dma_start(c, d);
Russell King7bedaa52012-04-13 12:10:24 +0100383}
384
385static void omap_dma_start_desc(struct omap_chan *c)
386{
387 struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
388 struct omap_desc *d;
Russell King893e63e2013-11-03 11:17:11 +0000389 unsigned cxsa, cxei, cxfi;
Russell King7bedaa52012-04-13 12:10:24 +0100390
391 if (!vd) {
392 c->desc = NULL;
393 return;
394 }
395
396 list_del(&vd->node);
397
398 c->desc = d = to_omap_dma_desc(&vd->tx);
399 c->sgidx = 0;
400
Russell King59871902013-11-06 17:15:16 +0000401 /*
402 * This provides the necessary barrier to ensure data held in
403 * DMA coherent memory is visible to the DMA engine prior to
404 * the transfer starting.
405 */
406 mb();
407
Russell Kingc5ed98b2013-11-06 17:33:09 +0000408 omap_dma_chan_write(c, CCR, d->ccr);
Russell King3ed4d182013-11-02 19:16:09 +0000409 if (dma_omap1())
Russell Kingc5ed98b2013-11-06 17:33:09 +0000410 omap_dma_chan_write(c, CCR2, d->ccr >> 16);
Russell Kingb9e97822013-11-02 13:26:57 +0000411
Peter Ujfalusi4ce98c02015-04-22 10:34:29 +0300412 if (d->dir == DMA_DEV_TO_MEM || d->dir == DMA_MEM_TO_MEM) {
Russell King893e63e2013-11-03 11:17:11 +0000413 cxsa = CSSA;
414 cxei = CSEI;
415 cxfi = CSFI;
Russell Kingb9e97822013-11-02 13:26:57 +0000416 } else {
Russell King893e63e2013-11-03 11:17:11 +0000417 cxsa = CDSA;
418 cxei = CDEI;
419 cxfi = CDFI;
Russell Kingb9e97822013-11-02 13:26:57 +0000420 }
Russell King7bedaa52012-04-13 12:10:24 +0100421
Russell Kingc5ed98b2013-11-06 17:33:09 +0000422 omap_dma_chan_write(c, cxsa, d->dev_addr);
423 omap_dma_chan_write(c, cxei, 0);
424 omap_dma_chan_write(c, cxfi, d->fi);
425 omap_dma_chan_write(c, CSDP, d->csdp);
426 omap_dma_chan_write(c, CLNK_CTRL, d->clnk_ctrl);
Russell King913a2d02013-11-02 14:41:42 +0000427
Russell King7bedaa52012-04-13 12:10:24 +0100428 omap_dma_start_sg(c, d, 0);
429}
430
431static void omap_dma_callback(int ch, u16 status, void *data)
432{
433 struct omap_chan *c = data;
434 struct omap_desc *d;
435 unsigned long flags;
436
437 spin_lock_irqsave(&c->vc.lock, flags);
438 d = c->desc;
439 if (d) {
Russell King3a774ea2012-06-21 10:40:15 +0100440 if (!c->cyclic) {
441 if (++c->sgidx < d->sglen) {
442 omap_dma_start_sg(c, d, c->sgidx);
443 } else {
444 omap_dma_start_desc(c);
445 vchan_cookie_complete(&d->vd);
446 }
Russell King7bedaa52012-04-13 12:10:24 +0100447 } else {
Russell King3a774ea2012-06-21 10:40:15 +0100448 vchan_cyclic_callback(&d->vd);
Russell King7bedaa52012-04-13 12:10:24 +0100449 }
450 }
451 spin_unlock_irqrestore(&c->vc.lock, flags);
452}
453
Russell King6ddeb6d2013-12-10 19:05:50 +0000454static irqreturn_t omap_dma_irq(int irq, void *devid)
455{
456 struct omap_dmadev *od = devid;
457 unsigned status, channel;
458
459 spin_lock(&od->irq_lock);
460
461 status = omap_dma_glbl_read(od, IRQSTATUS_L1);
462 status &= od->irq_enable_mask;
463 if (status == 0) {
464 spin_unlock(&od->irq_lock);
465 return IRQ_NONE;
466 }
467
468 while ((channel = ffs(status)) != 0) {
469 unsigned mask, csr;
470 struct omap_chan *c;
471
472 channel -= 1;
473 mask = BIT(channel);
474 status &= ~mask;
475
476 c = od->lch_map[channel];
477 if (c == NULL) {
478 /* This should never happen */
479 dev_err(od->ddev.dev, "invalid channel %u\n", channel);
480 continue;
481 }
482
483 csr = omap_dma_get_csr(c);
484 omap_dma_glbl_write(od, IRQSTATUS_L1, mask);
485
486 omap_dma_callback(channel, csr, c);
487 }
488
489 spin_unlock(&od->irq_lock);
490
491 return IRQ_HANDLED;
492}
493
Russell King7bedaa52012-04-13 12:10:24 +0100494static int omap_dma_alloc_chan_resources(struct dma_chan *chan)
495{
Russell King596c4712013-12-10 11:08:01 +0000496 struct omap_dmadev *od = to_omap_dma_dev(chan->device);
Russell King7bedaa52012-04-13 12:10:24 +0100497 struct omap_chan *c = to_omap_dma_chan(chan);
Russell King596c4712013-12-10 11:08:01 +0000498 int ret;
Russell King7bedaa52012-04-13 12:10:24 +0100499
Russell King6ddeb6d2013-12-10 19:05:50 +0000500 if (od->legacy) {
501 ret = omap_request_dma(c->dma_sig, "DMA engine",
502 omap_dma_callback, c, &c->dma_ch);
503 } else {
504 ret = omap_request_dma(c->dma_sig, "DMA engine", NULL, NULL,
505 &c->dma_ch);
506 }
Russell King7bedaa52012-04-13 12:10:24 +0100507
Russell King6ddeb6d2013-12-10 19:05:50 +0000508 dev_dbg(od->ddev.dev, "allocating channel %u for %u\n",
509 c->dma_ch, c->dma_sig);
Russell King596c4712013-12-10 11:08:01 +0000510
Russell King6ddeb6d2013-12-10 19:05:50 +0000511 if (ret >= 0) {
Russell King596c4712013-12-10 11:08:01 +0000512 omap_dma_assign(od, c, c->dma_ch);
513
Russell King6ddeb6d2013-12-10 19:05:50 +0000514 if (!od->legacy) {
515 unsigned val;
516
517 spin_lock_irq(&od->irq_lock);
518 val = BIT(c->dma_ch);
519 omap_dma_glbl_write(od, IRQSTATUS_L1, val);
520 od->irq_enable_mask |= val;
521 omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);
522
523 val = omap_dma_glbl_read(od, IRQENABLE_L0);
524 val &= ~BIT(c->dma_ch);
525 omap_dma_glbl_write(od, IRQENABLE_L0, val);
526 spin_unlock_irq(&od->irq_lock);
527 }
528 }
529
Russell Kingaa4c5b92014-01-14 23:58:10 +0000530 if (dma_omap1()) {
531 if (__dma_omap16xx(od->plat->dma_attr)) {
532 c->ccr = CCR_OMAP31_DISABLE;
533 /* Duplicate what plat-omap/dma.c does */
534 c->ccr |= c->dma_ch + 1;
535 } else {
536 c->ccr = c->dma_sig & 0x1f;
537 }
538 } else {
539 c->ccr = c->dma_sig & 0x1f;
540 c->ccr |= (c->dma_sig & ~0x1f) << 14;
541 }
542 if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING)
543 c->ccr |= CCR_BUFFERING_DISABLE;
544
Russell King596c4712013-12-10 11:08:01 +0000545 return ret;
Russell King7bedaa52012-04-13 12:10:24 +0100546}
547
548static void omap_dma_free_chan_resources(struct dma_chan *chan)
549{
Russell King6ddeb6d2013-12-10 19:05:50 +0000550 struct omap_dmadev *od = to_omap_dma_dev(chan->device);
Russell King7bedaa52012-04-13 12:10:24 +0100551 struct omap_chan *c = to_omap_dma_chan(chan);
552
Russell King6ddeb6d2013-12-10 19:05:50 +0000553 if (!od->legacy) {
554 spin_lock_irq(&od->irq_lock);
555 od->irq_enable_mask &= ~BIT(c->dma_ch);
556 omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);
557 spin_unlock_irq(&od->irq_lock);
558 }
559
Russell King596c4712013-12-10 11:08:01 +0000560 c->channel_base = NULL;
Russell King6ddeb6d2013-12-10 19:05:50 +0000561 od->lch_map[c->dma_ch] = NULL;
Russell King7bedaa52012-04-13 12:10:24 +0100562 vchan_free_chan_resources(&c->vc);
563 omap_free_dma(c->dma_ch);
564
Russell King6ddeb6d2013-12-10 19:05:50 +0000565 dev_dbg(od->ddev.dev, "freeing channel for %u\n", c->dma_sig);
Peter Ujfalusieea531e2015-04-09 12:35:52 +0300566 c->dma_sig = 0;
Russell King7bedaa52012-04-13 12:10:24 +0100567}
568
Russell King3850e222012-06-21 10:37:35 +0100569static size_t omap_dma_sg_size(struct omap_sg *sg)
570{
571 return sg->en * sg->fn;
572}
573
574static size_t omap_dma_desc_size(struct omap_desc *d)
575{
576 unsigned i;
577 size_t size;
578
579 for (size = i = 0; i < d->sglen; i++)
580 size += omap_dma_sg_size(&d->sg[i]);
581
582 return size * es_bytes[d->es];
583}
584
585static size_t omap_dma_desc_size_pos(struct omap_desc *d, dma_addr_t addr)
586{
587 unsigned i;
588 size_t size, es_size = es_bytes[d->es];
589
590 for (size = i = 0; i < d->sglen; i++) {
591 size_t this_size = omap_dma_sg_size(&d->sg[i]) * es_size;
592
593 if (size)
594 size += this_size;
595 else if (addr >= d->sg[i].addr &&
596 addr < d->sg[i].addr + this_size)
597 size += d->sg[i].addr + this_size - addr;
598 }
599 return size;
600}
601
Russell Kingb07fd622013-11-06 19:26:45 +0000602/*
603 * OMAP 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
604 * read before the DMA controller finished disabling the channel.
605 */
606static uint32_t omap_dma_chan_read_3_3(struct omap_chan *c, unsigned reg)
607{
608 struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
609 uint32_t val;
610
611 val = omap_dma_chan_read(c, reg);
612 if (val == 0 && od->plat->errata & DMA_ERRATA_3_3)
613 val = omap_dma_chan_read(c, reg);
614
615 return val;
616}
617
Russell King3997cab2013-11-02 18:04:17 +0000618static dma_addr_t omap_dma_get_src_pos(struct omap_chan *c)
619{
620 struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
Russell Kingb07fd622013-11-06 19:26:45 +0000621 dma_addr_t addr, cdac;
Russell King3997cab2013-11-02 18:04:17 +0000622
Russell Kingb07fd622013-11-06 19:26:45 +0000623 if (__dma_omap15xx(od->plat->dma_attr)) {
Russell Kingc5ed98b2013-11-06 17:33:09 +0000624 addr = omap_dma_chan_read(c, CPC);
Russell Kingb07fd622013-11-06 19:26:45 +0000625 } else {
626 addr = omap_dma_chan_read_3_3(c, CSAC);
627 cdac = omap_dma_chan_read_3_3(c, CDAC);
Russell King3997cab2013-11-02 18:04:17 +0000628
Russell King3997cab2013-11-02 18:04:17 +0000629 /*
630 * CDAC == 0 indicates that the DMA transfer on the channel has
631 * not been started (no data has been transferred so far).
632 * Return the programmed source start address in this case.
633 */
Russell Kingb07fd622013-11-06 19:26:45 +0000634 if (cdac == 0)
Russell Kingc5ed98b2013-11-06 17:33:09 +0000635 addr = omap_dma_chan_read(c, CSSA);
Russell King3997cab2013-11-02 18:04:17 +0000636 }
637
638 if (dma_omap1())
Russell Kingc5ed98b2013-11-06 17:33:09 +0000639 addr |= omap_dma_chan_read(c, CSSA) & 0xffff0000;
Russell King3997cab2013-11-02 18:04:17 +0000640
641 return addr;
642}
643
644static dma_addr_t omap_dma_get_dst_pos(struct omap_chan *c)
645{
646 struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
647 dma_addr_t addr;
648
Russell Kingb07fd622013-11-06 19:26:45 +0000649 if (__dma_omap15xx(od->plat->dma_attr)) {
Russell Kingc5ed98b2013-11-06 17:33:09 +0000650 addr = omap_dma_chan_read(c, CPC);
Russell Kingb07fd622013-11-06 19:26:45 +0000651 } else {
652 addr = omap_dma_chan_read_3_3(c, CDAC);
Russell King3997cab2013-11-02 18:04:17 +0000653
Russell King3997cab2013-11-02 18:04:17 +0000654 /*
Russell Kingb07fd622013-11-06 19:26:45 +0000655 * CDAC == 0 indicates that the DMA transfer on the channel
656 * has not been started (no data has been transferred so
657 * far). Return the programmed destination start address in
658 * this case.
Russell King3997cab2013-11-02 18:04:17 +0000659 */
660 if (addr == 0)
Russell Kingc5ed98b2013-11-06 17:33:09 +0000661 addr = omap_dma_chan_read(c, CDSA);
Russell King3997cab2013-11-02 18:04:17 +0000662 }
663
664 if (dma_omap1())
Russell Kingc5ed98b2013-11-06 17:33:09 +0000665 addr |= omap_dma_chan_read(c, CDSA) & 0xffff0000;
Russell King3997cab2013-11-02 18:04:17 +0000666
667 return addr;
668}
669
Russell King7bedaa52012-04-13 12:10:24 +0100670static enum dma_status omap_dma_tx_status(struct dma_chan *chan,
671 dma_cookie_t cookie, struct dma_tx_state *txstate)
672{
Russell King3850e222012-06-21 10:37:35 +0100673 struct omap_chan *c = to_omap_dma_chan(chan);
674 struct virt_dma_desc *vd;
675 enum dma_status ret;
Peter Ujfalusi1a7cf7b2015-11-11 12:37:58 +0200676 uint32_t ccr;
Russell King3850e222012-06-21 10:37:35 +0100677 unsigned long flags;
678
Peter Ujfalusi1a7cf7b2015-11-11 12:37:58 +0200679 ccr = omap_dma_chan_read(c, CCR);
680 /* The channel is no longer active, handle the completion right away */
681 if (!(ccr & CCR_ENABLE))
682 omap_dma_callback(c->dma_ch, 0, c);
683
Russell King3850e222012-06-21 10:37:35 +0100684 ret = dma_cookie_status(chan, cookie, txstate);
Vinod Koul7cce5082013-10-16 20:51:54 +0530685 if (ret == DMA_COMPLETE || !txstate)
Russell King3850e222012-06-21 10:37:35 +0100686 return ret;
687
688 spin_lock_irqsave(&c->vc.lock, flags);
689 vd = vchan_find_desc(&c->vc, cookie);
690 if (vd) {
691 txstate->residue = omap_dma_desc_size(to_omap_dma_desc(&vd->tx));
692 } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
693 struct omap_desc *d = c->desc;
694 dma_addr_t pos;
695
696 if (d->dir == DMA_MEM_TO_DEV)
Russell King3997cab2013-11-02 18:04:17 +0000697 pos = omap_dma_get_src_pos(c);
Peter Ujfalusiadf850b2015-11-11 12:37:55 +0200698 else if (d->dir == DMA_DEV_TO_MEM || d->dir == DMA_MEM_TO_MEM)
Russell King3997cab2013-11-02 18:04:17 +0000699 pos = omap_dma_get_dst_pos(c);
Russell King3850e222012-06-21 10:37:35 +0100700 else
701 pos = 0;
702
703 txstate->residue = omap_dma_desc_size_pos(d, pos);
704 } else {
705 txstate->residue = 0;
706 }
707 spin_unlock_irqrestore(&c->vc.lock, flags);
708
709 return ret;
Russell King7bedaa52012-04-13 12:10:24 +0100710}
711
712static void omap_dma_issue_pending(struct dma_chan *chan)
713{
714 struct omap_chan *c = to_omap_dma_chan(chan);
715 unsigned long flags;
716
717 spin_lock_irqsave(&c->vc.lock, flags);
Peter Ujfalusi1c1d25f2015-11-11 12:37:57 +0200718 if (vchan_issue_pending(&c->vc) && !c->desc)
719 omap_dma_start_desc(c);
Russell King7bedaa52012-04-13 12:10:24 +0100720 spin_unlock_irqrestore(&c->vc.lock, flags);
721}
722
723static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
724 struct dma_chan *chan, struct scatterlist *sgl, unsigned sglen,
725 enum dma_transfer_direction dir, unsigned long tx_flags, void *context)
726{
Russell King49ae0b22013-11-02 21:09:18 +0000727 struct omap_dmadev *od = to_omap_dma_dev(chan->device);
Russell King7bedaa52012-04-13 12:10:24 +0100728 struct omap_chan *c = to_omap_dma_chan(chan);
729 enum dma_slave_buswidth dev_width;
730 struct scatterlist *sgent;
731 struct omap_desc *d;
732 dma_addr_t dev_addr;
Peter Ujfalusie8a5e792015-11-11 12:37:56 +0200733 unsigned i, es, en, frame_bytes;
Russell King7bedaa52012-04-13 12:10:24 +0100734 u32 burst;
735
736 if (dir == DMA_DEV_TO_MEM) {
737 dev_addr = c->cfg.src_addr;
738 dev_width = c->cfg.src_addr_width;
739 burst = c->cfg.src_maxburst;
Russell King7bedaa52012-04-13 12:10:24 +0100740 } else if (dir == DMA_MEM_TO_DEV) {
741 dev_addr = c->cfg.dst_addr;
742 dev_width = c->cfg.dst_addr_width;
743 burst = c->cfg.dst_maxburst;
Russell King7bedaa52012-04-13 12:10:24 +0100744 } else {
745 dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
746 return NULL;
747 }
748
749 /* Bus width translates to the element size (ES) */
750 switch (dev_width) {
751 case DMA_SLAVE_BUSWIDTH_1_BYTE:
Russell King90438262013-11-02 19:57:06 +0000752 es = CSDP_DATA_TYPE_8;
Russell King7bedaa52012-04-13 12:10:24 +0100753 break;
754 case DMA_SLAVE_BUSWIDTH_2_BYTES:
Russell King90438262013-11-02 19:57:06 +0000755 es = CSDP_DATA_TYPE_16;
Russell King7bedaa52012-04-13 12:10:24 +0100756 break;
757 case DMA_SLAVE_BUSWIDTH_4_BYTES:
Russell King90438262013-11-02 19:57:06 +0000758 es = CSDP_DATA_TYPE_32;
Russell King7bedaa52012-04-13 12:10:24 +0100759 break;
760 default: /* not reached */
761 return NULL;
762 }
763
764 /* Now allocate and setup the descriptor. */
765 d = kzalloc(sizeof(*d) + sglen * sizeof(d->sg[0]), GFP_ATOMIC);
766 if (!d)
767 return NULL;
768
769 d->dir = dir;
770 d->dev_addr = dev_addr;
771 d->es = es;
Russell King3ed4d182013-11-02 19:16:09 +0000772
Russell Kingaa4c5b92014-01-14 23:58:10 +0000773 d->ccr = c->ccr | CCR_SYNC_FRAME;
Russell King3ed4d182013-11-02 19:16:09 +0000774 if (dir == DMA_DEV_TO_MEM)
Russell King90438262013-11-02 19:57:06 +0000775 d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT;
Russell King3ed4d182013-11-02 19:16:09 +0000776 else
Russell King90438262013-11-02 19:57:06 +0000777 d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC;
Russell King3ed4d182013-11-02 19:16:09 +0000778
Russell King90438262013-11-02 19:57:06 +0000779 d->cicr = CICR_DROP_IE | CICR_BLOCK_IE;
Russell King2f0d13b2013-11-02 18:51:53 +0000780 d->csdp = es;
Russell Kingfa3ad862013-11-02 17:07:09 +0000781
Russell King2f0d13b2013-11-02 18:51:53 +0000782 if (dma_omap1()) {
Russell King90438262013-11-02 19:57:06 +0000783 d->cicr |= CICR_TOUT_IE;
Russell King2f0d13b2013-11-02 18:51:53 +0000784
785 if (dir == DMA_DEV_TO_MEM)
Russell King90438262013-11-02 19:57:06 +0000786 d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_TIPB;
Russell King2f0d13b2013-11-02 18:51:53 +0000787 else
Russell King90438262013-11-02 19:57:06 +0000788 d->csdp |= CSDP_DST_PORT_TIPB | CSDP_SRC_PORT_EMIFF;
Russell King2f0d13b2013-11-02 18:51:53 +0000789 } else {
Russell King3ed4d182013-11-02 19:16:09 +0000790 if (dir == DMA_DEV_TO_MEM)
Russell King90438262013-11-02 19:57:06 +0000791 d->ccr |= CCR_TRIGGER_SRC;
Russell King3ed4d182013-11-02 19:16:09 +0000792
Russell King90438262013-11-02 19:57:06 +0000793 d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE;
Russell King2f0d13b2013-11-02 18:51:53 +0000794 }
Russell King965aeb4d2013-11-06 17:12:30 +0000795 if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS)
796 d->clnk_ctrl = c->dma_ch;
Russell King7bedaa52012-04-13 12:10:24 +0100797
798 /*
799 * Build our scatterlist entries: each contains the address,
800 * the number of elements (EN) in each frame, and the number of
801 * frames (FN). Number of bytes for this entry = ES * EN * FN.
802 *
803 * Burst size translates to number of elements with frame sync.
804 * Note: DMA engine defines burst to be the number of dev-width
805 * transfers.
806 */
807 en = burst;
808 frame_bytes = es_bytes[es] * en;
809 for_each_sg(sgl, sgent, sglen, i) {
Peter Ujfalusie8a5e792015-11-11 12:37:56 +0200810 d->sg[i].addr = sg_dma_address(sgent);
811 d->sg[i].en = en;
812 d->sg[i].fn = sg_dma_len(sgent) / frame_bytes;
Russell King7bedaa52012-04-13 12:10:24 +0100813 }
814
Peter Ujfalusie8a5e792015-11-11 12:37:56 +0200815 d->sglen = sglen;
Russell King7bedaa52012-04-13 12:10:24 +0100816
817 return vchan_tx_prep(&c->vc, &d->vd, tx_flags);
818}
819
Russell King3a774ea2012-06-21 10:40:15 +0100820static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
821 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
Laurent Pinchart31c1e5a2014-08-01 12:20:10 +0200822 size_t period_len, enum dma_transfer_direction dir, unsigned long flags)
Russell King3a774ea2012-06-21 10:40:15 +0100823{
Russell Kingfa3ad862013-11-02 17:07:09 +0000824 struct omap_dmadev *od = to_omap_dma_dev(chan->device);
Russell King3a774ea2012-06-21 10:40:15 +0100825 struct omap_chan *c = to_omap_dma_chan(chan);
826 enum dma_slave_buswidth dev_width;
827 struct omap_desc *d;
828 dma_addr_t dev_addr;
Russell King3ed4d182013-11-02 19:16:09 +0000829 unsigned es;
Russell King3a774ea2012-06-21 10:40:15 +0100830 u32 burst;
831
832 if (dir == DMA_DEV_TO_MEM) {
833 dev_addr = c->cfg.src_addr;
834 dev_width = c->cfg.src_addr_width;
835 burst = c->cfg.src_maxburst;
Russell King3a774ea2012-06-21 10:40:15 +0100836 } else if (dir == DMA_MEM_TO_DEV) {
837 dev_addr = c->cfg.dst_addr;
838 dev_width = c->cfg.dst_addr_width;
839 burst = c->cfg.dst_maxburst;
Russell King3a774ea2012-06-21 10:40:15 +0100840 } else {
841 dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
842 return NULL;
843 }
844
845 /* Bus width translates to the element size (ES) */
846 switch (dev_width) {
847 case DMA_SLAVE_BUSWIDTH_1_BYTE:
Russell King90438262013-11-02 19:57:06 +0000848 es = CSDP_DATA_TYPE_8;
Russell King3a774ea2012-06-21 10:40:15 +0100849 break;
850 case DMA_SLAVE_BUSWIDTH_2_BYTES:
Russell King90438262013-11-02 19:57:06 +0000851 es = CSDP_DATA_TYPE_16;
Russell King3a774ea2012-06-21 10:40:15 +0100852 break;
853 case DMA_SLAVE_BUSWIDTH_4_BYTES:
Russell King90438262013-11-02 19:57:06 +0000854 es = CSDP_DATA_TYPE_32;
Russell King3a774ea2012-06-21 10:40:15 +0100855 break;
856 default: /* not reached */
857 return NULL;
858 }
859
860 /* Now allocate and setup the descriptor. */
861 d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC);
862 if (!d)
863 return NULL;
864
865 d->dir = dir;
866 d->dev_addr = dev_addr;
867 d->fi = burst;
868 d->es = es;
Russell King3a774ea2012-06-21 10:40:15 +0100869 d->sg[0].addr = buf_addr;
870 d->sg[0].en = period_len / es_bytes[es];
871 d->sg[0].fn = buf_len / period_len;
872 d->sglen = 1;
Russell King3ed4d182013-11-02 19:16:09 +0000873
Russell Kingaa4c5b92014-01-14 23:58:10 +0000874 d->ccr = c->ccr;
Russell King3ed4d182013-11-02 19:16:09 +0000875 if (dir == DMA_DEV_TO_MEM)
Russell King90438262013-11-02 19:57:06 +0000876 d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT;
Russell King3ed4d182013-11-02 19:16:09 +0000877 else
Russell King90438262013-11-02 19:57:06 +0000878 d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC;
Russell King3ed4d182013-11-02 19:16:09 +0000879
Russell King90438262013-11-02 19:57:06 +0000880 d->cicr = CICR_DROP_IE;
Russell Kingfa3ad862013-11-02 17:07:09 +0000881 if (flags & DMA_PREP_INTERRUPT)
Russell King90438262013-11-02 19:57:06 +0000882 d->cicr |= CICR_FRAME_IE;
Russell Kingfa3ad862013-11-02 17:07:09 +0000883
Russell King2f0d13b2013-11-02 18:51:53 +0000884 d->csdp = es;
885
886 if (dma_omap1()) {
Russell King90438262013-11-02 19:57:06 +0000887 d->cicr |= CICR_TOUT_IE;
Russell King2f0d13b2013-11-02 18:51:53 +0000888
889 if (dir == DMA_DEV_TO_MEM)
Russell King90438262013-11-02 19:57:06 +0000890 d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_MPUI;
Russell King2f0d13b2013-11-02 18:51:53 +0000891 else
Russell King90438262013-11-02 19:57:06 +0000892 d->csdp |= CSDP_DST_PORT_MPUI | CSDP_SRC_PORT_EMIFF;
Russell King2f0d13b2013-11-02 18:51:53 +0000893 } else {
Russell King3ed4d182013-11-02 19:16:09 +0000894 if (burst)
Russell King90438262013-11-02 19:57:06 +0000895 d->ccr |= CCR_SYNC_PACKET;
896 else
897 d->ccr |= CCR_SYNC_ELEMENT;
Russell King3ed4d182013-11-02 19:16:09 +0000898
Misael Lopez Cruz47fac242015-09-14 15:31:05 +0300899 if (dir == DMA_DEV_TO_MEM) {
Russell King90438262013-11-02 19:57:06 +0000900 d->ccr |= CCR_TRIGGER_SRC;
Misael Lopez Cruz47fac242015-09-14 15:31:05 +0300901 d->csdp |= CSDP_DST_PACKED;
902 } else {
903 d->csdp |= CSDP_SRC_PACKED;
904 }
Russell King3ed4d182013-11-02 19:16:09 +0000905
Russell King90438262013-11-02 19:57:06 +0000906 d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE;
Russell King3a774ea2012-06-21 10:40:15 +0100907
Russell King90438262013-11-02 19:57:06 +0000908 d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64;
Russell King2f0d13b2013-11-02 18:51:53 +0000909 }
910
Russell King965aeb4d2013-11-06 17:12:30 +0000911 if (__dma_omap15xx(od->plat->dma_attr))
912 d->ccr |= CCR_AUTO_INIT | CCR_REPEAT;
913 else
914 d->clnk_ctrl = c->dma_ch | CLNK_CTRL_ENABLE_LNK;
915
Russell King3ed4d182013-11-02 19:16:09 +0000916 c->cyclic = true;
Russell King3a774ea2012-06-21 10:40:15 +0100917
Peter Ujfalusi2dde5b92012-09-14 15:05:48 +0300918 return vchan_tx_prep(&c->vc, &d->vd, flags);
Russell King3a774ea2012-06-21 10:40:15 +0100919}
920
Peter Ujfalusi4ce98c02015-04-22 10:34:29 +0300921static struct dma_async_tx_descriptor *omap_dma_prep_dma_memcpy(
922 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
923 size_t len, unsigned long tx_flags)
924{
925 struct omap_chan *c = to_omap_dma_chan(chan);
926 struct omap_desc *d;
927 uint8_t data_type;
928
929 d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC);
930 if (!d)
931 return NULL;
932
933 data_type = __ffs((src | dest | len));
934 if (data_type > CSDP_DATA_TYPE_32)
935 data_type = CSDP_DATA_TYPE_32;
936
937 d->dir = DMA_MEM_TO_MEM;
938 d->dev_addr = src;
939 d->fi = 0;
940 d->es = data_type;
941 d->sg[0].en = len / BIT(data_type);
942 d->sg[0].fn = 1;
943 d->sg[0].addr = dest;
944 d->sglen = 1;
945 d->ccr = c->ccr;
946 d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_POSTINC;
947
948 d->cicr = CICR_DROP_IE;
949 if (tx_flags & DMA_PREP_INTERRUPT)
950 d->cicr |= CICR_FRAME_IE;
951
952 d->csdp = data_type;
953
954 if (dma_omap1()) {
955 d->cicr |= CICR_TOUT_IE;
956 d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_EMIFF;
957 } else {
958 d->csdp |= CSDP_DST_PACKED | CSDP_SRC_PACKED;
959 d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE;
960 d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64;
961 }
962
963 return vchan_tx_prep(&c->vc, &d->vd, tx_flags);
964}
965
Maxime Ripard78ea4fe2014-11-17 14:42:28 +0100966static int omap_dma_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg)
Russell King7bedaa52012-04-13 12:10:24 +0100967{
Maxime Ripard78ea4fe2014-11-17 14:42:28 +0100968 struct omap_chan *c = to_omap_dma_chan(chan);
969
Russell King7bedaa52012-04-13 12:10:24 +0100970 if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
971 cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
972 return -EINVAL;
973
974 memcpy(&c->cfg, cfg, sizeof(c->cfg));
975
976 return 0;
977}
978
Maxime Ripard78ea4fe2014-11-17 14:42:28 +0100979static int omap_dma_terminate_all(struct dma_chan *chan)
Russell King7bedaa52012-04-13 12:10:24 +0100980{
Maxime Ripard78ea4fe2014-11-17 14:42:28 +0100981 struct omap_chan *c = to_omap_dma_chan(chan);
Russell King7bedaa52012-04-13 12:10:24 +0100982 unsigned long flags;
983 LIST_HEAD(head);
984
985 spin_lock_irqsave(&c->vc.lock, flags);
986
Russell King7bedaa52012-04-13 12:10:24 +0100987 /*
988 * Stop DMA activity: we assume the callback will not be called
Russell Kingfa3ad862013-11-02 17:07:09 +0000989 * after omap_dma_stop() returns (even if it does, it will see
Russell King7bedaa52012-04-13 12:10:24 +0100990 * c->desc is NULL and exit.)
991 */
992 if (c->desc) {
Peter Ujfalusi02d88b72015-03-27 13:35:52 +0200993 omap_dma_desc_free(&c->desc->vd);
Russell King7bedaa52012-04-13 12:10:24 +0100994 c->desc = NULL;
Peter Ujfalusi2dcdf572012-09-14 15:05:45 +0300995 /* Avoid stopping the dma twice */
996 if (!c->paused)
Russell Kingfa3ad862013-11-02 17:07:09 +0000997 omap_dma_stop(c);
Russell King7bedaa52012-04-13 12:10:24 +0100998 }
999
Russell King3a774ea2012-06-21 10:40:15 +01001000 if (c->cyclic) {
1001 c->cyclic = false;
Peter Ujfalusi2dcdf572012-09-14 15:05:45 +03001002 c->paused = false;
Russell King3a774ea2012-06-21 10:40:15 +01001003 }
1004
Russell King7bedaa52012-04-13 12:10:24 +01001005 vchan_get_all_descriptors(&c->vc, &head);
1006 spin_unlock_irqrestore(&c->vc.lock, flags);
1007 vchan_dma_desc_free_list(&c->vc, &head);
1008
1009 return 0;
1010}
1011
Maxime Ripard78ea4fe2014-11-17 14:42:28 +01001012static int omap_dma_pause(struct dma_chan *chan)
Russell King7bedaa52012-04-13 12:10:24 +01001013{
Maxime Ripard78ea4fe2014-11-17 14:42:28 +01001014 struct omap_chan *c = to_omap_dma_chan(chan);
1015
Peter Ujfalusi2dcdf572012-09-14 15:05:45 +03001016 /* Pause/Resume only allowed with cyclic mode */
1017 if (!c->cyclic)
1018 return -EINVAL;
1019
1020 if (!c->paused) {
Russell Kingfa3ad862013-11-02 17:07:09 +00001021 omap_dma_stop(c);
Peter Ujfalusi2dcdf572012-09-14 15:05:45 +03001022 c->paused = true;
1023 }
1024
1025 return 0;
Russell King7bedaa52012-04-13 12:10:24 +01001026}
1027
Maxime Ripard78ea4fe2014-11-17 14:42:28 +01001028static int omap_dma_resume(struct dma_chan *chan)
Russell King7bedaa52012-04-13 12:10:24 +01001029{
Maxime Ripard78ea4fe2014-11-17 14:42:28 +01001030 struct omap_chan *c = to_omap_dma_chan(chan);
1031
Peter Ujfalusi2dcdf572012-09-14 15:05:45 +03001032 /* Pause/Resume only allowed with cyclic mode */
1033 if (!c->cyclic)
1034 return -EINVAL;
1035
1036 if (c->paused) {
Peter Ujfalusib3d09da2014-09-16 22:45:56 +03001037 mb();
1038
Peter Ujfalusibfb60742014-09-16 22:45:57 +03001039 /* Restore channel link register */
1040 omap_dma_chan_write(c, CLNK_CTRL, c->desc->clnk_ctrl);
1041
Russell Kingfa3ad862013-11-02 17:07:09 +00001042 omap_dma_start(c, c->desc);
Peter Ujfalusi2dcdf572012-09-14 15:05:45 +03001043 c->paused = false;
1044 }
1045
1046 return 0;
Russell King7bedaa52012-04-13 12:10:24 +01001047}
1048
Peter Ujfalusieea531e2015-04-09 12:35:52 +03001049static int omap_dma_chan_init(struct omap_dmadev *od)
Russell King7bedaa52012-04-13 12:10:24 +01001050{
1051 struct omap_chan *c;
1052
1053 c = kzalloc(sizeof(*c), GFP_KERNEL);
1054 if (!c)
1055 return -ENOMEM;
1056
Russell King596c4712013-12-10 11:08:01 +00001057 c->reg_map = od->reg_map;
Russell King7bedaa52012-04-13 12:10:24 +01001058 c->vc.desc_free = omap_dma_desc_free;
1059 vchan_init(&c->vc, &od->ddev);
Russell King7bedaa52012-04-13 12:10:24 +01001060
Russell King7bedaa52012-04-13 12:10:24 +01001061 return 0;
1062}
1063
1064static void omap_dma_free(struct omap_dmadev *od)
1065{
Russell King7bedaa52012-04-13 12:10:24 +01001066 while (!list_empty(&od->ddev.channels)) {
1067 struct omap_chan *c = list_first_entry(&od->ddev.channels,
1068 struct omap_chan, vc.chan.device_node);
1069
1070 list_del(&c->vc.chan.device_node);
1071 tasklet_kill(&c->vc.task);
1072 kfree(c);
1073 }
Russell King7bedaa52012-04-13 12:10:24 +01001074}
1075
Peter Ujfalusi80b0e0a2014-03-29 19:03:30 +05301076#define OMAP_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
1077 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
1078 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
1079
Russell King7bedaa52012-04-13 12:10:24 +01001080static int omap_dma_probe(struct platform_device *pdev)
1081{
1082 struct omap_dmadev *od;
Russell King596c4712013-12-10 11:08:01 +00001083 struct resource *res;
Russell King6ddeb6d2013-12-10 19:05:50 +00001084 int rc, i, irq;
Russell King7bedaa52012-04-13 12:10:24 +01001085
Russell King104fce72013-11-02 12:58:29 +00001086 od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
Russell King7bedaa52012-04-13 12:10:24 +01001087 if (!od)
1088 return -ENOMEM;
1089
Russell King596c4712013-12-10 11:08:01 +00001090 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1091 od->base = devm_ioremap_resource(&pdev->dev, res);
1092 if (IS_ERR(od->base))
1093 return PTR_ERR(od->base);
1094
Russell King1b416c42013-11-02 13:00:03 +00001095 od->plat = omap_get_plat_info();
1096 if (!od->plat)
1097 return -EPROBE_DEFER;
1098
Russell King596c4712013-12-10 11:08:01 +00001099 od->reg_map = od->plat->reg_map;
1100
Russell King7bedaa52012-04-13 12:10:24 +01001101 dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
Russell King3a774ea2012-06-21 10:40:15 +01001102 dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
Peter Ujfalusi4ce98c02015-04-22 10:34:29 +03001103 dma_cap_set(DMA_MEMCPY, od->ddev.cap_mask);
Russell King7bedaa52012-04-13 12:10:24 +01001104 od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources;
1105 od->ddev.device_free_chan_resources = omap_dma_free_chan_resources;
1106 od->ddev.device_tx_status = omap_dma_tx_status;
1107 od->ddev.device_issue_pending = omap_dma_issue_pending;
1108 od->ddev.device_prep_slave_sg = omap_dma_prep_slave_sg;
Russell King3a774ea2012-06-21 10:40:15 +01001109 od->ddev.device_prep_dma_cyclic = omap_dma_prep_dma_cyclic;
Peter Ujfalusi4ce98c02015-04-22 10:34:29 +03001110 od->ddev.device_prep_dma_memcpy = omap_dma_prep_dma_memcpy;
Vinod Koul6c04cd42014-12-07 23:12:31 +05301111 od->ddev.device_config = omap_dma_slave_config;
Maxime Ripard78ea4fe2014-11-17 14:42:28 +01001112 od->ddev.device_pause = omap_dma_pause;
1113 od->ddev.device_resume = omap_dma_resume;
1114 od->ddev.device_terminate_all = omap_dma_terminate_all;
Maxime Ripard7d15b872014-11-17 14:42:49 +01001115 od->ddev.src_addr_widths = OMAP_DMA_BUSWIDTHS;
1116 od->ddev.dst_addr_widths = OMAP_DMA_BUSWIDTHS;
1117 od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1118 od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
Russell King7bedaa52012-04-13 12:10:24 +01001119 od->ddev.dev = &pdev->dev;
1120 INIT_LIST_HEAD(&od->ddev.channels);
Russell King7bedaa52012-04-13 12:10:24 +01001121 spin_lock_init(&od->lock);
Russell King6ddeb6d2013-12-10 19:05:50 +00001122 spin_lock_init(&od->irq_lock);
Russell King7bedaa52012-04-13 12:10:24 +01001123
Peter Ujfaluside506082015-04-09 12:35:51 +03001124 od->dma_requests = OMAP_SDMA_REQUESTS;
1125 if (pdev->dev.of_node && of_property_read_u32(pdev->dev.of_node,
1126 "dma-requests",
1127 &od->dma_requests)) {
1128 dev_info(&pdev->dev,
1129 "Missing dma-requests property, using %u.\n",
1130 OMAP_SDMA_REQUESTS);
1131 }
1132
Peter Ujfalusi8a322222015-04-09 12:35:53 +03001133 for (i = 0; i < OMAP_SDMA_CHANNELS; i++) {
Peter Ujfalusieea531e2015-04-09 12:35:52 +03001134 rc = omap_dma_chan_init(od);
Russell King7bedaa52012-04-13 12:10:24 +01001135 if (rc) {
1136 omap_dma_free(od);
1137 return rc;
1138 }
1139 }
1140
Russell King6ddeb6d2013-12-10 19:05:50 +00001141 irq = platform_get_irq(pdev, 1);
1142 if (irq <= 0) {
1143 dev_info(&pdev->dev, "failed to get L1 IRQ: %d\n", irq);
1144 od->legacy = true;
1145 } else {
1146 /* Disable all interrupts */
1147 od->irq_enable_mask = 0;
1148 omap_dma_glbl_write(od, IRQENABLE_L1, 0);
1149
1150 rc = devm_request_irq(&pdev->dev, irq, omap_dma_irq,
1151 IRQF_SHARED, "omap-dma-engine", od);
1152 if (rc)
1153 return rc;
1154 }
1155
Peter Ujfalusi020c62a2015-12-14 22:47:42 +02001156 od->ddev.filter.map = od->plat->slave_map;
1157 od->ddev.filter.mapcnt = od->plat->slavecnt;
1158 od->ddev.filter.fn = omap_dma_filter_fn;
1159
Russell King7bedaa52012-04-13 12:10:24 +01001160 rc = dma_async_device_register(&od->ddev);
1161 if (rc) {
1162 pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n",
1163 rc);
1164 omap_dma_free(od);
Jon Hunter8d306622013-02-26 12:27:24 -06001165 return rc;
1166 }
1167
1168 platform_set_drvdata(pdev, od);
1169
1170 if (pdev->dev.of_node) {
1171 omap_dma_info.dma_cap = od->ddev.cap_mask;
1172
1173 /* Device-tree DMA controller registration */
1174 rc = of_dma_controller_register(pdev->dev.of_node,
1175 of_dma_simple_xlate, &omap_dma_info);
1176 if (rc) {
1177 pr_warn("OMAP-DMA: failed to register DMA controller\n");
1178 dma_async_device_unregister(&od->ddev);
1179 omap_dma_free(od);
1180 }
Russell King7bedaa52012-04-13 12:10:24 +01001181 }
1182
1183 dev_info(&pdev->dev, "OMAP DMA engine driver\n");
1184
1185 return rc;
1186}
1187
1188static int omap_dma_remove(struct platform_device *pdev)
1189{
1190 struct omap_dmadev *od = platform_get_drvdata(pdev);
1191
Jon Hunter8d306622013-02-26 12:27:24 -06001192 if (pdev->dev.of_node)
1193 of_dma_controller_free(pdev->dev.of_node);
1194
Russell King7bedaa52012-04-13 12:10:24 +01001195 dma_async_device_unregister(&od->ddev);
Russell King6ddeb6d2013-12-10 19:05:50 +00001196
1197 if (!od->legacy) {
1198 /* Disable all interrupts */
1199 omap_dma_glbl_write(od, IRQENABLE_L0, 0);
1200 }
1201
Russell King7bedaa52012-04-13 12:10:24 +01001202 omap_dma_free(od);
1203
1204 return 0;
1205}
1206
Jon Hunter8d306622013-02-26 12:27:24 -06001207static const struct of_device_id omap_dma_match[] = {
1208 { .compatible = "ti,omap2420-sdma", },
1209 { .compatible = "ti,omap2430-sdma", },
1210 { .compatible = "ti,omap3430-sdma", },
1211 { .compatible = "ti,omap3630-sdma", },
1212 { .compatible = "ti,omap4430-sdma", },
1213 {},
1214};
1215MODULE_DEVICE_TABLE(of, omap_dma_match);
1216
Russell King7bedaa52012-04-13 12:10:24 +01001217static struct platform_driver omap_dma_driver = {
1218 .probe = omap_dma_probe,
1219 .remove = omap_dma_remove,
1220 .driver = {
1221 .name = "omap-dma-engine",
Jon Hunter8d306622013-02-26 12:27:24 -06001222 .of_match_table = of_match_ptr(omap_dma_match),
Russell King7bedaa52012-04-13 12:10:24 +01001223 },
1224};
1225
1226bool omap_dma_filter_fn(struct dma_chan *chan, void *param)
1227{
1228 if (chan->device->dev->driver == &omap_dma_driver.driver) {
Peter Ujfalusieea531e2015-04-09 12:35:52 +03001229 struct omap_dmadev *od = to_omap_dma_dev(chan->device);
Russell King7bedaa52012-04-13 12:10:24 +01001230 struct omap_chan *c = to_omap_dma_chan(chan);
1231 unsigned req = *(unsigned *)param;
1232
Peter Ujfalusieea531e2015-04-09 12:35:52 +03001233 if (req <= od->dma_requests) {
1234 c->dma_sig = req;
1235 return true;
1236 }
Russell King7bedaa52012-04-13 12:10:24 +01001237 }
1238 return false;
1239}
1240EXPORT_SYMBOL_GPL(omap_dma_filter_fn);
1241
Russell King7bedaa52012-04-13 12:10:24 +01001242static int omap_dma_init(void)
1243{
Tony Lindgrenbe1f9482013-01-11 11:24:19 -08001244 return platform_driver_register(&omap_dma_driver);
Russell King7bedaa52012-04-13 12:10:24 +01001245}
1246subsys_initcall(omap_dma_init);
1247
1248static void __exit omap_dma_exit(void)
1249{
Russell King7bedaa52012-04-13 12:10:24 +01001250 platform_driver_unregister(&omap_dma_driver);
1251}
1252module_exit(omap_dma_exit);
1253
1254MODULE_AUTHOR("Russell King");
1255MODULE_LICENSE("GPL");