Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 1 | /* |
| 2 | * pci-rcar-gen2: internal PCI bus support |
| 3 | * |
| 4 | * Copyright (C) 2013 Renesas Solutions Corp. |
| 5 | * Copyright (C) 2013 Cogent Embedded, Inc. |
| 6 | * |
Paul Gortmaker | 0b9c158 | 2016-07-02 19:13:30 -0400 | [diff] [blame^] | 7 | * Author: Valentine Barshak <valentine.barshak@cogentembedded.com> |
| 8 | * |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/delay.h> |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/io.h> |
| 18 | #include <linux/kernel.h> |
Phil Edworthy | 8d598ca | 2015-11-03 16:19:26 +0000 | [diff] [blame] | 19 | #include <linux/of_address.h> |
Lucas Stach | b9bfe1b | 2014-04-07 11:30:20 +0200 | [diff] [blame] | 20 | #include <linux/of_pci.h> |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 21 | #include <linux/pci.h> |
| 22 | #include <linux/platform_device.h> |
Valentine Barshak | fb178d8 | 2013-12-04 20:33:35 +0400 | [diff] [blame] | 23 | #include <linux/pm_runtime.h> |
Magnus Damm | 33966fd | 2014-02-18 11:11:32 +0900 | [diff] [blame] | 24 | #include <linux/sizes.h> |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 25 | #include <linux/slab.h> |
| 26 | |
| 27 | /* AHB-PCI Bridge PCI communication registers */ |
| 28 | #define RCAR_AHBPCI_PCICOM_OFFSET 0x800 |
| 29 | |
| 30 | #define RCAR_PCIAHB_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x00) |
| 31 | #define RCAR_PCIAHB_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x04) |
| 32 | #define RCAR_PCIAHB_PREFETCH0 0x0 |
| 33 | #define RCAR_PCIAHB_PREFETCH4 0x1 |
| 34 | #define RCAR_PCIAHB_PREFETCH8 0x2 |
| 35 | #define RCAR_PCIAHB_PREFETCH16 0x3 |
| 36 | |
| 37 | #define RCAR_AHBPCI_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x10) |
| 38 | #define RCAR_AHBPCI_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x14) |
| 39 | #define RCAR_AHBPCI_WIN_CTR_MEM (3 << 1) |
| 40 | #define RCAR_AHBPCI_WIN_CTR_CFG (5 << 1) |
| 41 | #define RCAR_AHBPCI_WIN1_HOST (1 << 30) |
| 42 | #define RCAR_AHBPCI_WIN1_DEVICE (1 << 31) |
| 43 | |
| 44 | #define RCAR_PCI_INT_ENABLE_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x20) |
| 45 | #define RCAR_PCI_INT_STATUS_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x24) |
Ben Dooks | 80a595d | 2014-02-18 11:11:01 +0900 | [diff] [blame] | 46 | #define RCAR_PCI_INT_SIGTABORT (1 << 0) |
| 47 | #define RCAR_PCI_INT_SIGRETABORT (1 << 1) |
| 48 | #define RCAR_PCI_INT_REMABORT (1 << 2) |
| 49 | #define RCAR_PCI_INT_PERR (1 << 3) |
| 50 | #define RCAR_PCI_INT_SIGSERR (1 << 4) |
| 51 | #define RCAR_PCI_INT_RESERR (1 << 5) |
| 52 | #define RCAR_PCI_INT_WIN1ERR (1 << 12) |
| 53 | #define RCAR_PCI_INT_WIN2ERR (1 << 13) |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 54 | #define RCAR_PCI_INT_A (1 << 16) |
| 55 | #define RCAR_PCI_INT_B (1 << 17) |
| 56 | #define RCAR_PCI_INT_PME (1 << 19) |
Ben Dooks | 80a595d | 2014-02-18 11:11:01 +0900 | [diff] [blame] | 57 | #define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT | \ |
| 58 | RCAR_PCI_INT_SIGRETABORT | \ |
| 59 | RCAR_PCI_INT_SIGRETABORT | \ |
| 60 | RCAR_PCI_INT_REMABORT | \ |
| 61 | RCAR_PCI_INT_PERR | \ |
| 62 | RCAR_PCI_INT_SIGSERR | \ |
| 63 | RCAR_PCI_INT_RESERR | \ |
| 64 | RCAR_PCI_INT_WIN1ERR | \ |
| 65 | RCAR_PCI_INT_WIN2ERR) |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 66 | |
| 67 | #define RCAR_AHB_BUS_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x30) |
| 68 | #define RCAR_AHB_BUS_MMODE_HTRANS (1 << 0) |
| 69 | #define RCAR_AHB_BUS_MMODE_BYTE_BURST (1 << 1) |
| 70 | #define RCAR_AHB_BUS_MMODE_WR_INCR (1 << 2) |
| 71 | #define RCAR_AHB_BUS_MMODE_HBUS_REQ (1 << 7) |
| 72 | #define RCAR_AHB_BUS_SMODE_READYCTR (1 << 17) |
| 73 | #define RCAR_AHB_BUS_MODE (RCAR_AHB_BUS_MMODE_HTRANS | \ |
| 74 | RCAR_AHB_BUS_MMODE_BYTE_BURST | \ |
| 75 | RCAR_AHB_BUS_MMODE_WR_INCR | \ |
| 76 | RCAR_AHB_BUS_MMODE_HBUS_REQ | \ |
| 77 | RCAR_AHB_BUS_SMODE_READYCTR) |
| 78 | |
| 79 | #define RCAR_USBCTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x34) |
| 80 | #define RCAR_USBCTR_USBH_RST (1 << 0) |
| 81 | #define RCAR_USBCTR_PCICLK_MASK (1 << 1) |
| 82 | #define RCAR_USBCTR_PLL_RST (1 << 2) |
| 83 | #define RCAR_USBCTR_DIRPD (1 << 8) |
| 84 | #define RCAR_USBCTR_PCIAHB_WIN2_EN (1 << 9) |
| 85 | #define RCAR_USBCTR_PCIAHB_WIN1_256M (0 << 10) |
| 86 | #define RCAR_USBCTR_PCIAHB_WIN1_512M (1 << 10) |
| 87 | #define RCAR_USBCTR_PCIAHB_WIN1_1G (2 << 10) |
| 88 | #define RCAR_USBCTR_PCIAHB_WIN1_2G (3 << 10) |
| 89 | #define RCAR_USBCTR_PCIAHB_WIN1_MASK (3 << 10) |
| 90 | |
| 91 | #define RCAR_PCI_ARBITER_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x40) |
| 92 | #define RCAR_PCI_ARBITER_PCIREQ0 (1 << 0) |
| 93 | #define RCAR_PCI_ARBITER_PCIREQ1 (1 << 1) |
| 94 | #define RCAR_PCI_ARBITER_PCIBP_MODE (1 << 12) |
| 95 | |
| 96 | #define RCAR_PCI_UNIT_REV_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x48) |
| 97 | |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 98 | struct rcar_pci_priv { |
Valentine Barshak | fb178d8 | 2013-12-04 20:33:35 +0400 | [diff] [blame] | 99 | struct device *dev; |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 100 | void __iomem *reg; |
| 101 | struct resource io_res; |
| 102 | struct resource mem_res; |
| 103 | struct resource *cfg_res; |
Ben Dooks | d47b62f | 2014-05-20 01:10:20 +0400 | [diff] [blame] | 104 | unsigned busnr; |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 105 | int irq; |
Magnus Damm | 33966fd | 2014-02-18 11:11:32 +0900 | [diff] [blame] | 106 | unsigned long window_size; |
Phil Edworthy | 8d598ca | 2015-11-03 16:19:26 +0000 | [diff] [blame] | 107 | unsigned long window_addr; |
| 108 | unsigned long window_pci; |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 109 | }; |
| 110 | |
| 111 | /* PCI configuration space operations */ |
| 112 | static void __iomem *rcar_pci_cfg_base(struct pci_bus *bus, unsigned int devfn, |
| 113 | int where) |
| 114 | { |
| 115 | struct pci_sys_data *sys = bus->sysdata; |
| 116 | struct rcar_pci_priv *priv = sys->private_data; |
| 117 | int slot, val; |
| 118 | |
| 119 | if (sys->busnr != bus->number || PCI_FUNC(devfn)) |
| 120 | return NULL; |
| 121 | |
| 122 | /* Only one EHCI/OHCI device built-in */ |
| 123 | slot = PCI_SLOT(devfn); |
| 124 | if (slot > 2) |
| 125 | return NULL; |
| 126 | |
Ben Dooks | e64a2a9 | 2014-02-18 11:11:11 +0900 | [diff] [blame] | 127 | /* bridge logic only has registers to 0x40 */ |
| 128 | if (slot == 0x0 && where >= 0x40) |
| 129 | return NULL; |
| 130 | |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 131 | val = slot ? RCAR_AHBPCI_WIN1_DEVICE | RCAR_AHBPCI_WIN_CTR_CFG : |
| 132 | RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG; |
| 133 | |
| 134 | iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG); |
| 135 | return priv->reg + (slot >> 1) * 0x100 + where; |
| 136 | } |
| 137 | |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 138 | /* PCI interrupt mapping */ |
Magnus Damm | 546cadd | 2014-02-18 11:11:21 +0900 | [diff] [blame] | 139 | static int rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 140 | { |
| 141 | struct pci_sys_data *sys = dev->bus->sysdata; |
| 142 | struct rcar_pci_priv *priv = sys->private_data; |
Lucas Stach | b9bfe1b | 2014-04-07 11:30:20 +0200 | [diff] [blame] | 143 | int irq; |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 144 | |
Lucas Stach | b9bfe1b | 2014-04-07 11:30:20 +0200 | [diff] [blame] | 145 | irq = of_irq_parse_and_map_pci(dev, slot, pin); |
| 146 | if (!irq) |
| 147 | irq = priv->irq; |
| 148 | |
| 149 | return irq; |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 150 | } |
| 151 | |
Ben Dooks | 80a595d | 2014-02-18 11:11:01 +0900 | [diff] [blame] | 152 | #ifdef CONFIG_PCI_DEBUG |
| 153 | /* if debug enabled, then attach an error handler irq to the bridge */ |
| 154 | |
| 155 | static irqreturn_t rcar_pci_err_irq(int irq, void *pw) |
| 156 | { |
| 157 | struct rcar_pci_priv *priv = pw; |
| 158 | u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG); |
| 159 | |
| 160 | if (status & RCAR_PCI_INT_ALLERRORS) { |
| 161 | dev_err(priv->dev, "error irq: status %08x\n", status); |
| 162 | |
| 163 | /* clear the error(s) */ |
| 164 | iowrite32(status & RCAR_PCI_INT_ALLERRORS, |
| 165 | priv->reg + RCAR_PCI_INT_STATUS_REG); |
| 166 | return IRQ_HANDLED; |
| 167 | } |
| 168 | |
| 169 | return IRQ_NONE; |
| 170 | } |
| 171 | |
| 172 | static void rcar_pci_setup_errirq(struct rcar_pci_priv *priv) |
| 173 | { |
| 174 | int ret; |
| 175 | u32 val; |
| 176 | |
| 177 | ret = devm_request_irq(priv->dev, priv->irq, rcar_pci_err_irq, |
| 178 | IRQF_SHARED, "error irq", priv); |
| 179 | if (ret) { |
| 180 | dev_err(priv->dev, "cannot claim IRQ for error handling\n"); |
| 181 | return; |
| 182 | } |
| 183 | |
| 184 | val = ioread32(priv->reg + RCAR_PCI_INT_ENABLE_REG); |
| 185 | val |= RCAR_PCI_INT_ALLERRORS; |
| 186 | iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG); |
| 187 | } |
| 188 | #else |
| 189 | static inline void rcar_pci_setup_errirq(struct rcar_pci_priv *priv) { } |
| 190 | #endif |
| 191 | |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 192 | /* PCI host controller setup */ |
Magnus Damm | 546cadd | 2014-02-18 11:11:21 +0900 | [diff] [blame] | 193 | static int rcar_pci_setup(int nr, struct pci_sys_data *sys) |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 194 | { |
| 195 | struct rcar_pci_priv *priv = sys->private_data; |
| 196 | void __iomem *reg = priv->reg; |
| 197 | u32 val; |
| 198 | |
Valentine Barshak | fb178d8 | 2013-12-04 20:33:35 +0400 | [diff] [blame] | 199 | pm_runtime_enable(priv->dev); |
| 200 | pm_runtime_get_sync(priv->dev); |
| 201 | |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 202 | val = ioread32(reg + RCAR_PCI_UNIT_REV_REG); |
Valentine Barshak | fb178d8 | 2013-12-04 20:33:35 +0400 | [diff] [blame] | 203 | dev_info(priv->dev, "PCI: bus%u revision %x\n", sys->busnr, val); |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 204 | |
| 205 | /* Disable Direct Power Down State and assert reset */ |
| 206 | val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD; |
| 207 | val |= RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST; |
| 208 | iowrite32(val, reg + RCAR_USBCTR_REG); |
| 209 | udelay(4); |
| 210 | |
Magnus Damm | 33966fd | 2014-02-18 11:11:32 +0900 | [diff] [blame] | 211 | /* De-assert reset and reset PCIAHB window1 size */ |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 212 | val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK | RCAR_USBCTR_PCICLK_MASK | |
| 213 | RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST); |
Magnus Damm | 33966fd | 2014-02-18 11:11:32 +0900 | [diff] [blame] | 214 | |
| 215 | /* Setup PCIAHB window1 size */ |
| 216 | switch (priv->window_size) { |
| 217 | case SZ_2G: |
| 218 | val |= RCAR_USBCTR_PCIAHB_WIN1_2G; |
| 219 | break; |
| 220 | case SZ_1G: |
| 221 | val |= RCAR_USBCTR_PCIAHB_WIN1_1G; |
| 222 | break; |
| 223 | case SZ_512M: |
| 224 | val |= RCAR_USBCTR_PCIAHB_WIN1_512M; |
| 225 | break; |
| 226 | default: |
| 227 | pr_warn("unknown window size %ld - defaulting to 256M\n", |
| 228 | priv->window_size); |
| 229 | priv->window_size = SZ_256M; |
| 230 | /* fall-through */ |
| 231 | case SZ_256M: |
| 232 | val |= RCAR_USBCTR_PCIAHB_WIN1_256M; |
| 233 | break; |
| 234 | } |
| 235 | iowrite32(val, reg + RCAR_USBCTR_REG); |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 236 | |
| 237 | /* Configure AHB master and slave modes */ |
| 238 | iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG); |
| 239 | |
| 240 | /* Configure PCI arbiter */ |
| 241 | val = ioread32(reg + RCAR_PCI_ARBITER_CTR_REG); |
| 242 | val |= RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 | |
| 243 | RCAR_PCI_ARBITER_PCIBP_MODE; |
| 244 | iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG); |
| 245 | |
Phil Edworthy | 8d598ca | 2015-11-03 16:19:26 +0000 | [diff] [blame] | 246 | /* PCI-AHB mapping */ |
| 247 | iowrite32(priv->window_addr | RCAR_PCIAHB_PREFETCH16, |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 248 | reg + RCAR_PCIAHB_WIN1_CTR_REG); |
| 249 | |
| 250 | /* AHB-PCI mapping: OHCI/EHCI registers */ |
| 251 | val = priv->mem_res.start | RCAR_AHBPCI_WIN_CTR_MEM; |
| 252 | iowrite32(val, reg + RCAR_AHBPCI_WIN2_CTR_REG); |
| 253 | |
| 254 | /* Enable AHB-PCI bridge PCI configuration access */ |
| 255 | iowrite32(RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG, |
| 256 | reg + RCAR_AHBPCI_WIN1_CTR_REG); |
| 257 | /* Set PCI-AHB Window1 address */ |
Phil Edworthy | 8d598ca | 2015-11-03 16:19:26 +0000 | [diff] [blame] | 258 | iowrite32(priv->window_pci | PCI_BASE_ADDRESS_MEM_PREFETCH, |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 259 | reg + PCI_BASE_ADDRESS_1); |
| 260 | /* Set AHB-PCI bridge PCI communication area address */ |
| 261 | val = priv->cfg_res->start + RCAR_AHBPCI_PCICOM_OFFSET; |
| 262 | iowrite32(val, reg + PCI_BASE_ADDRESS_0); |
| 263 | |
| 264 | val = ioread32(reg + PCI_COMMAND); |
| 265 | val |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY | |
| 266 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; |
| 267 | iowrite32(val, reg + PCI_COMMAND); |
| 268 | |
| 269 | /* Enable PCI interrupts */ |
| 270 | iowrite32(RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME, |
| 271 | reg + RCAR_PCI_INT_ENABLE_REG); |
| 272 | |
Ben Dooks | 80a595d | 2014-02-18 11:11:01 +0900 | [diff] [blame] | 273 | if (priv->irq > 0) |
| 274 | rcar_pci_setup_errirq(priv); |
| 275 | |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 276 | /* Add PCI resources */ |
| 277 | pci_add_resource(&sys->resources, &priv->io_res); |
| 278 | pci_add_resource(&sys->resources, &priv->mem_res); |
| 279 | |
Ben Dooks | d47b62f | 2014-05-20 01:10:20 +0400 | [diff] [blame] | 280 | /* Setup bus number based on platform device id / of bus-range */ |
| 281 | sys->busnr = priv->busnr; |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 282 | return 1; |
| 283 | } |
| 284 | |
| 285 | static struct pci_ops rcar_pci_ops = { |
Rob Herring | b44923b | 2015-01-09 20:34:47 -0600 | [diff] [blame] | 286 | .map_bus = rcar_pci_cfg_base, |
| 287 | .read = pci_generic_config_read, |
| 288 | .write = pci_generic_config_write, |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 289 | }; |
| 290 | |
Phil Edworthy | 8d598ca | 2015-11-03 16:19:26 +0000 | [diff] [blame] | 291 | static int pci_dma_range_parser_init(struct of_pci_range_parser *parser, |
| 292 | struct device_node *node) |
| 293 | { |
| 294 | const int na = 3, ns = 2; |
| 295 | int rlen; |
| 296 | |
| 297 | parser->node = node; |
| 298 | parser->pna = of_n_addr_cells(node); |
| 299 | parser->np = parser->pna + na + ns; |
| 300 | |
| 301 | parser->range = of_get_property(node, "dma-ranges", &rlen); |
| 302 | if (!parser->range) |
| 303 | return -ENOENT; |
| 304 | |
| 305 | parser->end = parser->range + rlen / sizeof(__be32); |
| 306 | return 0; |
| 307 | } |
| 308 | |
| 309 | static int rcar_pci_parse_map_dma_ranges(struct rcar_pci_priv *pci, |
| 310 | struct device_node *np) |
| 311 | { |
| 312 | struct of_pci_range range; |
| 313 | struct of_pci_range_parser parser; |
| 314 | int index = 0; |
| 315 | |
| 316 | /* Failure to parse is ok as we fall back to defaults */ |
| 317 | if (pci_dma_range_parser_init(&parser, np)) |
| 318 | return 0; |
| 319 | |
| 320 | /* Get the dma-ranges from DT */ |
| 321 | for_each_of_pci_range(&parser, &range) { |
| 322 | /* Hardware only allows one inbound 32-bit range */ |
| 323 | if (index) |
| 324 | return -EINVAL; |
| 325 | |
| 326 | pci->window_addr = (unsigned long)range.cpu_addr; |
| 327 | pci->window_pci = (unsigned long)range.pci_addr; |
| 328 | pci->window_size = (unsigned long)range.size; |
| 329 | |
| 330 | /* Catch HW limitations */ |
| 331 | if (!(range.flags & IORESOURCE_PREFETCH)) { |
| 332 | dev_err(pci->dev, "window must be prefetchable\n"); |
| 333 | return -EINVAL; |
| 334 | } |
| 335 | if (pci->window_addr) { |
| 336 | u32 lowaddr = 1 << (ffs(pci->window_addr) - 1); |
| 337 | |
| 338 | if (lowaddr < pci->window_size) { |
| 339 | dev_err(pci->dev, "invalid window size/addr\n"); |
| 340 | return -EINVAL; |
| 341 | } |
| 342 | } |
| 343 | index++; |
| 344 | } |
| 345 | |
| 346 | return 0; |
| 347 | } |
| 348 | |
Magnus Damm | 546cadd | 2014-02-18 11:11:21 +0900 | [diff] [blame] | 349 | static int rcar_pci_probe(struct platform_device *pdev) |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 350 | { |
| 351 | struct resource *cfg_res, *mem_res; |
| 352 | struct rcar_pci_priv *priv; |
| 353 | void __iomem *reg; |
Magnus Damm | 546cadd | 2014-02-18 11:11:21 +0900 | [diff] [blame] | 354 | struct hw_pci hw; |
| 355 | void *hw_private[1]; |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 356 | |
| 357 | cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 358 | reg = devm_ioremap_resource(&pdev->dev, cfg_res); |
Wei Yongjun | c176d1c | 2013-11-19 11:40:28 +0800 | [diff] [blame] | 359 | if (IS_ERR(reg)) |
| 360 | return PTR_ERR(reg); |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 361 | |
| 362 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
| 363 | if (!mem_res || !mem_res->start) |
| 364 | return -ENODEV; |
| 365 | |
Nobuhiro Iwamatsu | 7a27db2 | 2015-02-16 10:54:08 +0900 | [diff] [blame] | 366 | if (mem_res->start & 0xFFFF) |
| 367 | return -EINVAL; |
| 368 | |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 369 | priv = devm_kzalloc(&pdev->dev, |
| 370 | sizeof(struct rcar_pci_priv), GFP_KERNEL); |
| 371 | if (!priv) |
| 372 | return -ENOMEM; |
| 373 | |
| 374 | priv->mem_res = *mem_res; |
| 375 | /* |
| 376 | * The controller does not support/use port I/O, |
| 377 | * so setup a dummy port I/O region here. |
| 378 | */ |
| 379 | priv->io_res.start = priv->mem_res.start; |
| 380 | priv->io_res.end = priv->mem_res.end; |
| 381 | priv->io_res.flags = IORESOURCE_IO; |
| 382 | |
| 383 | priv->cfg_res = cfg_res; |
| 384 | |
| 385 | priv->irq = platform_get_irq(pdev, 0); |
| 386 | priv->reg = reg; |
Valentine Barshak | fb178d8 | 2013-12-04 20:33:35 +0400 | [diff] [blame] | 387 | priv->dev = &pdev->dev; |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 388 | |
Ben Dooks | ed65b78 | 2014-02-18 11:10:51 +0900 | [diff] [blame] | 389 | if (priv->irq < 0) { |
| 390 | dev_err(&pdev->dev, "no valid irq found\n"); |
| 391 | return priv->irq; |
| 392 | } |
| 393 | |
Phil Edworthy | 8d598ca | 2015-11-03 16:19:26 +0000 | [diff] [blame] | 394 | /* default window addr and size if not specified in DT */ |
| 395 | priv->window_addr = 0x40000000; |
| 396 | priv->window_pci = 0x40000000; |
Magnus Damm | 33966fd | 2014-02-18 11:11:32 +0900 | [diff] [blame] | 397 | priv->window_size = SZ_1G; |
| 398 | |
Ben Dooks | d47b62f | 2014-05-20 01:10:20 +0400 | [diff] [blame] | 399 | if (pdev->dev.of_node) { |
| 400 | struct resource busnr; |
| 401 | int ret; |
| 402 | |
| 403 | ret = of_pci_parse_bus_range(pdev->dev.of_node, &busnr); |
| 404 | if (ret < 0) { |
| 405 | dev_err(&pdev->dev, "failed to parse bus-range\n"); |
| 406 | return ret; |
| 407 | } |
| 408 | |
| 409 | priv->busnr = busnr.start; |
| 410 | if (busnr.end != busnr.start) |
| 411 | dev_warn(&pdev->dev, "only one bus number supported\n"); |
Phil Edworthy | 8d598ca | 2015-11-03 16:19:26 +0000 | [diff] [blame] | 412 | |
| 413 | ret = rcar_pci_parse_map_dma_ranges(priv, pdev->dev.of_node); |
| 414 | if (ret < 0) { |
| 415 | dev_err(&pdev->dev, "failed to parse dma-range\n"); |
| 416 | return ret; |
| 417 | } |
Ben Dooks | d47b62f | 2014-05-20 01:10:20 +0400 | [diff] [blame] | 418 | } else { |
| 419 | priv->busnr = pdev->id; |
| 420 | } |
| 421 | |
Magnus Damm | 546cadd | 2014-02-18 11:11:21 +0900 | [diff] [blame] | 422 | hw_private[0] = priv; |
| 423 | memset(&hw, 0, sizeof(hw)); |
| 424 | hw.nr_controllers = ARRAY_SIZE(hw_private); |
| 425 | hw.private_data = hw_private; |
| 426 | hw.map_irq = rcar_pci_map_irq; |
| 427 | hw.ops = &rcar_pci_ops; |
| 428 | hw.setup = rcar_pci_setup; |
| 429 | pci_common_init_dev(&pdev->dev, &hw); |
| 430 | return 0; |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 431 | } |
| 432 | |
Ben Dooks | d47b62f | 2014-05-20 01:10:20 +0400 | [diff] [blame] | 433 | static struct of_device_id rcar_pci_of_match[] = { |
Simon Horman | 3517652 | 2015-12-03 07:51:37 +0900 | [diff] [blame] | 434 | { .compatible = "renesas,pci-rcar-gen2", }, |
Ben Dooks | d47b62f | 2014-05-20 01:10:20 +0400 | [diff] [blame] | 435 | { .compatible = "renesas,pci-r8a7790", }, |
| 436 | { .compatible = "renesas,pci-r8a7791", }, |
Sergei Shtylyov | de24c18 | 2015-09-12 02:06:09 +0300 | [diff] [blame] | 437 | { .compatible = "renesas,pci-r8a7794", }, |
Ben Dooks | d47b62f | 2014-05-20 01:10:20 +0400 | [diff] [blame] | 438 | { }, |
| 439 | }; |
| 440 | |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 441 | static struct platform_driver rcar_pci_driver = { |
| 442 | .driver = { |
| 443 | .name = "pci-rcar-gen2", |
Magnus Damm | 546cadd | 2014-02-18 11:11:21 +0900 | [diff] [blame] | 444 | .suppress_bind_attrs = true, |
Ben Dooks | d47b62f | 2014-05-20 01:10:20 +0400 | [diff] [blame] | 445 | .of_match_table = rcar_pci_of_match, |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 446 | }, |
Magnus Damm | 546cadd | 2014-02-18 11:11:21 +0900 | [diff] [blame] | 447 | .probe = rcar_pci_probe, |
Valentine Barshak | ba3eb9f | 2013-10-29 20:12:51 +0400 | [diff] [blame] | 448 | }; |
Paul Gortmaker | 0b9c158 | 2016-07-02 19:13:30 -0400 | [diff] [blame^] | 449 | builtin_platform_driver(rcar_pci_driver); |