Erik Gilling | c5f8006 | 2010-01-21 16:53:02 -0800 | [diff] [blame] | 1 | /* |
Peter De Schrijver | c37c07d | 2011-12-14 17:03:17 +0200 | [diff] [blame] | 2 | * arch/arm/mach-tegra/common.c |
Erik Gilling | c5f8006 | 2010-01-21 16:53:02 -0800 | [diff] [blame] | 3 | * |
Olof Johansson | d2ffb91 | 2013-02-09 17:45:28 -0800 | [diff] [blame] | 4 | * Copyright (c) 2013 NVIDIA Corporation. All rights reserved. |
Erik Gilling | c5f8006 | 2010-01-21 16:53:02 -0800 | [diff] [blame] | 5 | * Copyright (C) 2010 Google, Inc. |
| 6 | * |
| 7 | * Author: |
| 8 | * Colin Cross <ccross@android.com> |
| 9 | * |
| 10 | * This software is licensed under the terms of the GNU General Public |
| 11 | * License version 2, as published by the Free Software Foundation, and |
| 12 | * may be copied, distributed, and modified under those terms. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | */ |
| 20 | |
| 21 | #include <linux/init.h> |
| 22 | #include <linux/io.h> |
Colin Cross | 4de3a8f | 2010-04-05 13:16:42 -0700 | [diff] [blame] | 23 | #include <linux/clk.h> |
| 24 | #include <linux/delay.h> |
Rob Herring | 0529e315 | 2012-11-05 16:18:28 -0600 | [diff] [blame] | 25 | #include <linux/irqchip.h> |
Prashant Gaikwad | 61fd290 | 2013-01-11 13:16:26 +0530 | [diff] [blame] | 26 | #include <linux/clk/tegra.h> |
Erik Gilling | c5f8006 | 2010-01-21 16:53:02 -0800 | [diff] [blame] | 27 | |
| 28 | #include <asm/hardware/cache-l2x0.h> |
| 29 | |
Erik Gilling | c5f8006 | 2010-01-21 16:53:02 -0800 | [diff] [blame] | 30 | #include "board.h" |
Marc Zyngier | a172573 | 2011-09-08 13:15:22 +0100 | [diff] [blame] | 31 | #include "common.h" |
Colin Cross | 73625e3 | 2010-06-23 15:49:17 -0700 | [diff] [blame] | 32 | #include "fuse.h" |
Stephen Warren | 2be39c0 | 2012-10-04 14:24:09 -0600 | [diff] [blame] | 33 | #include "iomap.h" |
Joseph Lo | e307cc8 | 2013-04-03 19:31:45 +0800 | [diff] [blame] | 34 | #include "irq.h" |
Stephen Warren | d3b8bdd | 2012-01-25 14:43:28 -0700 | [diff] [blame] | 35 | #include "pmc.h" |
Laxman Dewangan | b861c27 | 2012-06-20 18:06:34 +0530 | [diff] [blame] | 36 | #include "apbio.h" |
Joseph Lo | 59b0f68 | 2012-08-16 17:31:51 +0800 | [diff] [blame] | 37 | #include "sleep.h" |
Joseph Lo | 29a0e7b | 2012-11-13 10:04:48 +0800 | [diff] [blame] | 38 | #include "pm.h" |
Joseph Lo | 9e32366 | 2013-01-04 17:32:22 +0800 | [diff] [blame] | 39 | #include "reset.h" |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 40 | |
Stephen Warren | 6d7d7b3 | 2012-01-06 10:43:22 +0000 | [diff] [blame] | 41 | /* |
| 42 | * Storage for debug-macro.S's state. |
| 43 | * |
| 44 | * This must be in .data not .bss so that it gets initialized each time the |
| 45 | * kernel is loaded. The data is declared here rather than debug-macro.S so |
| 46 | * that multiple inclusions of debug-macro.S point at the same data. |
| 47 | */ |
Stephen Warren | 1a6d3da | 2012-10-01 15:33:20 -0600 | [diff] [blame] | 48 | u32 tegra_uart_config[4] = { |
Stephen Warren | 6d7d7b3 | 2012-01-06 10:43:22 +0000 | [diff] [blame] | 49 | /* Debug UART initialization required */ |
| 50 | 1, |
| 51 | /* Debug UART physical address */ |
Stephen Warren | adc1831 | 2012-10-01 15:21:20 -0600 | [diff] [blame] | 52 | 0, |
Stephen Warren | 6d7d7b3 | 2012-01-06 10:43:22 +0000 | [diff] [blame] | 53 | /* Debug UART virtual address */ |
Stephen Warren | adc1831 | 2012-10-01 15:21:20 -0600 | [diff] [blame] | 54 | 0, |
Stephen Warren | 1a6d3da | 2012-10-01 15:33:20 -0600 | [diff] [blame] | 55 | /* Scratch space for debug macro */ |
| 56 | 0, |
Stephen Warren | 6d7d7b3 | 2012-01-06 10:43:22 +0000 | [diff] [blame] | 57 | }; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 58 | |
Stephen Warren | 6cc04a4 | 2011-12-19 12:24:05 -0700 | [diff] [blame] | 59 | #ifdef CONFIG_OF |
Peter De Schrijver | c37c07d | 2011-12-14 17:03:17 +0200 | [diff] [blame] | 60 | void __init tegra_dt_init_irq(void) |
| 61 | { |
Prashant Gaikwad | 61fd290 | 2013-01-11 13:16:26 +0530 | [diff] [blame] | 62 | tegra_clocks_init(); |
Joseph Lo | 0337c3e | 2013-04-03 19:31:28 +0800 | [diff] [blame] | 63 | tegra_pmc_init(); |
Peter De Schrijver | c37c07d | 2011-12-14 17:03:17 +0200 | [diff] [blame] | 64 | tegra_init_irq(); |
Rob Herring | 0529e315 | 2012-11-05 16:18:28 -0600 | [diff] [blame] | 65 | irqchip_init(); |
Joseph Lo | e307cc8 | 2013-04-03 19:31:45 +0800 | [diff] [blame] | 66 | tegra_legacy_irq_syscore_init(); |
Peter De Schrijver | c37c07d | 2011-12-14 17:03:17 +0200 | [diff] [blame] | 67 | } |
Stephen Warren | 6cc04a4 | 2011-12-19 12:24:05 -0700 | [diff] [blame] | 68 | #endif |
Peter De Schrijver | c37c07d | 2011-12-14 17:03:17 +0200 | [diff] [blame] | 69 | |
Colin Cross | 699fe14 | 2010-08-23 18:37:25 -0700 | [diff] [blame] | 70 | void tegra_assert_system_reset(char mode, const char *cmd) |
| 71 | { |
Peter De Schrijver | 9bfc3f0 | 2011-12-14 17:03:19 +0200 | [diff] [blame] | 72 | void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0); |
Colin Cross | 699fe14 | 2010-08-23 18:37:25 -0700 | [diff] [blame] | 73 | u32 reg; |
| 74 | |
Simon Glass | 375b19c | 2011-02-17 08:13:57 -0800 | [diff] [blame] | 75 | reg = readl_relaxed(reset); |
Peter De Schrijver | 9bfc3f0 | 2011-12-14 17:03:19 +0200 | [diff] [blame] | 76 | reg |= 0x10; |
Simon Glass | 375b19c | 2011-02-17 08:13:57 -0800 | [diff] [blame] | 77 | writel_relaxed(reg, reset); |
Colin Cross | 699fe14 | 2010-08-23 18:37:25 -0700 | [diff] [blame] | 78 | } |
| 79 | |
Joseph Lo | d065ab7 | 2012-10-29 18:25:57 +0800 | [diff] [blame] | 80 | static void __init tegra_init_cache(void) |
Erik Gilling | c5f8006 | 2010-01-21 16:53:02 -0800 | [diff] [blame] | 81 | { |
| 82 | #ifdef CONFIG_CACHE_L2X0 |
Joseph Lo | 29a0e7b | 2012-11-13 10:04:48 +0800 | [diff] [blame] | 83 | int ret; |
Erik Gilling | c5f8006 | 2010-01-21 16:53:02 -0800 | [diff] [blame] | 84 | void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; |
Peter De Schrijver | 0154867 | 2011-12-14 17:03:20 +0200 | [diff] [blame] | 85 | u32 aux_ctrl, cache_type; |
Erik Gilling | c5f8006 | 2010-01-21 16:53:02 -0800 | [diff] [blame] | 86 | |
Peter De Schrijver | 0154867 | 2011-12-14 17:03:20 +0200 | [diff] [blame] | 87 | cache_type = readl(p + L2X0_CACHE_TYPE); |
| 88 | aux_ctrl = (cache_type & 0x700) << (17-8); |
Peter De Schrijver | fd072a8 | 2012-11-14 16:27:23 +0200 | [diff] [blame] | 89 | aux_ctrl |= 0x7C400001; |
Peter De Schrijver | 0154867 | 2011-12-14 17:03:20 +0200 | [diff] [blame] | 90 | |
Joseph Lo | 29a0e7b | 2012-11-13 10:04:48 +0800 | [diff] [blame] | 91 | ret = l2x0_of_init(aux_ctrl, 0x8200c3fe); |
| 92 | if (!ret) |
| 93 | l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs); |
Erik Gilling | c5f8006 | 2010-01-21 16:53:02 -0800 | [diff] [blame] | 94 | #endif |
Colin Cross | 4de3a8f | 2010-04-05 13:16:42 -0700 | [diff] [blame] | 95 | |
Erik Gilling | c5f8006 | 2010-01-21 16:53:02 -0800 | [diff] [blame] | 96 | } |
| 97 | |
Hiroshi Doyu | 7469688 | 2013-02-13 19:15:48 +0200 | [diff] [blame] | 98 | void __init tegra_init_early(void) |
Olof Johansson | d2ffb91 | 2013-02-09 17:45:28 -0800 | [diff] [blame] | 99 | { |
| 100 | tegra_cpu_reset_handler_init(); |
| 101 | tegra_apb_io_init(); |
| 102 | tegra_init_fuse(); |
| 103 | tegra_init_cache(); |
Olof Johansson | d2ffb91 | 2013-02-09 17:45:28 -0800 | [diff] [blame] | 104 | tegra_powergate_init(); |
Hiroshi Doyu | 7469688 | 2013-02-13 19:15:48 +0200 | [diff] [blame] | 105 | tegra_hotplug_init(); |
Olof Johansson | d2ffb91 | 2013-02-09 17:45:28 -0800 | [diff] [blame] | 106 | } |
| 107 | |
Shawn Guo | 390e0cf | 2012-05-02 17:08:06 +0800 | [diff] [blame] | 108 | void __init tegra_init_late(void) |
| 109 | { |
Joseph Lo | c8c2e60 | 2013-04-03 19:31:47 +0800 | [diff] [blame] | 110 | tegra_init_suspend(); |
Shawn Guo | 390e0cf | 2012-05-02 17:08:06 +0800 | [diff] [blame] | 111 | tegra_powergate_debugfs_init(); |
| 112 | } |