Erik Gilling | c5f8006 | 2010-01-21 16:53:02 -0800 | [diff] [blame] | 1 | /* |
Peter De Schrijver | c37c07d | 2011-12-14 17:03:17 +0200 | [diff] [blame] | 2 | * arch/arm/mach-tegra/common.c |
Erik Gilling | c5f8006 | 2010-01-21 16:53:02 -0800 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2010 Google, Inc. |
| 5 | * |
| 6 | * Author: |
| 7 | * Colin Cross <ccross@android.com> |
| 8 | * |
| 9 | * This software is licensed under the terms of the GNU General Public |
| 10 | * License version 2, as published by the Free Software Foundation, and |
| 11 | * may be copied, distributed, and modified under those terms. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | */ |
| 19 | |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/io.h> |
Colin Cross | 4de3a8f | 2010-04-05 13:16:42 -0700 | [diff] [blame] | 22 | #include <linux/clk.h> |
| 23 | #include <linux/delay.h> |
Peter De Schrijver | c37c07d | 2011-12-14 17:03:17 +0200 | [diff] [blame] | 24 | #include <linux/of_irq.h> |
Erik Gilling | c5f8006 | 2010-01-21 16:53:02 -0800 | [diff] [blame] | 25 | |
| 26 | #include <asm/hardware/cache-l2x0.h> |
Peter De Schrijver | c37c07d | 2011-12-14 17:03:17 +0200 | [diff] [blame] | 27 | #include <asm/hardware/gic.h> |
Erik Gilling | c5f8006 | 2010-01-21 16:53:02 -0800 | [diff] [blame] | 28 | |
Peter De Schrijver | 65fe31d | 2012-02-10 01:47:49 +0200 | [diff] [blame] | 29 | #include <mach/powergate.h> |
Erik Gilling | c5f8006 | 2010-01-21 16:53:02 -0800 | [diff] [blame] | 30 | |
| 31 | #include "board.h" |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 32 | #include "clock.h" |
Marc Zyngier | a172573 | 2011-09-08 13:15:22 +0100 | [diff] [blame] | 33 | #include "common.h" |
Colin Cross | 73625e3 | 2010-06-23 15:49:17 -0700 | [diff] [blame] | 34 | #include "fuse.h" |
Stephen Warren | 2be39c0 | 2012-10-04 14:24:09 -0600 | [diff] [blame] | 35 | #include "iomap.h" |
Stephen Warren | d3b8bdd | 2012-01-25 14:43:28 -0700 | [diff] [blame] | 36 | #include "pmc.h" |
Laxman Dewangan | b861c27 | 2012-06-20 18:06:34 +0530 | [diff] [blame] | 37 | #include "apbio.h" |
Joseph Lo | 59b0f68 | 2012-08-16 17:31:51 +0800 | [diff] [blame] | 38 | #include "sleep.h" |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 39 | |
Stephen Warren | 6d7d7b3 | 2012-01-06 10:43:22 +0000 | [diff] [blame] | 40 | /* |
| 41 | * Storage for debug-macro.S's state. |
| 42 | * |
| 43 | * This must be in .data not .bss so that it gets initialized each time the |
| 44 | * kernel is loaded. The data is declared here rather than debug-macro.S so |
| 45 | * that multiple inclusions of debug-macro.S point at the same data. |
| 46 | */ |
Stephen Warren | 6d7d7b3 | 2012-01-06 10:43:22 +0000 | [diff] [blame] | 47 | u32 tegra_uart_config[3] = { |
| 48 | /* Debug UART initialization required */ |
| 49 | 1, |
| 50 | /* Debug UART physical address */ |
Stephen Warren | adc1831 | 2012-10-01 15:21:20 -0600 | [diff] [blame^] | 51 | 0, |
Stephen Warren | 6d7d7b3 | 2012-01-06 10:43:22 +0000 | [diff] [blame] | 52 | /* Debug UART virtual address */ |
Stephen Warren | adc1831 | 2012-10-01 15:21:20 -0600 | [diff] [blame^] | 53 | 0, |
Stephen Warren | 6d7d7b3 | 2012-01-06 10:43:22 +0000 | [diff] [blame] | 54 | }; |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 55 | |
Stephen Warren | 6cc04a4 | 2011-12-19 12:24:05 -0700 | [diff] [blame] | 56 | #ifdef CONFIG_OF |
Peter De Schrijver | c37c07d | 2011-12-14 17:03:17 +0200 | [diff] [blame] | 57 | static const struct of_device_id tegra_dt_irq_match[] __initconst = { |
| 58 | { .compatible = "arm,cortex-a9-gic", .data = gic_of_init }, |
| 59 | { } |
| 60 | }; |
| 61 | |
| 62 | void __init tegra_dt_init_irq(void) |
| 63 | { |
| 64 | tegra_init_irq(); |
| 65 | of_irq_init(tegra_dt_irq_match); |
| 66 | } |
Stephen Warren | 6cc04a4 | 2011-12-19 12:24:05 -0700 | [diff] [blame] | 67 | #endif |
Peter De Schrijver | c37c07d | 2011-12-14 17:03:17 +0200 | [diff] [blame] | 68 | |
Colin Cross | 699fe14 | 2010-08-23 18:37:25 -0700 | [diff] [blame] | 69 | void tegra_assert_system_reset(char mode, const char *cmd) |
| 70 | { |
Peter De Schrijver | 9bfc3f0 | 2011-12-14 17:03:19 +0200 | [diff] [blame] | 71 | void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0); |
Colin Cross | 699fe14 | 2010-08-23 18:37:25 -0700 | [diff] [blame] | 72 | u32 reg; |
| 73 | |
Simon Glass | 375b19c | 2011-02-17 08:13:57 -0800 | [diff] [blame] | 74 | reg = readl_relaxed(reset); |
Peter De Schrijver | 9bfc3f0 | 2011-12-14 17:03:19 +0200 | [diff] [blame] | 75 | reg |= 0x10; |
Simon Glass | 375b19c | 2011-02-17 08:13:57 -0800 | [diff] [blame] | 76 | writel_relaxed(reg, reset); |
Colin Cross | 699fe14 | 2010-08-23 18:37:25 -0700 | [diff] [blame] | 77 | } |
| 78 | |
Peter De Schrijver | c37c07d | 2011-12-14 17:03:17 +0200 | [diff] [blame] | 79 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC |
| 80 | static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 81 | /* name parent rate enabled */ |
| 82 | { "clk_m", NULL, 0, true }, |
| 83 | { "pll_p", "clk_m", 216000000, true }, |
| 84 | { "pll_p_out1", "pll_p", 28800000, true }, |
| 85 | { "pll_p_out2", "pll_p", 48000000, true }, |
| 86 | { "pll_p_out3", "pll_p", 72000000, true }, |
Stephen Warren | 9abafa0 | 2012-04-12 14:13:05 -0600 | [diff] [blame] | 87 | { "pll_p_out4", "pll_p", 24000000, true }, |
Stephen Warren | 60f975b | 2012-04-12 14:09:39 -0600 | [diff] [blame] | 88 | { "pll_c", "clk_m", 600000000, true }, |
| 89 | { "pll_c_out1", "pll_c", 120000000, true }, |
| 90 | { "sclk", "pll_c_out1", 120000000, true }, |
| 91 | { "hclk", "sclk", 120000000, true }, |
Stephen Warren | 7ff4db0 | 2012-04-20 16:58:18 -0600 | [diff] [blame] | 92 | { "pclk", "hclk", 60000000, true }, |
Colin Cross | cd51d0e | 2011-02-21 17:05:36 -0800 | [diff] [blame] | 93 | { "csite", NULL, 0, true }, |
| 94 | { "emc", NULL, 0, true }, |
| 95 | { "cpu", NULL, 0, true }, |
Colin Cross | d861196 | 2010-01-28 16:40:29 -0800 | [diff] [blame] | 96 | { NULL, NULL, 0, 0}, |
| 97 | }; |
Peter De Schrijver | c37c07d | 2011-12-14 17:03:17 +0200 | [diff] [blame] | 98 | #endif |
Erik Gilling | c5f8006 | 2010-01-21 16:53:02 -0800 | [diff] [blame] | 99 | |
Peter De Schrijver | 6437626 | 2012-04-23 01:31:49 -0700 | [diff] [blame] | 100 | #ifdef CONFIG_ARCH_TEGRA_3x_SOC |
| 101 | static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = { |
| 102 | /* name parent rate enabled */ |
| 103 | { "clk_m", NULL, 0, true }, |
| 104 | { "pll_p", "clk_m", 408000000, true }, |
| 105 | { "pll_p_out1", "pll_p", 9600000, true }, |
Joseph Lo | d534b5d | 2012-10-29 18:25:29 +0800 | [diff] [blame] | 106 | { "pll_p_out4", "pll_p", 102000000, true }, |
| 107 | { "sclk", "pll_p_out4", 102000000, true }, |
| 108 | { "hclk", "sclk", 102000000, true }, |
| 109 | { "pclk", "hclk", 51000000, true }, |
Peter De Schrijver | 6437626 | 2012-04-23 01:31:49 -0700 | [diff] [blame] | 110 | { NULL, NULL, 0, 0}, |
| 111 | }; |
| 112 | #endif |
| 113 | |
| 114 | |
Joseph Lo | d065ab7 | 2012-10-29 18:25:57 +0800 | [diff] [blame] | 115 | static void __init tegra_init_cache(void) |
Erik Gilling | c5f8006 | 2010-01-21 16:53:02 -0800 | [diff] [blame] | 116 | { |
| 117 | #ifdef CONFIG_CACHE_L2X0 |
| 118 | void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; |
Peter De Schrijver | 0154867 | 2011-12-14 17:03:20 +0200 | [diff] [blame] | 119 | u32 aux_ctrl, cache_type; |
Erik Gilling | c5f8006 | 2010-01-21 16:53:02 -0800 | [diff] [blame] | 120 | |
Peter De Schrijver | 0154867 | 2011-12-14 17:03:20 +0200 | [diff] [blame] | 121 | cache_type = readl(p + L2X0_CACHE_TYPE); |
| 122 | aux_ctrl = (cache_type & 0x700) << (17-8); |
Peter De Schrijver | fd072a8 | 2012-11-14 16:27:23 +0200 | [diff] [blame] | 123 | aux_ctrl |= 0x7C400001; |
Peter De Schrijver | 0154867 | 2011-12-14 17:03:20 +0200 | [diff] [blame] | 124 | |
Joseph Lo | d065ab7 | 2012-10-29 18:25:57 +0800 | [diff] [blame] | 125 | l2x0_of_init(aux_ctrl, 0x8200c3fe); |
Erik Gilling | c5f8006 | 2010-01-21 16:53:02 -0800 | [diff] [blame] | 126 | #endif |
Colin Cross | 4de3a8f | 2010-04-05 13:16:42 -0700 | [diff] [blame] | 127 | |
Erik Gilling | c5f8006 | 2010-01-21 16:53:02 -0800 | [diff] [blame] | 128 | } |
| 129 | |
Peter De Schrijver | c37c07d | 2011-12-14 17:03:17 +0200 | [diff] [blame] | 130 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC |
| 131 | void __init tegra20_init_early(void) |
Erik Gilling | c5f8006 | 2010-01-21 16:53:02 -0800 | [diff] [blame] | 132 | { |
Laxman Dewangan | b861c27 | 2012-06-20 18:06:34 +0530 | [diff] [blame] | 133 | tegra_apb_io_init(); |
Colin Cross | 73625e3 | 2010-06-23 15:49:17 -0700 | [diff] [blame] | 134 | tegra_init_fuse(); |
Peter De Schrijver | c37c07d | 2011-12-14 17:03:17 +0200 | [diff] [blame] | 135 | tegra2_init_clocks(); |
| 136 | tegra_clk_init_from_table(tegra20_clk_init_table); |
Joseph Lo | d065ab7 | 2012-10-29 18:25:57 +0800 | [diff] [blame] | 137 | tegra_init_cache(); |
Stephen Warren | d3b8bdd | 2012-01-25 14:43:28 -0700 | [diff] [blame] | 138 | tegra_pmc_init(); |
Peter De Schrijver | 65fe31d | 2012-02-10 01:47:49 +0200 | [diff] [blame] | 139 | tegra_powergate_init(); |
Joseph Lo | 453689e | 2012-08-16 17:31:52 +0800 | [diff] [blame] | 140 | tegra20_hotplug_init(); |
Erik Gilling | c5f8006 | 2010-01-21 16:53:02 -0800 | [diff] [blame] | 141 | } |
Peter De Schrijver | c37c07d | 2011-12-14 17:03:17 +0200 | [diff] [blame] | 142 | #endif |
Peter De Schrijver | 44107d8 | 2011-12-14 17:03:25 +0200 | [diff] [blame] | 143 | #ifdef CONFIG_ARCH_TEGRA_3x_SOC |
| 144 | void __init tegra30_init_early(void) |
| 145 | { |
Laxman Dewangan | b861c27 | 2012-06-20 18:06:34 +0530 | [diff] [blame] | 146 | tegra_apb_io_init(); |
Peter De Schrijver | cec6006 | 2012-02-10 01:47:43 +0200 | [diff] [blame] | 147 | tegra_init_fuse(); |
Peter De Schrijver | 7ff43ee | 2012-01-09 05:35:13 +0000 | [diff] [blame] | 148 | tegra30_init_clocks(); |
Peter De Schrijver | 6437626 | 2012-04-23 01:31:49 -0700 | [diff] [blame] | 149 | tegra_clk_init_from_table(tegra30_clk_init_table); |
Joseph Lo | d065ab7 | 2012-10-29 18:25:57 +0800 | [diff] [blame] | 150 | tegra_init_cache(); |
Stephen Warren | d3b8bdd | 2012-01-25 14:43:28 -0700 | [diff] [blame] | 151 | tegra_pmc_init(); |
Peter De Schrijver | 65fe31d | 2012-02-10 01:47:49 +0200 | [diff] [blame] | 152 | tegra_powergate_init(); |
Joseph Lo | 59b0f68 | 2012-08-16 17:31:51 +0800 | [diff] [blame] | 153 | tegra30_hotplug_init(); |
Peter De Schrijver | 44107d8 | 2011-12-14 17:03:25 +0200 | [diff] [blame] | 154 | } |
| 155 | #endif |
Shawn Guo | 390e0cf | 2012-05-02 17:08:06 +0800 | [diff] [blame] | 156 | |
| 157 | void __init tegra_init_late(void) |
| 158 | { |
Shawn Guo | 390e0cf | 2012-05-02 17:08:06 +0800 | [diff] [blame] | 159 | tegra_powergate_debugfs_init(); |
| 160 | } |