Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 27 | * Christian König |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 28 | */ |
| 29 | #include <linux/seq_file.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 30 | #include <linux/slab.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 31 | #include <drm/drmP.h> |
| 32 | #include <drm/radeon_drm.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 33 | #include "radeon_reg.h" |
| 34 | #include "radeon.h" |
| 35 | #include "atom.h" |
| 36 | |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 37 | /* |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 38 | * IB |
| 39 | * IBs (Indirect Buffers) and areas of GPU accessible memory where |
| 40 | * commands are stored. You can put a pointer to the IB in the |
| 41 | * command ring and the hw will fetch the commands from the IB |
| 42 | * and execute them. Generally userspace acceleration drivers |
| 43 | * produce command buffers which are send to the kernel and |
| 44 | * put in IBs for execution by the requested ring. |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 45 | */ |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 46 | static int radeon_debugfs_sa_init(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 47 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 48 | /** |
| 49 | * radeon_ib_get - request an IB (Indirect Buffer) |
| 50 | * |
| 51 | * @rdev: radeon_device pointer |
| 52 | * @ring: ring index the IB is associated with |
| 53 | * @ib: IB object returned |
| 54 | * @size: requested IB size |
| 55 | * |
| 56 | * Request an IB (all asics). IBs are allocated using the |
| 57 | * suballocator. |
| 58 | * Returns 0 on success, error on failure. |
| 59 | */ |
Jerome Glisse | 69e130a | 2011-12-21 12:13:46 -0500 | [diff] [blame] | 60 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
Christian König | 4bf3dd9 | 2012-08-06 18:57:44 +0200 | [diff] [blame] | 61 | struct radeon_ib *ib, struct radeon_vm *vm, |
| 62 | unsigned size) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 63 | { |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 64 | int i, r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 65 | |
Jerome Glisse | f2e3922 | 2012-05-09 15:35:02 +0200 | [diff] [blame] | 66 | r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256, true); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 67 | if (r) { |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 68 | dev_err(rdev->dev, "failed to get a new IB (%d)\n", r); |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 69 | return r; |
| 70 | } |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 71 | |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 72 | r = radeon_semaphore_create(rdev, &ib->semaphore); |
| 73 | if (r) { |
| 74 | return r; |
| 75 | } |
| 76 | |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 77 | ib->ring = ring; |
| 78 | ib->fence = NULL; |
Jerome Glisse | f2e3922 | 2012-05-09 15:35:02 +0200 | [diff] [blame] | 79 | ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo); |
Christian König | 4bf3dd9 | 2012-08-06 18:57:44 +0200 | [diff] [blame] | 80 | ib->vm = vm; |
| 81 | if (vm) { |
Christian König | ca19f21 | 2012-09-11 16:09:59 +0200 | [diff] [blame] | 82 | /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address |
| 83 | * space and soffset is the offset inside the pool bo |
Christian König | 4bf3dd9 | 2012-08-06 18:57:44 +0200 | [diff] [blame] | 84 | */ |
Christian König | ca19f21 | 2012-09-11 16:09:59 +0200 | [diff] [blame] | 85 | ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET; |
Christian König | 4bf3dd9 | 2012-08-06 18:57:44 +0200 | [diff] [blame] | 86 | } else { |
| 87 | ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo); |
| 88 | } |
Jerome Glisse | f2e3922 | 2012-05-09 15:35:02 +0200 | [diff] [blame] | 89 | ib->is_const_ib = false; |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 90 | for (i = 0; i < RADEON_NUM_RINGS; ++i) |
| 91 | ib->sync_to[i] = NULL; |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 92 | |
| 93 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 94 | } |
| 95 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 96 | /** |
| 97 | * radeon_ib_free - free an IB (Indirect Buffer) |
| 98 | * |
| 99 | * @rdev: radeon_device pointer |
| 100 | * @ib: IB object to free |
| 101 | * |
| 102 | * Free an IB (all asics). |
| 103 | */ |
Jerome Glisse | f2e3922 | 2012-05-09 15:35:02 +0200 | [diff] [blame] | 104 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 105 | { |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 106 | radeon_semaphore_free(rdev, &ib->semaphore, ib->fence); |
Jerome Glisse | f2e3922 | 2012-05-09 15:35:02 +0200 | [diff] [blame] | 107 | radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence); |
| 108 | radeon_fence_unref(&ib->fence); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 109 | } |
| 110 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 111 | /** |
| 112 | * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring |
| 113 | * |
| 114 | * @rdev: radeon_device pointer |
| 115 | * @ib: IB object to schedule |
| 116 | * @const_ib: Const IB to schedule (SI only) |
| 117 | * |
| 118 | * Schedule an IB on the associated ring (all asics). |
| 119 | * Returns 0 on success, error on failure. |
| 120 | * |
| 121 | * On SI, there are two parallel engines fed from the primary ring, |
| 122 | * the CE (Constant Engine) and the DE (Drawing Engine). Since |
| 123 | * resource descriptors have moved to memory, the CE allows you to |
| 124 | * prime the caches while the DE is updating register state so that |
| 125 | * the resource descriptors will be already in cache when the draw is |
| 126 | * processed. To accomplish this, the userspace driver submits two |
| 127 | * IBs, one for the CE and one for the DE. If there is a CE IB (called |
| 128 | * a CONST_IB), it will be put on the ring prior to the DE IB. Prior |
| 129 | * to SI there was just a DE IB. |
| 130 | */ |
Christian König | 4ef7256 | 2012-07-13 13:06:00 +0200 | [diff] [blame] | 131 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
| 132 | struct radeon_ib *const_ib) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 133 | { |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 134 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 135 | bool need_sync = false; |
| 136 | int i, r = 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 137 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 138 | if (!ib->length_dw || !ring->ready) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 139 | /* TODO: Nothings in the ib we should report. */ |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 140 | dev_err(rdev->dev, "couldn't schedule ib\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 141 | return -EINVAL; |
| 142 | } |
Dave Airlie | ecb114a | 2009-09-15 11:12:56 +1000 | [diff] [blame] | 143 | |
Dave Airlie | 6cdf658 | 2009-06-29 18:29:13 +1000 | [diff] [blame] | 144 | /* 64 dwords should be enough for fence too */ |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 145 | r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_RINGS * 8); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 146 | if (r) { |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 147 | dev_err(rdev->dev, "scheduling IB failed (%d).\n", r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 148 | return r; |
| 149 | } |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 150 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
| 151 | struct radeon_fence *fence = ib->sync_to[i]; |
| 152 | if (radeon_fence_need_sync(fence, ib->ring)) { |
| 153 | need_sync = true; |
| 154 | radeon_semaphore_sync_rings(rdev, ib->semaphore, |
| 155 | fence->ring, ib->ring); |
| 156 | radeon_fence_note_sync(fence, ib->ring); |
| 157 | } |
| 158 | } |
| 159 | /* immediately free semaphore when we don't need to sync */ |
| 160 | if (!need_sync) { |
| 161 | radeon_semaphore_free(rdev, &ib->semaphore, NULL); |
| 162 | } |
Christian König | 9b40e5d | 2012-08-08 12:22:43 +0200 | [diff] [blame] | 163 | /* if we can't remember our last VM flush then flush now! */ |
| 164 | if (ib->vm && !ib->vm->last_flush) { |
Alex Deucher | 498522b | 2012-10-02 14:43:38 -0400 | [diff] [blame] | 165 | radeon_ring_vm_flush(rdev, ib->ring, ib->vm); |
Christian König | 9b40e5d | 2012-08-08 12:22:43 +0200 | [diff] [blame] | 166 | } |
Christian König | 4ef7256 | 2012-07-13 13:06:00 +0200 | [diff] [blame] | 167 | if (const_ib) { |
| 168 | radeon_ring_ib_execute(rdev, const_ib->ring, const_ib); |
| 169 | radeon_semaphore_free(rdev, &const_ib->semaphore, NULL); |
| 170 | } |
Christian König | 876dc9f | 2012-05-08 14:24:01 +0200 | [diff] [blame] | 171 | radeon_ring_ib_execute(rdev, ib->ring, ib); |
| 172 | r = radeon_fence_emit(rdev, &ib->fence, ib->ring); |
| 173 | if (r) { |
| 174 | dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r); |
| 175 | radeon_ring_unlock_undo(rdev, ring); |
| 176 | return r; |
| 177 | } |
Christian König | 4ef7256 | 2012-07-13 13:06:00 +0200 | [diff] [blame] | 178 | if (const_ib) { |
| 179 | const_ib->fence = radeon_fence_ref(ib->fence); |
| 180 | } |
Christian König | 9b40e5d | 2012-08-08 12:22:43 +0200 | [diff] [blame] | 181 | /* we just flushed the VM, remember that */ |
| 182 | if (ib->vm && !ib->vm->last_flush) { |
| 183 | ib->vm->last_flush = radeon_fence_ref(ib->fence); |
| 184 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 185 | radeon_ring_unlock_commit(rdev, ring); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 186 | return 0; |
| 187 | } |
| 188 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 189 | /** |
| 190 | * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool |
| 191 | * |
| 192 | * @rdev: radeon_device pointer |
| 193 | * |
| 194 | * Initialize the suballocator to manage a pool of memory |
| 195 | * for use as IBs (all asics). |
| 196 | * Returns 0 on success, error on failure. |
| 197 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 198 | int radeon_ib_pool_init(struct radeon_device *rdev) |
| 199 | { |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 200 | int r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 201 | |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 202 | if (rdev->ib_pool_ready) { |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 203 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 204 | } |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 205 | r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo, |
Christian König | c3b7fe8 | 2012-05-09 15:34:56 +0200 | [diff] [blame] | 206 | RADEON_IB_POOL_SIZE*64*1024, |
| 207 | RADEON_GEM_DOMAIN_GTT); |
| 208 | if (r) { |
Christian König | c3b7fe8 | 2012-05-09 15:34:56 +0200 | [diff] [blame] | 209 | return r; |
| 210 | } |
Christian König | 2898c34 | 2012-07-05 11:55:34 +0200 | [diff] [blame] | 211 | |
| 212 | r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo); |
| 213 | if (r) { |
| 214 | return r; |
| 215 | } |
| 216 | |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 217 | rdev->ib_pool_ready = true; |
| 218 | if (radeon_debugfs_sa_init(rdev)) { |
| 219 | dev_err(rdev->dev, "failed to register debugfs file for SA\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 220 | } |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 221 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 222 | } |
| 223 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 224 | /** |
| 225 | * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool |
| 226 | * |
| 227 | * @rdev: radeon_device pointer |
| 228 | * |
| 229 | * Tear down the suballocator managing the pool of memory |
| 230 | * for use as IBs (all asics). |
| 231 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 232 | void radeon_ib_pool_fini(struct radeon_device *rdev) |
| 233 | { |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 234 | if (rdev->ib_pool_ready) { |
Christian König | 2898c34 | 2012-07-05 11:55:34 +0200 | [diff] [blame] | 235 | radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo); |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 236 | radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo); |
| 237 | rdev->ib_pool_ready = false; |
Alex Deucher | ca2af92 | 2010-05-06 11:02:24 -0400 | [diff] [blame] | 238 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 239 | } |
| 240 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 241 | /** |
| 242 | * radeon_ib_ring_tests - test IBs on the rings |
| 243 | * |
| 244 | * @rdev: radeon_device pointer |
| 245 | * |
| 246 | * Test an IB (Indirect Buffer) on each ring. |
| 247 | * If the test fails, disable the ring. |
| 248 | * Returns 0 on success, error if the primary GFX ring |
| 249 | * IB test fails. |
| 250 | */ |
Christian König | 7bd560e | 2012-05-02 15:11:12 +0200 | [diff] [blame] | 251 | int radeon_ib_ring_tests(struct radeon_device *rdev) |
| 252 | { |
| 253 | unsigned i; |
| 254 | int r; |
| 255 | |
| 256 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
| 257 | struct radeon_ring *ring = &rdev->ring[i]; |
| 258 | |
| 259 | if (!ring->ready) |
| 260 | continue; |
| 261 | |
| 262 | r = radeon_ib_test(rdev, i, ring); |
| 263 | if (r) { |
| 264 | ring->ready = false; |
| 265 | |
| 266 | if (i == RADEON_RING_TYPE_GFX_INDEX) { |
| 267 | /* oh, oh, that's really bad */ |
| 268 | DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r); |
| 269 | rdev->accel_working = false; |
| 270 | return r; |
| 271 | |
| 272 | } else { |
| 273 | /* still not good, but we can live with it */ |
| 274 | DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r); |
| 275 | } |
| 276 | } |
| 277 | } |
| 278 | return 0; |
| 279 | } |
| 280 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 281 | /* |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 282 | * Rings |
| 283 | * Most engines on the GPU are fed via ring buffers. Ring |
| 284 | * buffers are areas of GPU accessible memory that the host |
| 285 | * writes commands into and the GPU reads commands out of. |
| 286 | * There is a rptr (read pointer) that determines where the |
| 287 | * GPU is currently reading, and a wptr (write pointer) |
| 288 | * which determines where the host has written. When the |
| 289 | * pointers are equal, the ring is idle. When the host |
| 290 | * writes commands to the ring buffer, it increments the |
| 291 | * wptr. The GPU then starts fetching commands and executes |
| 292 | * them until the pointers are equal again. |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 293 | */ |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 294 | static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring); |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 295 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 296 | /** |
| 297 | * radeon_ring_write - write a value to the ring |
| 298 | * |
| 299 | * @ring: radeon_ring structure holding ring information |
| 300 | * @v: dword (dw) value to write |
| 301 | * |
| 302 | * Write a value to the requested ring buffer (all asics). |
| 303 | */ |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 304 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
| 305 | { |
| 306 | #if DRM_DEBUG_CODE |
| 307 | if (ring->count_dw <= 0) { |
Thomas Friebel | 8ad33cd | 2012-10-15 13:16:22 -0400 | [diff] [blame] | 308 | DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 309 | } |
| 310 | #endif |
| 311 | ring->ring[ring->wptr++] = v; |
| 312 | ring->wptr &= ring->ptr_mask; |
| 313 | ring->count_dw--; |
| 314 | ring->ring_free_dw--; |
| 315 | } |
| 316 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 317 | /** |
| 318 | * radeon_ring_supports_scratch_reg - check if the ring supports |
| 319 | * writing to scratch registers |
| 320 | * |
| 321 | * @rdev: radeon_device pointer |
| 322 | * @ring: radeon_ring structure holding ring information |
| 323 | * |
| 324 | * Check if a specific ring supports writing to scratch registers (all asics). |
| 325 | * Returns true if the ring supports writing to scratch regs, false if not. |
| 326 | */ |
Alex Deucher | 89d3580 | 2012-07-17 14:02:31 -0400 | [diff] [blame] | 327 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
| 328 | struct radeon_ring *ring) |
| 329 | { |
| 330 | switch (ring->idx) { |
| 331 | case RADEON_RING_TYPE_GFX_INDEX: |
| 332 | case CAYMAN_RING_TYPE_CP1_INDEX: |
| 333 | case CAYMAN_RING_TYPE_CP2_INDEX: |
| 334 | return true; |
| 335 | default: |
| 336 | return false; |
| 337 | } |
| 338 | } |
| 339 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 340 | /** |
| 341 | * radeon_ring_free_size - update the free size |
| 342 | * |
| 343 | * @rdev: radeon_device pointer |
| 344 | * @ring: radeon_ring structure holding ring information |
| 345 | * |
| 346 | * Update the free dw slots in the ring buffer (all asics). |
| 347 | */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 348 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 349 | { |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 350 | u32 rptr; |
| 351 | |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 352 | if (rdev->wb.enabled) |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 353 | rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); |
Christian König | 5596a9d | 2011-10-13 12:48:45 +0200 | [diff] [blame] | 354 | else |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 355 | rptr = RREG32(ring->rptr_reg); |
| 356 | ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 357 | /* This works because ring_size is a power of 2 */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 358 | ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4)); |
| 359 | ring->ring_free_dw -= ring->wptr; |
| 360 | ring->ring_free_dw &= ring->ptr_mask; |
| 361 | if (!ring->ring_free_dw) { |
| 362 | ring->ring_free_dw = ring->ring_size / 4; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 363 | } |
| 364 | } |
| 365 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 366 | /** |
| 367 | * radeon_ring_alloc - allocate space on the ring buffer |
| 368 | * |
| 369 | * @rdev: radeon_device pointer |
| 370 | * @ring: radeon_ring structure holding ring information |
| 371 | * @ndw: number of dwords to allocate in the ring buffer |
| 372 | * |
| 373 | * Allocate @ndw dwords in the ring buffer (all asics). |
| 374 | * Returns 0 on success, error on failure. |
| 375 | */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 376 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 377 | { |
| 378 | int r; |
| 379 | |
Alex Deucher | fd5d93a | 2013-01-30 14:24:09 -0500 | [diff] [blame] | 380 | /* make sure we aren't trying to allocate more space than there is on the ring */ |
| 381 | if (ndw > (ring->ring_size / 4)) |
| 382 | return -ENOMEM; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 383 | /* Align requested size with padding so unlock_commit can |
| 384 | * pad safely */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 385 | ndw = (ndw + ring->align_mask) & ~ring->align_mask; |
| 386 | while (ndw > (ring->ring_free_dw - 1)) { |
| 387 | radeon_ring_free_size(rdev, ring); |
| 388 | if (ndw < ring->ring_free_dw) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 389 | break; |
| 390 | } |
Alex Deucher | 8b25ed3 | 2012-07-17 14:02:30 -0400 | [diff] [blame] | 391 | r = radeon_fence_wait_next_locked(rdev, ring->idx); |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 392 | if (r) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 393 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 394 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 395 | ring->count_dw = ndw; |
| 396 | ring->wptr_old = ring->wptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 397 | return 0; |
| 398 | } |
| 399 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 400 | /** |
| 401 | * radeon_ring_lock - lock the ring and allocate space on it |
| 402 | * |
| 403 | * @rdev: radeon_device pointer |
| 404 | * @ring: radeon_ring structure holding ring information |
| 405 | * @ndw: number of dwords to allocate in the ring buffer |
| 406 | * |
| 407 | * Lock the ring and allocate @ndw dwords in the ring buffer |
| 408 | * (all asics). |
| 409 | * Returns 0 on success, error on failure. |
| 410 | */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 411 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw) |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 412 | { |
| 413 | int r; |
| 414 | |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 415 | mutex_lock(&rdev->ring_lock); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 416 | r = radeon_ring_alloc(rdev, ring, ndw); |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 417 | if (r) { |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 418 | mutex_unlock(&rdev->ring_lock); |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 419 | return r; |
| 420 | } |
| 421 | return 0; |
| 422 | } |
| 423 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 424 | /** |
| 425 | * radeon_ring_commit - tell the GPU to execute the new |
| 426 | * commands on the ring buffer |
| 427 | * |
| 428 | * @rdev: radeon_device pointer |
| 429 | * @ring: radeon_ring structure holding ring information |
| 430 | * |
| 431 | * Update the wptr (write pointer) to tell the GPU to |
| 432 | * execute new commands on the ring buffer (all asics). |
| 433 | */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 434 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 435 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 436 | /* We pad to match fetch size */ |
Christian König | 07a7133 | 2012-07-07 12:11:32 +0200 | [diff] [blame] | 437 | while (ring->wptr & ring->align_mask) { |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 438 | radeon_ring_write(ring, ring->nop); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 439 | } |
| 440 | DRM_MEMORYBARRIER(); |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 441 | WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 442 | (void)RREG32(ring->wptr_reg); |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 443 | } |
| 444 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 445 | /** |
| 446 | * radeon_ring_unlock_commit - tell the GPU to execute the new |
| 447 | * commands on the ring buffer and unlock it |
| 448 | * |
| 449 | * @rdev: radeon_device pointer |
| 450 | * @ring: radeon_ring structure holding ring information |
| 451 | * |
| 452 | * Call radeon_ring_commit() then unlock the ring (all asics). |
| 453 | */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 454 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring) |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 455 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 456 | radeon_ring_commit(rdev, ring); |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 457 | mutex_unlock(&rdev->ring_lock); |
| 458 | } |
| 459 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 460 | /** |
| 461 | * radeon_ring_undo - reset the wptr |
| 462 | * |
| 463 | * @ring: radeon_ring structure holding ring information |
| 464 | * |
Paul Bolle | 501f9d4c | 2012-11-20 22:31:06 +0100 | [diff] [blame] | 465 | * Reset the driver's copy of the wptr (all asics). |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 466 | */ |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 467 | void radeon_ring_undo(struct radeon_ring *ring) |
| 468 | { |
| 469 | ring->wptr = ring->wptr_old; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 470 | } |
| 471 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 472 | /** |
| 473 | * radeon_ring_unlock_undo - reset the wptr and unlock the ring |
| 474 | * |
| 475 | * @ring: radeon_ring structure holding ring information |
| 476 | * |
| 477 | * Call radeon_ring_undo() then unlock the ring (all asics). |
| 478 | */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 479 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 480 | { |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 481 | radeon_ring_undo(ring); |
| 482 | mutex_unlock(&rdev->ring_lock); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 483 | } |
| 484 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 485 | /** |
| 486 | * radeon_ring_force_activity - add some nop packets to the ring |
| 487 | * |
| 488 | * @rdev: radeon_device pointer |
| 489 | * @ring: radeon_ring structure holding ring information |
| 490 | * |
| 491 | * Add some nop packets to the ring to force activity (all asics). |
| 492 | * Used for lockup detection to see if the rptr is advancing. |
| 493 | */ |
Christian König | 7b9ef16 | 2012-05-02 15:11:23 +0200 | [diff] [blame] | 494 | void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring) |
| 495 | { |
| 496 | int r; |
| 497 | |
Christian König | 7b9ef16 | 2012-05-02 15:11:23 +0200 | [diff] [blame] | 498 | radeon_ring_free_size(rdev, ring); |
| 499 | if (ring->rptr == ring->wptr) { |
| 500 | r = radeon_ring_alloc(rdev, ring, 1); |
| 501 | if (!r) { |
| 502 | radeon_ring_write(ring, ring->nop); |
| 503 | radeon_ring_commit(rdev, ring); |
| 504 | } |
| 505 | } |
Christian König | 7b9ef16 | 2012-05-02 15:11:23 +0200 | [diff] [blame] | 506 | } |
| 507 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 508 | /** |
Paul Bolle | 501f9d4c | 2012-11-20 22:31:06 +0100 | [diff] [blame] | 509 | * radeon_ring_lockup_update - update lockup variables |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 510 | * |
| 511 | * @ring: radeon_ring structure holding ring information |
| 512 | * |
| 513 | * Update the last rptr value and timestamp (all asics). |
| 514 | */ |
Christian König | 069211e | 2012-05-02 15:11:20 +0200 | [diff] [blame] | 515 | void radeon_ring_lockup_update(struct radeon_ring *ring) |
| 516 | { |
| 517 | ring->last_rptr = ring->rptr; |
| 518 | ring->last_activity = jiffies; |
| 519 | } |
| 520 | |
| 521 | /** |
| 522 | * radeon_ring_test_lockup() - check if ring is lockedup by recording information |
| 523 | * @rdev: radeon device structure |
| 524 | * @ring: radeon_ring structure holding ring information |
| 525 | * |
| 526 | * We don't need to initialize the lockup tracking information as we will either |
| 527 | * have CP rptr to a different value of jiffies wrap around which will force |
| 528 | * initialization of the lockup tracking informations. |
| 529 | * |
| 530 | * A possible false positivie is if we get call after while and last_cp_rptr == |
| 531 | * the current CP rptr, even if it's unlikely it might happen. To avoid this |
| 532 | * if the elapsed time since last call is bigger than 2 second than we return |
| 533 | * false and update the tracking information. Due to this the caller must call |
| 534 | * radeon_ring_test_lockup several time in less than 2sec for lockup to be reported |
| 535 | * the fencing code should be cautious about that. |
| 536 | * |
| 537 | * Caller should write to the ring to force CP to do something so we don't get |
| 538 | * false positive when CP is just gived nothing to do. |
| 539 | * |
| 540 | **/ |
| 541 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
| 542 | { |
| 543 | unsigned long cjiffies, elapsed; |
| 544 | uint32_t rptr; |
| 545 | |
| 546 | cjiffies = jiffies; |
| 547 | if (!time_after(cjiffies, ring->last_activity)) { |
| 548 | /* likely a wrap around */ |
| 549 | radeon_ring_lockup_update(ring); |
| 550 | return false; |
| 551 | } |
| 552 | rptr = RREG32(ring->rptr_reg); |
| 553 | ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; |
| 554 | if (ring->rptr != ring->last_rptr) { |
| 555 | /* CP is still working no lockup */ |
| 556 | radeon_ring_lockup_update(ring); |
| 557 | return false; |
| 558 | } |
| 559 | elapsed = jiffies_to_msecs(cjiffies - ring->last_activity); |
Christian König | 3368ff0 | 2012-05-02 15:11:21 +0200 | [diff] [blame] | 560 | if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) { |
Christian König | 069211e | 2012-05-02 15:11:20 +0200 | [diff] [blame] | 561 | dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); |
| 562 | return true; |
| 563 | } |
| 564 | /* give a chance to the GPU ... */ |
| 565 | return false; |
| 566 | } |
| 567 | |
Christian König | 55d7c22 | 2012-07-09 11:52:44 +0200 | [diff] [blame] | 568 | /** |
| 569 | * radeon_ring_backup - Back up the content of a ring |
| 570 | * |
| 571 | * @rdev: radeon_device pointer |
| 572 | * @ring: the ring we want to back up |
| 573 | * |
| 574 | * Saves all unprocessed commits from a ring, returns the number of dwords saved. |
| 575 | */ |
| 576 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, |
| 577 | uint32_t **data) |
| 578 | { |
| 579 | unsigned size, ptr, i; |
Christian König | 55d7c22 | 2012-07-09 11:52:44 +0200 | [diff] [blame] | 580 | |
| 581 | /* just in case lock the ring */ |
| 582 | mutex_lock(&rdev->ring_lock); |
| 583 | *data = NULL; |
| 584 | |
Alex Deucher | 89d3580 | 2012-07-17 14:02:31 -0400 | [diff] [blame] | 585 | if (ring->ring_obj == NULL) { |
Christian König | 55d7c22 | 2012-07-09 11:52:44 +0200 | [diff] [blame] | 586 | mutex_unlock(&rdev->ring_lock); |
| 587 | return 0; |
| 588 | } |
| 589 | |
| 590 | /* it doesn't make sense to save anything if all fences are signaled */ |
Alex Deucher | 8b25ed3 | 2012-07-17 14:02:30 -0400 | [diff] [blame] | 591 | if (!radeon_fence_count_emitted(rdev, ring->idx)) { |
Christian König | 55d7c22 | 2012-07-09 11:52:44 +0200 | [diff] [blame] | 592 | mutex_unlock(&rdev->ring_lock); |
| 593 | return 0; |
| 594 | } |
| 595 | |
| 596 | /* calculate the number of dw on the ring */ |
Alex Deucher | 89d3580 | 2012-07-17 14:02:31 -0400 | [diff] [blame] | 597 | if (ring->rptr_save_reg) |
| 598 | ptr = RREG32(ring->rptr_save_reg); |
| 599 | else if (rdev->wb.enabled) |
| 600 | ptr = le32_to_cpu(*ring->next_rptr_cpu_addr); |
| 601 | else { |
| 602 | /* no way to read back the next rptr */ |
| 603 | mutex_unlock(&rdev->ring_lock); |
| 604 | return 0; |
| 605 | } |
| 606 | |
Christian König | 55d7c22 | 2012-07-09 11:52:44 +0200 | [diff] [blame] | 607 | size = ring->wptr + (ring->ring_size / 4); |
| 608 | size -= ptr; |
| 609 | size &= ring->ptr_mask; |
| 610 | if (size == 0) { |
| 611 | mutex_unlock(&rdev->ring_lock); |
| 612 | return 0; |
| 613 | } |
| 614 | |
| 615 | /* and then save the content of the ring */ |
Dan Carpenter | 1e179d4 | 2012-07-20 14:17:00 +0300 | [diff] [blame] | 616 | *data = kmalloc_array(size, sizeof(uint32_t), GFP_KERNEL); |
| 617 | if (!*data) { |
| 618 | mutex_unlock(&rdev->ring_lock); |
| 619 | return 0; |
| 620 | } |
Christian König | 55d7c22 | 2012-07-09 11:52:44 +0200 | [diff] [blame] | 621 | for (i = 0; i < size; ++i) { |
| 622 | (*data)[i] = ring->ring[ptr++]; |
| 623 | ptr &= ring->ptr_mask; |
| 624 | } |
| 625 | |
| 626 | mutex_unlock(&rdev->ring_lock); |
| 627 | return size; |
| 628 | } |
| 629 | |
| 630 | /** |
| 631 | * radeon_ring_restore - append saved commands to the ring again |
| 632 | * |
| 633 | * @rdev: radeon_device pointer |
| 634 | * @ring: ring to append commands to |
| 635 | * @size: number of dwords we want to write |
| 636 | * @data: saved commands |
| 637 | * |
| 638 | * Allocates space on the ring and restore the previously saved commands. |
| 639 | */ |
| 640 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, |
| 641 | unsigned size, uint32_t *data) |
| 642 | { |
| 643 | int i, r; |
| 644 | |
| 645 | if (!size || !data) |
| 646 | return 0; |
| 647 | |
| 648 | /* restore the saved ring content */ |
| 649 | r = radeon_ring_lock(rdev, ring, size); |
| 650 | if (r) |
| 651 | return r; |
| 652 | |
| 653 | for (i = 0; i < size; ++i) { |
| 654 | radeon_ring_write(ring, data[i]); |
| 655 | } |
| 656 | |
| 657 | radeon_ring_unlock_commit(rdev, ring); |
| 658 | kfree(data); |
| 659 | return 0; |
| 660 | } |
| 661 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 662 | /** |
| 663 | * radeon_ring_init - init driver ring struct. |
| 664 | * |
| 665 | * @rdev: radeon_device pointer |
| 666 | * @ring: radeon_ring structure holding ring information |
| 667 | * @ring_size: size of the ring |
| 668 | * @rptr_offs: offset of the rptr writeback location in the WB buffer |
| 669 | * @rptr_reg: MMIO offset of the rptr register |
| 670 | * @wptr_reg: MMIO offset of the wptr register |
| 671 | * @ptr_reg_shift: bit offset of the rptr/wptr values |
| 672 | * @ptr_reg_mask: bit mask of the rptr/wptr values |
| 673 | * @nop: nop packet for this ring |
| 674 | * |
| 675 | * Initialize the driver information for the selected ring (all asics). |
| 676 | * Returns 0 on success, error on failure. |
| 677 | */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 678 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size, |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 679 | unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, |
| 680 | u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 681 | { |
| 682 | int r; |
| 683 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 684 | ring->ring_size = ring_size; |
| 685 | ring->rptr_offs = rptr_offs; |
| 686 | ring->rptr_reg = rptr_reg; |
| 687 | ring->wptr_reg = wptr_reg; |
Alex Deucher | 78c5560 | 2011-11-17 14:25:56 -0500 | [diff] [blame] | 688 | ring->ptr_reg_shift = ptr_reg_shift; |
| 689 | ring->ptr_reg_mask = ptr_reg_mask; |
| 690 | ring->nop = nop; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 691 | /* Allocate ring buffer */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 692 | if (ring->ring_obj == NULL) { |
| 693 | r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true, |
Alex Deucher | 40f5cf9 | 2012-05-10 18:33:13 -0400 | [diff] [blame] | 694 | RADEON_GEM_DOMAIN_GTT, |
| 695 | NULL, &ring->ring_obj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 696 | if (r) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 697 | dev_err(rdev->dev, "(%d) ring create failed\n", r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 698 | return r; |
| 699 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 700 | r = radeon_bo_reserve(ring->ring_obj, false); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 701 | if (unlikely(r != 0)) |
| 702 | return r; |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 703 | r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT, |
| 704 | &ring->gpu_addr); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 705 | if (r) { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 706 | radeon_bo_unreserve(ring->ring_obj); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 707 | dev_err(rdev->dev, "(%d) ring pin failed\n", r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 708 | return r; |
| 709 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 710 | r = radeon_bo_kmap(ring->ring_obj, |
| 711 | (void **)&ring->ring); |
| 712 | radeon_bo_unreserve(ring->ring_obj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 713 | if (r) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 714 | dev_err(rdev->dev, "(%d) ring map failed\n", r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 715 | return r; |
| 716 | } |
| 717 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 718 | ring->ptr_mask = (ring->ring_size / 4) - 1; |
| 719 | ring->ring_free_dw = ring->ring_size / 4; |
Alex Deucher | 89d3580 | 2012-07-17 14:02:31 -0400 | [diff] [blame] | 720 | if (rdev->wb.enabled) { |
| 721 | u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4); |
| 722 | ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index; |
| 723 | ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4]; |
| 724 | } |
Christian König | ec1a6cc | 2012-05-02 15:11:11 +0200 | [diff] [blame] | 725 | if (radeon_debugfs_ring_init(rdev, ring)) { |
| 726 | DRM_ERROR("Failed to register debugfs file for rings !\n"); |
| 727 | } |
Christian König | 48c0ac9 | 2012-08-20 15:38:47 +0200 | [diff] [blame] | 728 | radeon_ring_lockup_update(ring); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 729 | return 0; |
| 730 | } |
| 731 | |
Alex Deucher | 7592328 | 2012-07-17 14:02:38 -0400 | [diff] [blame] | 732 | /** |
| 733 | * radeon_ring_fini - tear down the driver ring struct. |
| 734 | * |
| 735 | * @rdev: radeon_device pointer |
| 736 | * @ring: radeon_ring structure holding ring information |
| 737 | * |
| 738 | * Tear down the driver information for the selected ring (all asics). |
| 739 | */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 740 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 741 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 742 | int r; |
Alex Deucher | ca2af92 | 2010-05-06 11:02:24 -0400 | [diff] [blame] | 743 | struct radeon_bo *ring_obj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 744 | |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 745 | mutex_lock(&rdev->ring_lock); |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 746 | ring_obj = ring->ring_obj; |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 747 | ring->ready = false; |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 748 | ring->ring = NULL; |
| 749 | ring->ring_obj = NULL; |
Christian König | d6999bc | 2012-05-09 15:34:45 +0200 | [diff] [blame] | 750 | mutex_unlock(&rdev->ring_lock); |
Alex Deucher | ca2af92 | 2010-05-06 11:02:24 -0400 | [diff] [blame] | 751 | |
| 752 | if (ring_obj) { |
| 753 | r = radeon_bo_reserve(ring_obj, false); |
| 754 | if (likely(r == 0)) { |
| 755 | radeon_bo_kunmap(ring_obj); |
| 756 | radeon_bo_unpin(ring_obj); |
| 757 | radeon_bo_unreserve(ring_obj); |
| 758 | } |
| 759 | radeon_bo_unref(&ring_obj); |
| 760 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 761 | } |
| 762 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 763 | /* |
| 764 | * Debugfs info |
| 765 | */ |
| 766 | #if defined(CONFIG_DEBUG_FS) |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 767 | |
| 768 | static int radeon_debugfs_ring_info(struct seq_file *m, void *data) |
| 769 | { |
| 770 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 771 | struct drm_device *dev = node->minor->dev; |
| 772 | struct radeon_device *rdev = dev->dev_private; |
| 773 | int ridx = *(int*)node->info_ent->data; |
| 774 | struct radeon_ring *ring = &rdev->ring[ridx]; |
| 775 | unsigned count, i, j; |
Jerome Glisse | 4d00919 | 2013-01-02 17:30:34 -0500 | [diff] [blame] | 776 | u32 tmp; |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 777 | |
| 778 | radeon_ring_free_size(rdev, ring); |
| 779 | count = (ring->ring_size / 4) - ring->ring_free_dw; |
Jerome Glisse | 4d00919 | 2013-01-02 17:30:34 -0500 | [diff] [blame] | 780 | tmp = RREG32(ring->wptr_reg) >> ring->ptr_reg_shift; |
| 781 | seq_printf(m, "wptr(0x%04x): 0x%08x [%5d]\n", ring->wptr_reg, tmp, tmp); |
| 782 | tmp = RREG32(ring->rptr_reg) >> ring->ptr_reg_shift; |
| 783 | seq_printf(m, "rptr(0x%04x): 0x%08x [%5d]\n", ring->rptr_reg, tmp, tmp); |
Christian König | 45df680 | 2012-07-06 16:22:55 +0200 | [diff] [blame] | 784 | if (ring->rptr_save_reg) { |
| 785 | seq_printf(m, "rptr next(0x%04x): 0x%08x\n", ring->rptr_save_reg, |
| 786 | RREG32(ring->rptr_save_reg)); |
| 787 | } |
Jerome Glisse | 4d00919 | 2013-01-02 17:30:34 -0500 | [diff] [blame] | 788 | seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", ring->wptr, ring->wptr); |
| 789 | seq_printf(m, "driver's copy of the rptr: 0x%08x [%5d]\n", ring->rptr, ring->rptr); |
Jerome Glisse | 5f0839c | 2013-01-11 15:19:43 -0500 | [diff] [blame] | 790 | seq_printf(m, "last semaphore signal addr : 0x%016llx\n", ring->last_semaphore_signal_addr); |
| 791 | seq_printf(m, "last semaphore wait addr : 0x%016llx\n", ring->last_semaphore_wait_addr); |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 792 | seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); |
| 793 | seq_printf(m, "%u dwords in ring\n", count); |
Jerome Glisse | 4d00919 | 2013-01-02 17:30:34 -0500 | [diff] [blame] | 794 | /* print 8 dw before current rptr as often it's the last executed |
| 795 | * packet that is the root issue |
| 796 | */ |
| 797 | i = (ring->rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask; |
| 798 | for (j = 0; j <= (count + 32); j++) { |
| 799 | seq_printf(m, "r[%5d]=0x%08x\n", i, ring->ring[i]); |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 800 | i = (i + 1) & ring->ptr_mask; |
| 801 | } |
| 802 | return 0; |
| 803 | } |
| 804 | |
| 805 | static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX; |
| 806 | static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX; |
| 807 | static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX; |
Jerome Glisse | 7479548 | 2013-01-02 15:12:14 -0500 | [diff] [blame] | 808 | static int radeon_ring_type_dma1_index = R600_RING_TYPE_DMA_INDEX; |
| 809 | static int radeon_ring_type_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX; |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 810 | |
| 811 | static struct drm_info_list radeon_debugfs_ring_info_list[] = { |
| 812 | {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index}, |
| 813 | {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index}, |
| 814 | {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index}, |
Jerome Glisse | 7479548 | 2013-01-02 15:12:14 -0500 | [diff] [blame] | 815 | {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_ring_type_dma1_index}, |
| 816 | {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_ring_type_dma2_index}, |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 817 | }; |
| 818 | |
Christian König | 711a972 | 2012-05-09 15:34:51 +0200 | [diff] [blame] | 819 | static int radeon_debugfs_sa_info(struct seq_file *m, void *data) |
| 820 | { |
| 821 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 822 | struct drm_device *dev = node->minor->dev; |
| 823 | struct radeon_device *rdev = dev->dev_private; |
| 824 | |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 825 | radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m); |
Christian König | 711a972 | 2012-05-09 15:34:51 +0200 | [diff] [blame] | 826 | |
| 827 | return 0; |
| 828 | |
| 829 | } |
| 830 | |
| 831 | static struct drm_info_list radeon_debugfs_sa_list[] = { |
| 832 | {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL}, |
| 833 | }; |
| 834 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 835 | #endif |
| 836 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 837 | static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring) |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 838 | { |
| 839 | #if defined(CONFIG_DEBUG_FS) |
Christian König | ec1a6cc | 2012-05-02 15:11:11 +0200 | [diff] [blame] | 840 | unsigned i; |
| 841 | for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) { |
| 842 | struct drm_info_list *info = &radeon_debugfs_ring_info_list[i]; |
| 843 | int ridx = *(int*)radeon_debugfs_ring_info_list[i].data; |
| 844 | unsigned r; |
| 845 | |
| 846 | if (&rdev->ring[ridx] != ring) |
| 847 | continue; |
| 848 | |
| 849 | r = radeon_debugfs_add_files(rdev, info, 1); |
| 850 | if (r) |
| 851 | return r; |
| 852 | } |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 853 | #endif |
Christian König | ec1a6cc | 2012-05-02 15:11:11 +0200 | [diff] [blame] | 854 | return 0; |
Christian König | af9720f | 2011-10-24 17:08:44 +0200 | [diff] [blame] | 855 | } |
| 856 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 857 | static int radeon_debugfs_sa_init(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 858 | { |
| 859 | #if defined(CONFIG_DEBUG_FS) |
Jerome Glisse | c507f7e | 2012-05-09 15:34:58 +0200 | [diff] [blame] | 860 | return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 861 | #else |
| 862 | return 0; |
| 863 | #endif |
| 864 | } |