blob: 66719925970f74755865320e81a83fb43a5d8992 [file] [log] [blame]
Alan Coxda9bb1d2006-01-18 17:44:13 -08001#
2# EDAC Kconfig
Doug Thompson4577ca52009-04-02 16:58:43 -07003# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
Alan Coxda9bb1d2006-01-18 17:44:13 -08004# Licensed and distributed under the GPL
5#
Alan Coxda9bb1d2006-01-18 17:44:13 -08006
Borislav Petkov544516632012-12-18 22:02:56 +01007config EDAC_SUPPORT
8 bool
9
Jan Engelhardt751cb5e2007-07-15 23:39:27 -070010menuconfig EDAC
GeunSik Lime24aca62009-06-17 16:28:02 -070011 bool "EDAC (Error Detection And Correction) reporting"
Martin Schwidefskye25df122007-05-10 15:45:57 +020012 depends on HAS_IOMEM
Ralf Baechlef65aad42012-10-17 00:39:09 +020013 depends on X86 || PPC || TILE || ARM || EDAC_SUPPORT
Alan Coxda9bb1d2006-01-18 17:44:13 -080014 help
15 EDAC is designed to report errors in the core system.
16 These are low-level errors that are reported in the CPU or
Douglas Thompson8cb2a392007-07-19 01:50:12 -070017 supporting chipset or other subsystems:
18 memory errors, cache errors, PCI errors, thermal throttling, etc..
19 If unsure, select 'Y'.
Alan Coxda9bb1d2006-01-18 17:44:13 -080020
Tim Small57c432b2006-03-09 17:33:50 -080021 If this code is reporting problems on your system, please
22 see the EDAC project web pages for more information at:
23
24 <http://bluesmoke.sourceforge.net/>
25
26 and:
27
28 <http://buttersideup.com/edacwiki>
29
30 There is also a mailing list for the EDAC project, which can
31 be found via the sourceforge page.
32
Jan Engelhardt751cb5e2007-07-15 23:39:27 -070033if EDAC
Alan Coxda9bb1d2006-01-18 17:44:13 -080034
Mauro Carvalho Chehab19974712012-03-21 17:06:53 -030035config EDAC_LEGACY_SYSFS
36 bool "EDAC legacy sysfs"
37 default y
38 help
39 Enable the compatibility sysfs nodes.
40 Use 'Y' if your edac utilities aren't ported to work with the newer
41 structures.
42
Alan Coxda9bb1d2006-01-18 17:44:13 -080043config EDAC_DEBUG
44 bool "Debugging"
Alan Coxda9bb1d2006-01-18 17:44:13 -080045 help
Borislav Petkov37929872012-09-10 16:50:54 +020046 This turns on debugging information for the entire EDAC subsystem.
47 You do so by inserting edac_module with "edac_debug_level=x." Valid
48 levels are 0-4 (from low to high) and by default it is set to 2.
49 Usually you should select 'N' here.
Alan Coxda9bb1d2006-01-18 17:44:13 -080050
Borislav Petkov9cdeb402010-09-02 18:33:24 +020051config EDAC_DECODE_MCE
Borislav Petkov0d18b2e2009-10-02 15:31:48 +020052 tristate "Decode MCEs in human-readable form (only on AMD for now)"
Borislav Petkov168eb342011-08-10 09:43:30 -030053 depends on CPU_SUP_AMD && X86_MCE_AMD
Borislav Petkov0d18b2e2009-10-02 15:31:48 +020054 default y
55 ---help---
56 Enable this option if you want to decode Machine Check Exceptions
Lucas De Marchi25985ed2011-03-30 22:57:33 -030057 occurring on your machine in human-readable form.
Borislav Petkov0d18b2e2009-10-02 15:31:48 +020058
59 You should definitely say Y here in case you want to decode MCEs
60 which occur really early upon boot, before the module infrastructure
61 has been initialized.
62
Borislav Petkov9cdeb402010-09-02 18:33:24 +020063config EDAC_MCE_INJ
64 tristate "Simple MCE injection interface over /sysfs"
65 depends on EDAC_DECODE_MCE
66 default n
67 help
68 This is a simple interface to inject MCEs over /sysfs and test
69 the MCE decoding code in EDAC.
70
71 This is currently AMD-only.
72
Alan Coxda9bb1d2006-01-18 17:44:13 -080073config EDAC_MM_EDAC
74 tristate "Main Memory EDAC (Error Detection And Correction) reporting"
Alan Coxda9bb1d2006-01-18 17:44:13 -080075 help
76 Some systems are able to detect and correct errors in main
77 memory. EDAC can report statistics on memory error
78 detection and correction (EDAC - or commonly referred to ECC
79 errors). EDAC will also try to decode where these errors
80 occurred so that a particular failing memory module can be
81 replaced. If unsure, select 'Y'.
82
Doug Thompson7d6034d2009-04-27 20:01:01 +020083config EDAC_AMD64
Borislav Petkov027dbd62010-10-13 22:12:15 +020084 tristate "AMD64 (Opteron, Athlon64) K8, F10h"
85 depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE
Doug Thompson7d6034d2009-04-27 20:01:01 +020086 help
Borislav Petkov027dbd62010-10-13 22:12:15 +020087 Support for error detection and correction of DRAM ECC errors on
88 the AMD64 families of memory controllers (K8 and F10h)
Doug Thompson7d6034d2009-04-27 20:01:01 +020089
90config EDAC_AMD64_ERROR_INJECTION
Borislav Petkov9cdeb402010-09-02 18:33:24 +020091 bool "Sysfs HW Error injection facilities"
Doug Thompson7d6034d2009-04-27 20:01:01 +020092 depends on EDAC_AMD64
93 help
94 Recent Opterons (Family 10h and later) provide for Memory Error
95 Injection into the ECC detection circuits. The amd64_edac module
96 allows the operator/user to inject Uncorrectable and Correctable
97 errors into DRAM.
98
99 When enabled, in each of the respective memory controller directories
100 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
101
102 - inject_section (0..3, 16-byte section of 64-byte cacheline),
103 - inject_word (0..8, 16-bit word of 16-byte section),
104 - inject_ecc_vector (hex ecc vector: select bits of inject word)
105
106 In addition, there are two control files, inject_read and inject_write,
107 which trigger the DRAM ECC Read and Write respectively.
Alan Coxda9bb1d2006-01-18 17:44:13 -0800108
109config EDAC_AMD76X
110 tristate "AMD 76x (760, 762, 768)"
Dave Jones90cbc452006-02-03 03:04:11 -0800111 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800112 help
113 Support for error detection and correction on the AMD 76x
114 series of chipsets used with the Athlon processor.
115
116config EDAC_E7XXX
117 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800118 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800119 help
120 Support for error detection and correction on the Intel
121 E7205, E7500, E7501 and E7505 server chipsets.
122
123config EDAC_E752X
Andrei Konovalov5135b792008-04-29 01:03:13 -0700124 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
Randy Dunlapda960a62006-03-31 02:30:34 -0800125 depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
Alan Coxda9bb1d2006-01-18 17:44:13 -0800126 help
127 Support for error detection and correction on the Intel
128 E7520, E7525, E7320 server chipsets.
129
Tim Small5a2c6752007-07-19 01:49:42 -0700130config EDAC_I82443BXGX
131 tristate "Intel 82443BX/GX (440BX/GX)"
132 depends on EDAC_MM_EDAC && PCI && X86_32
Andrew Morton28f96eea2007-07-19 01:49:45 -0700133 depends on BROKEN
Tim Small5a2c6752007-07-19 01:49:42 -0700134 help
135 Support for error detection and correction on the Intel
136 82443BX/GX memory controllers (440BX/GX chipsets).
137
Alan Coxda9bb1d2006-01-18 17:44:13 -0800138config EDAC_I82875P
139 tristate "Intel 82875p (D82875P, E7210)"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800140 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800141 help
142 Support for error detection and correction on the Intel
143 DP82785P and E7210 server chipsets.
144
Ranganathan Desikan420390f2007-07-19 01:50:31 -0700145config EDAC_I82975X
146 tristate "Intel 82975x (D82975x)"
147 depends on EDAC_MM_EDAC && PCI && X86
148 help
149 Support for error detection and correction on the Intel
150 DP82975x server chipsets.
151
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700152config EDAC_I3000
153 tristate "Intel 3000/3010"
Jason Uhlenkottf5c04542008-02-07 00:15:01 -0800154 depends on EDAC_MM_EDAC && PCI && X86
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700155 help
156 Support for error detection and correction on the Intel
157 3000 and 3010 server chipsets.
158
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700159config EDAC_I3200
160 tristate "Intel 3200"
161 depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL
162 help
163 Support for error detection and correction on the Intel
164 3200 and 3210 server chipsets.
165
Hitoshi Mitakedf8bc08c2008-10-29 14:00:50 -0700166config EDAC_X38
167 tristate "Intel X38"
168 depends on EDAC_MM_EDAC && PCI && X86
169 help
170 Support for error detection and correction on the Intel
171 X38 server chipsets.
172
Mauro Carvalho Chehab920c8df2009-01-06 14:43:00 -0800173config EDAC_I5400
174 tristate "Intel 5400 (Seaburg) chipsets"
175 depends on EDAC_MM_EDAC && PCI && X86
176 help
177 Support for error detection and correction the Intel
178 i5400 MCH chipset (Seaburg).
179
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300180config EDAC_I7CORE
181 tristate "Intel i7 Core (Nehalem) processors"
Borislav Petkov168eb342011-08-10 09:43:30 -0300182 depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300183 help
184 Support for error detection and correction the Intel
Mauro Carvalho Chehab696e4092009-07-23 06:57:45 -0300185 i7 Core (Nehalem) Integrated Memory Controller that exists on
186 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
187 and Xeon 55xx processors.
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300188
Alan Coxda9bb1d2006-01-18 17:44:13 -0800189config EDAC_I82860
190 tristate "Intel 82860"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800191 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800192 help
193 Support for error detection and correction on the Intel
194 82860 chipset.
195
196config EDAC_R82600
197 tristate "Radisys 82600 embedded chipset"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800198 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800199 help
200 Support for error detection and correction on the Radisys
201 82600 embedded chipset.
202
Eric Wolleseneb607052007-07-19 01:49:39 -0700203config EDAC_I5000
204 tristate "Intel Greencreek/Blackford chipset"
205 depends on EDAC_MM_EDAC && X86 && PCI
206 help
207 Support for error detection and correction the Intel
208 Greekcreek/Blackford chipsets.
209
Arthur Jones8f421c592008-07-25 01:49:04 -0700210config EDAC_I5100
211 tristate "Intel San Clemente MCH"
212 depends on EDAC_MM_EDAC && X86 && PCI
213 help
214 Support for error detection and correction the Intel
215 San Clemente MCH.
216
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300217config EDAC_I7300
218 tristate "Intel Clarksboro MCH"
219 depends on EDAC_MM_EDAC && X86 && PCI
220 help
221 Support for error detection and correction the Intel
222 Clarksboro MCH (Intel 7300 chipset).
223
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -0200224config EDAC_SBRIDGE
225 tristate "Intel Sandy-Bridge Integrated MC"
Hui Wang22a5c272012-02-06 04:10:59 -0300226 depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
227 depends on PCI_MMCONFIG && EXPERIMENTAL
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -0200228 help
229 Support for error detection and correction the Intel
230 Sandy Bridge Integrated Memory Controller.
231
Dave Jianga9a753d2008-02-07 00:14:55 -0800232config EDAC_MPC85XX
Ira W. Snyderb4846252009-09-23 15:57:25 -0700233 tristate "Freescale MPC83xx / MPC85xx"
Anton Vorontsov1cd85212010-07-20 13:24:27 -0700234 depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
Dave Jianga9a753d2008-02-07 00:14:55 -0800235 help
236 Support for error detection and correction on the Freescale
Ira W. Snyderb4846252009-09-23 15:57:25 -0700237 MPC8349, MPC8560, MPC8540, MPC8548
Dave Jianga9a753d2008-02-07 00:14:55 -0800238
Dave Jiang4f4aeea2008-02-07 00:14:56 -0800239config EDAC_MV64X60
240 tristate "Marvell MV64x60"
241 depends on EDAC_MM_EDAC && MV64X60
242 help
243 Support for error detection and correction on the Marvell
244 MV64360 and MV64460 chipsets.
245
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700246config EDAC_PASEMI
247 tristate "PA Semi PWRficient"
248 depends on EDAC_MM_EDAC && PCI
Doug Thompsonddcc3052007-07-26 10:41:16 -0700249 depends on PPC_PASEMI
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700250 help
251 Support for error detection and correction on PA Semi
252 PWRficient.
253
Benjamin Herrenschmidt48764e42008-02-07 00:14:53 -0800254config EDAC_CELL
255 tristate "Cell Broadband Engine memory controller"
Benjamin Krilldef434c2008-11-27 16:15:44 +0100256 depends on EDAC_MM_EDAC && PPC_CELL_COMMON
Benjamin Herrenschmidt48764e42008-02-07 00:14:53 -0800257 help
258 Support for error detection and correction on the
259 Cell Broadband Engine internal memory controller
260 on platform without a hypervisor
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700261
Grant Ericksondba7a772009-04-02 16:58:45 -0700262config EDAC_PPC4XX
263 tristate "PPC4xx IBM DDR2 Memory Controller"
264 depends on EDAC_MM_EDAC && 4xx
265 help
266 This enables support for EDAC on the ECC memory used
267 with the IBM DDR2 memory controller found in various
268 PowerPC 4xx embedded processors such as the 405EX[r],
269 440SP, 440SPe, 460EX, 460GT and 460SX.
270
Harry Ciaoe8765582009-04-02 16:58:51 -0700271config EDAC_AMD8131
272 tristate "AMD8131 HyperTransport PCI-X Tunnel"
Harry Ciao715fe7a2009-05-28 14:34:43 -0700273 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
Harry Ciaoe8765582009-04-02 16:58:51 -0700274 help
275 Support for error detection and correction on the
276 AMD8131 HyperTransport PCI-X Tunnel chip.
Harry Ciao715fe7a2009-05-28 14:34:43 -0700277 Note, add more Kconfig dependency if it's adopted
278 on some machine other than Maple.
Harry Ciaoe8765582009-04-02 16:58:51 -0700279
Harry Ciao58b4ce62009-04-02 16:58:51 -0700280config EDAC_AMD8111
281 tristate "AMD8111 HyperTransport I/O Hub"
Harry Ciao715fe7a2009-05-28 14:34:43 -0700282 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
Harry Ciao58b4ce62009-04-02 16:58:51 -0700283 help
284 Support for error detection and correction on the
285 AMD8111 HyperTransport I/O Hub chip.
Harry Ciao715fe7a2009-05-28 14:34:43 -0700286 Note, add more Kconfig dependency if it's adopted
287 on some machine other than Maple.
Harry Ciao58b4ce62009-04-02 16:58:51 -0700288
Harry Ciao2a9036a2009-06-17 16:27:58 -0700289config EDAC_CPC925
290 tristate "IBM CPC925 Memory Controller (PPC970FX)"
291 depends on EDAC_MM_EDAC && PPC64
292 help
293 Support for error detection and correction on the
294 IBM CPC925 Bridge and Memory Controller, which is
295 a companion chip to the PowerPC 970 family of
296 processors.
297
Chris Metcalf5c770752011-03-01 13:01:49 -0500298config EDAC_TILE
299 tristate "Tilera Memory Controller"
300 depends on EDAC_MM_EDAC && TILE
301 default y
302 help
303 Support for error detection and correction on the
304 Tilera memory controller.
305
Rob Herringa1b01ed2012-06-13 12:01:55 -0500306config EDAC_HIGHBANK_MC
307 tristate "Highbank Memory Controller"
308 depends on EDAC_MM_EDAC && ARCH_HIGHBANK
309 help
310 Support for error detection and correction on the
311 Calxeda Highbank memory controller.
312
Rob Herring69154d02012-06-11 21:32:14 -0500313config EDAC_HIGHBANK_L2
314 tristate "Highbank L2 Cache"
315 depends on EDAC_MM_EDAC && ARCH_HIGHBANK
316 help
317 Support for error detection and correction on the
318 Calxeda Highbank memory controller.
319
Ralf Baechlef65aad42012-10-17 00:39:09 +0200320config EDAC_OCTEON_PC
321 tristate "Cavium Octeon Primary Caches"
322 depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
323 help
324 Support for error detection and correction on the primary caches of
325 the cnMIPS cores of Cavium Octeon family SOCs.
326
327config EDAC_OCTEON_L2C
328 tristate "Cavium Octeon Secondary Caches (L2C)"
329 depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
330 help
331 Support for error detection and correction on the
332 Cavium Octeon family of SOCs.
333
334config EDAC_OCTEON_LMC
335 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
336 depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
337 help
338 Support for error detection and correction on the
339 Cavium Octeon family of SOCs.
340
341config EDAC_OCTEON_PCI
342 tristate "Cavium Octeon PCI Controller"
343 depends on EDAC_MM_EDAC && PCI && CPU_CAVIUM_OCTEON
344 help
345 Support for error detection and correction on the
346 Cavium Octeon family of SOCs.
347
Jan Engelhardt751cb5e2007-07-15 23:39:27 -0700348endif # EDAC