Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 1 | # |
| 2 | # EDAC Kconfig |
Doug Thompson | 4577ca5 | 2009-04-02 16:58:43 -0700 | [diff] [blame] | 3 | # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 4 | # Licensed and distributed under the GPL |
| 5 | # |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 6 | |
Borislav Petkov | 54451663 | 2012-12-18 22:02:56 +0100 | [diff] [blame] | 7 | config EDAC_SUPPORT |
| 8 | bool |
| 9 | |
Jan Engelhardt | 751cb5e | 2007-07-15 23:39:27 -0700 | [diff] [blame] | 10 | menuconfig EDAC |
GeunSik Lim | e24aca6 | 2009-06-17 16:28:02 -0700 | [diff] [blame] | 11 | bool "EDAC (Error Detection And Correction) reporting" |
Martin Schwidefsky | e25df12 | 2007-05-10 15:45:57 +0200 | [diff] [blame] | 12 | depends on HAS_IOMEM |
Ralf Baechle | f65aad4 | 2012-10-17 00:39:09 +0200 | [diff] [blame] | 13 | depends on X86 || PPC || TILE || ARM || EDAC_SUPPORT |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 14 | help |
| 15 | EDAC is designed to report errors in the core system. |
| 16 | These are low-level errors that are reported in the CPU or |
Douglas Thompson | 8cb2a39 | 2007-07-19 01:50:12 -0700 | [diff] [blame] | 17 | supporting chipset or other subsystems: |
| 18 | memory errors, cache errors, PCI errors, thermal throttling, etc.. |
| 19 | If unsure, select 'Y'. |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 20 | |
Tim Small | 57c432b | 2006-03-09 17:33:50 -0800 | [diff] [blame] | 21 | If this code is reporting problems on your system, please |
| 22 | see the EDAC project web pages for more information at: |
| 23 | |
| 24 | <http://bluesmoke.sourceforge.net/> |
| 25 | |
| 26 | and: |
| 27 | |
| 28 | <http://buttersideup.com/edacwiki> |
| 29 | |
| 30 | There is also a mailing list for the EDAC project, which can |
| 31 | be found via the sourceforge page. |
| 32 | |
Jan Engelhardt | 751cb5e | 2007-07-15 23:39:27 -0700 | [diff] [blame] | 33 | if EDAC |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 34 | |
Mauro Carvalho Chehab | 1997471 | 2012-03-21 17:06:53 -0300 | [diff] [blame] | 35 | config EDAC_LEGACY_SYSFS |
| 36 | bool "EDAC legacy sysfs" |
| 37 | default y |
| 38 | help |
| 39 | Enable the compatibility sysfs nodes. |
| 40 | Use 'Y' if your edac utilities aren't ported to work with the newer |
| 41 | structures. |
| 42 | |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 43 | config EDAC_DEBUG |
| 44 | bool "Debugging" |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 45 | help |
Borislav Petkov | 3792987 | 2012-09-10 16:50:54 +0200 | [diff] [blame] | 46 | This turns on debugging information for the entire EDAC subsystem. |
| 47 | You do so by inserting edac_module with "edac_debug_level=x." Valid |
| 48 | levels are 0-4 (from low to high) and by default it is set to 2. |
| 49 | Usually you should select 'N' here. |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 50 | |
Borislav Petkov | 9cdeb40 | 2010-09-02 18:33:24 +0200 | [diff] [blame] | 51 | config EDAC_DECODE_MCE |
Borislav Petkov | 0d18b2e | 2009-10-02 15:31:48 +0200 | [diff] [blame] | 52 | tristate "Decode MCEs in human-readable form (only on AMD for now)" |
Borislav Petkov | 168eb34 | 2011-08-10 09:43:30 -0300 | [diff] [blame] | 53 | depends on CPU_SUP_AMD && X86_MCE_AMD |
Borislav Petkov | 0d18b2e | 2009-10-02 15:31:48 +0200 | [diff] [blame] | 54 | default y |
| 55 | ---help--- |
| 56 | Enable this option if you want to decode Machine Check Exceptions |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 57 | occurring on your machine in human-readable form. |
Borislav Petkov | 0d18b2e | 2009-10-02 15:31:48 +0200 | [diff] [blame] | 58 | |
| 59 | You should definitely say Y here in case you want to decode MCEs |
| 60 | which occur really early upon boot, before the module infrastructure |
| 61 | has been initialized. |
| 62 | |
Borislav Petkov | 9cdeb40 | 2010-09-02 18:33:24 +0200 | [diff] [blame] | 63 | config EDAC_MCE_INJ |
| 64 | tristate "Simple MCE injection interface over /sysfs" |
| 65 | depends on EDAC_DECODE_MCE |
| 66 | default n |
| 67 | help |
| 68 | This is a simple interface to inject MCEs over /sysfs and test |
| 69 | the MCE decoding code in EDAC. |
| 70 | |
| 71 | This is currently AMD-only. |
| 72 | |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 73 | config EDAC_MM_EDAC |
| 74 | tristate "Main Memory EDAC (Error Detection And Correction) reporting" |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 75 | help |
| 76 | Some systems are able to detect and correct errors in main |
| 77 | memory. EDAC can report statistics on memory error |
| 78 | detection and correction (EDAC - or commonly referred to ECC |
| 79 | errors). EDAC will also try to decode where these errors |
| 80 | occurred so that a particular failing memory module can be |
| 81 | replaced. If unsure, select 'Y'. |
| 82 | |
Doug Thompson | 7d6034d | 2009-04-27 20:01:01 +0200 | [diff] [blame] | 83 | config EDAC_AMD64 |
Borislav Petkov | 027dbd6 | 2010-10-13 22:12:15 +0200 | [diff] [blame] | 84 | tristate "AMD64 (Opteron, Athlon64) K8, F10h" |
| 85 | depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE |
Doug Thompson | 7d6034d | 2009-04-27 20:01:01 +0200 | [diff] [blame] | 86 | help |
Borislav Petkov | 027dbd6 | 2010-10-13 22:12:15 +0200 | [diff] [blame] | 87 | Support for error detection and correction of DRAM ECC errors on |
| 88 | the AMD64 families of memory controllers (K8 and F10h) |
Doug Thompson | 7d6034d | 2009-04-27 20:01:01 +0200 | [diff] [blame] | 89 | |
| 90 | config EDAC_AMD64_ERROR_INJECTION |
Borislav Petkov | 9cdeb40 | 2010-09-02 18:33:24 +0200 | [diff] [blame] | 91 | bool "Sysfs HW Error injection facilities" |
Doug Thompson | 7d6034d | 2009-04-27 20:01:01 +0200 | [diff] [blame] | 92 | depends on EDAC_AMD64 |
| 93 | help |
| 94 | Recent Opterons (Family 10h and later) provide for Memory Error |
| 95 | Injection into the ECC detection circuits. The amd64_edac module |
| 96 | allows the operator/user to inject Uncorrectable and Correctable |
| 97 | errors into DRAM. |
| 98 | |
| 99 | When enabled, in each of the respective memory controller directories |
| 100 | (/sys/devices/system/edac/mc/mcX), there are 3 input files: |
| 101 | |
| 102 | - inject_section (0..3, 16-byte section of 64-byte cacheline), |
| 103 | - inject_word (0..8, 16-bit word of 16-byte section), |
| 104 | - inject_ecc_vector (hex ecc vector: select bits of inject word) |
| 105 | |
| 106 | In addition, there are two control files, inject_read and inject_write, |
| 107 | which trigger the DRAM ECC Read and Write respectively. |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 108 | |
| 109 | config EDAC_AMD76X |
| 110 | tristate "AMD 76x (760, 762, 768)" |
Dave Jones | 90cbc45 | 2006-02-03 03:04:11 -0800 | [diff] [blame] | 111 | depends on EDAC_MM_EDAC && PCI && X86_32 |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 112 | help |
| 113 | Support for error detection and correction on the AMD 76x |
| 114 | series of chipsets used with the Athlon processor. |
| 115 | |
| 116 | config EDAC_E7XXX |
| 117 | tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" |
Dave Peterson | 39f1d8d | 2006-03-26 01:38:50 -0800 | [diff] [blame] | 118 | depends on EDAC_MM_EDAC && PCI && X86_32 |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 119 | help |
| 120 | Support for error detection and correction on the Intel |
| 121 | E7205, E7500, E7501 and E7505 server chipsets. |
| 122 | |
| 123 | config EDAC_E752X |
Andrei Konovalov | 5135b79 | 2008-04-29 01:03:13 -0700 | [diff] [blame] | 124 | tristate "Intel e752x (e7520, e7525, e7320) and 3100" |
Randy Dunlap | da960a6 | 2006-03-31 02:30:34 -0800 | [diff] [blame] | 125 | depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 126 | help |
| 127 | Support for error detection and correction on the Intel |
| 128 | E7520, E7525, E7320 server chipsets. |
| 129 | |
Tim Small | 5a2c675 | 2007-07-19 01:49:42 -0700 | [diff] [blame] | 130 | config EDAC_I82443BXGX |
| 131 | tristate "Intel 82443BX/GX (440BX/GX)" |
| 132 | depends on EDAC_MM_EDAC && PCI && X86_32 |
Andrew Morton | 28f96eea | 2007-07-19 01:49:45 -0700 | [diff] [blame] | 133 | depends on BROKEN |
Tim Small | 5a2c675 | 2007-07-19 01:49:42 -0700 | [diff] [blame] | 134 | help |
| 135 | Support for error detection and correction on the Intel |
| 136 | 82443BX/GX memory controllers (440BX/GX chipsets). |
| 137 | |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 138 | config EDAC_I82875P |
| 139 | tristate "Intel 82875p (D82875P, E7210)" |
Dave Peterson | 39f1d8d | 2006-03-26 01:38:50 -0800 | [diff] [blame] | 140 | depends on EDAC_MM_EDAC && PCI && X86_32 |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 141 | help |
| 142 | Support for error detection and correction on the Intel |
| 143 | DP82785P and E7210 server chipsets. |
| 144 | |
Ranganathan Desikan | 420390f | 2007-07-19 01:50:31 -0700 | [diff] [blame] | 145 | config EDAC_I82975X |
| 146 | tristate "Intel 82975x (D82975x)" |
| 147 | depends on EDAC_MM_EDAC && PCI && X86 |
| 148 | help |
| 149 | Support for error detection and correction on the Intel |
| 150 | DP82975x server chipsets. |
| 151 | |
Jason Uhlenkott | 535c6a5 | 2007-07-19 01:49:48 -0700 | [diff] [blame] | 152 | config EDAC_I3000 |
| 153 | tristate "Intel 3000/3010" |
Jason Uhlenkott | f5c0454 | 2008-02-07 00:15:01 -0800 | [diff] [blame] | 154 | depends on EDAC_MM_EDAC && PCI && X86 |
Jason Uhlenkott | 535c6a5 | 2007-07-19 01:49:48 -0700 | [diff] [blame] | 155 | help |
| 156 | Support for error detection and correction on the Intel |
| 157 | 3000 and 3010 server chipsets. |
| 158 | |
Jason Uhlenkott | dd8ef1d | 2009-09-23 15:57:27 -0700 | [diff] [blame] | 159 | config EDAC_I3200 |
| 160 | tristate "Intel 3200" |
| 161 | depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL |
| 162 | help |
| 163 | Support for error detection and correction on the Intel |
| 164 | 3200 and 3210 server chipsets. |
| 165 | |
Hitoshi Mitake | df8bc08c | 2008-10-29 14:00:50 -0700 | [diff] [blame] | 166 | config EDAC_X38 |
| 167 | tristate "Intel X38" |
| 168 | depends on EDAC_MM_EDAC && PCI && X86 |
| 169 | help |
| 170 | Support for error detection and correction on the Intel |
| 171 | X38 server chipsets. |
| 172 | |
Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 173 | config EDAC_I5400 |
| 174 | tristate "Intel 5400 (Seaburg) chipsets" |
| 175 | depends on EDAC_MM_EDAC && PCI && X86 |
| 176 | help |
| 177 | Support for error detection and correction the Intel |
| 178 | i5400 MCH chipset (Seaburg). |
| 179 | |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 180 | config EDAC_I7CORE |
| 181 | tristate "Intel i7 Core (Nehalem) processors" |
Borislav Petkov | 168eb34 | 2011-08-10 09:43:30 -0300 | [diff] [blame] | 182 | depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 183 | help |
| 184 | Support for error detection and correction the Intel |
Mauro Carvalho Chehab | 696e409 | 2009-07-23 06:57:45 -0300 | [diff] [blame] | 185 | i7 Core (Nehalem) Integrated Memory Controller that exists on |
| 186 | newer processors like i7 Core, i7 Core Extreme, Xeon 35xx |
| 187 | and Xeon 55xx processors. |
Mauro Carvalho Chehab | a0c36a1 | 2009-06-22 22:41:15 -0300 | [diff] [blame] | 188 | |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 189 | config EDAC_I82860 |
| 190 | tristate "Intel 82860" |
Dave Peterson | 39f1d8d | 2006-03-26 01:38:50 -0800 | [diff] [blame] | 191 | depends on EDAC_MM_EDAC && PCI && X86_32 |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 192 | help |
| 193 | Support for error detection and correction on the Intel |
| 194 | 82860 chipset. |
| 195 | |
| 196 | config EDAC_R82600 |
| 197 | tristate "Radisys 82600 embedded chipset" |
Dave Peterson | 39f1d8d | 2006-03-26 01:38:50 -0800 | [diff] [blame] | 198 | depends on EDAC_MM_EDAC && PCI && X86_32 |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 199 | help |
| 200 | Support for error detection and correction on the Radisys |
| 201 | 82600 embedded chipset. |
| 202 | |
Eric Wollesen | eb60705 | 2007-07-19 01:49:39 -0700 | [diff] [blame] | 203 | config EDAC_I5000 |
| 204 | tristate "Intel Greencreek/Blackford chipset" |
| 205 | depends on EDAC_MM_EDAC && X86 && PCI |
| 206 | help |
| 207 | Support for error detection and correction the Intel |
| 208 | Greekcreek/Blackford chipsets. |
| 209 | |
Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 210 | config EDAC_I5100 |
| 211 | tristate "Intel San Clemente MCH" |
| 212 | depends on EDAC_MM_EDAC && X86 && PCI |
| 213 | help |
| 214 | Support for error detection and correction the Intel |
| 215 | San Clemente MCH. |
| 216 | |
Mauro Carvalho Chehab | fcaf780 | 2010-08-24 23:22:57 -0300 | [diff] [blame] | 217 | config EDAC_I7300 |
| 218 | tristate "Intel Clarksboro MCH" |
| 219 | depends on EDAC_MM_EDAC && X86 && PCI |
| 220 | help |
| 221 | Support for error detection and correction the Intel |
| 222 | Clarksboro MCH (Intel 7300 chipset). |
| 223 | |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 224 | config EDAC_SBRIDGE |
| 225 | tristate "Intel Sandy-Bridge Integrated MC" |
Hui Wang | 22a5c27 | 2012-02-06 04:10:59 -0300 | [diff] [blame] | 226 | depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL |
| 227 | depends on PCI_MMCONFIG && EXPERIMENTAL |
Mauro Carvalho Chehab | 3d78c9a | 2011-10-20 19:33:46 -0200 | [diff] [blame] | 228 | help |
| 229 | Support for error detection and correction the Intel |
| 230 | Sandy Bridge Integrated Memory Controller. |
| 231 | |
Dave Jiang | a9a753d | 2008-02-07 00:14:55 -0800 | [diff] [blame] | 232 | config EDAC_MPC85XX |
Ira W. Snyder | b484625 | 2009-09-23 15:57:25 -0700 | [diff] [blame] | 233 | tristate "Freescale MPC83xx / MPC85xx" |
Anton Vorontsov | 1cd8521 | 2010-07-20 13:24:27 -0700 | [diff] [blame] | 234 | depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx) |
Dave Jiang | a9a753d | 2008-02-07 00:14:55 -0800 | [diff] [blame] | 235 | help |
| 236 | Support for error detection and correction on the Freescale |
Ira W. Snyder | b484625 | 2009-09-23 15:57:25 -0700 | [diff] [blame] | 237 | MPC8349, MPC8560, MPC8540, MPC8548 |
Dave Jiang | a9a753d | 2008-02-07 00:14:55 -0800 | [diff] [blame] | 238 | |
Dave Jiang | 4f4aeea | 2008-02-07 00:14:56 -0800 | [diff] [blame] | 239 | config EDAC_MV64X60 |
| 240 | tristate "Marvell MV64x60" |
| 241 | depends on EDAC_MM_EDAC && MV64X60 |
| 242 | help |
| 243 | Support for error detection and correction on the Marvell |
| 244 | MV64360 and MV64460 chipsets. |
| 245 | |
Egor Martovetsky | 7d8536f | 2007-07-19 01:50:24 -0700 | [diff] [blame] | 246 | config EDAC_PASEMI |
| 247 | tristate "PA Semi PWRficient" |
| 248 | depends on EDAC_MM_EDAC && PCI |
Doug Thompson | ddcc305 | 2007-07-26 10:41:16 -0700 | [diff] [blame] | 249 | depends on PPC_PASEMI |
Egor Martovetsky | 7d8536f | 2007-07-19 01:50:24 -0700 | [diff] [blame] | 250 | help |
| 251 | Support for error detection and correction on PA Semi |
| 252 | PWRficient. |
| 253 | |
Benjamin Herrenschmidt | 48764e4 | 2008-02-07 00:14:53 -0800 | [diff] [blame] | 254 | config EDAC_CELL |
| 255 | tristate "Cell Broadband Engine memory controller" |
Benjamin Krill | def434c | 2008-11-27 16:15:44 +0100 | [diff] [blame] | 256 | depends on EDAC_MM_EDAC && PPC_CELL_COMMON |
Benjamin Herrenschmidt | 48764e4 | 2008-02-07 00:14:53 -0800 | [diff] [blame] | 257 | help |
| 258 | Support for error detection and correction on the |
| 259 | Cell Broadband Engine internal memory controller |
| 260 | on platform without a hypervisor |
Egor Martovetsky | 7d8536f | 2007-07-19 01:50:24 -0700 | [diff] [blame] | 261 | |
Grant Erickson | dba7a77 | 2009-04-02 16:58:45 -0700 | [diff] [blame] | 262 | config EDAC_PPC4XX |
| 263 | tristate "PPC4xx IBM DDR2 Memory Controller" |
| 264 | depends on EDAC_MM_EDAC && 4xx |
| 265 | help |
| 266 | This enables support for EDAC on the ECC memory used |
| 267 | with the IBM DDR2 memory controller found in various |
| 268 | PowerPC 4xx embedded processors such as the 405EX[r], |
| 269 | 440SP, 440SPe, 460EX, 460GT and 460SX. |
| 270 | |
Harry Ciao | e876558 | 2009-04-02 16:58:51 -0700 | [diff] [blame] | 271 | config EDAC_AMD8131 |
| 272 | tristate "AMD8131 HyperTransport PCI-X Tunnel" |
Harry Ciao | 715fe7a | 2009-05-28 14:34:43 -0700 | [diff] [blame] | 273 | depends on EDAC_MM_EDAC && PCI && PPC_MAPLE |
Harry Ciao | e876558 | 2009-04-02 16:58:51 -0700 | [diff] [blame] | 274 | help |
| 275 | Support for error detection and correction on the |
| 276 | AMD8131 HyperTransport PCI-X Tunnel chip. |
Harry Ciao | 715fe7a | 2009-05-28 14:34:43 -0700 | [diff] [blame] | 277 | Note, add more Kconfig dependency if it's adopted |
| 278 | on some machine other than Maple. |
Harry Ciao | e876558 | 2009-04-02 16:58:51 -0700 | [diff] [blame] | 279 | |
Harry Ciao | 58b4ce6 | 2009-04-02 16:58:51 -0700 | [diff] [blame] | 280 | config EDAC_AMD8111 |
| 281 | tristate "AMD8111 HyperTransport I/O Hub" |
Harry Ciao | 715fe7a | 2009-05-28 14:34:43 -0700 | [diff] [blame] | 282 | depends on EDAC_MM_EDAC && PCI && PPC_MAPLE |
Harry Ciao | 58b4ce6 | 2009-04-02 16:58:51 -0700 | [diff] [blame] | 283 | help |
| 284 | Support for error detection and correction on the |
| 285 | AMD8111 HyperTransport I/O Hub chip. |
Harry Ciao | 715fe7a | 2009-05-28 14:34:43 -0700 | [diff] [blame] | 286 | Note, add more Kconfig dependency if it's adopted |
| 287 | on some machine other than Maple. |
Harry Ciao | 58b4ce6 | 2009-04-02 16:58:51 -0700 | [diff] [blame] | 288 | |
Harry Ciao | 2a9036a | 2009-06-17 16:27:58 -0700 | [diff] [blame] | 289 | config EDAC_CPC925 |
| 290 | tristate "IBM CPC925 Memory Controller (PPC970FX)" |
| 291 | depends on EDAC_MM_EDAC && PPC64 |
| 292 | help |
| 293 | Support for error detection and correction on the |
| 294 | IBM CPC925 Bridge and Memory Controller, which is |
| 295 | a companion chip to the PowerPC 970 family of |
| 296 | processors. |
| 297 | |
Chris Metcalf | 5c77075 | 2011-03-01 13:01:49 -0500 | [diff] [blame] | 298 | config EDAC_TILE |
| 299 | tristate "Tilera Memory Controller" |
| 300 | depends on EDAC_MM_EDAC && TILE |
| 301 | default y |
| 302 | help |
| 303 | Support for error detection and correction on the |
| 304 | Tilera memory controller. |
| 305 | |
Rob Herring | a1b01ed | 2012-06-13 12:01:55 -0500 | [diff] [blame] | 306 | config EDAC_HIGHBANK_MC |
| 307 | tristate "Highbank Memory Controller" |
| 308 | depends on EDAC_MM_EDAC && ARCH_HIGHBANK |
| 309 | help |
| 310 | Support for error detection and correction on the |
| 311 | Calxeda Highbank memory controller. |
| 312 | |
Rob Herring | 69154d0 | 2012-06-11 21:32:14 -0500 | [diff] [blame] | 313 | config EDAC_HIGHBANK_L2 |
| 314 | tristate "Highbank L2 Cache" |
| 315 | depends on EDAC_MM_EDAC && ARCH_HIGHBANK |
| 316 | help |
| 317 | Support for error detection and correction on the |
| 318 | Calxeda Highbank memory controller. |
| 319 | |
Ralf Baechle | f65aad4 | 2012-10-17 00:39:09 +0200 | [diff] [blame] | 320 | config EDAC_OCTEON_PC |
| 321 | tristate "Cavium Octeon Primary Caches" |
| 322 | depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON |
| 323 | help |
| 324 | Support for error detection and correction on the primary caches of |
| 325 | the cnMIPS cores of Cavium Octeon family SOCs. |
| 326 | |
| 327 | config EDAC_OCTEON_L2C |
| 328 | tristate "Cavium Octeon Secondary Caches (L2C)" |
| 329 | depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON |
| 330 | help |
| 331 | Support for error detection and correction on the |
| 332 | Cavium Octeon family of SOCs. |
| 333 | |
| 334 | config EDAC_OCTEON_LMC |
| 335 | tristate "Cavium Octeon DRAM Memory Controller (LMC)" |
| 336 | depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON |
| 337 | help |
| 338 | Support for error detection and correction on the |
| 339 | Cavium Octeon family of SOCs. |
| 340 | |
| 341 | config EDAC_OCTEON_PCI |
| 342 | tristate "Cavium Octeon PCI Controller" |
| 343 | depends on EDAC_MM_EDAC && PCI && CPU_CAVIUM_OCTEON |
| 344 | help |
| 345 | Support for error detection and correction on the |
| 346 | Cavium Octeon family of SOCs. |
| 347 | |
Jan Engelhardt | 751cb5e | 2007-07-15 23:39:27 -0700 | [diff] [blame] | 348 | endif # EDAC |