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Heiko Stübnerd3e51162013-06-10 22:16:22 +02001/*
2 * Pinctrl driver for Rockchip SoCs
3 *
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
6 *
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
12 *
13 * and pinctrl-at91:
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 */
25
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/io.h>
29#include <linux/bitops.h>
30#include <linux/gpio.h>
31#include <linux/of_address.h>
32#include <linux/of_irq.h>
33#include <linux/pinctrl/machine.h>
34#include <linux/pinctrl/pinconf.h>
35#include <linux/pinctrl/pinctrl.h>
36#include <linux/pinctrl/pinmux.h>
37#include <linux/pinctrl/pinconf-generic.h>
38#include <linux/irqchip/chained_irq.h>
Heiko Stübner7e865ab2013-07-23 13:34:20 +020039#include <linux/clk.h>
Heiko Stübner751a99a2014-05-05 13:58:20 +020040#include <linux/regmap.h>
Heiko Stübner14dee862014-05-05 13:59:09 +020041#include <linux/mfd/syscon.h>
Heiko Stübnerd3e51162013-06-10 22:16:22 +020042#include <dt-bindings/pinctrl/rockchip.h>
43
44#include "core.h"
45#include "pinconf.h"
46
47/* GPIO control registers */
48#define GPIO_SWPORT_DR 0x00
49#define GPIO_SWPORT_DDR 0x04
50#define GPIO_INTEN 0x30
51#define GPIO_INTMASK 0x34
52#define GPIO_INTTYPE_LEVEL 0x38
53#define GPIO_INT_POLARITY 0x3c
54#define GPIO_INT_STATUS 0x40
55#define GPIO_INT_RAWSTATUS 0x44
56#define GPIO_DEBOUNCE 0x48
57#define GPIO_PORTS_EOI 0x4c
58#define GPIO_EXT_PORT 0x50
59#define GPIO_LS_SYNC 0x60
60
Heiko Stübnera2829262013-10-16 01:07:20 +020061enum rockchip_pinctrl_type {
62 RK2928,
63 RK3066B,
64 RK3188,
Heiko Stübner66d750e2014-07-20 01:49:17 +020065 RK3288,
Heiko Stübnerdaecdc62015-06-12 23:51:01 +020066 RK3368,
Heiko Stübnera2829262013-10-16 01:07:20 +020067};
68
Heiko Stübnerfc72c922014-06-16 01:36:05 +020069/**
70 * Encode variants of iomux registers into a type variable
71 */
72#define IOMUX_GPIO_ONLY BIT(0)
Heiko Stübner03716e12014-06-16 01:36:57 +020073#define IOMUX_WIDTH_4BIT BIT(1)
Heiko Stübner95ec8ae2014-06-16 01:37:23 +020074#define IOMUX_SOURCE_PMU BIT(2)
Heiko Stübner62f49222014-06-16 01:37:49 +020075#define IOMUX_UNROUTED BIT(3)
Heiko Stübnerfc72c922014-06-16 01:36:05 +020076
77/**
78 * @type: iomux variant using IOMUX_* constants
Heiko Stübner6bc0d1212014-06-16 01:36:33 +020079 * @offset: if initialized to -1 it will be autocalculated, by specifying
80 * an initial offset value the relevant source offset can be reset
81 * to a new value for autocalculating the following iomux registers.
Heiko Stübnerfc72c922014-06-16 01:36:05 +020082 */
83struct rockchip_iomux {
84 int type;
Heiko Stübner6bc0d1212014-06-16 01:36:33 +020085 int offset;
Heiko Stübner65fca612013-10-16 01:07:49 +020086};
87
Heiko Stübnerd3e51162013-06-10 22:16:22 +020088/**
89 * @reg_base: register base of the gpio bank
Heiko Stübner6ca52742013-10-16 01:08:42 +020090 * @reg_pull: optional separate register for additional pull settings
Heiko Stübnerd3e51162013-06-10 22:16:22 +020091 * @clk: clock of the gpio bank
92 * @irq: interrupt of the gpio bank
Doug Anderson5ae0c7a2015-01-26 08:24:03 -080093 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
Heiko Stübnerd3e51162013-06-10 22:16:22 +020094 * @pin_base: first pin number
95 * @nr_pins: number of pins in this bank
96 * @name: name of the bank
97 * @bank_num: number of the bank, to account for holes
Heiko Stübnerfc72c922014-06-16 01:36:05 +020098 * @iomux: array describing the 4 iomux sources of the bank
Heiko Stübnerd3e51162013-06-10 22:16:22 +020099 * @valid: are all necessary informations present
100 * @of_node: dt node of this bank
101 * @drvdata: common pinctrl basedata
102 * @domain: irqdomain of the gpio bank
103 * @gpio_chip: gpiolib chip
104 * @grange: gpio range
105 * @slock: spinlock for the gpio bank
106 */
107struct rockchip_pin_bank {
108 void __iomem *reg_base;
Heiko Stübner751a99a2014-05-05 13:58:20 +0200109 struct regmap *regmap_pull;
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200110 struct clk *clk;
111 int irq;
Doug Anderson5ae0c7a2015-01-26 08:24:03 -0800112 u32 saved_masks;
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200113 u32 pin_base;
114 u8 nr_pins;
115 char *name;
116 u8 bank_num;
Heiko Stübnerfc72c922014-06-16 01:36:05 +0200117 struct rockchip_iomux iomux[4];
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200118 bool valid;
119 struct device_node *of_node;
120 struct rockchip_pinctrl *drvdata;
121 struct irq_domain *domain;
122 struct gpio_chip gpio_chip;
123 struct pinctrl_gpio_range grange;
124 spinlock_t slock;
Heiko Stübner5a927502013-10-16 01:09:08 +0200125 u32 toggle_edge_mode;
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200126};
127
128#define PIN_BANK(id, pins, label) \
129 { \
130 .bank_num = id, \
131 .nr_pins = pins, \
132 .name = label, \
Heiko Stübner6bc0d1212014-06-16 01:36:33 +0200133 .iomux = { \
134 { .offset = -1 }, \
135 { .offset = -1 }, \
136 { .offset = -1 }, \
137 { .offset = -1 }, \
138 }, \
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200139 }
140
Heiko Stübnerfc72c922014-06-16 01:36:05 +0200141#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
142 { \
143 .bank_num = id, \
144 .nr_pins = pins, \
145 .name = label, \
146 .iomux = { \
Heiko Stübner6bc0d1212014-06-16 01:36:33 +0200147 { .type = iom0, .offset = -1 }, \
148 { .type = iom1, .offset = -1 }, \
149 { .type = iom2, .offset = -1 }, \
150 { .type = iom3, .offset = -1 }, \
Heiko Stübnerfc72c922014-06-16 01:36:05 +0200151 }, \
152 }
153
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200154/**
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200155 */
156struct rockchip_pin_ctrl {
157 struct rockchip_pin_bank *pin_banks;
158 u32 nr_banks;
159 u32 nr_pins;
160 char *label;
Heiko Stübnera2829262013-10-16 01:07:20 +0200161 enum rockchip_pinctrl_type type;
Heiko Stübner95ec8ae2014-06-16 01:37:23 +0200162 int grf_mux_offset;
163 int pmu_mux_offset;
Heiko Stübner751a99a2014-05-05 13:58:20 +0200164 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
165 int pin_num, struct regmap **regmap,
166 int *reg, u8 *bit);
Heiko Stübneref17f692015-06-12 23:50:11 +0200167 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
168 int pin_num, struct regmap **regmap,
169 int *reg, u8 *bit);
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200170};
171
172struct rockchip_pin_config {
173 unsigned int func;
174 unsigned long *configs;
175 unsigned int nconfigs;
176};
177
178/**
179 * struct rockchip_pin_group: represent group of pins of a pinmux function.
180 * @name: name of the pin group, used to lookup the group.
181 * @pins: the pins included in this group.
182 * @npins: number of pins included in this group.
183 * @func: the mux function number to be programmed when selected.
184 * @configs: the config values to be set for each pin
185 * @nconfigs: number of configs for each pin
186 */
187struct rockchip_pin_group {
188 const char *name;
189 unsigned int npins;
190 unsigned int *pins;
191 struct rockchip_pin_config *data;
192};
193
194/**
195 * struct rockchip_pmx_func: represent a pin function.
196 * @name: name of the pin function, used to lookup the function.
197 * @groups: one or more names of pin groups that provide this function.
198 * @num_groups: number of groups included in @groups.
199 */
200struct rockchip_pmx_func {
201 const char *name;
202 const char **groups;
203 u8 ngroups;
204};
205
206struct rockchip_pinctrl {
Heiko Stübner751a99a2014-05-05 13:58:20 +0200207 struct regmap *regmap_base;
Heiko Stübnerbfc7a422014-05-05 13:58:00 +0200208 int reg_size;
Heiko Stübner751a99a2014-05-05 13:58:20 +0200209 struct regmap *regmap_pull;
Heiko Stübner14dee862014-05-05 13:59:09 +0200210 struct regmap *regmap_pmu;
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200211 struct device *dev;
212 struct rockchip_pin_ctrl *ctrl;
213 struct pinctrl_desc pctl;
214 struct pinctrl_dev *pctl_dev;
215 struct rockchip_pin_group *groups;
216 unsigned int ngroups;
217 struct rockchip_pmx_func *functions;
218 unsigned int nfunctions;
219};
220
Heiko Stübner751a99a2014-05-05 13:58:20 +0200221static struct regmap_config rockchip_regmap_config = {
222 .reg_bits = 32,
223 .val_bits = 32,
224 .reg_stride = 4,
225};
226
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200227static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
228{
229 return container_of(gc, struct rockchip_pin_bank, gpio_chip);
230}
231
232static const inline struct rockchip_pin_group *pinctrl_name_to_group(
233 const struct rockchip_pinctrl *info,
234 const char *name)
235{
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200236 int i;
237
238 for (i = 0; i < info->ngroups; i++) {
Axel Lin1cb95392013-08-21 10:28:50 +0800239 if (!strcmp(info->groups[i].name, name))
240 return &info->groups[i];
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200241 }
242
Axel Lin1cb95392013-08-21 10:28:50 +0800243 return NULL;
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200244}
245
246/*
247 * given a pin number that is local to a pin controller, find out the pin bank
248 * and the register base of the pin bank.
249 */
250static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
251 unsigned pin)
252{
253 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
254
Axel Lin51578b92013-08-23 15:49:00 +0800255 while (pin >= (b->pin_base + b->nr_pins))
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200256 b++;
257
258 return b;
259}
260
261static struct rockchip_pin_bank *bank_num_to_bank(
262 struct rockchip_pinctrl *info,
263 unsigned num)
264{
265 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
266 int i;
267
Axel Lin1cb95392013-08-21 10:28:50 +0800268 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200269 if (b->bank_num == num)
Axel Lin1cb95392013-08-21 10:28:50 +0800270 return b;
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200271 }
272
Axel Lin1cb95392013-08-21 10:28:50 +0800273 return ERR_PTR(-EINVAL);
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200274}
275
276/*
277 * Pinctrl_ops handling
278 */
279
280static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
281{
282 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
283
284 return info->ngroups;
285}
286
287static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
288 unsigned selector)
289{
290 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
291
292 return info->groups[selector].name;
293}
294
295static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
296 unsigned selector, const unsigned **pins,
297 unsigned *npins)
298{
299 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
300
301 if (selector >= info->ngroups)
302 return -EINVAL;
303
304 *pins = info->groups[selector].pins;
305 *npins = info->groups[selector].npins;
306
307 return 0;
308}
309
310static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
311 struct device_node *np,
312 struct pinctrl_map **map, unsigned *num_maps)
313{
314 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
315 const struct rockchip_pin_group *grp;
316 struct pinctrl_map *new_map;
317 struct device_node *parent;
318 int map_num = 1;
319 int i;
320
321 /*
322 * first find the group of this node and check if we need to create
323 * config maps for pins
324 */
325 grp = pinctrl_name_to_group(info, np->name);
326 if (!grp) {
327 dev_err(info->dev, "unable to find group for node %s\n",
328 np->name);
329 return -EINVAL;
330 }
331
332 map_num += grp->npins;
333 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
334 GFP_KERNEL);
335 if (!new_map)
336 return -ENOMEM;
337
338 *map = new_map;
339 *num_maps = map_num;
340
341 /* create mux map */
342 parent = of_get_parent(np);
343 if (!parent) {
344 devm_kfree(pctldev->dev, new_map);
345 return -EINVAL;
346 }
347 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
348 new_map[0].data.mux.function = parent->name;
349 new_map[0].data.mux.group = np->name;
350 of_node_put(parent);
351
352 /* create config map */
353 new_map++;
354 for (i = 0; i < grp->npins; i++) {
355 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
356 new_map[i].data.configs.group_or_pin =
357 pin_get_name(pctldev, grp->pins[i]);
358 new_map[i].data.configs.configs = grp->data[i].configs;
359 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
360 }
361
362 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
363 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
364
365 return 0;
366}
367
368static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
369 struct pinctrl_map *map, unsigned num_maps)
370{
371}
372
373static const struct pinctrl_ops rockchip_pctrl_ops = {
374 .get_groups_count = rockchip_get_groups_count,
375 .get_group_name = rockchip_get_group_name,
376 .get_group_pins = rockchip_get_group_pins,
377 .dt_node_to_map = rockchip_dt_node_to_map,
378 .dt_free_map = rockchip_dt_free_map,
379};
380
381/*
382 * Hardware access
383 */
384
Heiko Stübnera076e2e2014-04-23 14:28:59 +0200385static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
386{
387 struct rockchip_pinctrl *info = bank->drvdata;
Heiko Stübnerfc72c922014-06-16 01:36:05 +0200388 int iomux_num = (pin / 8);
Heiko Stübner95ec8ae2014-06-16 01:37:23 +0200389 struct regmap *regmap;
Heiko Stübner751a99a2014-05-05 13:58:20 +0200390 unsigned int val;
Heiko Stübner03716e12014-06-16 01:36:57 +0200391 int reg, ret, mask;
Heiko Stübnera076e2e2014-04-23 14:28:59 +0200392 u8 bit;
393
Heiko Stübnerfc72c922014-06-16 01:36:05 +0200394 if (iomux_num > 3)
395 return -EINVAL;
396
Heiko Stübner62f49222014-06-16 01:37:49 +0200397 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
398 dev_err(info->dev, "pin %d is unrouted\n", pin);
399 return -EINVAL;
400 }
401
Heiko Stübnerfc72c922014-06-16 01:36:05 +0200402 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
Heiko Stübnera076e2e2014-04-23 14:28:59 +0200403 return RK_FUNC_GPIO;
404
Heiko Stübner95ec8ae2014-06-16 01:37:23 +0200405 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
406 ? info->regmap_pmu : info->regmap_base;
407
Heiko Stübnera076e2e2014-04-23 14:28:59 +0200408 /* get basic quadrupel of mux registers and the correct reg inside */
Heiko Stübner03716e12014-06-16 01:36:57 +0200409 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
Heiko Stübner6bc0d1212014-06-16 01:36:33 +0200410 reg = bank->iomux[iomux_num].offset;
Heiko Stübner03716e12014-06-16 01:36:57 +0200411 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
412 if ((pin % 8) >= 4)
413 reg += 0x4;
414 bit = (pin % 4) * 4;
415 } else {
416 bit = (pin % 8) * 2;
417 }
Heiko Stübnera076e2e2014-04-23 14:28:59 +0200418
Heiko Stübner95ec8ae2014-06-16 01:37:23 +0200419 ret = regmap_read(regmap, reg, &val);
Heiko Stübner751a99a2014-05-05 13:58:20 +0200420 if (ret)
421 return ret;
422
Heiko Stübner03716e12014-06-16 01:36:57 +0200423 return ((val >> bit) & mask);
Heiko Stübnera076e2e2014-04-23 14:28:59 +0200424}
425
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200426/*
427 * Set a new mux function for a pin.
428 *
429 * The register is divided into the upper and lower 16 bit. When changing
430 * a value, the previous register value is not read and changed. Instead
431 * it seems the changed bits are marked in the upper 16 bit, while the
432 * changed value gets set in the same offset in the lower 16 bit.
433 * All pin settings seem to be 2 bit wide in both the upper and lower
434 * parts.
435 * @bank: pin bank to change
436 * @pin: pin to change
437 * @mux: new mux function to set
438 */
Heiko Stübner14797182014-03-26 00:57:00 +0100439static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200440{
441 struct rockchip_pinctrl *info = bank->drvdata;
Heiko Stübnerfc72c922014-06-16 01:36:05 +0200442 int iomux_num = (pin / 8);
Heiko Stübner95ec8ae2014-06-16 01:37:23 +0200443 struct regmap *regmap;
Heiko Stübner03716e12014-06-16 01:36:57 +0200444 int reg, ret, mask;
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200445 unsigned long flags;
446 u8 bit;
Sonny Rao99e872d2014-07-31 22:58:00 -0700447 u32 data, rmask;
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200448
Heiko Stübnerfc72c922014-06-16 01:36:05 +0200449 if (iomux_num > 3)
450 return -EINVAL;
451
Heiko Stübner62f49222014-06-16 01:37:49 +0200452 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
453 dev_err(info->dev, "pin %d is unrouted\n", pin);
454 return -EINVAL;
455 }
456
Heiko Stübnerfc72c922014-06-16 01:36:05 +0200457 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
Heiko Stübnerc4a532de2014-03-26 00:57:52 +0100458 if (mux != RK_FUNC_GPIO) {
459 dev_err(info->dev,
460 "pin %d only supports a gpio mux\n", pin);
461 return -ENOTSUPP;
462 } else {
463 return 0;
464 }
465 }
466
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200467 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
468 bank->bank_num, pin, mux);
469
Heiko Stübner95ec8ae2014-06-16 01:37:23 +0200470 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
471 ? info->regmap_pmu : info->regmap_base;
472
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200473 /* get basic quadrupel of mux registers and the correct reg inside */
Heiko Stübner03716e12014-06-16 01:36:57 +0200474 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
Heiko Stübner6bc0d1212014-06-16 01:36:33 +0200475 reg = bank->iomux[iomux_num].offset;
Heiko Stübner03716e12014-06-16 01:36:57 +0200476 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
477 if ((pin % 8) >= 4)
478 reg += 0x4;
479 bit = (pin % 4) * 4;
480 } else {
481 bit = (pin % 8) * 2;
482 }
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200483
484 spin_lock_irqsave(&bank->slock, flags);
485
Heiko Stübner03716e12014-06-16 01:36:57 +0200486 data = (mask << (bit + 16));
Sonny Rao99e872d2014-07-31 22:58:00 -0700487 rmask = data | (data >> 16);
Heiko Stübner03716e12014-06-16 01:36:57 +0200488 data |= (mux & mask) << bit;
Sonny Rao99e872d2014-07-31 22:58:00 -0700489 ret = regmap_update_bits(regmap, reg, rmask, data);
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200490
491 spin_unlock_irqrestore(&bank->slock, flags);
Heiko Stübner14797182014-03-26 00:57:00 +0100492
Heiko Stübner751a99a2014-05-05 13:58:20 +0200493 return ret;
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200494}
495
Heiko Stübnera2829262013-10-16 01:07:20 +0200496#define RK2928_PULL_OFFSET 0x118
497#define RK2928_PULL_PINS_PER_REG 16
498#define RK2928_PULL_BANK_STRIDE 8
499
500static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
Heiko Stübner751a99a2014-05-05 13:58:20 +0200501 int pin_num, struct regmap **regmap,
502 int *reg, u8 *bit)
Heiko Stübnera2829262013-10-16 01:07:20 +0200503{
504 struct rockchip_pinctrl *info = bank->drvdata;
505
Heiko Stübner751a99a2014-05-05 13:58:20 +0200506 *regmap = info->regmap_base;
507 *reg = RK2928_PULL_OFFSET;
Heiko Stübnera2829262013-10-16 01:07:20 +0200508 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
509 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
510
511 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
512};
513
Heiko Stübnerbfc7a422014-05-05 13:58:00 +0200514#define RK3188_PULL_OFFSET 0x164
Heiko Stübner6ca52742013-10-16 01:08:42 +0200515#define RK3188_PULL_BITS_PER_PIN 2
516#define RK3188_PULL_PINS_PER_REG 8
517#define RK3188_PULL_BANK_STRIDE 16
Heiko Stübner14dee862014-05-05 13:59:09 +0200518#define RK3188_PULL_PMU_OFFSET 0x64
Heiko Stübner6ca52742013-10-16 01:08:42 +0200519
520static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
Heiko Stübner751a99a2014-05-05 13:58:20 +0200521 int pin_num, struct regmap **regmap,
522 int *reg, u8 *bit)
Heiko Stübner6ca52742013-10-16 01:08:42 +0200523{
524 struct rockchip_pinctrl *info = bank->drvdata;
525
526 /* The first 12 pins of the first bank are located elsewhere */
Heiko Stübnerfc72c922014-06-16 01:36:05 +0200527 if (bank->bank_num == 0 && pin_num < 12) {
Heiko Stübner14dee862014-05-05 13:59:09 +0200528 *regmap = info->regmap_pmu ? info->regmap_pmu
529 : bank->regmap_pull;
530 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
Heiko Stübner751a99a2014-05-05 13:58:20 +0200531 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
Heiko Stübner6ca52742013-10-16 01:08:42 +0200532 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
533 *bit *= RK3188_PULL_BITS_PER_PIN;
534 } else {
Heiko Stübner751a99a2014-05-05 13:58:20 +0200535 *regmap = info->regmap_pull ? info->regmap_pull
536 : info->regmap_base;
537 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
538
Heiko Stübnerbfc7a422014-05-05 13:58:00 +0200539 /* correct the offset, as it is the 2nd pull register */
540 *reg -= 4;
Heiko Stübner6ca52742013-10-16 01:08:42 +0200541 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
542 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
543
544 /*
545 * The bits in these registers have an inverse ordering
546 * with the lowest pin being in bits 15:14 and the highest
547 * pin in bits 1:0
548 */
549 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
550 *bit *= RK3188_PULL_BITS_PER_PIN;
551 }
552}
553
Heiko Stübner304f0772014-06-16 01:38:14 +0200554#define RK3288_PULL_OFFSET 0x140
555static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
556 int pin_num, struct regmap **regmap,
557 int *reg, u8 *bit)
558{
559 struct rockchip_pinctrl *info = bank->drvdata;
560
561 /* The first 24 pins of the first bank are located in PMU */
562 if (bank->bank_num == 0) {
563 *regmap = info->regmap_pmu;
564 *reg = RK3188_PULL_PMU_OFFSET;
565
566 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
567 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
568 *bit *= RK3188_PULL_BITS_PER_PIN;
569 } else {
570 *regmap = info->regmap_base;
571 *reg = RK3288_PULL_OFFSET;
572
573 /* correct the offset, as we're starting with the 2nd bank */
574 *reg -= 0x10;
575 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
576 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
577
578 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
579 *bit *= RK3188_PULL_BITS_PER_PIN;
580 }
581}
582
Heiko Stübnerb547c802014-07-20 01:50:11 +0200583#define RK3288_DRV_PMU_OFFSET 0x70
584#define RK3288_DRV_GRF_OFFSET 0x1c0
585#define RK3288_DRV_BITS_PER_PIN 2
586#define RK3288_DRV_PINS_PER_REG 8
587#define RK3288_DRV_BANK_STRIDE 16
Heiko Stübnerb547c802014-07-20 01:50:11 +0200588
589static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
590 int pin_num, struct regmap **regmap,
591 int *reg, u8 *bit)
592{
593 struct rockchip_pinctrl *info = bank->drvdata;
594
595 /* The first 24 pins of the first bank are located in PMU */
596 if (bank->bank_num == 0) {
597 *regmap = info->regmap_pmu;
598 *reg = RK3288_DRV_PMU_OFFSET;
599
600 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
601 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
602 *bit *= RK3288_DRV_BITS_PER_PIN;
603 } else {
604 *regmap = info->regmap_base;
605 *reg = RK3288_DRV_GRF_OFFSET;
606
607 /* correct the offset, as we're starting with the 2nd bank */
608 *reg -= 0x10;
609 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
610 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
611
612 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
613 *bit *= RK3288_DRV_BITS_PER_PIN;
614 }
615}
616
Heiko Stübnerdaecdc62015-06-12 23:51:01 +0200617#define RK3368_PULL_GRF_OFFSET 0x100
618#define RK3368_PULL_PMU_OFFSET 0x10
619
620static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
621 int pin_num, struct regmap **regmap,
622 int *reg, u8 *bit)
623{
624 struct rockchip_pinctrl *info = bank->drvdata;
625
626 /* The first 32 pins of the first bank are located in PMU */
627 if (bank->bank_num == 0) {
628 *regmap = info->regmap_pmu;
629 *reg = RK3368_PULL_PMU_OFFSET;
630
631 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
632 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
633 *bit *= RK3188_PULL_BITS_PER_PIN;
634 } else {
635 *regmap = info->regmap_base;
636 *reg = RK3368_PULL_GRF_OFFSET;
637
638 /* correct the offset, as we're starting with the 2nd bank */
639 *reg -= 0x10;
640 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
641 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
642
643 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
644 *bit *= RK3188_PULL_BITS_PER_PIN;
645 }
646}
647
648#define RK3368_DRV_PMU_OFFSET 0x20
649#define RK3368_DRV_GRF_OFFSET 0x200
650
651static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
652 int pin_num, struct regmap **regmap,
653 int *reg, u8 *bit)
654{
655 struct rockchip_pinctrl *info = bank->drvdata;
656
657 /* The first 32 pins of the first bank are located in PMU */
658 if (bank->bank_num == 0) {
659 *regmap = info->regmap_pmu;
660 *reg = RK3368_DRV_PMU_OFFSET;
661
662 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
663 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
664 *bit *= RK3288_DRV_BITS_PER_PIN;
665 } else {
666 *regmap = info->regmap_base;
667 *reg = RK3368_DRV_GRF_OFFSET;
668
669 /* correct the offset, as we're starting with the 2nd bank */
670 *reg -= 0x10;
671 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
672 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
673
674 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
675 *bit *= RK3288_DRV_BITS_PER_PIN;
676 }
677}
678
Heiko Stübneref17f692015-06-12 23:50:11 +0200679static int rockchip_perpin_drv_list[] = { 2, 4, 8, 12 };
680
681static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
682 int pin_num)
Heiko Stübnerb547c802014-07-20 01:50:11 +0200683{
Heiko Stübneref17f692015-06-12 23:50:11 +0200684 struct rockchip_pinctrl *info = bank->drvdata;
685 struct rockchip_pin_ctrl *ctrl = info->ctrl;
Heiko Stübnerb547c802014-07-20 01:50:11 +0200686 struct regmap *regmap;
687 int reg, ret;
688 u32 data;
689 u8 bit;
690
Heiko Stübneref17f692015-06-12 23:50:11 +0200691 ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
Heiko Stübnerb547c802014-07-20 01:50:11 +0200692
693 ret = regmap_read(regmap, reg, &data);
694 if (ret)
695 return ret;
696
697 data >>= bit;
698 data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1;
699
Heiko Stübneref17f692015-06-12 23:50:11 +0200700 return rockchip_perpin_drv_list[data];
Heiko Stübnerb547c802014-07-20 01:50:11 +0200701}
702
Heiko Stübneref17f692015-06-12 23:50:11 +0200703static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
704 int pin_num, int strength)
Heiko Stübnerb547c802014-07-20 01:50:11 +0200705{
706 struct rockchip_pinctrl *info = bank->drvdata;
Heiko Stübneref17f692015-06-12 23:50:11 +0200707 struct rockchip_pin_ctrl *ctrl = info->ctrl;
Heiko Stübnerb547c802014-07-20 01:50:11 +0200708 struct regmap *regmap;
709 unsigned long flags;
710 int reg, ret, i;
Sonny Rao99e872d2014-07-31 22:58:00 -0700711 u32 data, rmask;
Heiko Stübnerb547c802014-07-20 01:50:11 +0200712 u8 bit;
713
Heiko Stübneref17f692015-06-12 23:50:11 +0200714 ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
Heiko Stübnerb547c802014-07-20 01:50:11 +0200715
716 ret = -EINVAL;
Heiko Stübneref17f692015-06-12 23:50:11 +0200717 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list); i++) {
718 if (rockchip_perpin_drv_list[i] == strength) {
Heiko Stübnerb547c802014-07-20 01:50:11 +0200719 ret = i;
720 break;
721 }
722 }
723
724 if (ret < 0) {
725 dev_err(info->dev, "unsupported driver strength %d\n",
726 strength);
727 return ret;
728 }
729
730 spin_lock_irqsave(&bank->slock, flags);
731
732 /* enable the write to the equivalent lower bits */
733 data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16);
Sonny Rao99e872d2014-07-31 22:58:00 -0700734 rmask = data | (data >> 16);
Heiko Stübnerb547c802014-07-20 01:50:11 +0200735 data |= (ret << bit);
736
Sonny Rao99e872d2014-07-31 22:58:00 -0700737 ret = regmap_update_bits(regmap, reg, rmask, data);
Heiko Stübnerb547c802014-07-20 01:50:11 +0200738 spin_unlock_irqrestore(&bank->slock, flags);
739
740 return ret;
741}
742
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200743static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
744{
745 struct rockchip_pinctrl *info = bank->drvdata;
746 struct rockchip_pin_ctrl *ctrl = info->ctrl;
Heiko Stübner751a99a2014-05-05 13:58:20 +0200747 struct regmap *regmap;
748 int reg, ret;
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200749 u8 bit;
Heiko Stübner6ca52742013-10-16 01:08:42 +0200750 u32 data;
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200751
752 /* rk3066b does support any pulls */
Heiko Stübnera2829262013-10-16 01:07:20 +0200753 if (ctrl->type == RK3066B)
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200754 return PIN_CONFIG_BIAS_DISABLE;
755
Heiko Stübner751a99a2014-05-05 13:58:20 +0200756 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
757
758 ret = regmap_read(regmap, reg, &data);
759 if (ret)
760 return ret;
Heiko Stübner6ca52742013-10-16 01:08:42 +0200761
Heiko Stübnera2829262013-10-16 01:07:20 +0200762 switch (ctrl->type) {
763 case RK2928:
Heiko Stübner751a99a2014-05-05 13:58:20 +0200764 return !(data & BIT(bit))
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200765 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
766 : PIN_CONFIG_BIAS_DISABLE;
Heiko Stübnera2829262013-10-16 01:07:20 +0200767 case RK3188:
Heiko Stübner66d750e2014-07-20 01:49:17 +0200768 case RK3288:
Heiko Stübnerdaecdc62015-06-12 23:51:01 +0200769 case RK3368:
Heiko Stübner751a99a2014-05-05 13:58:20 +0200770 data >>= bit;
Heiko Stübner6ca52742013-10-16 01:08:42 +0200771 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
772
773 switch (data) {
774 case 0:
775 return PIN_CONFIG_BIAS_DISABLE;
776 case 1:
777 return PIN_CONFIG_BIAS_PULL_UP;
778 case 2:
779 return PIN_CONFIG_BIAS_PULL_DOWN;
780 case 3:
781 return PIN_CONFIG_BIAS_BUS_HOLD;
782 }
783
784 dev_err(info->dev, "unknown pull setting\n");
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200785 return -EIO;
Heiko Stübnera2829262013-10-16 01:07:20 +0200786 default:
787 dev_err(info->dev, "unsupported pinctrl type\n");
788 return -EINVAL;
789 };
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200790}
791
792static int rockchip_set_pull(struct rockchip_pin_bank *bank,
793 int pin_num, int pull)
794{
795 struct rockchip_pinctrl *info = bank->drvdata;
796 struct rockchip_pin_ctrl *ctrl = info->ctrl;
Heiko Stübner751a99a2014-05-05 13:58:20 +0200797 struct regmap *regmap;
798 int reg, ret;
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200799 unsigned long flags;
800 u8 bit;
Sonny Rao99e872d2014-07-31 22:58:00 -0700801 u32 data, rmask;
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200802
803 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
804 bank->bank_num, pin_num, pull);
805
806 /* rk3066b does support any pulls */
Heiko Stübnera2829262013-10-16 01:07:20 +0200807 if (ctrl->type == RK3066B)
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200808 return pull ? -EINVAL : 0;
809
Heiko Stübner751a99a2014-05-05 13:58:20 +0200810 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
Heiko Stübner6ca52742013-10-16 01:08:42 +0200811
Heiko Stübnera2829262013-10-16 01:07:20 +0200812 switch (ctrl->type) {
813 case RK2928:
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200814 spin_lock_irqsave(&bank->slock, flags);
815
816 data = BIT(bit + 16);
817 if (pull == PIN_CONFIG_BIAS_DISABLE)
818 data |= BIT(bit);
Heiko Stübner751a99a2014-05-05 13:58:20 +0200819 ret = regmap_write(regmap, reg, data);
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200820
821 spin_unlock_irqrestore(&bank->slock, flags);
Heiko Stübnera2829262013-10-16 01:07:20 +0200822 break;
823 case RK3188:
Heiko Stübner66d750e2014-07-20 01:49:17 +0200824 case RK3288:
Heiko Stübnerdaecdc62015-06-12 23:51:01 +0200825 case RK3368:
Heiko Stübner6ca52742013-10-16 01:08:42 +0200826 spin_lock_irqsave(&bank->slock, flags);
827
828 /* enable the write to the equivalent lower bits */
829 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
Sonny Rao99e872d2014-07-31 22:58:00 -0700830 rmask = data | (data >> 16);
Heiko Stübner6ca52742013-10-16 01:08:42 +0200831
832 switch (pull) {
833 case PIN_CONFIG_BIAS_DISABLE:
834 break;
835 case PIN_CONFIG_BIAS_PULL_UP:
836 data |= (1 << bit);
837 break;
838 case PIN_CONFIG_BIAS_PULL_DOWN:
839 data |= (2 << bit);
840 break;
841 case PIN_CONFIG_BIAS_BUS_HOLD:
842 data |= (3 << bit);
843 break;
844 default:
Dan Carpenterd32c3e22013-11-14 11:22:54 +0300845 spin_unlock_irqrestore(&bank->slock, flags);
Heiko Stübner6ca52742013-10-16 01:08:42 +0200846 dev_err(info->dev, "unsupported pull setting %d\n",
847 pull);
848 return -EINVAL;
849 }
850
Sonny Rao99e872d2014-07-31 22:58:00 -0700851 ret = regmap_update_bits(regmap, reg, rmask, data);
Heiko Stübner6ca52742013-10-16 01:08:42 +0200852
853 spin_unlock_irqrestore(&bank->slock, flags);
854 break;
Heiko Stübnera2829262013-10-16 01:07:20 +0200855 default:
856 dev_err(info->dev, "unsupported pinctrl type\n");
857 return -EINVAL;
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200858 }
859
Heiko Stübner751a99a2014-05-05 13:58:20 +0200860 return ret;
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200861}
862
863/*
864 * Pinmux_ops handling
865 */
866
867static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
868{
869 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
870
871 return info->nfunctions;
872}
873
874static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
875 unsigned selector)
876{
877 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
878
879 return info->functions[selector].name;
880}
881
882static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
883 unsigned selector, const char * const **groups,
884 unsigned * const num_groups)
885{
886 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
887
888 *groups = info->functions[selector].groups;
889 *num_groups = info->functions[selector].ngroups;
890
891 return 0;
892}
893
Linus Walleij03e9f0c2014-09-03 13:02:56 +0200894static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
895 unsigned group)
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200896{
897 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
898 const unsigned int *pins = info->groups[group].pins;
899 const struct rockchip_pin_config *data = info->groups[group].data;
900 struct rockchip_pin_bank *bank;
Heiko Stübner14797182014-03-26 00:57:00 +0100901 int cnt, ret = 0;
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200902
903 dev_dbg(info->dev, "enable function %s group %s\n",
904 info->functions[selector].name, info->groups[group].name);
905
906 /*
907 * for each pin in the pin group selected, program the correspoding pin
908 * pin function number in the config register.
909 */
910 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
911 bank = pin_to_bank(info, pins[cnt]);
Heiko Stübner14797182014-03-26 00:57:00 +0100912 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
913 data[cnt].func);
914 if (ret)
915 break;
916 }
917
918 if (ret) {
919 /* revert the already done pin settings */
920 for (cnt--; cnt >= 0; cnt--)
921 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
922
923 return ret;
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200924 }
925
926 return 0;
927}
928
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200929/*
930 * The calls to gpio_direction_output() and gpio_direction_input()
931 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
932 * function called from the gpiolib interface).
933 */
Doug Andersone5c2c9d2014-10-21 10:47:33 -0700934static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
935 int pin, bool input)
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200936{
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200937 struct rockchip_pin_bank *bank;
Doug Andersone5c2c9d2014-10-21 10:47:33 -0700938 int ret;
Doug Andersonfab262f2014-10-21 10:47:35 -0700939 unsigned long flags;
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200940 u32 data;
941
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200942 bank = gc_to_pin_bank(chip);
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200943
Heiko Stübner14797182014-03-26 00:57:00 +0100944 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
945 if (ret < 0)
946 return ret;
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200947
Lin Huang07a06ae2015-08-11 18:12:04 +0800948 clk_enable(bank->clk);
Doug Andersonfab262f2014-10-21 10:47:35 -0700949 spin_lock_irqsave(&bank->slock, flags);
950
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200951 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
952 /* set bit to 1 for output, 0 for input */
953 if (!input)
954 data |= BIT(pin);
955 else
956 data &= ~BIT(pin);
957 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
958
Doug Andersonfab262f2014-10-21 10:47:35 -0700959 spin_unlock_irqrestore(&bank->slock, flags);
Lin Huang07a06ae2015-08-11 18:12:04 +0800960 clk_disable(bank->clk);
Doug Andersonfab262f2014-10-21 10:47:35 -0700961
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200962 return 0;
963}
964
Doug Andersone5c2c9d2014-10-21 10:47:33 -0700965static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
966 struct pinctrl_gpio_range *range,
967 unsigned offset, bool input)
968{
969 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
970 struct gpio_chip *chip;
971 int pin;
972
973 chip = range->gc;
974 pin = offset - chip->base;
975 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
976 offset, range->name, pin, input ? "input" : "output");
977
978 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
979 input);
980}
981
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200982static const struct pinmux_ops rockchip_pmx_ops = {
983 .get_functions_count = rockchip_pmx_get_funcs_count,
984 .get_function_name = rockchip_pmx_get_func_name,
985 .get_function_groups = rockchip_pmx_get_groups,
Linus Walleij03e9f0c2014-09-03 13:02:56 +0200986 .set_mux = rockchip_pmx_set,
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200987 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
988};
989
990/*
991 * Pinconf_ops handling
992 */
993
Heiko Stübner44b6d932013-06-16 17:41:16 +0200994static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
995 enum pin_config_param pull)
996{
Heiko Stübnera2829262013-10-16 01:07:20 +0200997 switch (ctrl->type) {
998 case RK2928:
999 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
1000 pull == PIN_CONFIG_BIAS_DISABLE);
1001 case RK3066B:
Heiko Stübner44b6d932013-06-16 17:41:16 +02001002 return pull ? false : true;
Heiko Stübnera2829262013-10-16 01:07:20 +02001003 case RK3188:
Heiko Stübner66d750e2014-07-20 01:49:17 +02001004 case RK3288:
Heiko Stübnerdaecdc62015-06-12 23:51:01 +02001005 case RK3368:
Heiko Stübnera2829262013-10-16 01:07:20 +02001006 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
Heiko Stübner44b6d932013-06-16 17:41:16 +02001007 }
1008
Heiko Stübnera2829262013-10-16 01:07:20 +02001009 return false;
Heiko Stübner44b6d932013-06-16 17:41:16 +02001010}
1011
Doug Andersone5c2c9d2014-10-21 10:47:33 -07001012static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
Heiko Stübnera076e2e2014-04-23 14:28:59 +02001013static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
1014
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001015/* set the pin config settings for a specified pin */
1016static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
Sherman Yin03b054e2013-08-27 11:32:12 -07001017 unsigned long *configs, unsigned num_configs)
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001018{
1019 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1020 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
Sherman Yin03b054e2013-08-27 11:32:12 -07001021 enum pin_config_param param;
1022 u16 arg;
1023 int i;
1024 int rc;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001025
Sherman Yin03b054e2013-08-27 11:32:12 -07001026 for (i = 0; i < num_configs; i++) {
1027 param = pinconf_to_config_param(configs[i]);
1028 arg = pinconf_to_config_argument(configs[i]);
1029
1030 switch (param) {
1031 case PIN_CONFIG_BIAS_DISABLE:
1032 rc = rockchip_set_pull(bank, pin - bank->pin_base,
1033 param);
1034 if (rc)
1035 return rc;
1036 break;
1037 case PIN_CONFIG_BIAS_PULL_UP:
1038 case PIN_CONFIG_BIAS_PULL_DOWN:
1039 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
Heiko Stübner6ca52742013-10-16 01:08:42 +02001040 case PIN_CONFIG_BIAS_BUS_HOLD:
Sherman Yin03b054e2013-08-27 11:32:12 -07001041 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1042 return -ENOTSUPP;
1043
1044 if (!arg)
1045 return -EINVAL;
1046
1047 rc = rockchip_set_pull(bank, pin - bank->pin_base,
1048 param);
1049 if (rc)
1050 return rc;
1051 break;
Heiko Stübnera076e2e2014-04-23 14:28:59 +02001052 case PIN_CONFIG_OUTPUT:
Doug Andersone5c2c9d2014-10-21 10:47:33 -07001053 rockchip_gpio_set(&bank->gpio_chip,
1054 pin - bank->pin_base, arg);
1055 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
1056 pin - bank->pin_base, false);
Heiko Stübnera076e2e2014-04-23 14:28:59 +02001057 if (rc)
1058 return rc;
1059 break;
Heiko Stübnerb547c802014-07-20 01:50:11 +02001060 case PIN_CONFIG_DRIVE_STRENGTH:
1061 /* rk3288 is the first with per-pin drive-strength */
Heiko Stübneref17f692015-06-12 23:50:11 +02001062 if (!info->ctrl->drv_calc_reg)
Heiko Stübnerb547c802014-07-20 01:50:11 +02001063 return -ENOTSUPP;
1064
Heiko Stübneref17f692015-06-12 23:50:11 +02001065 rc = rockchip_set_drive_perpin(bank,
1066 pin - bank->pin_base, arg);
Heiko Stübnerb547c802014-07-20 01:50:11 +02001067 if (rc < 0)
1068 return rc;
1069 break;
Sherman Yin03b054e2013-08-27 11:32:12 -07001070 default:
Heiko Stübner44b6d932013-06-16 17:41:16 +02001071 return -ENOTSUPP;
Sherman Yin03b054e2013-08-27 11:32:12 -07001072 break;
1073 }
1074 } /* for each config */
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001075
1076 return 0;
1077}
1078
1079/* get the pin config settings for a specified pin */
1080static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1081 unsigned long *config)
1082{
1083 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1084 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1085 enum pin_config_param param = pinconf_to_config_param(*config);
Heiko Stübnerdab3eba2014-04-23 14:27:51 +02001086 u16 arg;
Heiko Stübnera076e2e2014-04-23 14:28:59 +02001087 int rc;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001088
1089 switch (param) {
1090 case PIN_CONFIG_BIAS_DISABLE:
Heiko Stübner44b6d932013-06-16 17:41:16 +02001091 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001092 return -EINVAL;
1093
Heiko Stübnerdab3eba2014-04-23 14:27:51 +02001094 arg = 0;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001095 break;
Heiko Stübner44b6d932013-06-16 17:41:16 +02001096 case PIN_CONFIG_BIAS_PULL_UP:
1097 case PIN_CONFIG_BIAS_PULL_DOWN:
1098 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
Heiko Stübner6ca52742013-10-16 01:08:42 +02001099 case PIN_CONFIG_BIAS_BUS_HOLD:
Heiko Stübner44b6d932013-06-16 17:41:16 +02001100 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1101 return -ENOTSUPP;
1102
1103 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1104 return -EINVAL;
1105
Heiko Stübnerdab3eba2014-04-23 14:27:51 +02001106 arg = 1;
Heiko Stübner44b6d932013-06-16 17:41:16 +02001107 break;
Heiko Stübnera076e2e2014-04-23 14:28:59 +02001108 case PIN_CONFIG_OUTPUT:
1109 rc = rockchip_get_mux(bank, pin - bank->pin_base);
1110 if (rc != RK_FUNC_GPIO)
1111 return -EINVAL;
1112
1113 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
1114 if (rc < 0)
1115 return rc;
1116
1117 arg = rc ? 1 : 0;
1118 break;
Heiko Stübnerb547c802014-07-20 01:50:11 +02001119 case PIN_CONFIG_DRIVE_STRENGTH:
1120 /* rk3288 is the first with per-pin drive-strength */
Heiko Stübneref17f692015-06-12 23:50:11 +02001121 if (!info->ctrl->drv_calc_reg)
Heiko Stübnerb547c802014-07-20 01:50:11 +02001122 return -ENOTSUPP;
1123
Heiko Stübneref17f692015-06-12 23:50:11 +02001124 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
Heiko Stübnerb547c802014-07-20 01:50:11 +02001125 if (rc < 0)
1126 return rc;
1127
1128 arg = rc;
1129 break;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001130 default:
1131 return -ENOTSUPP;
1132 break;
1133 }
1134
Heiko Stübnerdab3eba2014-04-23 14:27:51 +02001135 *config = pinconf_to_config_packed(param, arg);
1136
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001137 return 0;
1138}
1139
1140static const struct pinconf_ops rockchip_pinconf_ops = {
1141 .pin_config_get = rockchip_pinconf_get,
1142 .pin_config_set = rockchip_pinconf_set,
Heiko Stübnered62f2f2014-07-20 01:48:45 +02001143 .is_generic = true,
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001144};
1145
Heiko Stübner65fca612013-10-16 01:07:49 +02001146static const struct of_device_id rockchip_bank_match[] = {
1147 { .compatible = "rockchip,gpio-bank" },
Heiko Stübner6ca52742013-10-16 01:08:42 +02001148 { .compatible = "rockchip,rk3188-gpio-bank0" },
Heiko Stübner65fca612013-10-16 01:07:49 +02001149 {},
1150};
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001151
1152static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
1153 struct device_node *np)
1154{
1155 struct device_node *child;
1156
1157 for_each_child_of_node(np, child) {
Heiko Stübner65fca612013-10-16 01:07:49 +02001158 if (of_match_node(rockchip_bank_match, child))
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001159 continue;
1160
1161 info->nfunctions++;
1162 info->ngroups += of_get_child_count(child);
1163 }
1164}
1165
1166static int rockchip_pinctrl_parse_groups(struct device_node *np,
1167 struct rockchip_pin_group *grp,
1168 struct rockchip_pinctrl *info,
1169 u32 index)
1170{
1171 struct rockchip_pin_bank *bank;
1172 int size;
1173 const __be32 *list;
1174 int num;
1175 int i, j;
1176 int ret;
1177
1178 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1179
1180 /* Initialise group */
1181 grp->name = np->name;
1182
1183 /*
1184 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
1185 * do sanity check and calculate pins number
1186 */
1187 list = of_get_property(np, "rockchip,pins", &size);
1188 /* we do not check return since it's safe node passed down */
1189 size /= sizeof(*list);
1190 if (!size || size % 4) {
1191 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1192 return -EINVAL;
1193 }
1194
1195 grp->npins = size / 4;
1196
1197 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1198 GFP_KERNEL);
1199 grp->data = devm_kzalloc(info->dev, grp->npins *
1200 sizeof(struct rockchip_pin_config),
1201 GFP_KERNEL);
1202 if (!grp->pins || !grp->data)
1203 return -ENOMEM;
1204
1205 for (i = 0, j = 0; i < size; i += 4, j++) {
1206 const __be32 *phandle;
1207 struct device_node *np_config;
1208
1209 num = be32_to_cpu(*list++);
1210 bank = bank_num_to_bank(info, num);
1211 if (IS_ERR(bank))
1212 return PTR_ERR(bank);
1213
1214 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
1215 grp->data[j].func = be32_to_cpu(*list++);
1216
1217 phandle = list++;
1218 if (!phandle)
1219 return -EINVAL;
1220
1221 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
Soren Brinkmanndd4d01f2015-01-09 07:43:46 -08001222 ret = pinconf_generic_parse_dt_config(np_config, NULL,
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001223 &grp->data[j].configs, &grp->data[j].nconfigs);
1224 if (ret)
1225 return ret;
1226 }
1227
1228 return 0;
1229}
1230
1231static int rockchip_pinctrl_parse_functions(struct device_node *np,
1232 struct rockchip_pinctrl *info,
1233 u32 index)
1234{
1235 struct device_node *child;
1236 struct rockchip_pmx_func *func;
1237 struct rockchip_pin_group *grp;
1238 int ret;
1239 static u32 grp_index;
1240 u32 i = 0;
1241
1242 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1243
1244 func = &info->functions[index];
1245
1246 /* Initialise function */
1247 func->name = np->name;
1248 func->ngroups = of_get_child_count(np);
1249 if (func->ngroups <= 0)
1250 return 0;
1251
1252 func->groups = devm_kzalloc(info->dev,
1253 func->ngroups * sizeof(char *), GFP_KERNEL);
1254 if (!func->groups)
1255 return -ENOMEM;
1256
1257 for_each_child_of_node(np, child) {
1258 func->groups[i] = child->name;
1259 grp = &info->groups[grp_index++];
1260 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
1261 if (ret)
1262 return ret;
1263 }
1264
1265 return 0;
1266}
1267
1268static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1269 struct rockchip_pinctrl *info)
1270{
1271 struct device *dev = &pdev->dev;
1272 struct device_node *np = dev->of_node;
1273 struct device_node *child;
1274 int ret;
1275 int i;
1276
1277 rockchip_pinctrl_child_count(info, np);
1278
1279 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1280 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1281
1282 info->functions = devm_kzalloc(dev, info->nfunctions *
1283 sizeof(struct rockchip_pmx_func),
1284 GFP_KERNEL);
1285 if (!info->functions) {
1286 dev_err(dev, "failed to allocate memory for function list\n");
1287 return -EINVAL;
1288 }
1289
1290 info->groups = devm_kzalloc(dev, info->ngroups *
1291 sizeof(struct rockchip_pin_group),
1292 GFP_KERNEL);
1293 if (!info->groups) {
1294 dev_err(dev, "failed allocate memory for ping group list\n");
1295 return -EINVAL;
1296 }
1297
1298 i = 0;
1299
1300 for_each_child_of_node(np, child) {
Heiko Stübner65fca612013-10-16 01:07:49 +02001301 if (of_match_node(rockchip_bank_match, child))
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001302 continue;
Heiko Stübner65fca612013-10-16 01:07:49 +02001303
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001304 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1305 if (ret) {
1306 dev_err(&pdev->dev, "failed to parse function\n");
1307 return ret;
1308 }
1309 }
1310
1311 return 0;
1312}
1313
1314static int rockchip_pinctrl_register(struct platform_device *pdev,
1315 struct rockchip_pinctrl *info)
1316{
1317 struct pinctrl_desc *ctrldesc = &info->pctl;
1318 struct pinctrl_pin_desc *pindesc, *pdesc;
1319 struct rockchip_pin_bank *pin_bank;
1320 int pin, bank, ret;
1321 int k;
1322
1323 ctrldesc->name = "rockchip-pinctrl";
1324 ctrldesc->owner = THIS_MODULE;
1325 ctrldesc->pctlops = &rockchip_pctrl_ops;
1326 ctrldesc->pmxops = &rockchip_pmx_ops;
1327 ctrldesc->confops = &rockchip_pinconf_ops;
1328
1329 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1330 info->ctrl->nr_pins, GFP_KERNEL);
1331 if (!pindesc) {
1332 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1333 return -ENOMEM;
1334 }
1335 ctrldesc->pins = pindesc;
1336 ctrldesc->npins = info->ctrl->nr_pins;
1337
1338 pdesc = pindesc;
1339 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1340 pin_bank = &info->ctrl->pin_banks[bank];
1341 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1342 pdesc->number = k;
1343 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1344 pin_bank->name, pin);
1345 pdesc++;
1346 }
1347 }
1348
Doug Anderson0fb7dcb2014-10-21 10:47:34 -07001349 ret = rockchip_pinctrl_parse_dt(pdev, info);
1350 if (ret)
1351 return ret;
1352
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001353 info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
Masahiro Yamada323de9e2015-06-09 13:01:16 +09001354 if (IS_ERR(info->pctl_dev)) {
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001355 dev_err(&pdev->dev, "could not register pinctrl driver\n");
Masahiro Yamada323de9e2015-06-09 13:01:16 +09001356 return PTR_ERR(info->pctl_dev);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001357 }
1358
1359 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1360 pin_bank = &info->ctrl->pin_banks[bank];
1361 pin_bank->grange.name = pin_bank->name;
1362 pin_bank->grange.id = bank;
1363 pin_bank->grange.pin_base = pin_bank->pin_base;
1364 pin_bank->grange.base = pin_bank->gpio_chip.base;
1365 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1366 pin_bank->grange.gc = &pin_bank->gpio_chip;
1367 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1368 }
1369
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001370 return 0;
1371}
1372
1373/*
1374 * GPIO handling
1375 */
1376
Axel Lin0351c282013-08-27 22:30:17 +08001377static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
1378{
1379 return pinctrl_request_gpio(chip->base + offset);
1380}
1381
1382static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
1383{
1384 pinctrl_free_gpio(chip->base + offset);
1385}
1386
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001387static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1388{
1389 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1390 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1391 unsigned long flags;
1392 u32 data;
1393
Lin Huang07a06ae2015-08-11 18:12:04 +08001394 clk_enable(bank->clk);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001395 spin_lock_irqsave(&bank->slock, flags);
1396
1397 data = readl(reg);
1398 data &= ~BIT(offset);
1399 if (value)
1400 data |= BIT(offset);
1401 writel(data, reg);
1402
1403 spin_unlock_irqrestore(&bank->slock, flags);
Lin Huang07a06ae2015-08-11 18:12:04 +08001404 clk_disable(bank->clk);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001405}
1406
1407/*
1408 * Returns the level of the pin for input direction and setting of the DR
1409 * register for output gpios.
1410 */
1411static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1412{
1413 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1414 u32 data;
1415
Lin Huang07a06ae2015-08-11 18:12:04 +08001416 clk_enable(bank->clk);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001417 data = readl(bank->reg_base + GPIO_EXT_PORT);
Lin Huang07a06ae2015-08-11 18:12:04 +08001418 clk_disable(bank->clk);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001419 data >>= offset;
1420 data &= 1;
1421 return data;
1422}
1423
1424/*
1425 * gpiolib gpio_direction_input callback function. The setting of the pin
1426 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1427 * interface.
1428 */
1429static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1430{
1431 return pinctrl_gpio_direction_input(gc->base + offset);
1432}
1433
1434/*
1435 * gpiolib gpio_direction_output callback function. The setting of the pin
1436 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1437 * interface.
1438 */
1439static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1440 unsigned offset, int value)
1441{
1442 rockchip_gpio_set(gc, offset, value);
1443 return pinctrl_gpio_direction_output(gc->base + offset);
1444}
1445
1446/*
1447 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1448 * and a virtual IRQ, if not already present.
1449 */
1450static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1451{
1452 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1453 unsigned int virq;
1454
1455 if (!bank->domain)
1456 return -ENXIO;
1457
1458 virq = irq_create_mapping(bank->domain, offset);
1459
1460 return (virq) ? : -ENXIO;
1461}
1462
1463static const struct gpio_chip rockchip_gpiolib_chip = {
Axel Lin0351c282013-08-27 22:30:17 +08001464 .request = rockchip_gpio_request,
1465 .free = rockchip_gpio_free,
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001466 .set = rockchip_gpio_set,
1467 .get = rockchip_gpio_get,
1468 .direction_input = rockchip_gpio_direction_input,
1469 .direction_output = rockchip_gpio_direction_output,
1470 .to_irq = rockchip_gpio_to_irq,
1471 .owner = THIS_MODULE,
1472};
1473
1474/*
1475 * Interrupt handling
1476 */
1477
Thomas Gleixner415f7482015-07-13 01:52:00 +02001478static void rockchip_irq_demux(unsigned int __irq, struct irq_desc *desc)
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001479{
Jiang Liu5663bb22015-06-04 12:13:16 +08001480 struct irq_chip *chip = irq_desc_get_chip(desc);
1481 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001482 u32 pend;
1483
1484 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1485
1486 chained_irq_enter(chip, desc);
1487
1488 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1489
1490 while (pend) {
Thomas Gleixner415f7482015-07-13 01:52:00 +02001491 unsigned int irq, virq;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001492
1493 irq = __ffs(pend);
1494 pend &= ~BIT(irq);
1495 virq = irq_linear_revmap(bank->domain, irq);
1496
1497 if (!virq) {
1498 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1499 continue;
1500 }
1501
1502 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1503
Heiko Stübner5a927502013-10-16 01:09:08 +02001504 /*
1505 * Triggering IRQ on both rising and falling edge
1506 * needs manual intervention.
1507 */
1508 if (bank->toggle_edge_mode & BIT(irq)) {
Doug Anderson53b1bfc2014-12-22 10:47:29 -08001509 u32 data, data_old, polarity;
1510 unsigned long flags;
Heiko Stübner5a927502013-10-16 01:09:08 +02001511
Doug Anderson53b1bfc2014-12-22 10:47:29 -08001512 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1513 do {
1514 spin_lock_irqsave(&bank->slock, flags);
1515
1516 polarity = readl_relaxed(bank->reg_base +
1517 GPIO_INT_POLARITY);
1518 if (data & BIT(irq))
1519 polarity &= ~BIT(irq);
1520 else
1521 polarity |= BIT(irq);
1522 writel(polarity,
1523 bank->reg_base + GPIO_INT_POLARITY);
1524
1525 spin_unlock_irqrestore(&bank->slock, flags);
1526
1527 data_old = data;
1528 data = readl_relaxed(bank->reg_base +
1529 GPIO_EXT_PORT);
1530 } while ((data & BIT(irq)) != (data_old & BIT(irq)));
Heiko Stübner5a927502013-10-16 01:09:08 +02001531 }
1532
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001533 generic_handle_irq(virq);
1534 }
1535
1536 chained_irq_exit(chip, desc);
1537}
1538
1539static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1540{
1541 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1542 struct rockchip_pin_bank *bank = gc->private;
1543 u32 mask = BIT(d->hwirq);
1544 u32 polarity;
1545 u32 level;
1546 u32 data;
Doug Andersonfab262f2014-10-21 10:47:35 -07001547 unsigned long flags;
Heiko Stübner14797182014-03-26 00:57:00 +01001548 int ret;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001549
Heiko Stübner5a927502013-10-16 01:09:08 +02001550 /* make sure the pin is configured as gpio input */
Heiko Stübner14797182014-03-26 00:57:00 +01001551 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1552 if (ret < 0)
1553 return ret;
1554
Lin Huang07a06ae2015-08-11 18:12:04 +08001555 clk_enable(bank->clk);
Doug Andersonfab262f2014-10-21 10:47:35 -07001556 spin_lock_irqsave(&bank->slock, flags);
1557
Heiko Stübner5a927502013-10-16 01:09:08 +02001558 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1559 data &= ~mask;
1560 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1561
Doug Andersonfab262f2014-10-21 10:47:35 -07001562 spin_unlock_irqrestore(&bank->slock, flags);
1563
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001564 if (type & IRQ_TYPE_EDGE_BOTH)
Thomas Gleixner2dbf1bc2015-06-23 15:52:50 +02001565 irq_set_handler_locked(d, handle_edge_irq);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001566 else
Thomas Gleixner2dbf1bc2015-06-23 15:52:50 +02001567 irq_set_handler_locked(d, handle_level_irq);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001568
Doug Andersonfab262f2014-10-21 10:47:35 -07001569 spin_lock_irqsave(&bank->slock, flags);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001570 irq_gc_lock(gc);
1571
1572 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1573 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1574
1575 switch (type) {
Heiko Stübner5a927502013-10-16 01:09:08 +02001576 case IRQ_TYPE_EDGE_BOTH:
1577 bank->toggle_edge_mode |= mask;
1578 level |= mask;
1579
1580 /*
1581 * Determine gpio state. If 1 next interrupt should be falling
1582 * otherwise rising.
1583 */
1584 data = readl(bank->reg_base + GPIO_EXT_PORT);
1585 if (data & mask)
1586 polarity &= ~mask;
1587 else
1588 polarity |= mask;
1589 break;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001590 case IRQ_TYPE_EDGE_RISING:
Heiko Stübner5a927502013-10-16 01:09:08 +02001591 bank->toggle_edge_mode &= ~mask;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001592 level |= mask;
1593 polarity |= mask;
1594 break;
1595 case IRQ_TYPE_EDGE_FALLING:
Heiko Stübner5a927502013-10-16 01:09:08 +02001596 bank->toggle_edge_mode &= ~mask;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001597 level |= mask;
1598 polarity &= ~mask;
1599 break;
1600 case IRQ_TYPE_LEVEL_HIGH:
Heiko Stübner5a927502013-10-16 01:09:08 +02001601 bank->toggle_edge_mode &= ~mask;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001602 level &= ~mask;
1603 polarity |= mask;
1604 break;
1605 case IRQ_TYPE_LEVEL_LOW:
Heiko Stübner5a927502013-10-16 01:09:08 +02001606 bank->toggle_edge_mode &= ~mask;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001607 level &= ~mask;
1608 polarity &= ~mask;
1609 break;
1610 default:
Axel Lin7cc5f972013-06-23 08:48:34 +08001611 irq_gc_unlock(gc);
Doug Andersonfab262f2014-10-21 10:47:35 -07001612 spin_unlock_irqrestore(&bank->slock, flags);
Lin Huang07a06ae2015-08-11 18:12:04 +08001613 clk_disable(bank->clk);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001614 return -EINVAL;
1615 }
1616
1617 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1618 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1619
1620 irq_gc_unlock(gc);
Doug Andersonfab262f2014-10-21 10:47:35 -07001621 spin_unlock_irqrestore(&bank->slock, flags);
Lin Huang07a06ae2015-08-11 18:12:04 +08001622 clk_disable(bank->clk);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001623
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001624 return 0;
1625}
1626
Doug Anderson68bda472014-11-19 14:51:32 -08001627static void rockchip_irq_suspend(struct irq_data *d)
1628{
1629 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1630 struct rockchip_pin_bank *bank = gc->private;
1631
Lin Huang07a06ae2015-08-11 18:12:04 +08001632 clk_enable(bank->clk);
Doug Anderson5ae0c7a2015-01-26 08:24:03 -08001633 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
1634 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
Lin Huang07a06ae2015-08-11 18:12:04 +08001635 clk_disable(bank->clk);
Doug Anderson68bda472014-11-19 14:51:32 -08001636}
1637
1638static void rockchip_irq_resume(struct irq_data *d)
1639{
1640 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1641 struct rockchip_pin_bank *bank = gc->private;
1642
Lin Huang07a06ae2015-08-11 18:12:04 +08001643 clk_enable(bank->clk);
Doug Anderson5ae0c7a2015-01-26 08:24:03 -08001644 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
Lin Huang07a06ae2015-08-11 18:12:04 +08001645 clk_disable(bank->clk);
1646}
1647
1648static void rockchip_irq_gc_mask_clr_bit(struct irq_data *d)
1649{
1650 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1651 struct rockchip_pin_bank *bank = gc->private;
1652
1653 clk_enable(bank->clk);
1654 irq_gc_mask_clr_bit(d);
1655}
1656
1657void rockchip_irq_gc_mask_set_bit(struct irq_data *d)
1658{
1659 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1660 struct rockchip_pin_bank *bank = gc->private;
1661
1662 irq_gc_mask_set_bit(d);
1663 clk_disable(bank->clk);
Doug Andersonf2dd0282014-11-19 14:51:33 -08001664}
1665
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001666static int rockchip_interrupts_register(struct platform_device *pdev,
1667 struct rockchip_pinctrl *info)
1668{
1669 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1670 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1671 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1672 struct irq_chip_generic *gc;
1673 int ret;
Lin Huang07a06ae2015-08-11 18:12:04 +08001674 int i, j;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001675
1676 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1677 if (!bank->valid) {
1678 dev_warn(&pdev->dev, "bank %s is not valid\n",
1679 bank->name);
1680 continue;
1681 }
1682
Lin Huang07a06ae2015-08-11 18:12:04 +08001683 ret = clk_enable(bank->clk);
1684 if (ret) {
1685 dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
1686 bank->name);
1687 continue;
1688 }
1689
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001690 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1691 &irq_generic_chip_ops, NULL);
1692 if (!bank->domain) {
1693 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1694 bank->name);
Lin Huang07a06ae2015-08-11 18:12:04 +08001695 clk_disable(bank->clk);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001696 continue;
1697 }
1698
1699 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1700 "rockchip_gpio_irq", handle_level_irq,
1701 clr, 0, IRQ_GC_INIT_MASK_CACHE);
1702 if (ret) {
1703 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1704 bank->name);
1705 irq_domain_remove(bank->domain);
Lin Huang07a06ae2015-08-11 18:12:04 +08001706 clk_disable(bank->clk);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001707 continue;
1708 }
1709
Doug Anderson5ae0c7a2015-01-26 08:24:03 -08001710 /*
1711 * Linux assumes that all interrupts start out disabled/masked.
1712 * Our driver only uses the concept of masked and always keeps
1713 * things enabled, so for us that's all masked and all enabled.
1714 */
1715 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
1716 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
1717
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001718 gc = irq_get_domain_generic_chip(bank->domain, 0);
1719 gc->reg_base = bank->reg_base;
1720 gc->private = bank;
Doug Andersonf2dd0282014-11-19 14:51:33 -08001721 gc->chip_types[0].regs.mask = GPIO_INTMASK;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001722 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1723 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
Lin Huang07a06ae2015-08-11 18:12:04 +08001724 gc->chip_types[0].chip.irq_mask = rockchip_irq_gc_mask_set_bit;
1725 gc->chip_types[0].chip.irq_unmask =
1726 rockchip_irq_gc_mask_clr_bit;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001727 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
Doug Anderson68bda472014-11-19 14:51:32 -08001728 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
1729 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001730 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
Doug Anderson876d7162014-10-21 10:47:32 -07001731 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001732
Thomas Gleixner03051bc2015-06-21 21:11:06 +02001733 irq_set_chained_handler_and_data(bank->irq,
1734 rockchip_irq_demux, bank);
Lin Huang07a06ae2015-08-11 18:12:04 +08001735
1736 /* map the gpio irqs here, when the clock is still running */
1737 for (j = 0 ; j < 32 ; j++)
1738 irq_create_mapping(bank->domain, j);
1739
1740 clk_disable(bank->clk);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001741 }
1742
1743 return 0;
1744}
1745
1746static int rockchip_gpiolib_register(struct platform_device *pdev,
1747 struct rockchip_pinctrl *info)
1748{
1749 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1750 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1751 struct gpio_chip *gc;
1752 int ret;
1753 int i;
1754
1755 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1756 if (!bank->valid) {
1757 dev_warn(&pdev->dev, "bank %s is not valid\n",
1758 bank->name);
1759 continue;
1760 }
1761
1762 bank->gpio_chip = rockchip_gpiolib_chip;
1763
1764 gc = &bank->gpio_chip;
1765 gc->base = bank->pin_base;
1766 gc->ngpio = bank->nr_pins;
1767 gc->dev = &pdev->dev;
1768 gc->of_node = bank->of_node;
1769 gc->label = bank->name;
1770
1771 ret = gpiochip_add(gc);
1772 if (ret) {
1773 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1774 gc->label, ret);
1775 goto fail;
1776 }
1777 }
1778
1779 rockchip_interrupts_register(pdev, info);
1780
1781 return 0;
1782
1783fail:
1784 for (--i, --bank; i >= 0; --i, --bank) {
1785 if (!bank->valid)
1786 continue;
abdoulaye bertheb4e7c552014-07-12 22:30:13 +02001787 gpiochip_remove(&bank->gpio_chip);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001788 }
1789 return ret;
1790}
1791
1792static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1793 struct rockchip_pinctrl *info)
1794{
1795 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1796 struct rockchip_pin_bank *bank = ctrl->pin_banks;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001797 int i;
1798
abdoulaye bertheb4e7c552014-07-12 22:30:13 +02001799 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001800 if (!bank->valid)
1801 continue;
abdoulaye bertheb4e7c552014-07-12 22:30:13 +02001802 gpiochip_remove(&bank->gpio_chip);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001803 }
1804
abdoulaye bertheb4e7c552014-07-12 22:30:13 +02001805 return 0;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001806}
1807
1808static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
Heiko Stübner622f3232014-05-05 13:58:46 +02001809 struct rockchip_pinctrl *info)
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001810{
1811 struct resource res;
Heiko Stübner751a99a2014-05-05 13:58:20 +02001812 void __iomem *base;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001813
1814 if (of_address_to_resource(bank->of_node, 0, &res)) {
Heiko Stübner622f3232014-05-05 13:58:46 +02001815 dev_err(info->dev, "cannot find IO resource for bank\n");
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001816 return -ENOENT;
1817 }
1818
Heiko Stübner622f3232014-05-05 13:58:46 +02001819 bank->reg_base = devm_ioremap_resource(info->dev, &res);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001820 if (IS_ERR(bank->reg_base))
1821 return PTR_ERR(bank->reg_base);
1822
Heiko Stübner6ca52742013-10-16 01:08:42 +02001823 /*
1824 * special case, where parts of the pull setting-registers are
1825 * part of the PMU register space
1826 */
1827 if (of_device_is_compatible(bank->of_node,
1828 "rockchip,rk3188-gpio-bank0")) {
Heiko Stübnera658efa2014-05-05 13:59:30 +02001829 struct device_node *node;
Heiko Stübnerbfc7a422014-05-05 13:58:00 +02001830
Heiko Stübnera658efa2014-05-05 13:59:30 +02001831 node = of_parse_phandle(bank->of_node->parent,
1832 "rockchip,pmu", 0);
1833 if (!node) {
1834 if (of_address_to_resource(bank->of_node, 1, &res)) {
1835 dev_err(info->dev, "cannot find IO resource for bank\n");
1836 return -ENOENT;
1837 }
Heiko Stübner6ca52742013-10-16 01:08:42 +02001838
Heiko Stübnera658efa2014-05-05 13:59:30 +02001839 base = devm_ioremap_resource(info->dev, &res);
1840 if (IS_ERR(base))
1841 return PTR_ERR(base);
1842 rockchip_regmap_config.max_register =
1843 resource_size(&res) - 4;
1844 rockchip_regmap_config.name =
1845 "rockchip,rk3188-gpio-bank0-pull";
1846 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
1847 base,
1848 &rockchip_regmap_config);
1849 }
Heiko Stübner6ca52742013-10-16 01:08:42 +02001850 }
Heiko Stübner65fca612013-10-16 01:07:49 +02001851
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001852 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1853
1854 bank->clk = of_clk_get(bank->of_node, 0);
1855 if (IS_ERR(bank->clk))
1856 return PTR_ERR(bank->clk);
1857
Lin Huang07a06ae2015-08-11 18:12:04 +08001858 return clk_prepare(bank->clk);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001859}
1860
1861static const struct of_device_id rockchip_pinctrl_dt_match[];
1862
1863/* retrieve the soc specific data */
1864static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1865 struct rockchip_pinctrl *d,
1866 struct platform_device *pdev)
1867{
1868 const struct of_device_id *match;
1869 struct device_node *node = pdev->dev.of_node;
1870 struct device_node *np;
1871 struct rockchip_pin_ctrl *ctrl;
1872 struct rockchip_pin_bank *bank;
Heiko Stübner95ec8ae2014-06-16 01:37:23 +02001873 int grf_offs, pmu_offs, i, j;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001874
1875 match = of_match_node(rockchip_pinctrl_dt_match, node);
1876 ctrl = (struct rockchip_pin_ctrl *)match->data;
1877
1878 for_each_child_of_node(node, np) {
1879 if (!of_find_property(np, "gpio-controller", NULL))
1880 continue;
1881
1882 bank = ctrl->pin_banks;
1883 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1884 if (!strcmp(bank->name, np->name)) {
1885 bank->of_node = np;
1886
Heiko Stübner622f3232014-05-05 13:58:46 +02001887 if (!rockchip_get_bank_data(bank, d))
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001888 bank->valid = true;
1889
1890 break;
1891 }
1892 }
1893 }
1894
Heiko Stübner95ec8ae2014-06-16 01:37:23 +02001895 grf_offs = ctrl->grf_mux_offset;
1896 pmu_offs = ctrl->pmu_mux_offset;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001897 bank = ctrl->pin_banks;
1898 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
Heiko Stübner6bc0d1212014-06-16 01:36:33 +02001899 int bank_pins = 0;
1900
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001901 spin_lock_init(&bank->slock);
1902 bank->drvdata = d;
1903 bank->pin_base = ctrl->nr_pins;
1904 ctrl->nr_pins += bank->nr_pins;
Heiko Stübner6bc0d1212014-06-16 01:36:33 +02001905
1906 /* calculate iomux offsets */
1907 for (j = 0; j < 4; j++) {
1908 struct rockchip_iomux *iom = &bank->iomux[j];
Heiko Stübner03716e12014-06-16 01:36:57 +02001909 int inc;
Heiko Stübner6bc0d1212014-06-16 01:36:33 +02001910
1911 if (bank_pins >= bank->nr_pins)
1912 break;
1913
1914 /* preset offset value, set new start value */
1915 if (iom->offset >= 0) {
Heiko Stübner95ec8ae2014-06-16 01:37:23 +02001916 if (iom->type & IOMUX_SOURCE_PMU)
1917 pmu_offs = iom->offset;
1918 else
1919 grf_offs = iom->offset;
Heiko Stübner6bc0d1212014-06-16 01:36:33 +02001920 } else { /* set current offset */
Heiko Stübner95ec8ae2014-06-16 01:37:23 +02001921 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
1922 pmu_offs : grf_offs;
Heiko Stübner6bc0d1212014-06-16 01:36:33 +02001923 }
1924
1925 dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n",
1926 i, j, iom->offset);
1927
1928 /*
1929 * Increase offset according to iomux width.
Heiko Stübner03716e12014-06-16 01:36:57 +02001930 * 4bit iomux'es are spread over two registers.
Heiko Stübner6bc0d1212014-06-16 01:36:33 +02001931 */
Heiko Stübner03716e12014-06-16 01:36:57 +02001932 inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4;
Heiko Stübner95ec8ae2014-06-16 01:37:23 +02001933 if (iom->type & IOMUX_SOURCE_PMU)
1934 pmu_offs += inc;
1935 else
1936 grf_offs += inc;
Heiko Stübner6bc0d1212014-06-16 01:36:33 +02001937
1938 bank_pins += 8;
1939 }
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001940 }
1941
1942 return ctrl;
1943}
1944
Chris Zhong8dca9332014-10-29 19:52:00 +08001945#define RK3288_GRF_GPIO6C_IOMUX 0x64
1946#define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
1947
1948static u32 rk3288_grf_gpio6c_iomux;
1949
Chris Zhong9198f502014-10-29 19:51:59 +08001950static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
1951{
1952 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
Chris Zhong8dca9332014-10-29 19:52:00 +08001953 int ret = pinctrl_force_sleep(info->pctl_dev);
Chris Zhong9198f502014-10-29 19:51:59 +08001954
Chris Zhong8dca9332014-10-29 19:52:00 +08001955 if (ret)
1956 return ret;
1957
1958 /*
1959 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
1960 * the setting here, and restore it at resume.
1961 */
1962 if (info->ctrl->type == RK3288) {
1963 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
1964 &rk3288_grf_gpio6c_iomux);
1965 if (ret) {
1966 pinctrl_force_default(info->pctl_dev);
1967 return ret;
1968 }
1969 }
1970
1971 return 0;
Chris Zhong9198f502014-10-29 19:51:59 +08001972}
1973
1974static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
1975{
1976 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
Chris Zhong8dca9332014-10-29 19:52:00 +08001977 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
1978 rk3288_grf_gpio6c_iomux |
1979 GPIO6C6_SEL_WRITE_ENABLE);
1980
1981 if (ret)
1982 return ret;
Chris Zhong9198f502014-10-29 19:51:59 +08001983
1984 return pinctrl_force_default(info->pctl_dev);
1985}
1986
1987static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
1988 rockchip_pinctrl_resume);
1989
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001990static int rockchip_pinctrl_probe(struct platform_device *pdev)
1991{
1992 struct rockchip_pinctrl *info;
1993 struct device *dev = &pdev->dev;
1994 struct rockchip_pin_ctrl *ctrl;
Heiko Stübner14dee862014-05-05 13:59:09 +02001995 struct device_node *np = pdev->dev.of_node, *node;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001996 struct resource *res;
Heiko Stübner751a99a2014-05-05 13:58:20 +02001997 void __iomem *base;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001998 int ret;
1999
2000 if (!dev->of_node) {
2001 dev_err(dev, "device tree node not found\n");
2002 return -ENODEV;
2003 }
2004
2005 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
2006 if (!info)
2007 return -ENOMEM;
2008
Heiko Stübner622f3232014-05-05 13:58:46 +02002009 info->dev = dev;
2010
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002011 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2012 if (!ctrl) {
2013 dev_err(dev, "driver data not available\n");
2014 return -EINVAL;
2015 }
2016 info->ctrl = ctrl;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002017
Heiko Stübner1e747e52014-05-05 13:59:51 +02002018 node = of_parse_phandle(np, "rockchip,grf", 0);
2019 if (node) {
2020 info->regmap_base = syscon_node_to_regmap(node);
2021 if (IS_ERR(info->regmap_base))
2022 return PTR_ERR(info->regmap_base);
2023 } else {
2024 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Heiko Stübner751a99a2014-05-05 13:58:20 +02002025 base = devm_ioremap_resource(&pdev->dev, res);
2026 if (IS_ERR(base))
2027 return PTR_ERR(base);
2028
2029 rockchip_regmap_config.max_register = resource_size(res) - 4;
Heiko Stübner1e747e52014-05-05 13:59:51 +02002030 rockchip_regmap_config.name = "rockchip,pinctrl";
2031 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
2032 &rockchip_regmap_config);
2033
2034 /* to check for the old dt-bindings */
2035 info->reg_size = resource_size(res);
2036
2037 /* Honor the old binding, with pull registers as 2nd resource */
2038 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
2039 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2040 base = devm_ioremap_resource(&pdev->dev, res);
2041 if (IS_ERR(base))
2042 return PTR_ERR(base);
2043
2044 rockchip_regmap_config.max_register =
2045 resource_size(res) - 4;
2046 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
2047 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
2048 base,
2049 &rockchip_regmap_config);
2050 }
Heiko Stübner6ca52742013-10-16 01:08:42 +02002051 }
2052
Heiko Stübner14dee862014-05-05 13:59:09 +02002053 /* try to find the optional reference to the pmu syscon */
2054 node = of_parse_phandle(np, "rockchip,pmu", 0);
2055 if (node) {
2056 info->regmap_pmu = syscon_node_to_regmap(node);
2057 if (IS_ERR(info->regmap_pmu))
2058 return PTR_ERR(info->regmap_pmu);
2059 }
2060
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002061 ret = rockchip_gpiolib_register(pdev, info);
2062 if (ret)
2063 return ret;
2064
2065 ret = rockchip_pinctrl_register(pdev, info);
2066 if (ret) {
2067 rockchip_gpiolib_unregister(pdev, info);
2068 return ret;
2069 }
2070
2071 platform_set_drvdata(pdev, info);
2072
2073 return 0;
2074}
2075
2076static struct rockchip_pin_bank rk2928_pin_banks[] = {
2077 PIN_BANK(0, 32, "gpio0"),
2078 PIN_BANK(1, 32, "gpio1"),
2079 PIN_BANK(2, 32, "gpio2"),
2080 PIN_BANK(3, 32, "gpio3"),
2081};
2082
2083static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2084 .pin_banks = rk2928_pin_banks,
2085 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
2086 .label = "RK2928-GPIO",
Heiko Stübnera2829262013-10-16 01:07:20 +02002087 .type = RK2928,
Heiko Stübner95ec8ae2014-06-16 01:37:23 +02002088 .grf_mux_offset = 0xa8,
Heiko Stübnera2829262013-10-16 01:07:20 +02002089 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002090};
2091
2092static struct rockchip_pin_bank rk3066a_pin_banks[] = {
2093 PIN_BANK(0, 32, "gpio0"),
2094 PIN_BANK(1, 32, "gpio1"),
2095 PIN_BANK(2, 32, "gpio2"),
2096 PIN_BANK(3, 32, "gpio3"),
2097 PIN_BANK(4, 32, "gpio4"),
2098 PIN_BANK(6, 16, "gpio6"),
2099};
2100
2101static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
2102 .pin_banks = rk3066a_pin_banks,
2103 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
2104 .label = "RK3066a-GPIO",
Heiko Stübnera2829262013-10-16 01:07:20 +02002105 .type = RK2928,
Heiko Stübner95ec8ae2014-06-16 01:37:23 +02002106 .grf_mux_offset = 0xa8,
Heiko Stübnera2829262013-10-16 01:07:20 +02002107 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002108};
2109
2110static struct rockchip_pin_bank rk3066b_pin_banks[] = {
2111 PIN_BANK(0, 32, "gpio0"),
2112 PIN_BANK(1, 32, "gpio1"),
2113 PIN_BANK(2, 32, "gpio2"),
2114 PIN_BANK(3, 32, "gpio3"),
2115};
2116
2117static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2118 .pin_banks = rk3066b_pin_banks,
2119 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
2120 .label = "RK3066b-GPIO",
Heiko Stübnera2829262013-10-16 01:07:20 +02002121 .type = RK3066B,
Heiko Stübner95ec8ae2014-06-16 01:37:23 +02002122 .grf_mux_offset = 0x60,
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002123};
2124
2125static struct rockchip_pin_bank rk3188_pin_banks[] = {
Heiko Stübnerfc72c922014-06-16 01:36:05 +02002126 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002127 PIN_BANK(1, 32, "gpio1"),
2128 PIN_BANK(2, 32, "gpio2"),
2129 PIN_BANK(3, 32, "gpio3"),
2130};
2131
2132static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
2133 .pin_banks = rk3188_pin_banks,
2134 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
2135 .label = "RK3188-GPIO",
Heiko Stübnera2829262013-10-16 01:07:20 +02002136 .type = RK3188,
Heiko Stübner95ec8ae2014-06-16 01:37:23 +02002137 .grf_mux_offset = 0x60,
Heiko Stübner6ca52742013-10-16 01:08:42 +02002138 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002139};
2140
Heiko Stübner304f0772014-06-16 01:38:14 +02002141static struct rockchip_pin_bank rk3288_pin_banks[] = {
2142 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
2143 IOMUX_SOURCE_PMU,
2144 IOMUX_SOURCE_PMU,
2145 IOMUX_UNROUTED
2146 ),
2147 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
2148 IOMUX_UNROUTED,
2149 IOMUX_UNROUTED,
2150 0
2151 ),
2152 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
2153 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
2154 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
2155 IOMUX_WIDTH_4BIT,
2156 0,
2157 0
2158 ),
2159 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
2160 0,
2161 0,
2162 IOMUX_UNROUTED
2163 ),
2164 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
2165 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
2166 0,
2167 IOMUX_WIDTH_4BIT,
2168 IOMUX_UNROUTED
2169 ),
2170 PIN_BANK(8, 16, "gpio8"),
2171};
2172
2173static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
2174 .pin_banks = rk3288_pin_banks,
2175 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
2176 .label = "RK3288-GPIO",
Heiko Stübner66d750e2014-07-20 01:49:17 +02002177 .type = RK3288,
Heiko Stübner304f0772014-06-16 01:38:14 +02002178 .grf_mux_offset = 0x0,
2179 .pmu_mux_offset = 0x84,
2180 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
Heiko Stübneref17f692015-06-12 23:50:11 +02002181 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
Heiko Stübner304f0772014-06-16 01:38:14 +02002182};
2183
Heiko Stübnerdaecdc62015-06-12 23:51:01 +02002184static struct rockchip_pin_bank rk3368_pin_banks[] = {
2185 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2186 IOMUX_SOURCE_PMU,
2187 IOMUX_SOURCE_PMU,
2188 IOMUX_SOURCE_PMU
2189 ),
2190 PIN_BANK(1, 32, "gpio1"),
2191 PIN_BANK(2, 32, "gpio2"),
2192 PIN_BANK(3, 32, "gpio3"),
2193};
2194
2195static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
2196 .pin_banks = rk3368_pin_banks,
2197 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
2198 .label = "RK3368-GPIO",
2199 .type = RK3368,
2200 .grf_mux_offset = 0x0,
2201 .pmu_mux_offset = 0x0,
2202 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
2203 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
2204};
2205
2206
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002207static const struct of_device_id rockchip_pinctrl_dt_match[] = {
2208 { .compatible = "rockchip,rk2928-pinctrl",
2209 .data = (void *)&rk2928_pin_ctrl },
2210 { .compatible = "rockchip,rk3066a-pinctrl",
2211 .data = (void *)&rk3066a_pin_ctrl },
2212 { .compatible = "rockchip,rk3066b-pinctrl",
2213 .data = (void *)&rk3066b_pin_ctrl },
2214 { .compatible = "rockchip,rk3188-pinctrl",
2215 .data = (void *)&rk3188_pin_ctrl },
Heiko Stübner304f0772014-06-16 01:38:14 +02002216 { .compatible = "rockchip,rk3288-pinctrl",
2217 .data = (void *)&rk3288_pin_ctrl },
Heiko Stübnerdaecdc62015-06-12 23:51:01 +02002218 { .compatible = "rockchip,rk3368-pinctrl",
2219 .data = (void *)&rk3368_pin_ctrl },
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002220 {},
2221};
2222MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
2223
2224static struct platform_driver rockchip_pinctrl_driver = {
2225 .probe = rockchip_pinctrl_probe,
2226 .driver = {
2227 .name = "rockchip-pinctrl",
Chris Zhong9198f502014-10-29 19:51:59 +08002228 .pm = &rockchip_pinctrl_dev_pm_ops,
Axel Lin0be9e702013-08-23 14:27:53 +08002229 .of_match_table = rockchip_pinctrl_dt_match,
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002230 },
2231};
2232
2233static int __init rockchip_pinctrl_drv_register(void)
2234{
2235 return platform_driver_register(&rockchip_pinctrl_driver);
2236}
2237postcore_initcall(rockchip_pinctrl_drv_register);
2238
2239MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
2240MODULE_DESCRIPTION("Rockchip pinctrl driver");
2241MODULE_LICENSE("GPL v2");