Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 1 | /* |
| 2 | * TI DaVinci GPIO Support |
| 3 | * |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 4 | * Copyright (c) 2006-2007 David Brownell |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 5 | * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/errno.h> |
| 14 | #include <linux/kernel.h> |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 15 | #include <linux/clk.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/io.h> |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 18 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 19 | #include <mach/gpio.h> |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 20 | |
| 21 | #include <asm/mach/irq.h> |
| 22 | |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 23 | struct davinci_gpio_regs { |
| 24 | u32 dir; |
| 25 | u32 out_data; |
| 26 | u32 set_data; |
| 27 | u32 clr_data; |
| 28 | u32 in_data; |
| 29 | u32 set_rising; |
| 30 | u32 clr_rising; |
| 31 | u32 set_falling; |
| 32 | u32 clr_falling; |
| 33 | u32 intstat; |
| 34 | }; |
| 35 | |
Cyril Chemparathy | ba4a984 | 2010-05-01 18:37:51 -0400 | [diff] [blame] | 36 | #define chip2controller(chip) \ |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 37 | container_of(chip, struct davinci_gpio_controller, chip) |
Cyril Chemparathy | ba4a984 | 2010-05-01 18:37:51 -0400 | [diff] [blame] | 38 | |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 39 | static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; |
Cyril Chemparathy | b8d4429 | 2010-05-07 17:06:32 -0400 | [diff] [blame] | 40 | static void __iomem *gpio_base; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 41 | |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 42 | static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 43 | { |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 44 | void __iomem *ptr; |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 45 | |
| 46 | if (gpio < 32 * 1) |
Cyril Chemparathy | b8d4429 | 2010-05-07 17:06:32 -0400 | [diff] [blame] | 47 | ptr = gpio_base + 0x10; |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 48 | else if (gpio < 32 * 2) |
Cyril Chemparathy | b8d4429 | 2010-05-07 17:06:32 -0400 | [diff] [blame] | 49 | ptr = gpio_base + 0x38; |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 50 | else if (gpio < 32 * 3) |
Cyril Chemparathy | b8d4429 | 2010-05-07 17:06:32 -0400 | [diff] [blame] | 51 | ptr = gpio_base + 0x60; |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 52 | else if (gpio < 32 * 4) |
Cyril Chemparathy | b8d4429 | 2010-05-07 17:06:32 -0400 | [diff] [blame] | 53 | ptr = gpio_base + 0x88; |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 54 | else if (gpio < 32 * 5) |
Cyril Chemparathy | b8d4429 | 2010-05-07 17:06:32 -0400 | [diff] [blame] | 55 | ptr = gpio_base + 0xb0; |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 56 | else |
| 57 | ptr = NULL; |
| 58 | return ptr; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 59 | } |
| 60 | |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 61 | static inline struct davinci_gpio_regs __iomem *irq2regs(int irq) |
Kevin Hilman | 21ce873 | 2010-02-25 16:49:56 -0800 | [diff] [blame] | 62 | { |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 63 | struct davinci_gpio_regs __iomem *g; |
Kevin Hilman | 21ce873 | 2010-02-25 16:49:56 -0800 | [diff] [blame] | 64 | |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 65 | g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq); |
Kevin Hilman | 21ce873 | 2010-02-25 16:49:56 -0800 | [diff] [blame] | 66 | |
| 67 | return g; |
| 68 | } |
| 69 | |
Kevin Hilman | dc75602 | 2009-05-11 11:04:53 -0700 | [diff] [blame] | 70 | static int __init davinci_gpio_irq_setup(void); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 71 | |
| 72 | /*--------------------------------------------------------------------------*/ |
| 73 | |
Cyril Chemparathy | 5b3a05c | 2010-05-01 18:38:27 -0400 | [diff] [blame] | 74 | /* board setup code *MUST* setup pinmux and enable the GPIO clock. */ |
Cyril Chemparathy | ba4a984 | 2010-05-01 18:37:51 -0400 | [diff] [blame] | 75 | static inline int __davinci_direction(struct gpio_chip *chip, |
| 76 | unsigned offset, bool out, int value) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 77 | { |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 78 | struct davinci_gpio_controller *d = chip2controller(chip); |
| 79 | struct davinci_gpio_regs __iomem *g = d->regs; |
Cyril Chemparathy | b27b6d0 | 2010-05-01 18:37:55 -0400 | [diff] [blame] | 80 | unsigned long flags; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 81 | u32 temp; |
Cyril Chemparathy | ba4a984 | 2010-05-01 18:37:51 -0400 | [diff] [blame] | 82 | u32 mask = 1 << offset; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 83 | |
Cyril Chemparathy | b27b6d0 | 2010-05-01 18:37:55 -0400 | [diff] [blame] | 84 | spin_lock_irqsave(&d->lock, flags); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 85 | temp = __raw_readl(&g->dir); |
Cyril Chemparathy | ba4a984 | 2010-05-01 18:37:51 -0400 | [diff] [blame] | 86 | if (out) { |
| 87 | temp &= ~mask; |
| 88 | __raw_writel(mask, value ? &g->set_data : &g->clr_data); |
| 89 | } else { |
| 90 | temp |= mask; |
| 91 | } |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 92 | __raw_writel(temp, &g->dir); |
Cyril Chemparathy | b27b6d0 | 2010-05-01 18:37:55 -0400 | [diff] [blame] | 93 | spin_unlock_irqrestore(&d->lock, flags); |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 94 | |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 95 | return 0; |
| 96 | } |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 97 | |
Cyril Chemparathy | ba4a984 | 2010-05-01 18:37:51 -0400 | [diff] [blame] | 98 | static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) |
| 99 | { |
| 100 | return __davinci_direction(chip, offset, false, 0); |
| 101 | } |
| 102 | |
| 103 | static int |
| 104 | davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) |
| 105 | { |
| 106 | return __davinci_direction(chip, offset, true, value); |
| 107 | } |
| 108 | |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 109 | /* |
| 110 | * Read the pin's value (works even if it's set up as output); |
| 111 | * returns zero/nonzero. |
| 112 | * |
| 113 | * Note that changes are synched to the GPIO clock, so reading values back |
| 114 | * right after you've set them may give old values. |
| 115 | */ |
| 116 | static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 117 | { |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 118 | struct davinci_gpio_controller *d = chip2controller(chip); |
| 119 | struct davinci_gpio_regs __iomem *g = d->regs; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 120 | |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 121 | return (1 << offset) & __raw_readl(&g->in_data); |
| 122 | } |
| 123 | |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 124 | /* |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 125 | * Assuming the pin is muxed as a gpio output, set its output value. |
| 126 | */ |
| 127 | static void |
| 128 | davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 129 | { |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 130 | struct davinci_gpio_controller *d = chip2controller(chip); |
| 131 | struct davinci_gpio_regs __iomem *g = d->regs; |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 132 | |
| 133 | __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data); |
| 134 | } |
| 135 | |
| 136 | static int __init davinci_gpio_setup(void) |
| 137 | { |
| 138 | int i, base; |
Mark A. Greer | a994955 | 2009-04-15 12:40:35 -0700 | [diff] [blame] | 139 | unsigned ngpio; |
| 140 | struct davinci_soc_info *soc_info = &davinci_soc_info; |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 141 | struct davinci_gpio_regs *regs; |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 142 | |
Cyril Chemparathy | 686b634 | 2010-05-01 18:37:54 -0400 | [diff] [blame] | 143 | if (soc_info->gpio_type != GPIO_TYPE_DAVINCI) |
| 144 | return 0; |
| 145 | |
Mark A. Greer | a994955 | 2009-04-15 12:40:35 -0700 | [diff] [blame] | 146 | /* |
| 147 | * The gpio banks conceptually expose a segmented bitmap, |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 148 | * and "ngpio" is one more than the largest zero-based |
| 149 | * bit index that's valid. |
| 150 | */ |
Mark A. Greer | a994955 | 2009-04-15 12:40:35 -0700 | [diff] [blame] | 151 | ngpio = soc_info->gpio_num; |
| 152 | if (ngpio == 0) { |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 153 | pr_err("GPIO setup: how many GPIOs?\n"); |
| 154 | return -EINVAL; |
| 155 | } |
| 156 | |
| 157 | if (WARN_ON(DAVINCI_N_GPIO < ngpio)) |
| 158 | ngpio = DAVINCI_N_GPIO; |
| 159 | |
Cyril Chemparathy | b8d4429 | 2010-05-07 17:06:32 -0400 | [diff] [blame] | 160 | gpio_base = ioremap(soc_info->gpio_base, SZ_4K); |
| 161 | if (WARN_ON(!gpio_base)) |
| 162 | return -ENOMEM; |
| 163 | |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 164 | for (i = 0, base = 0; base < ngpio; i++, base += 32) { |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 165 | chips[i].chip.label = "DaVinci"; |
| 166 | |
| 167 | chips[i].chip.direction_input = davinci_direction_in; |
| 168 | chips[i].chip.get = davinci_gpio_get; |
| 169 | chips[i].chip.direction_output = davinci_direction_out; |
| 170 | chips[i].chip.set = davinci_gpio_set; |
| 171 | |
| 172 | chips[i].chip.base = base; |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 173 | chips[i].chip.ngpio = ngpio - base; |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 174 | if (chips[i].chip.ngpio > 32) |
| 175 | chips[i].chip.ngpio = 32; |
| 176 | |
Cyril Chemparathy | b27b6d0 | 2010-05-01 18:37:55 -0400 | [diff] [blame] | 177 | spin_lock_init(&chips[i].lock); |
| 178 | |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 179 | regs = gpio2regs(base); |
| 180 | chips[i].regs = regs; |
| 181 | chips[i].set_data = ®s->set_data; |
| 182 | chips[i].clr_data = ®s->clr_data; |
| 183 | chips[i].in_data = ®s->in_data; |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 184 | |
| 185 | gpiochip_add(&chips[i].chip); |
| 186 | } |
| 187 | |
Cyril Chemparathy | c12f415 | 2010-05-01 18:37:53 -0400 | [diff] [blame] | 188 | soc_info->gpio_ctlrs = chips; |
| 189 | soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32); |
| 190 | |
Kevin Hilman | dc75602 | 2009-05-11 11:04:53 -0700 | [diff] [blame] | 191 | davinci_gpio_irq_setup(); |
David Brownell | dce1115 | 2008-09-07 23:41:04 -0700 | [diff] [blame] | 192 | return 0; |
| 193 | } |
| 194 | pure_initcall(davinci_gpio_setup); |
| 195 | |
| 196 | /*--------------------------------------------------------------------------*/ |
| 197 | /* |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 198 | * We expect irqs will normally be set up as input pins, but they can also be |
| 199 | * used as output pins ... which is convenient for testing. |
| 200 | * |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 201 | * NOTE: The first few GPIOs also have direct INTC hookups in addition |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 202 | * to their GPIOBNK0 irq, with a bit less overhead. |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 203 | * |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 204 | * All those INTC hookups (direct, plus several IRQ banks) can also |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 205 | * serve as EDMA event triggers. |
| 206 | */ |
| 207 | |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 208 | static void gpio_irq_disable(struct irq_data *d) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 209 | { |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 210 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 211 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 212 | |
| 213 | __raw_writel(mask, &g->clr_falling); |
| 214 | __raw_writel(mask, &g->clr_rising); |
| 215 | } |
| 216 | |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 217 | static void gpio_irq_enable(struct irq_data *d) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 218 | { |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 219 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 220 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
Thomas Gleixner | 5093aec | 2011-03-24 12:47:04 +0100 | [diff] [blame] | 221 | unsigned status = irqd_get_trigger_type(d); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 222 | |
David Brownell | df4aab4 | 2009-05-04 13:14:27 -0700 | [diff] [blame] | 223 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
| 224 | if (!status) |
| 225 | status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
| 226 | |
| 227 | if (status & IRQ_TYPE_EDGE_FALLING) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 228 | __raw_writel(mask, &g->set_falling); |
David Brownell | df4aab4 | 2009-05-04 13:14:27 -0700 | [diff] [blame] | 229 | if (status & IRQ_TYPE_EDGE_RISING) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 230 | __raw_writel(mask, &g->set_rising); |
| 231 | } |
| 232 | |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 233 | static int gpio_irq_type(struct irq_data *d, unsigned trigger) |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 234 | { |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 235 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 236 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 237 | |
| 238 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
| 239 | return -EINVAL; |
| 240 | |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 241 | return 0; |
| 242 | } |
| 243 | |
| 244 | static struct irq_chip gpio_irqchip = { |
| 245 | .name = "GPIO", |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 246 | .irq_enable = gpio_irq_enable, |
| 247 | .irq_disable = gpio_irq_disable, |
| 248 | .irq_set_type = gpio_irq_type, |
Thomas Gleixner | 5093aec | 2011-03-24 12:47:04 +0100 | [diff] [blame] | 249 | .flags = IRQCHIP_SET_TYPE_MASKED, |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 250 | }; |
| 251 | |
| 252 | static void |
| 253 | gpio_irq_handler(unsigned irq, struct irq_desc *desc) |
| 254 | { |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 255 | struct davinci_gpio_regs __iomem *g = irq2regs(irq); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 256 | u32 mask = 0xffff; |
| 257 | |
| 258 | /* we only care about one bank */ |
| 259 | if (irq & 1) |
| 260 | mask <<= 16; |
| 261 | |
| 262 | /* temporarily mask (level sensitive) parent IRQ */ |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 263 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
| 264 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 265 | while (1) { |
| 266 | u32 status; |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 267 | int n; |
| 268 | int res; |
| 269 | |
| 270 | /* ack any irqs */ |
| 271 | status = __raw_readl(&g->intstat) & mask; |
| 272 | if (!status) |
| 273 | break; |
| 274 | __raw_writel(status, &g->intstat); |
| 275 | if (irq & 1) |
| 276 | status >>= 16; |
| 277 | |
| 278 | /* now demux them to the right lowlevel handler */ |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 279 | n = (int)irq_get_handler_data(irq); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 280 | while (status) { |
| 281 | res = ffs(status); |
| 282 | n += res; |
Dmitry Baryshkov | d8aa025 | 2008-10-09 13:36:24 +0100 | [diff] [blame] | 283 | generic_handle_irq(n - 1); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 284 | status >>= res; |
| 285 | } |
| 286 | } |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 287 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 288 | /* now it may re-trigger */ |
| 289 | } |
| 290 | |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 291 | static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) |
| 292 | { |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 293 | struct davinci_gpio_controller *d = chip2controller(chip); |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 294 | |
| 295 | if (d->irq_base >= 0) |
| 296 | return d->irq_base + offset; |
| 297 | else |
| 298 | return -ENODEV; |
| 299 | } |
| 300 | |
| 301 | static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) |
| 302 | { |
| 303 | struct davinci_soc_info *soc_info = &davinci_soc_info; |
| 304 | |
| 305 | /* NOTE: we assume for now that only irqs in the first gpio_chip |
| 306 | * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). |
| 307 | */ |
| 308 | if (offset < soc_info->gpio_unbanked) |
| 309 | return soc_info->gpio_irq + offset; |
| 310 | else |
| 311 | return -ENODEV; |
| 312 | } |
| 313 | |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 314 | static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger) |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 315 | { |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 316 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 317 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 318 | |
| 319 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
| 320 | return -EINVAL; |
| 321 | |
| 322 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) |
| 323 | ? &g->set_falling : &g->clr_falling); |
| 324 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) |
| 325 | ? &g->set_rising : &g->clr_rising); |
| 326 | |
| 327 | return 0; |
| 328 | } |
| 329 | |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 330 | /* |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 331 | * NOTE: for suspend/resume, probably best to make a platform_device with |
| 332 | * suspend_late/resume_resume calls hooking into results of the set_wake() |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 333 | * calls ... so if no gpios are wakeup events the clock can be disabled, |
| 334 | * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 335 | * (dm6446) can be set appropriately for GPIOV33 pins. |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 336 | */ |
| 337 | |
| 338 | static int __init davinci_gpio_irq_setup(void) |
| 339 | { |
| 340 | unsigned gpio, irq, bank; |
| 341 | struct clk *clk; |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 342 | u32 binten = 0; |
Mark A. Greer | a994955 | 2009-04-15 12:40:35 -0700 | [diff] [blame] | 343 | unsigned ngpio, bank_irq; |
| 344 | struct davinci_soc_info *soc_info = &davinci_soc_info; |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 345 | struct davinci_gpio_regs __iomem *g; |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 346 | |
Mark A. Greer | a994955 | 2009-04-15 12:40:35 -0700 | [diff] [blame] | 347 | ngpio = soc_info->gpio_num; |
| 348 | |
| 349 | bank_irq = soc_info->gpio_irq; |
| 350 | if (bank_irq == 0) { |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 351 | printk(KERN_ERR "Don't know first GPIO bank IRQ.\n"); |
| 352 | return -EINVAL; |
| 353 | } |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 354 | |
| 355 | clk = clk_get(NULL, "gpio"); |
| 356 | if (IS_ERR(clk)) { |
| 357 | printk(KERN_ERR "Error %ld getting gpio clock?\n", |
| 358 | PTR_ERR(clk)); |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 359 | return PTR_ERR(clk); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 360 | } |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 361 | clk_enable(clk); |
| 362 | |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 363 | /* Arrange gpio_to_irq() support, handling either direct IRQs or |
| 364 | * banked IRQs. Having GPIOs in the first GPIO bank use direct |
| 365 | * IRQs, while the others use banked IRQs, would need some setup |
| 366 | * tweaks to recognize hardware which can do that. |
| 367 | */ |
| 368 | for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) { |
| 369 | chips[bank].chip.to_irq = gpio_to_irq_banked; |
| 370 | chips[bank].irq_base = soc_info->gpio_unbanked |
| 371 | ? -EINVAL |
| 372 | : (soc_info->intc_irq_num + gpio); |
| 373 | } |
| 374 | |
| 375 | /* |
| 376 | * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO |
| 377 | * controller only handling trigger modes. We currently assume no |
| 378 | * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. |
| 379 | */ |
| 380 | if (soc_info->gpio_unbanked) { |
| 381 | static struct irq_chip gpio_irqchip_unbanked; |
| 382 | |
| 383 | /* pass "bank 0" GPIO IRQs to AINTC */ |
| 384 | chips[0].chip.to_irq = gpio_to_irq_unbanked; |
| 385 | binten = BIT(0); |
| 386 | |
| 387 | /* AINTC handles mask/unmask; GPIO handles triggering */ |
| 388 | irq = bank_irq; |
Thomas Gleixner | 5093aec | 2011-03-24 12:47:04 +0100 | [diff] [blame] | 389 | gpio_irqchip_unbanked = *irq_get_chip(irq); |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 390 | gpio_irqchip_unbanked.name = "GPIO-AINTC"; |
Lennert Buytenhek | 2326544 | 2010-11-29 10:27:27 +0100 | [diff] [blame] | 391 | gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked; |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 392 | |
| 393 | /* default trigger: both edges */ |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 394 | g = gpio2regs(0); |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 395 | __raw_writel(~0, &g->set_falling); |
| 396 | __raw_writel(~0, &g->set_rising); |
| 397 | |
| 398 | /* set the direct IRQs up to use that irqchip */ |
| 399 | for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) { |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 400 | irq_set_chip(irq, &gpio_irqchip_unbanked); |
| 401 | irq_set_handler_data(irq, (void *)__gpio_mask(gpio)); |
| 402 | irq_set_chip_data(irq, (__force void *)g); |
Thomas Gleixner | 5093aec | 2011-03-24 12:47:04 +0100 | [diff] [blame] | 403 | irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH); |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 404 | } |
| 405 | |
| 406 | goto done; |
| 407 | } |
| 408 | |
| 409 | /* |
| 410 | * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we |
| 411 | * then chain through our own handler. |
| 412 | */ |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 413 | for (gpio = 0, irq = gpio_to_irq(0), bank = 0; |
| 414 | gpio < ngpio; |
| 415 | bank++, bank_irq++) { |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 416 | unsigned i; |
| 417 | |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 418 | /* disabled by default, enabled only as needed */ |
Cyril Chemparathy | 99e9e52 | 2010-05-01 18:37:52 -0400 | [diff] [blame] | 419 | g = gpio2regs(gpio); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 420 | __raw_writel(~0, &g->clr_falling); |
| 421 | __raw_writel(~0, &g->clr_rising); |
| 422 | |
| 423 | /* set up all irqs in this bank */ |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 424 | irq_set_chained_handler(bank_irq, gpio_irq_handler); |
| 425 | irq_set_chip_data(bank_irq, (__force void *)g); |
| 426 | irq_set_handler_data(bank_irq, (void *)irq); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 427 | |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 428 | for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { |
Thomas Gleixner | 6845664a | 2011-03-24 13:25:22 +0100 | [diff] [blame] | 429 | irq_set_chip(irq, &gpio_irqchip); |
| 430 | irq_set_chip_data(irq, (__force void *)g); |
| 431 | irq_set_handler_data(irq, (void *)__gpio_mask(gpio)); |
| 432 | irq_set_handler(irq, handle_simple_irq); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 433 | set_irq_flags(irq, IRQF_VALID); |
| 434 | } |
David Brownell | 474dad5 | 2008-12-07 11:46:23 -0800 | [diff] [blame] | 435 | |
| 436 | binten |= BIT(bank); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 437 | } |
| 438 | |
David Brownell | 7a36071 | 2009-06-25 17:01:31 -0700 | [diff] [blame] | 439 | done: |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 440 | /* BINTEN -- per-bank interrupt enable. genirq would also let these |
| 441 | * bits be set/cleared dynamically. |
| 442 | */ |
Cyril Chemparathy | b8d4429 | 2010-05-07 17:06:32 -0400 | [diff] [blame] | 443 | __raw_writel(binten, gpio_base + 0x08); |
Vladimir Barinov | 3d9edf0 | 2007-07-10 13:03:43 +0100 | [diff] [blame] | 444 | |
| 445 | printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); |
| 446 | |
| 447 | return 0; |
| 448 | } |