Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Cache maintenance |
| 3 | * |
| 4 | * Copyright (C) 2001 Deep Blue Solutions Ltd. |
| 5 | * Copyright (C) 2012 ARM Ltd. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
Vladimir Murzin | a2d25a5 | 2014-12-01 10:53:08 +0000 | [diff] [blame] | 20 | #include <linux/errno.h> |
Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 21 | #include <linux/linkage.h> |
| 22 | #include <linux/init.h> |
| 23 | #include <asm/assembler.h> |
Andre Przywara | 301bcfa | 2014-11-14 15:54:10 +0000 | [diff] [blame] | 24 | #include <asm/cpufeature.h> |
Marc Zyngier | 8d883b2 | 2015-06-01 10:47:41 +0100 | [diff] [blame] | 25 | #include <asm/alternative.h> |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 26 | #include <asm/uaccess.h> |
Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 27 | |
Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 28 | /* |
Rohit Vaswani | 5d49422 | 2016-01-04 14:08:32 -0800 | [diff] [blame] | 29 | * __flush_dcache_all() |
| 30 | * |
| 31 | * Flush the whole D-cache. |
| 32 | * |
| 33 | * Corrupted registers: x0-x7, x9-x11 |
| 34 | */ |
| 35 | __flush_dcache_all: |
| 36 | dmb sy // ensure ordering with previous memory accesses |
| 37 | mrs x0, clidr_el1 // read clidr |
| 38 | and x3, x0, #0x7000000 // extract loc from clidr |
| 39 | lsr x3, x3, #23 // left align loc bit field |
| 40 | cbz x3, finished // if loc is 0, then no need to clean |
| 41 | mov x10, #0 // start clean at cache level 0 |
| 42 | loop1: |
| 43 | add x2, x10, x10, lsr #1 // work out 3x current cache level |
| 44 | lsr x1, x0, x2 // extract cache type bits from clidr |
| 45 | and x1, x1, #7 // mask of the bits for current cache only |
| 46 | cmp x1, #2 // see what cache we have at this level |
| 47 | b.lt skip // skip if no cache, or just i-cache |
| 48 | save_and_disable_irqs x9 // make CSSELR and CCSIDR access atomic |
| 49 | msr csselr_el1, x10 // select current cache level in csselr |
| 50 | isb // isb to sych the new cssr&csidr |
| 51 | mrs x1, ccsidr_el1 // read the new ccsidr |
| 52 | restore_irqs x9 |
| 53 | and x2, x1, #7 // extract the length of the cache lines |
| 54 | add x2, x2, #4 // add 4 (line length offset) |
| 55 | mov x4, #0x3ff |
| 56 | and x4, x4, x1, lsr #3 // find maximum number on the way size |
| 57 | clz w5, w4 // find bit position of way size increment |
| 58 | mov x7, #0x7fff |
| 59 | and x7, x7, x1, lsr #13 // extract max number of the index size |
| 60 | loop2: |
| 61 | mov x9, x4 // create working copy of max way size |
| 62 | loop3: |
| 63 | lsl x6, x9, x5 |
| 64 | orr x11, x10, x6 // factor way and cache number into x11 |
| 65 | lsl x6, x7, x2 |
| 66 | orr x11, x11, x6 // factor index number into x11 |
| 67 | dc cisw, x11 // clean & invalidate by set/way |
| 68 | subs x9, x9, #1 // decrement the way |
| 69 | b.ge loop3 |
| 70 | subs x7, x7, #1 // decrement the index |
| 71 | b.ge loop2 |
| 72 | skip: |
| 73 | add x10, x10, #2 // increment cache number |
| 74 | cmp x3, x10 |
| 75 | b.gt loop1 |
| 76 | finished: |
| 77 | mov x10, #0 // swith back to cache level 0 |
| 78 | msr csselr_el1, x10 // select current cache level in csselr |
| 79 | dsb sy |
| 80 | isb |
| 81 | ret |
| 82 | ENDPROC(__flush_dcache_all) |
| 83 | |
| 84 | /* |
| 85 | * flush_cache_all() |
| 86 | * |
| 87 | * Flush the entire cache system. The data cache flush is now achieved |
| 88 | * using atomic clean / invalidates working outwards from L1 cache. This |
| 89 | * is done using Set/Way based cache maintenance instructions. The |
| 90 | * instruction cache can still be invalidated back to the point of |
| 91 | * unification in a single instruction. |
| 92 | */ |
| 93 | ENTRY(flush_cache_all) |
| 94 | mov x12, lr |
| 95 | bl __flush_dcache_all |
| 96 | mov x0, #0 |
| 97 | ic ialluis // I+BTB cache invalidate |
| 98 | ret x12 |
| 99 | ENDPROC(flush_cache_all) |
| 100 | |
| 101 | /* |
Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 102 | * flush_icache_range(start,end) |
| 103 | * |
| 104 | * Ensure that the I and D caches are coherent within specified region. |
| 105 | * This is typically used when code has been written to a memory region, |
| 106 | * and will be executed. |
| 107 | * |
| 108 | * - start - virtual start address of region |
| 109 | * - end - virtual end address of region |
| 110 | */ |
| 111 | ENTRY(flush_icache_range) |
| 112 | /* FALLTHROUGH */ |
| 113 | |
| 114 | /* |
| 115 | * __flush_cache_user_range(start,end) |
| 116 | * |
| 117 | * Ensure that the I and D caches are coherent within specified region. |
| 118 | * This is typically used when code has been written to a memory region, |
| 119 | * and will be executed. |
| 120 | * |
| 121 | * - start - virtual start address of region |
| 122 | * - end - virtual end address of region |
| 123 | */ |
| 124 | ENTRY(__flush_cache_user_range) |
Will Deacon | f7aa82e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 125 | uaccess_ttbr0_enable x2, x3, x4 |
Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 126 | dcache_line_size x2, x3 |
| 127 | sub x3, x2, #1 |
| 128 | bic x4, x0, x3 |
| 129 | 1: |
Andre Przywara | 290622e | 2016-06-28 18:07:28 +0100 | [diff] [blame] | 130 | user_alt 9f, "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE |
Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 131 | add x4, x4, x2 |
| 132 | cmp x4, x1 |
| 133 | b.lo 1b |
Will Deacon | dc60b77 | 2014-05-02 16:24:15 +0100 | [diff] [blame] | 134 | dsb ish |
Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 135 | |
| 136 | icache_line_size x2, x3 |
| 137 | sub x3, x2, #1 |
| 138 | bic x4, x0, x3 |
| 139 | 1: |
| 140 | USER(9f, ic ivau, x4 ) // invalidate I line PoU |
| 141 | add x4, x4, x2 |
| 142 | cmp x4, x1 |
| 143 | b.lo 1b |
Will Deacon | dc60b77 | 2014-05-02 16:24:15 +0100 | [diff] [blame] | 144 | dsb ish |
Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 145 | isb |
Vladimir Murzin | a2d25a5 | 2014-12-01 10:53:08 +0000 | [diff] [blame] | 146 | mov x0, #0 |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 147 | 1: |
Catalin Marinas | 874f778 | 2018-01-10 13:18:30 +0000 | [diff] [blame] | 148 | uaccess_ttbr0_disable x1, x2 |
Vladimir Murzin | a2d25a5 | 2014-12-01 10:53:08 +0000 | [diff] [blame] | 149 | ret |
| 150 | 9: |
| 151 | mov x0, #-EFAULT |
Catalin Marinas | cfa9377 | 2016-09-02 14:54:03 +0100 | [diff] [blame] | 152 | b 1b |
Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 153 | ENDPROC(flush_icache_range) |
| 154 | ENDPROC(__flush_cache_user_range) |
| 155 | |
| 156 | /* |
Jingoo Han | 03324e6 | 2014-01-21 01:17:47 +0000 | [diff] [blame] | 157 | * __flush_dcache_area(kaddr, size) |
Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 158 | * |
Ashok Kumar | 0a28714 | 2015-12-17 01:38:32 -0800 | [diff] [blame] | 159 | * Ensure that any D-cache lines for the interval [kaddr, kaddr+size) |
| 160 | * are cleaned and invalidated to the PoC. |
Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 161 | * |
| 162 | * - kaddr - kernel address |
| 163 | * - size - size in question |
| 164 | */ |
| 165 | ENTRY(__flush_dcache_area) |
Ashok Kumar | 0a28714 | 2015-12-17 01:38:32 -0800 | [diff] [blame] | 166 | dcache_by_line_op civac, sy, x0, x1, x2, x3 |
Catalin Marinas | f1a0c4a | 2012-03-05 11:49:28 +0000 | [diff] [blame] | 167 | ret |
Ard Biesheuvel | 2079184 | 2015-10-08 20:02:03 +0100 | [diff] [blame] | 168 | ENDPIPROC(__flush_dcache_area) |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 169 | |
| 170 | /* |
Ashok Kumar | 0a28714 | 2015-12-17 01:38:32 -0800 | [diff] [blame] | 171 | * __clean_dcache_area_pou(kaddr, size) |
| 172 | * |
| 173 | * Ensure that any D-cache lines for the interval [kaddr, kaddr+size) |
| 174 | * are cleaned to the PoU. |
| 175 | * |
| 176 | * - kaddr - kernel address |
| 177 | * - size - size in question |
| 178 | */ |
| 179 | ENTRY(__clean_dcache_area_pou) |
| 180 | dcache_by_line_op cvau, ish, x0, x1, x2, x3 |
| 181 | ret |
| 182 | ENDPROC(__clean_dcache_area_pou) |
| 183 | |
| 184 | /* |
Kwangwoo Lee | d34fdb7 | 2016-08-02 09:50:50 +0900 | [diff] [blame] | 185 | * __dma_inv_area(start, size) |
| 186 | * - start - virtual start address of region |
| 187 | * - size - size in question |
| 188 | */ |
Kyle Yan | 65be4a5 | 2016-10-31 15:05:00 -0700 | [diff] [blame] | 189 | ENTRY(__dma_inv_area) |
Kwangwoo Lee | d34fdb7 | 2016-08-02 09:50:50 +0900 | [diff] [blame] | 190 | add x1, x1, x0 |
| 191 | /* FALLTHROUGH */ |
| 192 | |
| 193 | /* |
Catalin Marinas | c218bca | 2014-03-26 18:25:55 +0000 | [diff] [blame] | 194 | * __inval_cache_range(start, end) |
| 195 | * - start - start address of region |
| 196 | * - end - end address of region |
| 197 | */ |
| 198 | ENTRY(__inval_cache_range) |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 199 | dcache_line_size x2, x3 |
| 200 | sub x3, x2, #1 |
Catalin Marinas | ebf81a9 | 2014-04-01 18:32:55 +0100 | [diff] [blame] | 201 | tst x1, x3 // end cache line aligned? |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 202 | bic x1, x1, x3 |
Catalin Marinas | ebf81a9 | 2014-04-01 18:32:55 +0100 | [diff] [blame] | 203 | b.eq 1f |
| 204 | dc civac, x1 // clean & invalidate D / U line |
| 205 | 1: tst x0, x3 // start cache line aligned? |
| 206 | bic x0, x0, x3 |
| 207 | b.eq 2f |
| 208 | dc civac, x0 // clean & invalidate D / U line |
| 209 | b 3f |
| 210 | 2: dc ivac, x0 // invalidate D / U line |
| 211 | 3: add x0, x0, x2 |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 212 | cmp x0, x1 |
Catalin Marinas | ebf81a9 | 2014-04-01 18:32:55 +0100 | [diff] [blame] | 213 | b.lo 2b |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 214 | dsb sy |
| 215 | ret |
Ard Biesheuvel | 2079184 | 2015-10-08 20:02:03 +0100 | [diff] [blame] | 216 | ENDPIPROC(__inval_cache_range) |
Kwangwoo Lee | d34fdb7 | 2016-08-02 09:50:50 +0900 | [diff] [blame] | 217 | ENDPROC(__dma_inv_area) |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 218 | |
| 219 | /* |
Kwangwoo Lee | d34fdb7 | 2016-08-02 09:50:50 +0900 | [diff] [blame] | 220 | * __clean_dcache_area_poc(kaddr, size) |
| 221 | * |
| 222 | * Ensure that any D-cache lines for the interval [kaddr, kaddr+size) |
| 223 | * are cleaned to the PoC. |
| 224 | * |
| 225 | * - kaddr - kernel address |
| 226 | * - size - size in question |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 227 | */ |
Kwangwoo Lee | d34fdb7 | 2016-08-02 09:50:50 +0900 | [diff] [blame] | 228 | ENTRY(__clean_dcache_area_poc) |
| 229 | /* FALLTHROUGH */ |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 230 | |
| 231 | /* |
Kwangwoo Lee | d34fdb7 | 2016-08-02 09:50:50 +0900 | [diff] [blame] | 232 | * __dma_clean_area(start, size) |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 233 | * - start - virtual start address of region |
Kwangwoo Lee | d34fdb7 | 2016-08-02 09:50:50 +0900 | [diff] [blame] | 234 | * - size - size in question |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 235 | */ |
Kyle Yan | 65be4a5 | 2016-10-31 15:05:00 -0700 | [diff] [blame] | 236 | ENTRY(__dma_clean_area) |
Kwangwoo Lee | d34fdb7 | 2016-08-02 09:50:50 +0900 | [diff] [blame] | 237 | dcache_by_line_op cvac, sy, x0, x1, x2, x3 |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 238 | ret |
Kwangwoo Lee | d34fdb7 | 2016-08-02 09:50:50 +0900 | [diff] [blame] | 239 | ENDPIPROC(__clean_dcache_area_poc) |
| 240 | ENDPROC(__dma_clean_area) |
| 241 | |
| 242 | /* |
| 243 | * __dma_flush_area(start, size) |
| 244 | * |
| 245 | * clean & invalidate D / U line |
| 246 | * |
| 247 | * - start - virtual start address of region |
| 248 | * - size - size in question |
| 249 | */ |
| 250 | ENTRY(__dma_flush_area) |
| 251 | dcache_by_line_op civac, sy, x0, x1, x2, x3 |
| 252 | ret |
| 253 | ENDPIPROC(__dma_flush_area) |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 254 | |
| 255 | /* |
| 256 | * __dma_map_area(start, size, dir) |
| 257 | * - start - kernel virtual start address |
| 258 | * - size - size of region |
| 259 | * - dir - DMA direction |
| 260 | */ |
| 261 | ENTRY(__dma_map_area) |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 262 | cmp w2, #DMA_FROM_DEVICE |
Kwangwoo Lee | d34fdb7 | 2016-08-02 09:50:50 +0900 | [diff] [blame] | 263 | b.eq __dma_inv_area |
| 264 | b __dma_clean_area |
Ard Biesheuvel | 2079184 | 2015-10-08 20:02:03 +0100 | [diff] [blame] | 265 | ENDPIPROC(__dma_map_area) |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 266 | |
| 267 | /* |
| 268 | * __dma_unmap_area(start, size, dir) |
| 269 | * - start - kernel virtual start address |
| 270 | * - size - size of region |
| 271 | * - dir - DMA direction |
| 272 | */ |
| 273 | ENTRY(__dma_unmap_area) |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 274 | cmp w2, #DMA_TO_DEVICE |
Kwangwoo Lee | d34fdb7 | 2016-08-02 09:50:50 +0900 | [diff] [blame] | 275 | b.ne __dma_inv_area |
Catalin Marinas | 7363590 | 2013-05-21 17:35:19 +0100 | [diff] [blame] | 276 | ret |
Ard Biesheuvel | 2079184 | 2015-10-08 20:02:03 +0100 | [diff] [blame] | 277 | ENDPIPROC(__dma_unmap_area) |