Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1 | /* |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 2 | * Copyright © 2006-2014 Intel Corporation. |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms and conditions of the GNU General Public License, |
| 6 | * version 2, as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 11 | * more details. |
| 12 | * |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 13 | * Authors: David Woodhouse <dwmw2@infradead.org>, |
| 14 | * Ashok Raj <ashok.raj@intel.com>, |
| 15 | * Shaohua Li <shaohua.li@intel.com>, |
| 16 | * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>, |
| 17 | * Fenghua Yu <fenghua.yu@intel.com> |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/bitmap.h> |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 22 | #include <linux/debugfs.h> |
Paul Gortmaker | 54485c3 | 2011-10-29 10:26:25 -0400 | [diff] [blame] | 23 | #include <linux/export.h> |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 24 | #include <linux/slab.h> |
| 25 | #include <linux/irq.h> |
| 26 | #include <linux/interrupt.h> |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 27 | #include <linux/spinlock.h> |
| 28 | #include <linux/pci.h> |
| 29 | #include <linux/dmar.h> |
| 30 | #include <linux/dma-mapping.h> |
| 31 | #include <linux/mempool.h> |
Jiang Liu | 75f0556 | 2014-02-19 14:07:37 +0800 | [diff] [blame] | 32 | #include <linux/memory.h> |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 33 | #include <linux/timer.h> |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 34 | #include <linux/iova.h> |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 35 | #include <linux/iommu.h> |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 36 | #include <linux/intel-iommu.h> |
Rafael J. Wysocki | 134fac3 | 2011-03-23 22:16:14 +0100 | [diff] [blame] | 37 | #include <linux/syscore_ops.h> |
Shane Wang | 69575d3 | 2009-09-01 18:25:07 -0700 | [diff] [blame] | 38 | #include <linux/tboot.h> |
Stephen Rothwell | adb2fe0 | 2009-08-31 15:24:23 +1000 | [diff] [blame] | 39 | #include <linux/dmi.h> |
Joerg Roedel | 5cdede2 | 2011-04-04 15:55:18 +0200 | [diff] [blame] | 40 | #include <linux/pci-ats.h> |
Tejun Heo | 0ee332c | 2011-12-08 10:22:09 -0800 | [diff] [blame] | 41 | #include <linux/memblock.h> |
Suresh Siddha | 8a8f422 | 2012-03-30 11:47:08 -0700 | [diff] [blame] | 42 | #include <asm/irq_remapping.h> |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 43 | #include <asm/cacheflush.h> |
FUJITA Tomonori | 46a7fa2 | 2008-07-11 10:23:42 +0900 | [diff] [blame] | 44 | #include <asm/iommu.h> |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 45 | |
Joerg Roedel | 078e1ee | 2012-09-26 12:44:43 +0200 | [diff] [blame] | 46 | #include "irq_remapping.h" |
Varun Sethi | 61e015a | 2013-04-23 10:05:24 +0530 | [diff] [blame] | 47 | #include "pci.h" |
Joerg Roedel | 078e1ee | 2012-09-26 12:44:43 +0200 | [diff] [blame] | 48 | |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 49 | #define ROOT_SIZE VTD_PAGE_SIZE |
| 50 | #define CONTEXT_SIZE VTD_PAGE_SIZE |
| 51 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 52 | #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY) |
| 53 | #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA) |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 54 | #define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 55 | |
| 56 | #define IOAPIC_RANGE_START (0xfee00000) |
| 57 | #define IOAPIC_RANGE_END (0xfeefffff) |
| 58 | #define IOVA_START_ADDR (0x1000) |
| 59 | |
| 60 | #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48 |
| 61 | |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 62 | #define MAX_AGAW_WIDTH 64 |
Jiang Liu | 5c645b3 | 2014-01-06 14:18:12 +0800 | [diff] [blame] | 63 | #define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT) |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 64 | |
David Woodhouse | 2ebe315 | 2009-09-19 07:34:04 -0700 | [diff] [blame] | 65 | #define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1) |
| 66 | #define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1) |
| 67 | |
| 68 | /* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR |
| 69 | to match. That way, we can use 'unsigned long' for PFNs with impunity. */ |
| 70 | #define DOMAIN_MAX_PFN(gaw) ((unsigned long) min_t(uint64_t, \ |
| 71 | __DOMAIN_MAX_PFN(gaw), (unsigned long)-1)) |
| 72 | #define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 73 | |
Mark McLoughlin | f27be03 | 2008-11-20 15:49:43 +0000 | [diff] [blame] | 74 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) |
Yang Hongyang | 284901a | 2009-04-06 19:01:15 -0700 | [diff] [blame] | 75 | #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32)) |
Yang Hongyang | 6a35528 | 2009-04-06 19:01:13 -0700 | [diff] [blame] | 76 | #define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64)) |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 77 | |
Andrew Morton | df08cdc | 2010-09-22 13:05:11 -0700 | [diff] [blame] | 78 | /* page table handling */ |
| 79 | #define LEVEL_STRIDE (9) |
| 80 | #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1) |
| 81 | |
Ohad Ben-Cohen | 6d1c56a | 2011-11-10 11:32:30 +0200 | [diff] [blame] | 82 | /* |
| 83 | * This bitmap is used to advertise the page sizes our hardware support |
| 84 | * to the IOMMU core, which will then use this information to split |
| 85 | * physically contiguous memory regions it is mapping into page sizes |
| 86 | * that we support. |
| 87 | * |
| 88 | * Traditionally the IOMMU core just handed us the mappings directly, |
| 89 | * after making sure the size is an order of a 4KiB page and that the |
| 90 | * mapping has natural alignment. |
| 91 | * |
| 92 | * To retain this behavior, we currently advertise that we support |
| 93 | * all page sizes that are an order of 4KiB. |
| 94 | * |
| 95 | * If at some point we'd like to utilize the IOMMU core's new behavior, |
| 96 | * we could change this to advertise the real page sizes we support. |
| 97 | */ |
| 98 | #define INTEL_IOMMU_PGSIZES (~0xFFFUL) |
| 99 | |
Andrew Morton | df08cdc | 2010-09-22 13:05:11 -0700 | [diff] [blame] | 100 | static inline int agaw_to_level(int agaw) |
| 101 | { |
| 102 | return agaw + 2; |
| 103 | } |
| 104 | |
| 105 | static inline int agaw_to_width(int agaw) |
| 106 | { |
Jiang Liu | 5c645b3 | 2014-01-06 14:18:12 +0800 | [diff] [blame] | 107 | return min_t(int, 30 + agaw * LEVEL_STRIDE, MAX_AGAW_WIDTH); |
Andrew Morton | df08cdc | 2010-09-22 13:05:11 -0700 | [diff] [blame] | 108 | } |
| 109 | |
| 110 | static inline int width_to_agaw(int width) |
| 111 | { |
Jiang Liu | 5c645b3 | 2014-01-06 14:18:12 +0800 | [diff] [blame] | 112 | return DIV_ROUND_UP(width - 30, LEVEL_STRIDE); |
Andrew Morton | df08cdc | 2010-09-22 13:05:11 -0700 | [diff] [blame] | 113 | } |
| 114 | |
| 115 | static inline unsigned int level_to_offset_bits(int level) |
| 116 | { |
| 117 | return (level - 1) * LEVEL_STRIDE; |
| 118 | } |
| 119 | |
| 120 | static inline int pfn_level_offset(unsigned long pfn, int level) |
| 121 | { |
| 122 | return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK; |
| 123 | } |
| 124 | |
| 125 | static inline unsigned long level_mask(int level) |
| 126 | { |
| 127 | return -1UL << level_to_offset_bits(level); |
| 128 | } |
| 129 | |
| 130 | static inline unsigned long level_size(int level) |
| 131 | { |
| 132 | return 1UL << level_to_offset_bits(level); |
| 133 | } |
| 134 | |
| 135 | static inline unsigned long align_to_level(unsigned long pfn, int level) |
| 136 | { |
| 137 | return (pfn + level_size(level) - 1) & level_mask(level); |
| 138 | } |
David Woodhouse | fd18de5 | 2009-05-10 23:57:41 +0100 | [diff] [blame] | 139 | |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 140 | static inline unsigned long lvl_to_nr_pages(unsigned int lvl) |
| 141 | { |
Jiang Liu | 5c645b3 | 2014-01-06 14:18:12 +0800 | [diff] [blame] | 142 | return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH); |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 143 | } |
| 144 | |
David Woodhouse | dd4e831 | 2009-06-27 16:21:20 +0100 | [diff] [blame] | 145 | /* VT-d pages must always be _smaller_ than MM pages. Otherwise things |
| 146 | are never going to work. */ |
| 147 | static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn) |
| 148 | { |
| 149 | return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT); |
| 150 | } |
| 151 | |
| 152 | static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn) |
| 153 | { |
| 154 | return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT); |
| 155 | } |
| 156 | static inline unsigned long page_to_dma_pfn(struct page *pg) |
| 157 | { |
| 158 | return mm_to_dma_pfn(page_to_pfn(pg)); |
| 159 | } |
| 160 | static inline unsigned long virt_to_dma_pfn(void *p) |
| 161 | { |
| 162 | return page_to_dma_pfn(virt_to_page(p)); |
| 163 | } |
| 164 | |
Weidong Han | d9630fe | 2008-12-08 11:06:32 +0800 | [diff] [blame] | 165 | /* global iommu list, set NULL for ignored DMAR units */ |
| 166 | static struct intel_iommu **g_iommus; |
| 167 | |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 168 | static void __init check_tylersburg_isoch(void); |
David Woodhouse | 9af8814 | 2009-02-13 23:18:03 +0000 | [diff] [blame] | 169 | static int rwbf_quirk; |
| 170 | |
Mark McLoughlin | 46b08e1 | 2008-11-20 15:49:44 +0000 | [diff] [blame] | 171 | /* |
Joseph Cihula | b779260 | 2011-05-03 00:08:37 -0700 | [diff] [blame] | 172 | * set to 1 to panic kernel if can't successfully enable VT-d |
| 173 | * (used when kernel is launched w/ TXT) |
| 174 | */ |
| 175 | static int force_on = 0; |
| 176 | |
| 177 | /* |
Mark McLoughlin | 46b08e1 | 2008-11-20 15:49:44 +0000 | [diff] [blame] | 178 | * 0: Present |
| 179 | * 1-11: Reserved |
| 180 | * 12-63: Context Ptr (12 - (haw-1)) |
| 181 | * 64-127: Reserved |
| 182 | */ |
| 183 | struct root_entry { |
| 184 | u64 val; |
| 185 | u64 rsvd1; |
| 186 | }; |
| 187 | #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry)) |
| 188 | static inline bool root_present(struct root_entry *root) |
| 189 | { |
| 190 | return (root->val & 1); |
| 191 | } |
| 192 | static inline void set_root_present(struct root_entry *root) |
| 193 | { |
| 194 | root->val |= 1; |
| 195 | } |
| 196 | static inline void set_root_value(struct root_entry *root, unsigned long value) |
| 197 | { |
| 198 | root->val |= value & VTD_PAGE_MASK; |
| 199 | } |
| 200 | |
| 201 | static inline struct context_entry * |
| 202 | get_context_addr_from_root(struct root_entry *root) |
| 203 | { |
| 204 | return (struct context_entry *) |
| 205 | (root_present(root)?phys_to_virt( |
| 206 | root->val & VTD_PAGE_MASK) : |
| 207 | NULL); |
| 208 | } |
| 209 | |
Mark McLoughlin | 7a8fc25 | 2008-11-20 15:49:45 +0000 | [diff] [blame] | 210 | /* |
| 211 | * low 64 bits: |
| 212 | * 0: present |
| 213 | * 1: fault processing disable |
| 214 | * 2-3: translation type |
| 215 | * 12-63: address space root |
| 216 | * high 64 bits: |
| 217 | * 0-2: address width |
| 218 | * 3-6: aval |
| 219 | * 8-23: domain id |
| 220 | */ |
| 221 | struct context_entry { |
| 222 | u64 lo; |
| 223 | u64 hi; |
| 224 | }; |
Mark McLoughlin | 7a8fc25 | 2008-11-20 15:49:45 +0000 | [diff] [blame] | 225 | |
Mark McLoughlin | c07e7d2 | 2008-11-21 16:54:46 +0000 | [diff] [blame] | 226 | static inline bool context_present(struct context_entry *context) |
| 227 | { |
| 228 | return (context->lo & 1); |
| 229 | } |
| 230 | static inline void context_set_present(struct context_entry *context) |
| 231 | { |
| 232 | context->lo |= 1; |
| 233 | } |
| 234 | |
| 235 | static inline void context_set_fault_enable(struct context_entry *context) |
| 236 | { |
| 237 | context->lo &= (((u64)-1) << 2) | 1; |
| 238 | } |
| 239 | |
Mark McLoughlin | c07e7d2 | 2008-11-21 16:54:46 +0000 | [diff] [blame] | 240 | static inline void context_set_translation_type(struct context_entry *context, |
| 241 | unsigned long value) |
| 242 | { |
| 243 | context->lo &= (((u64)-1) << 4) | 3; |
| 244 | context->lo |= (value & 3) << 2; |
| 245 | } |
| 246 | |
| 247 | static inline void context_set_address_root(struct context_entry *context, |
| 248 | unsigned long value) |
| 249 | { |
| 250 | context->lo |= value & VTD_PAGE_MASK; |
| 251 | } |
| 252 | |
| 253 | static inline void context_set_address_width(struct context_entry *context, |
| 254 | unsigned long value) |
| 255 | { |
| 256 | context->hi |= value & 7; |
| 257 | } |
| 258 | |
| 259 | static inline void context_set_domain_id(struct context_entry *context, |
| 260 | unsigned long value) |
| 261 | { |
| 262 | context->hi |= (value & ((1 << 16) - 1)) << 8; |
| 263 | } |
| 264 | |
| 265 | static inline void context_clear_entry(struct context_entry *context) |
| 266 | { |
| 267 | context->lo = 0; |
| 268 | context->hi = 0; |
| 269 | } |
Mark McLoughlin | 7a8fc25 | 2008-11-20 15:49:45 +0000 | [diff] [blame] | 270 | |
Mark McLoughlin | 622ba12 | 2008-11-20 15:49:46 +0000 | [diff] [blame] | 271 | /* |
| 272 | * 0: readable |
| 273 | * 1: writable |
| 274 | * 2-6: reserved |
| 275 | * 7: super page |
Sheng Yang | 9cf06697 | 2009-03-18 15:33:07 +0800 | [diff] [blame] | 276 | * 8-10: available |
| 277 | * 11: snoop behavior |
Mark McLoughlin | 622ba12 | 2008-11-20 15:49:46 +0000 | [diff] [blame] | 278 | * 12-63: Host physcial address |
| 279 | */ |
| 280 | struct dma_pte { |
| 281 | u64 val; |
| 282 | }; |
Mark McLoughlin | 622ba12 | 2008-11-20 15:49:46 +0000 | [diff] [blame] | 283 | |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 284 | static inline void dma_clear_pte(struct dma_pte *pte) |
| 285 | { |
| 286 | pte->val = 0; |
| 287 | } |
| 288 | |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 289 | static inline u64 dma_pte_addr(struct dma_pte *pte) |
| 290 | { |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 291 | #ifdef CONFIG_64BIT |
| 292 | return pte->val & VTD_PAGE_MASK; |
| 293 | #else |
| 294 | /* Must have a full atomic 64-bit read */ |
David Woodhouse | 1a8bd48 | 2010-08-10 01:38:53 +0100 | [diff] [blame] | 295 | return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK; |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 296 | #endif |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 297 | } |
| 298 | |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 299 | static inline bool dma_pte_present(struct dma_pte *pte) |
| 300 | { |
| 301 | return (pte->val & 3) != 0; |
| 302 | } |
Mark McLoughlin | 622ba12 | 2008-11-20 15:49:46 +0000 | [diff] [blame] | 303 | |
Allen Kay | 4399c8b | 2011-10-14 12:32:46 -0700 | [diff] [blame] | 304 | static inline bool dma_pte_superpage(struct dma_pte *pte) |
| 305 | { |
| 306 | return (pte->val & (1 << 7)); |
| 307 | } |
| 308 | |
David Woodhouse | 75e6bf9 | 2009-07-02 11:21:16 +0100 | [diff] [blame] | 309 | static inline int first_pte_in_page(struct dma_pte *pte) |
| 310 | { |
| 311 | return !((unsigned long)pte & ~VTD_PAGE_MASK); |
| 312 | } |
| 313 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 314 | /* |
| 315 | * This domain is a statically identity mapping domain. |
| 316 | * 1. This domain creats a static 1:1 mapping to all usable memory. |
| 317 | * 2. It maps to each iommu if successful. |
| 318 | * 3. Each iommu mapps to this domain if successful. |
| 319 | */ |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 320 | static struct dmar_domain *si_domain; |
| 321 | static int hw_pass_through = 1; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 322 | |
Weidong Han | 3b5410e | 2008-12-08 09:17:15 +0800 | [diff] [blame] | 323 | /* devices under the same p2p bridge are owned in one domain */ |
Mike Day | cdc7b83 | 2008-12-12 17:16:30 +0100 | [diff] [blame] | 324 | #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0) |
Weidong Han | 3b5410e | 2008-12-08 09:17:15 +0800 | [diff] [blame] | 325 | |
Weidong Han | 1ce28fe | 2008-12-08 16:35:39 +0800 | [diff] [blame] | 326 | /* domain represents a virtual machine, more than one devices |
| 327 | * across iommus may be owned in one domain, e.g. kvm guest. |
| 328 | */ |
| 329 | #define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1) |
| 330 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 331 | /* si_domain contains mulitple devices */ |
| 332 | #define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2) |
| 333 | |
Mike Travis | 1b198bb | 2012-03-05 15:05:16 -0800 | [diff] [blame] | 334 | /* define the limit of IOMMUs supported in each domain */ |
| 335 | #ifdef CONFIG_X86 |
| 336 | # define IOMMU_UNITS_SUPPORTED MAX_IO_APICS |
| 337 | #else |
| 338 | # define IOMMU_UNITS_SUPPORTED 64 |
| 339 | #endif |
| 340 | |
Mark McLoughlin | 99126f7 | 2008-11-20 15:49:47 +0000 | [diff] [blame] | 341 | struct dmar_domain { |
| 342 | int id; /* domain id */ |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 343 | int nid; /* node id */ |
Mike Travis | 1b198bb | 2012-03-05 15:05:16 -0800 | [diff] [blame] | 344 | DECLARE_BITMAP(iommu_bmp, IOMMU_UNITS_SUPPORTED); |
| 345 | /* bitmap of iommus this domain uses*/ |
Mark McLoughlin | 99126f7 | 2008-11-20 15:49:47 +0000 | [diff] [blame] | 346 | |
| 347 | struct list_head devices; /* all devices' list */ |
| 348 | struct iova_domain iovad; /* iova's that belong to this domain */ |
| 349 | |
| 350 | struct dma_pte *pgd; /* virtual address */ |
Mark McLoughlin | 99126f7 | 2008-11-20 15:49:47 +0000 | [diff] [blame] | 351 | int gaw; /* max guest address width */ |
| 352 | |
| 353 | /* adjusted guest address width, 0 is level 2 30-bit */ |
| 354 | int agaw; |
| 355 | |
Weidong Han | 3b5410e | 2008-12-08 09:17:15 +0800 | [diff] [blame] | 356 | int flags; /* flags to find out type of domain */ |
Weidong Han | 8e604097 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 357 | |
| 358 | int iommu_coherency;/* indicate coherency of iommu access */ |
Sheng Yang | 58c610b | 2009-03-18 15:33:05 +0800 | [diff] [blame] | 359 | int iommu_snooping; /* indicate snooping control feature*/ |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 360 | int iommu_count; /* reference count of iommu */ |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 361 | int iommu_superpage;/* Level of superpages supported: |
| 362 | 0 == 4KiB (no superpages), 1 == 2MiB, |
| 363 | 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */ |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 364 | spinlock_t iommu_lock; /* protect iommu set in domain */ |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 365 | u64 max_addr; /* maximum mapped address */ |
Mark McLoughlin | 99126f7 | 2008-11-20 15:49:47 +0000 | [diff] [blame] | 366 | }; |
| 367 | |
Mark McLoughlin | a647dac | 2008-11-20 15:49:48 +0000 | [diff] [blame] | 368 | /* PCI domain-device relationship */ |
| 369 | struct device_domain_info { |
| 370 | struct list_head link; /* link to domain siblings */ |
| 371 | struct list_head global; /* link to global list */ |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 372 | int segment; /* PCI domain */ |
| 373 | u8 bus; /* PCI bus number */ |
Mark McLoughlin | a647dac | 2008-11-20 15:49:48 +0000 | [diff] [blame] | 374 | u8 devfn; /* PCI devfn number */ |
Stefan Assmann | 45e829e | 2009-12-03 06:49:24 -0500 | [diff] [blame] | 375 | struct pci_dev *dev; /* it's NULL for PCIe-to-PCI bridge */ |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 376 | struct intel_iommu *iommu; /* IOMMU used by this device */ |
Mark McLoughlin | a647dac | 2008-11-20 15:49:48 +0000 | [diff] [blame] | 377 | struct dmar_domain *domain; /* pointer to domain */ |
| 378 | }; |
| 379 | |
Jiang Liu | b94e411 | 2014-02-19 14:07:25 +0800 | [diff] [blame] | 380 | struct dmar_rmrr_unit { |
| 381 | struct list_head list; /* list of rmrr units */ |
| 382 | struct acpi_dmar_header *hdr; /* ACPI header */ |
| 383 | u64 base_address; /* reserved base address*/ |
| 384 | u64 end_address; /* reserved end address */ |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 385 | struct dmar_dev_scope *devices; /* target devices */ |
Jiang Liu | b94e411 | 2014-02-19 14:07:25 +0800 | [diff] [blame] | 386 | int devices_cnt; /* target device count */ |
| 387 | }; |
| 388 | |
| 389 | struct dmar_atsr_unit { |
| 390 | struct list_head list; /* list of ATSR units */ |
| 391 | struct acpi_dmar_header *hdr; /* ACPI header */ |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 392 | struct dmar_dev_scope *devices; /* target devices */ |
Jiang Liu | b94e411 | 2014-02-19 14:07:25 +0800 | [diff] [blame] | 393 | int devices_cnt; /* target device count */ |
| 394 | u8 include_all:1; /* include all ports */ |
| 395 | }; |
| 396 | |
| 397 | static LIST_HEAD(dmar_atsr_units); |
| 398 | static LIST_HEAD(dmar_rmrr_units); |
| 399 | |
| 400 | #define for_each_rmrr_units(rmrr) \ |
| 401 | list_for_each_entry(rmrr, &dmar_rmrr_units, list) |
| 402 | |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 403 | static void flush_unmaps_timeout(unsigned long data); |
| 404 | |
Jiang Liu | b707cb0 | 2014-01-06 14:18:26 +0800 | [diff] [blame] | 405 | static DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 406 | |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 407 | #define HIGH_WATER_MARK 250 |
| 408 | struct deferred_flush_tables { |
| 409 | int next; |
| 410 | struct iova *iova[HIGH_WATER_MARK]; |
| 411 | struct dmar_domain *domain[HIGH_WATER_MARK]; |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 412 | struct page *freelist[HIGH_WATER_MARK]; |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 413 | }; |
| 414 | |
| 415 | static struct deferred_flush_tables *deferred_flush; |
| 416 | |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 417 | /* bitmap for indexing intel_iommus */ |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 418 | static int g_num_of_iommus; |
| 419 | |
| 420 | static DEFINE_SPINLOCK(async_umap_flush_lock); |
| 421 | static LIST_HEAD(unmaps_to_do); |
| 422 | |
| 423 | static int timer_on; |
| 424 | static long list_size; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 425 | |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 426 | static void domain_exit(struct dmar_domain *domain); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 427 | static void domain_remove_dev_info(struct dmar_domain *domain); |
Jiang Liu | b94e411 | 2014-02-19 14:07:25 +0800 | [diff] [blame] | 428 | static void domain_remove_one_dev_info(struct dmar_domain *domain, |
| 429 | struct pci_dev *pdev); |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 430 | static void iommu_detach_dependent_devices(struct intel_iommu *iommu, |
| 431 | struct pci_dev *pdev); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 432 | |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 433 | #ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON |
Kyle McMartin | 0cd5c3c | 2009-02-04 14:29:19 -0800 | [diff] [blame] | 434 | int dmar_disabled = 0; |
| 435 | #else |
| 436 | int dmar_disabled = 1; |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 437 | #endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/ |
Kyle McMartin | 0cd5c3c | 2009-02-04 14:29:19 -0800 | [diff] [blame] | 438 | |
Eugeni Dodonov | 8bc1f85 | 2011-11-23 16:42:14 -0200 | [diff] [blame] | 439 | int intel_iommu_enabled = 0; |
| 440 | EXPORT_SYMBOL_GPL(intel_iommu_enabled); |
| 441 | |
David Woodhouse | 2d9e667 | 2010-06-15 10:57:57 +0100 | [diff] [blame] | 442 | static int dmar_map_gfx = 1; |
Keshavamurthy, Anil S | 7d3b03c | 2007-10-21 16:41:53 -0700 | [diff] [blame] | 443 | static int dmar_forcedac; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 444 | static int intel_iommu_strict; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 445 | static int intel_iommu_superpage = 1; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 446 | |
David Woodhouse | c0771df | 2011-10-14 20:59:46 +0100 | [diff] [blame] | 447 | int intel_iommu_gfx_mapped; |
| 448 | EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped); |
| 449 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 450 | #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1)) |
| 451 | static DEFINE_SPINLOCK(device_domain_lock); |
| 452 | static LIST_HEAD(device_domain_list); |
| 453 | |
Joerg Roedel | a8bcbb0d | 2008-12-03 15:14:02 +0100 | [diff] [blame] | 454 | static struct iommu_ops intel_iommu_ops; |
| 455 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 456 | static int __init intel_iommu_setup(char *str) |
| 457 | { |
| 458 | if (!str) |
| 459 | return -EINVAL; |
| 460 | while (*str) { |
Kyle McMartin | 0cd5c3c | 2009-02-04 14:29:19 -0800 | [diff] [blame] | 461 | if (!strncmp(str, "on", 2)) { |
| 462 | dmar_disabled = 0; |
| 463 | printk(KERN_INFO "Intel-IOMMU: enabled\n"); |
| 464 | } else if (!strncmp(str, "off", 3)) { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 465 | dmar_disabled = 1; |
Kyle McMartin | 0cd5c3c | 2009-02-04 14:29:19 -0800 | [diff] [blame] | 466 | printk(KERN_INFO "Intel-IOMMU: disabled\n"); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 467 | } else if (!strncmp(str, "igfx_off", 8)) { |
| 468 | dmar_map_gfx = 0; |
| 469 | printk(KERN_INFO |
| 470 | "Intel-IOMMU: disable GFX device mapping\n"); |
Keshavamurthy, Anil S | 7d3b03c | 2007-10-21 16:41:53 -0700 | [diff] [blame] | 471 | } else if (!strncmp(str, "forcedac", 8)) { |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 472 | printk(KERN_INFO |
Keshavamurthy, Anil S | 7d3b03c | 2007-10-21 16:41:53 -0700 | [diff] [blame] | 473 | "Intel-IOMMU: Forcing DAC for PCI devices\n"); |
| 474 | dmar_forcedac = 1; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 475 | } else if (!strncmp(str, "strict", 6)) { |
| 476 | printk(KERN_INFO |
| 477 | "Intel-IOMMU: disable batched IOTLB flush\n"); |
| 478 | intel_iommu_strict = 1; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 479 | } else if (!strncmp(str, "sp_off", 6)) { |
| 480 | printk(KERN_INFO |
| 481 | "Intel-IOMMU: disable supported super page\n"); |
| 482 | intel_iommu_superpage = 0; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 483 | } |
| 484 | |
| 485 | str += strcspn(str, ","); |
| 486 | while (*str == ',') |
| 487 | str++; |
| 488 | } |
| 489 | return 0; |
| 490 | } |
| 491 | __setup("intel_iommu=", intel_iommu_setup); |
| 492 | |
| 493 | static struct kmem_cache *iommu_domain_cache; |
| 494 | static struct kmem_cache *iommu_devinfo_cache; |
| 495 | static struct kmem_cache *iommu_iova_cache; |
| 496 | |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 497 | static inline void *alloc_pgtable_page(int node) |
Keshavamurthy, Anil S | eb3fa7c | 2007-10-21 16:41:52 -0700 | [diff] [blame] | 498 | { |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 499 | struct page *page; |
| 500 | void *vaddr = NULL; |
Keshavamurthy, Anil S | eb3fa7c | 2007-10-21 16:41:52 -0700 | [diff] [blame] | 501 | |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 502 | page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0); |
| 503 | if (page) |
| 504 | vaddr = page_address(page); |
Keshavamurthy, Anil S | eb3fa7c | 2007-10-21 16:41:52 -0700 | [diff] [blame] | 505 | return vaddr; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 506 | } |
| 507 | |
| 508 | static inline void free_pgtable_page(void *vaddr) |
| 509 | { |
| 510 | free_page((unsigned long)vaddr); |
| 511 | } |
| 512 | |
| 513 | static inline void *alloc_domain_mem(void) |
| 514 | { |
KOSAKI Motohiro | 354bb65 | 2009-11-17 16:21:09 +0900 | [diff] [blame] | 515 | return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 516 | } |
| 517 | |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 518 | static void free_domain_mem(void *vaddr) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 519 | { |
| 520 | kmem_cache_free(iommu_domain_cache, vaddr); |
| 521 | } |
| 522 | |
| 523 | static inline void * alloc_devinfo_mem(void) |
| 524 | { |
KOSAKI Motohiro | 354bb65 | 2009-11-17 16:21:09 +0900 | [diff] [blame] | 525 | return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 526 | } |
| 527 | |
| 528 | static inline void free_devinfo_mem(void *vaddr) |
| 529 | { |
| 530 | kmem_cache_free(iommu_devinfo_cache, vaddr); |
| 531 | } |
| 532 | |
| 533 | struct iova *alloc_iova_mem(void) |
| 534 | { |
KOSAKI Motohiro | 354bb65 | 2009-11-17 16:21:09 +0900 | [diff] [blame] | 535 | return kmem_cache_alloc(iommu_iova_cache, GFP_ATOMIC); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 536 | } |
| 537 | |
| 538 | void free_iova_mem(struct iova *iova) |
| 539 | { |
| 540 | kmem_cache_free(iommu_iova_cache, iova); |
| 541 | } |
| 542 | |
Weidong Han | 1b57368 | 2008-12-08 15:34:06 +0800 | [diff] [blame] | 543 | |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 544 | static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw) |
Weidong Han | 1b57368 | 2008-12-08 15:34:06 +0800 | [diff] [blame] | 545 | { |
| 546 | unsigned long sagaw; |
| 547 | int agaw = -1; |
| 548 | |
| 549 | sagaw = cap_sagaw(iommu->cap); |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 550 | for (agaw = width_to_agaw(max_gaw); |
Weidong Han | 1b57368 | 2008-12-08 15:34:06 +0800 | [diff] [blame] | 551 | agaw >= 0; agaw--) { |
| 552 | if (test_bit(agaw, &sagaw)) |
| 553 | break; |
| 554 | } |
| 555 | |
| 556 | return agaw; |
| 557 | } |
| 558 | |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 559 | /* |
| 560 | * Calculate max SAGAW for each iommu. |
| 561 | */ |
| 562 | int iommu_calculate_max_sagaw(struct intel_iommu *iommu) |
| 563 | { |
| 564 | return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH); |
| 565 | } |
| 566 | |
| 567 | /* |
| 568 | * calculate agaw for each iommu. |
| 569 | * "SAGAW" may be different across iommus, use a default agaw, and |
| 570 | * get a supported less agaw for iommus that don't support the default agaw. |
| 571 | */ |
| 572 | int iommu_calculate_agaw(struct intel_iommu *iommu) |
| 573 | { |
| 574 | return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH); |
| 575 | } |
| 576 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 577 | /* This functionin only returns single iommu in a domain */ |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 578 | static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain) |
| 579 | { |
| 580 | int iommu_id; |
| 581 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 582 | /* si_domain and vm domain should not get here. */ |
Weidong Han | 1ce28fe | 2008-12-08 16:35:39 +0800 | [diff] [blame] | 583 | BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 584 | BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY); |
Weidong Han | 1ce28fe | 2008-12-08 16:35:39 +0800 | [diff] [blame] | 585 | |
Mike Travis | 1b198bb | 2012-03-05 15:05:16 -0800 | [diff] [blame] | 586 | iommu_id = find_first_bit(domain->iommu_bmp, g_num_of_iommus); |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 587 | if (iommu_id < 0 || iommu_id >= g_num_of_iommus) |
| 588 | return NULL; |
| 589 | |
| 590 | return g_iommus[iommu_id]; |
| 591 | } |
| 592 | |
Weidong Han | 8e604097 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 593 | static void domain_update_iommu_coherency(struct dmar_domain *domain) |
| 594 | { |
David Woodhouse | d050196 | 2014-03-11 17:10:29 -0700 | [diff] [blame] | 595 | struct dmar_drhd_unit *drhd; |
| 596 | struct intel_iommu *iommu; |
| 597 | int i, found = 0; |
Weidong Han | 8e604097 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 598 | |
David Woodhouse | d050196 | 2014-03-11 17:10:29 -0700 | [diff] [blame] | 599 | domain->iommu_coherency = 1; |
Weidong Han | 8e604097 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 600 | |
Mike Travis | 1b198bb | 2012-03-05 15:05:16 -0800 | [diff] [blame] | 601 | for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) { |
David Woodhouse | d050196 | 2014-03-11 17:10:29 -0700 | [diff] [blame] | 602 | found = 1; |
Weidong Han | 8e604097 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 603 | if (!ecap_coherent(g_iommus[i]->ecap)) { |
| 604 | domain->iommu_coherency = 0; |
| 605 | break; |
| 606 | } |
Weidong Han | 8e604097 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 607 | } |
David Woodhouse | d050196 | 2014-03-11 17:10:29 -0700 | [diff] [blame] | 608 | if (found) |
| 609 | return; |
| 610 | |
| 611 | /* No hardware attached; use lowest common denominator */ |
| 612 | rcu_read_lock(); |
| 613 | for_each_active_iommu(iommu, drhd) { |
| 614 | if (!ecap_coherent(iommu->ecap)) { |
| 615 | domain->iommu_coherency = 0; |
| 616 | break; |
| 617 | } |
| 618 | } |
| 619 | rcu_read_unlock(); |
Weidong Han | 8e604097 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 620 | } |
| 621 | |
Sheng Yang | 58c610b | 2009-03-18 15:33:05 +0800 | [diff] [blame] | 622 | static void domain_update_iommu_snooping(struct dmar_domain *domain) |
| 623 | { |
| 624 | int i; |
| 625 | |
| 626 | domain->iommu_snooping = 1; |
| 627 | |
Mike Travis | 1b198bb | 2012-03-05 15:05:16 -0800 | [diff] [blame] | 628 | for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) { |
Sheng Yang | 58c610b | 2009-03-18 15:33:05 +0800 | [diff] [blame] | 629 | if (!ecap_sc_support(g_iommus[i]->ecap)) { |
| 630 | domain->iommu_snooping = 0; |
| 631 | break; |
| 632 | } |
Sheng Yang | 58c610b | 2009-03-18 15:33:05 +0800 | [diff] [blame] | 633 | } |
| 634 | } |
| 635 | |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 636 | static void domain_update_iommu_superpage(struct dmar_domain *domain) |
| 637 | { |
Allen Kay | 8140a95 | 2011-10-14 12:32:17 -0700 | [diff] [blame] | 638 | struct dmar_drhd_unit *drhd; |
| 639 | struct intel_iommu *iommu = NULL; |
| 640 | int mask = 0xf; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 641 | |
| 642 | if (!intel_iommu_superpage) { |
| 643 | domain->iommu_superpage = 0; |
| 644 | return; |
| 645 | } |
| 646 | |
Allen Kay | 8140a95 | 2011-10-14 12:32:17 -0700 | [diff] [blame] | 647 | /* set iommu_superpage to the smallest common denominator */ |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 648 | rcu_read_lock(); |
Allen Kay | 8140a95 | 2011-10-14 12:32:17 -0700 | [diff] [blame] | 649 | for_each_active_iommu(iommu, drhd) { |
| 650 | mask &= cap_super_page_val(iommu->cap); |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 651 | if (!mask) { |
| 652 | break; |
| 653 | } |
| 654 | } |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 655 | rcu_read_unlock(); |
| 656 | |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 657 | domain->iommu_superpage = fls(mask); |
| 658 | } |
| 659 | |
Sheng Yang | 58c610b | 2009-03-18 15:33:05 +0800 | [diff] [blame] | 660 | /* Some capabilities may be different across iommus */ |
| 661 | static void domain_update_iommu_cap(struct dmar_domain *domain) |
| 662 | { |
| 663 | domain_update_iommu_coherency(domain); |
| 664 | domain_update_iommu_snooping(domain); |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 665 | domain_update_iommu_superpage(domain); |
Sheng Yang | 58c610b | 2009-03-18 15:33:05 +0800 | [diff] [blame] | 666 | } |
| 667 | |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 668 | static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn) |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 669 | { |
| 670 | struct dmar_drhd_unit *drhd = NULL; |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 671 | struct intel_iommu *iommu; |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 672 | struct device *dev; |
| 673 | struct pci_dev *pdev; |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 674 | int i; |
| 675 | |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 676 | rcu_read_lock(); |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 677 | for_each_active_iommu(iommu, drhd) { |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 678 | if (segment != drhd->segment) |
| 679 | continue; |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 680 | |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 681 | for_each_active_dev_scope(drhd->devices, |
| 682 | drhd->devices_cnt, i, dev) { |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 683 | if (!dev_is_pci(dev)) |
| 684 | continue; |
| 685 | pdev = to_pci_dev(dev); |
| 686 | if (pdev->bus->number == bus && pdev->devfn == devfn) |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 687 | goto out; |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 688 | if (pdev->subordinate && |
| 689 | pdev->subordinate->number <= bus && |
| 690 | pdev->subordinate->busn_res.end >= bus) |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 691 | goto out; |
David Woodhouse | 924b623 | 2009-04-04 00:39:25 +0100 | [diff] [blame] | 692 | } |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 693 | |
| 694 | if (drhd->include_all) |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 695 | goto out; |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 696 | } |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 697 | iommu = NULL; |
| 698 | out: |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 699 | rcu_read_unlock(); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 700 | |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 701 | return iommu; |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 702 | } |
| 703 | |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 704 | static void domain_flush_cache(struct dmar_domain *domain, |
| 705 | void *addr, int size) |
| 706 | { |
| 707 | if (!domain->iommu_coherency) |
| 708 | clflush_cache_range(addr, size); |
| 709 | } |
| 710 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 711 | /* Gets context entry for a given bus and devfn */ |
| 712 | static struct context_entry * device_to_context_entry(struct intel_iommu *iommu, |
| 713 | u8 bus, u8 devfn) |
| 714 | { |
| 715 | struct root_entry *root; |
| 716 | struct context_entry *context; |
| 717 | unsigned long phy_addr; |
| 718 | unsigned long flags; |
| 719 | |
| 720 | spin_lock_irqsave(&iommu->lock, flags); |
| 721 | root = &iommu->root_entry[bus]; |
| 722 | context = get_context_addr_from_root(root); |
| 723 | if (!context) { |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 724 | context = (struct context_entry *) |
| 725 | alloc_pgtable_page(iommu->node); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 726 | if (!context) { |
| 727 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 728 | return NULL; |
| 729 | } |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 730 | __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 731 | phy_addr = virt_to_phys((void *)context); |
| 732 | set_root_value(root, phy_addr); |
| 733 | set_root_present(root); |
| 734 | __iommu_flush_cache(iommu, root, sizeof(*root)); |
| 735 | } |
| 736 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 737 | return &context[devfn]; |
| 738 | } |
| 739 | |
| 740 | static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn) |
| 741 | { |
| 742 | struct root_entry *root; |
| 743 | struct context_entry *context; |
| 744 | int ret; |
| 745 | unsigned long flags; |
| 746 | |
| 747 | spin_lock_irqsave(&iommu->lock, flags); |
| 748 | root = &iommu->root_entry[bus]; |
| 749 | context = get_context_addr_from_root(root); |
| 750 | if (!context) { |
| 751 | ret = 0; |
| 752 | goto out; |
| 753 | } |
Mark McLoughlin | c07e7d2 | 2008-11-21 16:54:46 +0000 | [diff] [blame] | 754 | ret = context_present(&context[devfn]); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 755 | out: |
| 756 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 757 | return ret; |
| 758 | } |
| 759 | |
| 760 | static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn) |
| 761 | { |
| 762 | struct root_entry *root; |
| 763 | struct context_entry *context; |
| 764 | unsigned long flags; |
| 765 | |
| 766 | spin_lock_irqsave(&iommu->lock, flags); |
| 767 | root = &iommu->root_entry[bus]; |
| 768 | context = get_context_addr_from_root(root); |
| 769 | if (context) { |
Mark McLoughlin | c07e7d2 | 2008-11-21 16:54:46 +0000 | [diff] [blame] | 770 | context_clear_entry(&context[devfn]); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 771 | __iommu_flush_cache(iommu, &context[devfn], \ |
| 772 | sizeof(*context)); |
| 773 | } |
| 774 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 775 | } |
| 776 | |
| 777 | static void free_context_table(struct intel_iommu *iommu) |
| 778 | { |
| 779 | struct root_entry *root; |
| 780 | int i; |
| 781 | unsigned long flags; |
| 782 | struct context_entry *context; |
| 783 | |
| 784 | spin_lock_irqsave(&iommu->lock, flags); |
| 785 | if (!iommu->root_entry) { |
| 786 | goto out; |
| 787 | } |
| 788 | for (i = 0; i < ROOT_ENTRY_NR; i++) { |
| 789 | root = &iommu->root_entry[i]; |
| 790 | context = get_context_addr_from_root(root); |
| 791 | if (context) |
| 792 | free_pgtable_page(context); |
| 793 | } |
| 794 | free_pgtable_page(iommu->root_entry); |
| 795 | iommu->root_entry = NULL; |
| 796 | out: |
| 797 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 798 | } |
| 799 | |
David Woodhouse | b026fd2 | 2009-06-28 10:37:25 +0100 | [diff] [blame] | 800 | static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain, |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 801 | unsigned long pfn, int *target_level) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 802 | { |
David Woodhouse | b026fd2 | 2009-06-28 10:37:25 +0100 | [diff] [blame] | 803 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 804 | struct dma_pte *parent, *pte = NULL; |
| 805 | int level = agaw_to_level(domain->agaw); |
Allen Kay | 4399c8b | 2011-10-14 12:32:46 -0700 | [diff] [blame] | 806 | int offset; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 807 | |
| 808 | BUG_ON(!domain->pgd); |
Julian Stecklina | f942360 | 2013-10-09 10:03:52 +0200 | [diff] [blame] | 809 | |
| 810 | if (addr_width < BITS_PER_LONG && pfn >> addr_width) |
| 811 | /* Address beyond IOMMU's addressing capabilities. */ |
| 812 | return NULL; |
| 813 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 814 | parent = domain->pgd; |
| 815 | |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 816 | while (1) { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 817 | void *tmp_page; |
| 818 | |
David Woodhouse | b026fd2 | 2009-06-28 10:37:25 +0100 | [diff] [blame] | 819 | offset = pfn_level_offset(pfn, level); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 820 | pte = &parent[offset]; |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 821 | if (!*target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte))) |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 822 | break; |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 823 | if (level == *target_level) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 824 | break; |
| 825 | |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 826 | if (!dma_pte_present(pte)) { |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 827 | uint64_t pteval; |
| 828 | |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 829 | tmp_page = alloc_pgtable_page(domain->nid); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 830 | |
David Woodhouse | 206a73c1 | 2009-07-01 19:30:28 +0100 | [diff] [blame] | 831 | if (!tmp_page) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 832 | return NULL; |
David Woodhouse | 206a73c1 | 2009-07-01 19:30:28 +0100 | [diff] [blame] | 833 | |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 834 | domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE); |
Benjamin LaHaise | 64de5af | 2009-09-16 21:05:55 -0400 | [diff] [blame] | 835 | pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE; |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 836 | if (cmpxchg64(&pte->val, 0ULL, pteval)) { |
| 837 | /* Someone else set it while we were thinking; use theirs. */ |
| 838 | free_pgtable_page(tmp_page); |
| 839 | } else { |
| 840 | dma_pte_addr(pte); |
| 841 | domain_flush_cache(domain, pte, sizeof(*pte)); |
| 842 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 843 | } |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 844 | if (level == 1) |
| 845 | break; |
| 846 | |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 847 | parent = phys_to_virt(dma_pte_addr(pte)); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 848 | level--; |
| 849 | } |
| 850 | |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 851 | if (!*target_level) |
| 852 | *target_level = level; |
| 853 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 854 | return pte; |
| 855 | } |
| 856 | |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 857 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 858 | /* return address's pte at specific level */ |
David Woodhouse | 90dcfb5 | 2009-06-27 17:14:59 +0100 | [diff] [blame] | 859 | static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain, |
| 860 | unsigned long pfn, |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 861 | int level, int *large_page) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 862 | { |
| 863 | struct dma_pte *parent, *pte = NULL; |
| 864 | int total = agaw_to_level(domain->agaw); |
| 865 | int offset; |
| 866 | |
| 867 | parent = domain->pgd; |
| 868 | while (level <= total) { |
David Woodhouse | 90dcfb5 | 2009-06-27 17:14:59 +0100 | [diff] [blame] | 869 | offset = pfn_level_offset(pfn, total); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 870 | pte = &parent[offset]; |
| 871 | if (level == total) |
| 872 | return pte; |
| 873 | |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 874 | if (!dma_pte_present(pte)) { |
| 875 | *large_page = total; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 876 | break; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 877 | } |
| 878 | |
| 879 | if (pte->val & DMA_PTE_LARGE_PAGE) { |
| 880 | *large_page = total; |
| 881 | return pte; |
| 882 | } |
| 883 | |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 884 | parent = phys_to_virt(dma_pte_addr(pte)); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 885 | total--; |
| 886 | } |
| 887 | return NULL; |
| 888 | } |
| 889 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 890 | /* clear last level pte, a tlb flush should be followed */ |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 891 | static void dma_pte_clear_range(struct dmar_domain *domain, |
David Woodhouse | 595badf | 2009-06-27 22:09:11 +0100 | [diff] [blame] | 892 | unsigned long start_pfn, |
| 893 | unsigned long last_pfn) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 894 | { |
David Woodhouse | 04b18e6 | 2009-06-27 19:15:01 +0100 | [diff] [blame] | 895 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 896 | unsigned int large_page = 1; |
David Woodhouse | 310a5ab | 2009-06-28 18:52:20 +0100 | [diff] [blame] | 897 | struct dma_pte *first_pte, *pte; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 898 | |
David Woodhouse | 04b18e6 | 2009-06-27 19:15:01 +0100 | [diff] [blame] | 899 | BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width); |
David Woodhouse | 595badf | 2009-06-27 22:09:11 +0100 | [diff] [blame] | 900 | BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width); |
David Woodhouse | 59c3628 | 2009-09-19 07:36:28 -0700 | [diff] [blame] | 901 | BUG_ON(start_pfn > last_pfn); |
David Woodhouse | 66eae84 | 2009-06-27 19:00:32 +0100 | [diff] [blame] | 902 | |
David Woodhouse | 04b18e6 | 2009-06-27 19:15:01 +0100 | [diff] [blame] | 903 | /* we don't need lock here; nobody else touches the iova range */ |
David Woodhouse | 59c3628 | 2009-09-19 07:36:28 -0700 | [diff] [blame] | 904 | do { |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 905 | large_page = 1; |
| 906 | first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page); |
David Woodhouse | 310a5ab | 2009-06-28 18:52:20 +0100 | [diff] [blame] | 907 | if (!pte) { |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 908 | start_pfn = align_to_level(start_pfn + 1, large_page + 1); |
David Woodhouse | 310a5ab | 2009-06-28 18:52:20 +0100 | [diff] [blame] | 909 | continue; |
| 910 | } |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 911 | do { |
David Woodhouse | 310a5ab | 2009-06-28 18:52:20 +0100 | [diff] [blame] | 912 | dma_clear_pte(pte); |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 913 | start_pfn += lvl_to_nr_pages(large_page); |
David Woodhouse | 310a5ab | 2009-06-28 18:52:20 +0100 | [diff] [blame] | 914 | pte++; |
David Woodhouse | 75e6bf9 | 2009-07-02 11:21:16 +0100 | [diff] [blame] | 915 | } while (start_pfn <= last_pfn && !first_pte_in_page(pte)); |
| 916 | |
David Woodhouse | 310a5ab | 2009-06-28 18:52:20 +0100 | [diff] [blame] | 917 | domain_flush_cache(domain, first_pte, |
| 918 | (void *)pte - (void *)first_pte); |
David Woodhouse | 59c3628 | 2009-09-19 07:36:28 -0700 | [diff] [blame] | 919 | |
| 920 | } while (start_pfn && start_pfn <= last_pfn); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 921 | } |
| 922 | |
Alex Williamson | 3269ee0 | 2013-06-15 10:27:19 -0600 | [diff] [blame] | 923 | static void dma_pte_free_level(struct dmar_domain *domain, int level, |
| 924 | struct dma_pte *pte, unsigned long pfn, |
| 925 | unsigned long start_pfn, unsigned long last_pfn) |
| 926 | { |
| 927 | pfn = max(start_pfn, pfn); |
| 928 | pte = &pte[pfn_level_offset(pfn, level)]; |
| 929 | |
| 930 | do { |
| 931 | unsigned long level_pfn; |
| 932 | struct dma_pte *level_pte; |
| 933 | |
| 934 | if (!dma_pte_present(pte) || dma_pte_superpage(pte)) |
| 935 | goto next; |
| 936 | |
| 937 | level_pfn = pfn & level_mask(level - 1); |
| 938 | level_pte = phys_to_virt(dma_pte_addr(pte)); |
| 939 | |
| 940 | if (level > 2) |
| 941 | dma_pte_free_level(domain, level - 1, level_pte, |
| 942 | level_pfn, start_pfn, last_pfn); |
| 943 | |
| 944 | /* If range covers entire pagetable, free it */ |
| 945 | if (!(start_pfn > level_pfn || |
Alex Williamson | 08336fd | 2014-01-21 15:48:18 -0800 | [diff] [blame] | 946 | last_pfn < level_pfn + level_size(level) - 1)) { |
Alex Williamson | 3269ee0 | 2013-06-15 10:27:19 -0600 | [diff] [blame] | 947 | dma_clear_pte(pte); |
| 948 | domain_flush_cache(domain, pte, sizeof(*pte)); |
| 949 | free_pgtable_page(level_pte); |
| 950 | } |
| 951 | next: |
| 952 | pfn += level_size(level); |
| 953 | } while (!first_pte_in_page(++pte) && pfn <= last_pfn); |
| 954 | } |
| 955 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 956 | /* free page table pages. last level pte should already be cleared */ |
| 957 | static void dma_pte_free_pagetable(struct dmar_domain *domain, |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 958 | unsigned long start_pfn, |
| 959 | unsigned long last_pfn) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 960 | { |
David Woodhouse | 6660c63 | 2009-06-27 22:41:00 +0100 | [diff] [blame] | 961 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 962 | |
David Woodhouse | 6660c63 | 2009-06-27 22:41:00 +0100 | [diff] [blame] | 963 | BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width); |
| 964 | BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width); |
David Woodhouse | 59c3628 | 2009-09-19 07:36:28 -0700 | [diff] [blame] | 965 | BUG_ON(start_pfn > last_pfn); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 966 | |
David Woodhouse | f3a0a52 | 2009-06-30 03:40:07 +0100 | [diff] [blame] | 967 | /* We don't need lock here; nobody else touches the iova range */ |
Alex Williamson | 3269ee0 | 2013-06-15 10:27:19 -0600 | [diff] [blame] | 968 | dma_pte_free_level(domain, agaw_to_level(domain->agaw), |
| 969 | domain->pgd, 0, start_pfn, last_pfn); |
David Woodhouse | 6660c63 | 2009-06-27 22:41:00 +0100 | [diff] [blame] | 970 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 971 | /* free pgd */ |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 972 | if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 973 | free_pgtable_page(domain->pgd); |
| 974 | domain->pgd = NULL; |
| 975 | } |
| 976 | } |
| 977 | |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 978 | /* When a page at a given level is being unlinked from its parent, we don't |
| 979 | need to *modify* it at all. All we need to do is make a list of all the |
| 980 | pages which can be freed just as soon as we've flushed the IOTLB and we |
| 981 | know the hardware page-walk will no longer touch them. |
| 982 | The 'pte' argument is the *parent* PTE, pointing to the page that is to |
| 983 | be freed. */ |
| 984 | static struct page *dma_pte_list_pagetables(struct dmar_domain *domain, |
| 985 | int level, struct dma_pte *pte, |
| 986 | struct page *freelist) |
| 987 | { |
| 988 | struct page *pg; |
| 989 | |
| 990 | pg = pfn_to_page(dma_pte_addr(pte) >> PAGE_SHIFT); |
| 991 | pg->freelist = freelist; |
| 992 | freelist = pg; |
| 993 | |
| 994 | if (level == 1) |
| 995 | return freelist; |
| 996 | |
| 997 | for (pte = page_address(pg); !first_pte_in_page(pte); pte++) { |
| 998 | if (dma_pte_present(pte) && !dma_pte_superpage(pte)) |
| 999 | freelist = dma_pte_list_pagetables(domain, level - 1, |
| 1000 | pte, freelist); |
| 1001 | } |
| 1002 | |
| 1003 | return freelist; |
| 1004 | } |
| 1005 | |
| 1006 | static struct page *dma_pte_clear_level(struct dmar_domain *domain, int level, |
| 1007 | struct dma_pte *pte, unsigned long pfn, |
| 1008 | unsigned long start_pfn, |
| 1009 | unsigned long last_pfn, |
| 1010 | struct page *freelist) |
| 1011 | { |
| 1012 | struct dma_pte *first_pte = NULL, *last_pte = NULL; |
| 1013 | |
| 1014 | pfn = max(start_pfn, pfn); |
| 1015 | pte = &pte[pfn_level_offset(pfn, level)]; |
| 1016 | |
| 1017 | do { |
| 1018 | unsigned long level_pfn; |
| 1019 | |
| 1020 | if (!dma_pte_present(pte)) |
| 1021 | goto next; |
| 1022 | |
| 1023 | level_pfn = pfn & level_mask(level); |
| 1024 | |
| 1025 | /* If range covers entire pagetable, free it */ |
| 1026 | if (start_pfn <= level_pfn && |
| 1027 | last_pfn >= level_pfn + level_size(level) - 1) { |
| 1028 | /* These suborbinate page tables are going away entirely. Don't |
| 1029 | bother to clear them; we're just going to *free* them. */ |
| 1030 | if (level > 1 && !dma_pte_superpage(pte)) |
| 1031 | freelist = dma_pte_list_pagetables(domain, level - 1, pte, freelist); |
| 1032 | |
| 1033 | dma_clear_pte(pte); |
| 1034 | if (!first_pte) |
| 1035 | first_pte = pte; |
| 1036 | last_pte = pte; |
| 1037 | } else if (level > 1) { |
| 1038 | /* Recurse down into a level that isn't *entirely* obsolete */ |
| 1039 | freelist = dma_pte_clear_level(domain, level - 1, |
| 1040 | phys_to_virt(dma_pte_addr(pte)), |
| 1041 | level_pfn, start_pfn, last_pfn, |
| 1042 | freelist); |
| 1043 | } |
| 1044 | next: |
| 1045 | pfn += level_size(level); |
| 1046 | } while (!first_pte_in_page(++pte) && pfn <= last_pfn); |
| 1047 | |
| 1048 | if (first_pte) |
| 1049 | domain_flush_cache(domain, first_pte, |
| 1050 | (void *)++last_pte - (void *)first_pte); |
| 1051 | |
| 1052 | return freelist; |
| 1053 | } |
| 1054 | |
| 1055 | /* We can't just free the pages because the IOMMU may still be walking |
| 1056 | the page tables, and may have cached the intermediate levels. The |
| 1057 | pages can only be freed after the IOTLB flush has been done. */ |
| 1058 | struct page *domain_unmap(struct dmar_domain *domain, |
| 1059 | unsigned long start_pfn, |
| 1060 | unsigned long last_pfn) |
| 1061 | { |
| 1062 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
| 1063 | struct page *freelist = NULL; |
| 1064 | |
| 1065 | BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width); |
| 1066 | BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width); |
| 1067 | BUG_ON(start_pfn > last_pfn); |
| 1068 | |
| 1069 | /* we don't need lock here; nobody else touches the iova range */ |
| 1070 | freelist = dma_pte_clear_level(domain, agaw_to_level(domain->agaw), |
| 1071 | domain->pgd, 0, start_pfn, last_pfn, NULL); |
| 1072 | |
| 1073 | /* free pgd */ |
| 1074 | if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) { |
| 1075 | struct page *pgd_page = virt_to_page(domain->pgd); |
| 1076 | pgd_page->freelist = freelist; |
| 1077 | freelist = pgd_page; |
| 1078 | |
| 1079 | domain->pgd = NULL; |
| 1080 | } |
| 1081 | |
| 1082 | return freelist; |
| 1083 | } |
| 1084 | |
| 1085 | void dma_free_pagelist(struct page *freelist) |
| 1086 | { |
| 1087 | struct page *pg; |
| 1088 | |
| 1089 | while ((pg = freelist)) { |
| 1090 | freelist = pg->freelist; |
| 1091 | free_pgtable_page(page_address(pg)); |
| 1092 | } |
| 1093 | } |
| 1094 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1095 | /* iommu handling */ |
| 1096 | static int iommu_alloc_root_entry(struct intel_iommu *iommu) |
| 1097 | { |
| 1098 | struct root_entry *root; |
| 1099 | unsigned long flags; |
| 1100 | |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 1101 | root = (struct root_entry *)alloc_pgtable_page(iommu->node); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1102 | if (!root) |
| 1103 | return -ENOMEM; |
| 1104 | |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 1105 | __iommu_flush_cache(iommu, root, ROOT_SIZE); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1106 | |
| 1107 | spin_lock_irqsave(&iommu->lock, flags); |
| 1108 | iommu->root_entry = root; |
| 1109 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 1110 | |
| 1111 | return 0; |
| 1112 | } |
| 1113 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1114 | static void iommu_set_root_entry(struct intel_iommu *iommu) |
| 1115 | { |
| 1116 | void *addr; |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 1117 | u32 sts; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1118 | unsigned long flag; |
| 1119 | |
| 1120 | addr = iommu->root_entry; |
| 1121 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1122 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1123 | dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr)); |
| 1124 | |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 1125 | writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1126 | |
| 1127 | /* Make sure hardware complete it */ |
| 1128 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 1129 | readl, (sts & DMA_GSTS_RTPS), sts); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1130 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1131 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1132 | } |
| 1133 | |
| 1134 | static void iommu_flush_write_buffer(struct intel_iommu *iommu) |
| 1135 | { |
| 1136 | u32 val; |
| 1137 | unsigned long flag; |
| 1138 | |
David Woodhouse | 9af8814 | 2009-02-13 23:18:03 +0000 | [diff] [blame] | 1139 | if (!rwbf_quirk && !cap_rwbf(iommu->cap)) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1140 | return; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1141 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1142 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
David Woodhouse | 462b60f | 2009-05-10 20:18:18 +0100 | [diff] [blame] | 1143 | writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1144 | |
| 1145 | /* Make sure hardware complete it */ |
| 1146 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 1147 | readl, (!(val & DMA_GSTS_WBFS)), val); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1148 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1149 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1150 | } |
| 1151 | |
| 1152 | /* return value determine if we need a write buffer flush */ |
David Woodhouse | 4c25a2c | 2009-05-10 17:16:06 +0100 | [diff] [blame] | 1153 | static void __iommu_flush_context(struct intel_iommu *iommu, |
| 1154 | u16 did, u16 source_id, u8 function_mask, |
| 1155 | u64 type) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1156 | { |
| 1157 | u64 val = 0; |
| 1158 | unsigned long flag; |
| 1159 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1160 | switch (type) { |
| 1161 | case DMA_CCMD_GLOBAL_INVL: |
| 1162 | val = DMA_CCMD_GLOBAL_INVL; |
| 1163 | break; |
| 1164 | case DMA_CCMD_DOMAIN_INVL: |
| 1165 | val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did); |
| 1166 | break; |
| 1167 | case DMA_CCMD_DEVICE_INVL: |
| 1168 | val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did) |
| 1169 | | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask); |
| 1170 | break; |
| 1171 | default: |
| 1172 | BUG(); |
| 1173 | } |
| 1174 | val |= DMA_CCMD_ICC; |
| 1175 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1176 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1177 | dmar_writeq(iommu->reg + DMAR_CCMD_REG, val); |
| 1178 | |
| 1179 | /* Make sure hardware complete it */ |
| 1180 | IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG, |
| 1181 | dmar_readq, (!(val & DMA_CCMD_ICC)), val); |
| 1182 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1183 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1184 | } |
| 1185 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1186 | /* return value determine if we need a write buffer flush */ |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 1187 | static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did, |
| 1188 | u64 addr, unsigned int size_order, u64 type) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1189 | { |
| 1190 | int tlb_offset = ecap_iotlb_offset(iommu->ecap); |
| 1191 | u64 val = 0, val_iva = 0; |
| 1192 | unsigned long flag; |
| 1193 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1194 | switch (type) { |
| 1195 | case DMA_TLB_GLOBAL_FLUSH: |
| 1196 | /* global flush doesn't need set IVA_REG */ |
| 1197 | val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT; |
| 1198 | break; |
| 1199 | case DMA_TLB_DSI_FLUSH: |
| 1200 | val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); |
| 1201 | break; |
| 1202 | case DMA_TLB_PSI_FLUSH: |
| 1203 | val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1204 | /* IH bit is passed in as part of address */ |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1205 | val_iva = size_order | addr; |
| 1206 | break; |
| 1207 | default: |
| 1208 | BUG(); |
| 1209 | } |
| 1210 | /* Note: set drain read/write */ |
| 1211 | #if 0 |
| 1212 | /* |
| 1213 | * This is probably to be super secure.. Looks like we can |
| 1214 | * ignore it without any impact. |
| 1215 | */ |
| 1216 | if (cap_read_drain(iommu->cap)) |
| 1217 | val |= DMA_TLB_READ_DRAIN; |
| 1218 | #endif |
| 1219 | if (cap_write_drain(iommu->cap)) |
| 1220 | val |= DMA_TLB_WRITE_DRAIN; |
| 1221 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1222 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1223 | /* Note: Only uses first TLB reg currently */ |
| 1224 | if (val_iva) |
| 1225 | dmar_writeq(iommu->reg + tlb_offset, val_iva); |
| 1226 | dmar_writeq(iommu->reg + tlb_offset + 8, val); |
| 1227 | |
| 1228 | /* Make sure hardware complete it */ |
| 1229 | IOMMU_WAIT_OP(iommu, tlb_offset + 8, |
| 1230 | dmar_readq, (!(val & DMA_TLB_IVT)), val); |
| 1231 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1232 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1233 | |
| 1234 | /* check IOTLB invalidation granularity */ |
| 1235 | if (DMA_TLB_IAIG(val) == 0) |
| 1236 | printk(KERN_ERR"IOMMU: flush IOTLB failed\n"); |
| 1237 | if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type)) |
| 1238 | pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n", |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 1239 | (unsigned long long)DMA_TLB_IIRG(type), |
| 1240 | (unsigned long long)DMA_TLB_IAIG(val)); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1241 | } |
| 1242 | |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1243 | static struct device_domain_info *iommu_support_dev_iotlb( |
| 1244 | struct dmar_domain *domain, int segment, u8 bus, u8 devfn) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1245 | { |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1246 | int found = 0; |
| 1247 | unsigned long flags; |
| 1248 | struct device_domain_info *info; |
| 1249 | struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn); |
| 1250 | |
| 1251 | if (!ecap_dev_iotlb_support(iommu->ecap)) |
| 1252 | return NULL; |
| 1253 | |
| 1254 | if (!iommu->qi) |
| 1255 | return NULL; |
| 1256 | |
| 1257 | spin_lock_irqsave(&device_domain_lock, flags); |
| 1258 | list_for_each_entry(info, &domain->devices, link) |
| 1259 | if (info->bus == bus && info->devfn == devfn) { |
| 1260 | found = 1; |
| 1261 | break; |
| 1262 | } |
| 1263 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 1264 | |
| 1265 | if (!found || !info->dev) |
| 1266 | return NULL; |
| 1267 | |
| 1268 | if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS)) |
| 1269 | return NULL; |
| 1270 | |
| 1271 | if (!dmar_find_matched_atsr_unit(info->dev)) |
| 1272 | return NULL; |
| 1273 | |
| 1274 | info->iommu = iommu; |
| 1275 | |
| 1276 | return info; |
| 1277 | } |
| 1278 | |
| 1279 | static void iommu_enable_dev_iotlb(struct device_domain_info *info) |
| 1280 | { |
| 1281 | if (!info) |
| 1282 | return; |
| 1283 | |
| 1284 | pci_enable_ats(info->dev, VTD_PAGE_SHIFT); |
| 1285 | } |
| 1286 | |
| 1287 | static void iommu_disable_dev_iotlb(struct device_domain_info *info) |
| 1288 | { |
| 1289 | if (!info->dev || !pci_ats_enabled(info->dev)) |
| 1290 | return; |
| 1291 | |
| 1292 | pci_disable_ats(info->dev); |
| 1293 | } |
| 1294 | |
| 1295 | static void iommu_flush_dev_iotlb(struct dmar_domain *domain, |
| 1296 | u64 addr, unsigned mask) |
| 1297 | { |
| 1298 | u16 sid, qdep; |
| 1299 | unsigned long flags; |
| 1300 | struct device_domain_info *info; |
| 1301 | |
| 1302 | spin_lock_irqsave(&device_domain_lock, flags); |
| 1303 | list_for_each_entry(info, &domain->devices, link) { |
| 1304 | if (!info->dev || !pci_ats_enabled(info->dev)) |
| 1305 | continue; |
| 1306 | |
| 1307 | sid = info->bus << 8 | info->devfn; |
| 1308 | qdep = pci_ats_queue_depth(info->dev); |
| 1309 | qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask); |
| 1310 | } |
| 1311 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 1312 | } |
| 1313 | |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 1314 | static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did, |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1315 | unsigned long pfn, unsigned int pages, int ih, int map) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1316 | { |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 1317 | unsigned int mask = ilog2(__roundup_pow_of_two(pages)); |
David Woodhouse | 03d6a24 | 2009-06-28 15:33:46 +0100 | [diff] [blame] | 1318 | uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1319 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1320 | BUG_ON(pages == 0); |
| 1321 | |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1322 | if (ih) |
| 1323 | ih = 1 << 6; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1324 | /* |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 1325 | * Fallback to domain selective flush if no PSI support or the size is |
| 1326 | * too big. |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1327 | * PSI requires page size to be 2 ^ x, and the base address is naturally |
| 1328 | * aligned to the size |
| 1329 | */ |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 1330 | if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap)) |
| 1331 | iommu->flush.flush_iotlb(iommu, did, 0, 0, |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 1332 | DMA_TLB_DSI_FLUSH); |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 1333 | else |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1334 | iommu->flush.flush_iotlb(iommu, did, addr | ih, mask, |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 1335 | DMA_TLB_PSI_FLUSH); |
Yu Zhao | bf92df3 | 2009-06-29 11:31:45 +0800 | [diff] [blame] | 1336 | |
| 1337 | /* |
Nadav Amit | 8265363 | 2010-04-01 13:24:40 +0300 | [diff] [blame] | 1338 | * In caching mode, changes of pages from non-present to present require |
| 1339 | * flush. However, device IOTLB doesn't need to be flushed in this case. |
Yu Zhao | bf92df3 | 2009-06-29 11:31:45 +0800 | [diff] [blame] | 1340 | */ |
Nadav Amit | 8265363 | 2010-04-01 13:24:40 +0300 | [diff] [blame] | 1341 | if (!cap_caching_mode(iommu->cap) || !map) |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1342 | iommu_flush_dev_iotlb(iommu->domains[did], addr, mask); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1343 | } |
| 1344 | |
mark gross | f8bab73 | 2008-02-08 04:18:38 -0800 | [diff] [blame] | 1345 | static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu) |
| 1346 | { |
| 1347 | u32 pmen; |
| 1348 | unsigned long flags; |
| 1349 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1350 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
mark gross | f8bab73 | 2008-02-08 04:18:38 -0800 | [diff] [blame] | 1351 | pmen = readl(iommu->reg + DMAR_PMEN_REG); |
| 1352 | pmen &= ~DMA_PMEN_EPM; |
| 1353 | writel(pmen, iommu->reg + DMAR_PMEN_REG); |
| 1354 | |
| 1355 | /* wait for the protected region status bit to clear */ |
| 1356 | IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG, |
| 1357 | readl, !(pmen & DMA_PMEN_PRS), pmen); |
| 1358 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1359 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
mark gross | f8bab73 | 2008-02-08 04:18:38 -0800 | [diff] [blame] | 1360 | } |
| 1361 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1362 | static int iommu_enable_translation(struct intel_iommu *iommu) |
| 1363 | { |
| 1364 | u32 sts; |
| 1365 | unsigned long flags; |
| 1366 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1367 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 1368 | iommu->gcmd |= DMA_GCMD_TE; |
| 1369 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1370 | |
| 1371 | /* Make sure hardware complete it */ |
| 1372 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 1373 | readl, (sts & DMA_GSTS_TES), sts); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1374 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1375 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1376 | return 0; |
| 1377 | } |
| 1378 | |
| 1379 | static int iommu_disable_translation(struct intel_iommu *iommu) |
| 1380 | { |
| 1381 | u32 sts; |
| 1382 | unsigned long flag; |
| 1383 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1384 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1385 | iommu->gcmd &= ~DMA_GCMD_TE; |
| 1386 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
| 1387 | |
| 1388 | /* Make sure hardware complete it */ |
| 1389 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 1390 | readl, (!(sts & DMA_GSTS_TES)), sts); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1391 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1392 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1393 | return 0; |
| 1394 | } |
| 1395 | |
Keshavamurthy, Anil S | 3460a6d | 2007-10-21 16:41:54 -0700 | [diff] [blame] | 1396 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1397 | static int iommu_init_domains(struct intel_iommu *iommu) |
| 1398 | { |
| 1399 | unsigned long ndomains; |
| 1400 | unsigned long nlongs; |
| 1401 | |
| 1402 | ndomains = cap_ndoms(iommu->cap); |
Jiang Liu | 852bdb0 | 2014-01-06 14:18:11 +0800 | [diff] [blame] | 1403 | pr_debug("IOMMU%d: Number of Domains supported <%ld>\n", |
| 1404 | iommu->seq_id, ndomains); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1405 | nlongs = BITS_TO_LONGS(ndomains); |
| 1406 | |
Donald Dutile | 94a91b5 | 2009-08-20 16:51:34 -0400 | [diff] [blame] | 1407 | spin_lock_init(&iommu->lock); |
| 1408 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1409 | /* TBD: there might be 64K domains, |
| 1410 | * consider other allocation for future chip |
| 1411 | */ |
| 1412 | iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL); |
| 1413 | if (!iommu->domain_ids) { |
Jiang Liu | 852bdb0 | 2014-01-06 14:18:11 +0800 | [diff] [blame] | 1414 | pr_err("IOMMU%d: allocating domain id array failed\n", |
| 1415 | iommu->seq_id); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1416 | return -ENOMEM; |
| 1417 | } |
| 1418 | iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *), |
| 1419 | GFP_KERNEL); |
| 1420 | if (!iommu->domains) { |
Jiang Liu | 852bdb0 | 2014-01-06 14:18:11 +0800 | [diff] [blame] | 1421 | pr_err("IOMMU%d: allocating domain array failed\n", |
| 1422 | iommu->seq_id); |
| 1423 | kfree(iommu->domain_ids); |
| 1424 | iommu->domain_ids = NULL; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1425 | return -ENOMEM; |
| 1426 | } |
| 1427 | |
| 1428 | /* |
| 1429 | * if Caching mode is set, then invalid translations are tagged |
| 1430 | * with domainid 0. Hence we need to pre-allocate it. |
| 1431 | */ |
| 1432 | if (cap_caching_mode(iommu->cap)) |
| 1433 | set_bit(0, iommu->domain_ids); |
| 1434 | return 0; |
| 1435 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1436 | |
Jiang Liu | a868e6b | 2014-01-06 14:18:20 +0800 | [diff] [blame] | 1437 | static void free_dmar_iommu(struct intel_iommu *iommu) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1438 | { |
| 1439 | struct dmar_domain *domain; |
Jiang Liu | 5ced12a | 2014-01-06 14:18:22 +0800 | [diff] [blame] | 1440 | int i, count; |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 1441 | unsigned long flags; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1442 | |
Donald Dutile | 94a91b5 | 2009-08-20 16:51:34 -0400 | [diff] [blame] | 1443 | if ((iommu->domains) && (iommu->domain_ids)) { |
Akinobu Mita | a45946a | 2010-03-11 14:04:08 -0800 | [diff] [blame] | 1444 | for_each_set_bit(i, iommu->domain_ids, cap_ndoms(iommu->cap)) { |
Jiang Liu | a4eaa86 | 2014-02-19 14:07:30 +0800 | [diff] [blame] | 1445 | /* |
| 1446 | * Domain id 0 is reserved for invalid translation |
| 1447 | * if hardware supports caching mode. |
| 1448 | */ |
| 1449 | if (cap_caching_mode(iommu->cap) && i == 0) |
| 1450 | continue; |
| 1451 | |
Donald Dutile | 94a91b5 | 2009-08-20 16:51:34 -0400 | [diff] [blame] | 1452 | domain = iommu->domains[i]; |
| 1453 | clear_bit(i, iommu->domain_ids); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 1454 | |
Donald Dutile | 94a91b5 | 2009-08-20 16:51:34 -0400 | [diff] [blame] | 1455 | spin_lock_irqsave(&domain->iommu_lock, flags); |
Jiang Liu | 5ced12a | 2014-01-06 14:18:22 +0800 | [diff] [blame] | 1456 | count = --domain->iommu_count; |
| 1457 | spin_unlock_irqrestore(&domain->iommu_lock, flags); |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 1458 | if (count == 0) |
| 1459 | domain_exit(domain); |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 1460 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1461 | } |
| 1462 | |
| 1463 | if (iommu->gcmd & DMA_GCMD_TE) |
| 1464 | iommu_disable_translation(iommu); |
| 1465 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1466 | kfree(iommu->domains); |
| 1467 | kfree(iommu->domain_ids); |
Jiang Liu | a868e6b | 2014-01-06 14:18:20 +0800 | [diff] [blame] | 1468 | iommu->domains = NULL; |
| 1469 | iommu->domain_ids = NULL; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1470 | |
Weidong Han | d9630fe | 2008-12-08 11:06:32 +0800 | [diff] [blame] | 1471 | g_iommus[iommu->seq_id] = NULL; |
| 1472 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1473 | /* free context mapping */ |
| 1474 | free_context_table(iommu); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1475 | } |
| 1476 | |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 1477 | static struct dmar_domain *alloc_domain(bool vm) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1478 | { |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 1479 | /* domain id for virtual machine, it won't be set in context */ |
| 1480 | static atomic_t vm_domid = ATOMIC_INIT(0); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1481 | struct dmar_domain *domain; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1482 | |
| 1483 | domain = alloc_domain_mem(); |
| 1484 | if (!domain) |
| 1485 | return NULL; |
| 1486 | |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 1487 | domain->nid = -1; |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 1488 | domain->iommu_count = 0; |
Mike Travis | 1b198bb | 2012-03-05 15:05:16 -0800 | [diff] [blame] | 1489 | memset(domain->iommu_bmp, 0, sizeof(domain->iommu_bmp)); |
Weidong Han | d71a2f3 | 2008-12-07 21:13:41 +0800 | [diff] [blame] | 1490 | domain->flags = 0; |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 1491 | spin_lock_init(&domain->iommu_lock); |
| 1492 | INIT_LIST_HEAD(&domain->devices); |
| 1493 | if (vm) { |
| 1494 | domain->id = atomic_inc_return(&vm_domid); |
| 1495 | domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE; |
| 1496 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1497 | |
| 1498 | return domain; |
| 1499 | } |
| 1500 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1501 | static int iommu_attach_domain(struct dmar_domain *domain, |
| 1502 | struct intel_iommu *iommu) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1503 | { |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1504 | int num; |
| 1505 | unsigned long ndomains; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1506 | unsigned long flags; |
| 1507 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1508 | ndomains = cap_ndoms(iommu->cap); |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 1509 | |
| 1510 | spin_lock_irqsave(&iommu->lock, flags); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1511 | |
| 1512 | num = find_first_zero_bit(iommu->domain_ids, ndomains); |
| 1513 | if (num >= ndomains) { |
| 1514 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 1515 | printk(KERN_ERR "IOMMU: no free domain ids\n"); |
| 1516 | return -ENOMEM; |
| 1517 | } |
| 1518 | |
| 1519 | domain->id = num; |
Jiang Liu | 9ebd682 | 2014-02-19 14:07:29 +0800 | [diff] [blame] | 1520 | domain->iommu_count++; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1521 | set_bit(num, iommu->domain_ids); |
Mike Travis | 1b198bb | 2012-03-05 15:05:16 -0800 | [diff] [blame] | 1522 | set_bit(iommu->seq_id, domain->iommu_bmp); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1523 | iommu->domains[num] = domain; |
| 1524 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 1525 | |
| 1526 | return 0; |
| 1527 | } |
| 1528 | |
| 1529 | static void iommu_detach_domain(struct dmar_domain *domain, |
| 1530 | struct intel_iommu *iommu) |
| 1531 | { |
| 1532 | unsigned long flags; |
| 1533 | int num, ndomains; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1534 | |
| 1535 | spin_lock_irqsave(&iommu->lock, flags); |
| 1536 | ndomains = cap_ndoms(iommu->cap); |
Akinobu Mita | a45946a | 2010-03-11 14:04:08 -0800 | [diff] [blame] | 1537 | for_each_set_bit(num, iommu->domain_ids, ndomains) { |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1538 | if (iommu->domains[num] == domain) { |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 1539 | clear_bit(num, iommu->domain_ids); |
| 1540 | iommu->domains[num] = NULL; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1541 | break; |
| 1542 | } |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1543 | } |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 1544 | spin_unlock_irqrestore(&iommu->lock, flags); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1545 | } |
| 1546 | |
| 1547 | static struct iova_domain reserved_iova_list; |
Mark Gross | 8a443df | 2008-03-04 14:59:31 -0800 | [diff] [blame] | 1548 | static struct lock_class_key reserved_rbtree_key; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1549 | |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 1550 | static int dmar_init_reserved_ranges(void) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1551 | { |
| 1552 | struct pci_dev *pdev = NULL; |
| 1553 | struct iova *iova; |
| 1554 | int i; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1555 | |
David Miller | f661197 | 2008-02-06 01:36:23 -0800 | [diff] [blame] | 1556 | init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1557 | |
Mark Gross | 8a443df | 2008-03-04 14:59:31 -0800 | [diff] [blame] | 1558 | lockdep_set_class(&reserved_iova_list.iova_rbtree_lock, |
| 1559 | &reserved_rbtree_key); |
| 1560 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1561 | /* IOAPIC ranges shouldn't be accessed by DMA */ |
| 1562 | iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START), |
| 1563 | IOVA_PFN(IOAPIC_RANGE_END)); |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 1564 | if (!iova) { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1565 | printk(KERN_ERR "Reserve IOAPIC range failed\n"); |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 1566 | return -ENODEV; |
| 1567 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1568 | |
| 1569 | /* Reserve all PCI MMIO to avoid peer-to-peer access */ |
| 1570 | for_each_pci_dev(pdev) { |
| 1571 | struct resource *r; |
| 1572 | |
| 1573 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
| 1574 | r = &pdev->resource[i]; |
| 1575 | if (!r->flags || !(r->flags & IORESOURCE_MEM)) |
| 1576 | continue; |
David Woodhouse | 1a4a455 | 2009-06-28 16:00:42 +0100 | [diff] [blame] | 1577 | iova = reserve_iova(&reserved_iova_list, |
| 1578 | IOVA_PFN(r->start), |
| 1579 | IOVA_PFN(r->end)); |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 1580 | if (!iova) { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1581 | printk(KERN_ERR "Reserve iova failed\n"); |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 1582 | return -ENODEV; |
| 1583 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1584 | } |
| 1585 | } |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 1586 | return 0; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1587 | } |
| 1588 | |
| 1589 | static void domain_reserve_special_ranges(struct dmar_domain *domain) |
| 1590 | { |
| 1591 | copy_reserved_iova(&reserved_iova_list, &domain->iovad); |
| 1592 | } |
| 1593 | |
| 1594 | static inline int guestwidth_to_adjustwidth(int gaw) |
| 1595 | { |
| 1596 | int agaw; |
| 1597 | int r = (gaw - 12) % 9; |
| 1598 | |
| 1599 | if (r == 0) |
| 1600 | agaw = gaw; |
| 1601 | else |
| 1602 | agaw = gaw + 9 - r; |
| 1603 | if (agaw > 64) |
| 1604 | agaw = 64; |
| 1605 | return agaw; |
| 1606 | } |
| 1607 | |
| 1608 | static int domain_init(struct dmar_domain *domain, int guest_width) |
| 1609 | { |
| 1610 | struct intel_iommu *iommu; |
| 1611 | int adjust_width, agaw; |
| 1612 | unsigned long sagaw; |
| 1613 | |
David Miller | f661197 | 2008-02-06 01:36:23 -0800 | [diff] [blame] | 1614 | init_iova_domain(&domain->iovad, DMA_32BIT_PFN); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1615 | domain_reserve_special_ranges(domain); |
| 1616 | |
| 1617 | /* calculate AGAW */ |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 1618 | iommu = domain_get_iommu(domain); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1619 | if (guest_width > cap_mgaw(iommu->cap)) |
| 1620 | guest_width = cap_mgaw(iommu->cap); |
| 1621 | domain->gaw = guest_width; |
| 1622 | adjust_width = guestwidth_to_adjustwidth(guest_width); |
| 1623 | agaw = width_to_agaw(adjust_width); |
| 1624 | sagaw = cap_sagaw(iommu->cap); |
| 1625 | if (!test_bit(agaw, &sagaw)) { |
| 1626 | /* hardware doesn't support it, choose a bigger one */ |
| 1627 | pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw); |
| 1628 | agaw = find_next_bit(&sagaw, 5, agaw); |
| 1629 | if (agaw >= 5) |
| 1630 | return -ENODEV; |
| 1631 | } |
| 1632 | domain->agaw = agaw; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1633 | |
Weidong Han | 8e604097 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 1634 | if (ecap_coherent(iommu->ecap)) |
| 1635 | domain->iommu_coherency = 1; |
| 1636 | else |
| 1637 | domain->iommu_coherency = 0; |
| 1638 | |
Sheng Yang | 58c610b | 2009-03-18 15:33:05 +0800 | [diff] [blame] | 1639 | if (ecap_sc_support(iommu->ecap)) |
| 1640 | domain->iommu_snooping = 1; |
| 1641 | else |
| 1642 | domain->iommu_snooping = 0; |
| 1643 | |
David Woodhouse | 214e39a | 2014-03-19 10:38:49 +0000 | [diff] [blame] | 1644 | if (intel_iommu_superpage) |
| 1645 | domain->iommu_superpage = fls(cap_super_page_val(iommu->cap)); |
| 1646 | else |
| 1647 | domain->iommu_superpage = 0; |
| 1648 | |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 1649 | domain->nid = iommu->node; |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 1650 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1651 | /* always allocate the top pgd */ |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 1652 | domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1653 | if (!domain->pgd) |
| 1654 | return -ENOMEM; |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 1655 | __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1656 | return 0; |
| 1657 | } |
| 1658 | |
| 1659 | static void domain_exit(struct dmar_domain *domain) |
| 1660 | { |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1661 | struct dmar_drhd_unit *drhd; |
| 1662 | struct intel_iommu *iommu; |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1663 | struct page *freelist = NULL; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1664 | |
| 1665 | /* Domain 0 is reserved, so dont process it */ |
| 1666 | if (!domain) |
| 1667 | return; |
| 1668 | |
Alex Williamson | 7b66835 | 2011-05-24 12:02:41 +0100 | [diff] [blame] | 1669 | /* Flush any lazy unmaps that may reference this domain */ |
| 1670 | if (!intel_iommu_strict) |
| 1671 | flush_unmaps_timeout(0); |
| 1672 | |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 1673 | /* remove associated devices */ |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1674 | domain_remove_dev_info(domain); |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 1675 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1676 | /* destroy iovas */ |
| 1677 | put_iova_domain(&domain->iovad); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1678 | |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1679 | freelist = domain_unmap(domain, 0, DOMAIN_MAX_PFN(domain->gaw)); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1680 | |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 1681 | /* clear attached or cached domains */ |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 1682 | rcu_read_lock(); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1683 | for_each_active_iommu(iommu, drhd) |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 1684 | if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE || |
| 1685 | test_bit(iommu->seq_id, domain->iommu_bmp)) |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1686 | iommu_detach_domain(domain, iommu); |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 1687 | rcu_read_unlock(); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1688 | |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1689 | dma_free_pagelist(freelist); |
| 1690 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1691 | free_domain_mem(domain); |
| 1692 | } |
| 1693 | |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1694 | static int domain_context_mapping_one(struct dmar_domain *domain, int segment, |
| 1695 | u8 bus, u8 devfn, int translation) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1696 | { |
| 1697 | struct context_entry *context; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1698 | unsigned long flags; |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 1699 | struct intel_iommu *iommu; |
Weidong Han | ea6606b | 2008-12-08 23:08:15 +0800 | [diff] [blame] | 1700 | struct dma_pte *pgd; |
| 1701 | unsigned long num; |
| 1702 | unsigned long ndomains; |
| 1703 | int id; |
| 1704 | int agaw; |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1705 | struct device_domain_info *info = NULL; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1706 | |
| 1707 | pr_debug("Set context mapping for %02x:%02x.%d\n", |
| 1708 | bus, PCI_SLOT(devfn), PCI_FUNC(devfn)); |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1709 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1710 | BUG_ON(!domain->pgd); |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1711 | BUG_ON(translation != CONTEXT_TT_PASS_THROUGH && |
| 1712 | translation != CONTEXT_TT_MULTI_LEVEL); |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 1713 | |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1714 | iommu = device_to_iommu(segment, bus, devfn); |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 1715 | if (!iommu) |
| 1716 | return -ENODEV; |
| 1717 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1718 | context = device_to_context_entry(iommu, bus, devfn); |
| 1719 | if (!context) |
| 1720 | return -ENOMEM; |
| 1721 | spin_lock_irqsave(&iommu->lock, flags); |
Mark McLoughlin | c07e7d2 | 2008-11-21 16:54:46 +0000 | [diff] [blame] | 1722 | if (context_present(context)) { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1723 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 1724 | return 0; |
| 1725 | } |
| 1726 | |
Weidong Han | ea6606b | 2008-12-08 23:08:15 +0800 | [diff] [blame] | 1727 | id = domain->id; |
| 1728 | pgd = domain->pgd; |
| 1729 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1730 | if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE || |
| 1731 | domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) { |
Weidong Han | ea6606b | 2008-12-08 23:08:15 +0800 | [diff] [blame] | 1732 | int found = 0; |
| 1733 | |
| 1734 | /* find an available domain id for this device in iommu */ |
| 1735 | ndomains = cap_ndoms(iommu->cap); |
Akinobu Mita | a45946a | 2010-03-11 14:04:08 -0800 | [diff] [blame] | 1736 | for_each_set_bit(num, iommu->domain_ids, ndomains) { |
Weidong Han | ea6606b | 2008-12-08 23:08:15 +0800 | [diff] [blame] | 1737 | if (iommu->domains[num] == domain) { |
| 1738 | id = num; |
| 1739 | found = 1; |
| 1740 | break; |
| 1741 | } |
Weidong Han | ea6606b | 2008-12-08 23:08:15 +0800 | [diff] [blame] | 1742 | } |
| 1743 | |
| 1744 | if (found == 0) { |
| 1745 | num = find_first_zero_bit(iommu->domain_ids, ndomains); |
| 1746 | if (num >= ndomains) { |
| 1747 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 1748 | printk(KERN_ERR "IOMMU: no free domain ids\n"); |
| 1749 | return -EFAULT; |
| 1750 | } |
| 1751 | |
| 1752 | set_bit(num, iommu->domain_ids); |
| 1753 | iommu->domains[num] = domain; |
| 1754 | id = num; |
| 1755 | } |
| 1756 | |
| 1757 | /* Skip top levels of page tables for |
| 1758 | * iommu which has less agaw than default. |
Chris Wright | 1672af1 | 2009-12-02 12:06:34 -0800 | [diff] [blame] | 1759 | * Unnecessary for PT mode. |
Weidong Han | ea6606b | 2008-12-08 23:08:15 +0800 | [diff] [blame] | 1760 | */ |
Chris Wright | 1672af1 | 2009-12-02 12:06:34 -0800 | [diff] [blame] | 1761 | if (translation != CONTEXT_TT_PASS_THROUGH) { |
| 1762 | for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) { |
| 1763 | pgd = phys_to_virt(dma_pte_addr(pgd)); |
| 1764 | if (!dma_pte_present(pgd)) { |
| 1765 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 1766 | return -ENOMEM; |
| 1767 | } |
Weidong Han | ea6606b | 2008-12-08 23:08:15 +0800 | [diff] [blame] | 1768 | } |
| 1769 | } |
| 1770 | } |
| 1771 | |
| 1772 | context_set_domain_id(context, id); |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1773 | |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1774 | if (translation != CONTEXT_TT_PASS_THROUGH) { |
| 1775 | info = iommu_support_dev_iotlb(domain, segment, bus, devfn); |
| 1776 | translation = info ? CONTEXT_TT_DEV_IOTLB : |
| 1777 | CONTEXT_TT_MULTI_LEVEL; |
| 1778 | } |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1779 | /* |
| 1780 | * In pass through mode, AW must be programmed to indicate the largest |
| 1781 | * AGAW value supported by hardware. And ASR is ignored by hardware. |
| 1782 | */ |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1783 | if (unlikely(translation == CONTEXT_TT_PASS_THROUGH)) |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1784 | context_set_address_width(context, iommu->msagaw); |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1785 | else { |
| 1786 | context_set_address_root(context, virt_to_phys(pgd)); |
| 1787 | context_set_address_width(context, iommu->agaw); |
| 1788 | } |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1789 | |
| 1790 | context_set_translation_type(context, translation); |
Mark McLoughlin | c07e7d2 | 2008-11-21 16:54:46 +0000 | [diff] [blame] | 1791 | context_set_fault_enable(context); |
| 1792 | context_set_present(context); |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 1793 | domain_flush_cache(domain, context, sizeof(*context)); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1794 | |
David Woodhouse | 4c25a2c | 2009-05-10 17:16:06 +0100 | [diff] [blame] | 1795 | /* |
| 1796 | * It's a non-present to present mapping. If hardware doesn't cache |
| 1797 | * non-present entry we only need to flush the write-buffer. If the |
| 1798 | * _does_ cache non-present entries, then it does so in the special |
| 1799 | * domain #0, which we have to flush: |
| 1800 | */ |
| 1801 | if (cap_caching_mode(iommu->cap)) { |
| 1802 | iommu->flush.flush_context(iommu, 0, |
| 1803 | (((u16)bus) << 8) | devfn, |
| 1804 | DMA_CCMD_MASK_NOBIT, |
| 1805 | DMA_CCMD_DEVICE_INVL); |
Nadav Amit | 8265363 | 2010-04-01 13:24:40 +0300 | [diff] [blame] | 1806 | iommu->flush.flush_iotlb(iommu, domain->id, 0, 0, DMA_TLB_DSI_FLUSH); |
David Woodhouse | 4c25a2c | 2009-05-10 17:16:06 +0100 | [diff] [blame] | 1807 | } else { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1808 | iommu_flush_write_buffer(iommu); |
David Woodhouse | 4c25a2c | 2009-05-10 17:16:06 +0100 | [diff] [blame] | 1809 | } |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1810 | iommu_enable_dev_iotlb(info); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1811 | spin_unlock_irqrestore(&iommu->lock, flags); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 1812 | |
| 1813 | spin_lock_irqsave(&domain->iommu_lock, flags); |
Mike Travis | 1b198bb | 2012-03-05 15:05:16 -0800 | [diff] [blame] | 1814 | if (!test_and_set_bit(iommu->seq_id, domain->iommu_bmp)) { |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 1815 | domain->iommu_count++; |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 1816 | if (domain->iommu_count == 1) |
| 1817 | domain->nid = iommu->node; |
Sheng Yang | 58c610b | 2009-03-18 15:33:05 +0800 | [diff] [blame] | 1818 | domain_update_iommu_cap(domain); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 1819 | } |
| 1820 | spin_unlock_irqrestore(&domain->iommu_lock, flags); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1821 | return 0; |
| 1822 | } |
| 1823 | |
| 1824 | static int |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1825 | domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev, |
| 1826 | int translation) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1827 | { |
| 1828 | int ret; |
| 1829 | struct pci_dev *tmp, *parent; |
| 1830 | |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1831 | ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus), |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1832 | pdev->bus->number, pdev->devfn, |
| 1833 | translation); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1834 | if (ret) |
| 1835 | return ret; |
| 1836 | |
| 1837 | /* dependent device mapping */ |
| 1838 | tmp = pci_find_upstream_pcie_bridge(pdev); |
| 1839 | if (!tmp) |
| 1840 | return 0; |
| 1841 | /* Secondary interface's bus number and devfn 0 */ |
| 1842 | parent = pdev->bus->self; |
| 1843 | while (parent != tmp) { |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1844 | ret = domain_context_mapping_one(domain, |
| 1845 | pci_domain_nr(parent->bus), |
| 1846 | parent->bus->number, |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1847 | parent->devfn, translation); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1848 | if (ret) |
| 1849 | return ret; |
| 1850 | parent = parent->bus->self; |
| 1851 | } |
Stefan Assmann | 45e829e | 2009-12-03 06:49:24 -0500 | [diff] [blame] | 1852 | if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */ |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1853 | return domain_context_mapping_one(domain, |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1854 | pci_domain_nr(tmp->subordinate), |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1855 | tmp->subordinate->number, 0, |
| 1856 | translation); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1857 | else /* this is a legacy PCI bridge */ |
| 1858 | return domain_context_mapping_one(domain, |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1859 | pci_domain_nr(tmp->bus), |
| 1860 | tmp->bus->number, |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1861 | tmp->devfn, |
| 1862 | translation); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1863 | } |
| 1864 | |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 1865 | static int domain_context_mapped(struct pci_dev *pdev) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1866 | { |
| 1867 | int ret; |
| 1868 | struct pci_dev *tmp, *parent; |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 1869 | struct intel_iommu *iommu; |
| 1870 | |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1871 | iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number, |
| 1872 | pdev->devfn); |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 1873 | if (!iommu) |
| 1874 | return -ENODEV; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1875 | |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1876 | ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1877 | if (!ret) |
| 1878 | return ret; |
| 1879 | /* dependent device mapping */ |
| 1880 | tmp = pci_find_upstream_pcie_bridge(pdev); |
| 1881 | if (!tmp) |
| 1882 | return ret; |
| 1883 | /* Secondary interface's bus number and devfn 0 */ |
| 1884 | parent = pdev->bus->self; |
| 1885 | while (parent != tmp) { |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 1886 | ret = device_context_mapped(iommu, parent->bus->number, |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1887 | parent->devfn); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1888 | if (!ret) |
| 1889 | return ret; |
| 1890 | parent = parent->bus->self; |
| 1891 | } |
Kenji Kaneshige | 5f4d91a | 2009-11-11 14:36:17 +0900 | [diff] [blame] | 1892 | if (pci_is_pcie(tmp)) |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1893 | return device_context_mapped(iommu, tmp->subordinate->number, |
| 1894 | 0); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1895 | else |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 1896 | return device_context_mapped(iommu, tmp->bus->number, |
| 1897 | tmp->devfn); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1898 | } |
| 1899 | |
Fenghua Yu | f532959 | 2009-08-04 15:09:37 -0700 | [diff] [blame] | 1900 | /* Returns a number of VTD pages, but aligned to MM page size */ |
| 1901 | static inline unsigned long aligned_nrpages(unsigned long host_addr, |
| 1902 | size_t size) |
| 1903 | { |
| 1904 | host_addr &= ~PAGE_MASK; |
| 1905 | return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT; |
| 1906 | } |
| 1907 | |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 1908 | /* Return largest possible superpage level for a given mapping */ |
| 1909 | static inline int hardware_largepage_caps(struct dmar_domain *domain, |
| 1910 | unsigned long iov_pfn, |
| 1911 | unsigned long phy_pfn, |
| 1912 | unsigned long pages) |
| 1913 | { |
| 1914 | int support, level = 1; |
| 1915 | unsigned long pfnmerge; |
| 1916 | |
| 1917 | support = domain->iommu_superpage; |
| 1918 | |
| 1919 | /* To use a large page, the virtual *and* physical addresses |
| 1920 | must be aligned to 2MiB/1GiB/etc. Lower bits set in either |
| 1921 | of them will mean we have to use smaller pages. So just |
| 1922 | merge them and check both at once. */ |
| 1923 | pfnmerge = iov_pfn | phy_pfn; |
| 1924 | |
| 1925 | while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) { |
| 1926 | pages >>= VTD_STRIDE_SHIFT; |
| 1927 | if (!pages) |
| 1928 | break; |
| 1929 | pfnmerge >>= VTD_STRIDE_SHIFT; |
| 1930 | level++; |
| 1931 | support--; |
| 1932 | } |
| 1933 | return level; |
| 1934 | } |
| 1935 | |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 1936 | static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
| 1937 | struct scatterlist *sg, unsigned long phys_pfn, |
| 1938 | unsigned long nr_pages, int prot) |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 1939 | { |
| 1940 | struct dma_pte *first_pte = NULL, *pte = NULL; |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 1941 | phys_addr_t uninitialized_var(pteval); |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 1942 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 1943 | unsigned long sg_res; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 1944 | unsigned int largepage_lvl = 0; |
| 1945 | unsigned long lvl_pages = 0; |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 1946 | |
| 1947 | BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width); |
| 1948 | |
| 1949 | if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0) |
| 1950 | return -EINVAL; |
| 1951 | |
| 1952 | prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP; |
| 1953 | |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 1954 | if (sg) |
| 1955 | sg_res = 0; |
| 1956 | else { |
| 1957 | sg_res = nr_pages + 1; |
| 1958 | pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot; |
| 1959 | } |
| 1960 | |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 1961 | while (nr_pages > 0) { |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 1962 | uint64_t tmp; |
| 1963 | |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 1964 | if (!sg_res) { |
Fenghua Yu | f532959 | 2009-08-04 15:09:37 -0700 | [diff] [blame] | 1965 | sg_res = aligned_nrpages(sg->offset, sg->length); |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 1966 | sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset; |
| 1967 | sg->dma_length = sg->length; |
| 1968 | pteval = page_to_phys(sg_page(sg)) | prot; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 1969 | phys_pfn = pteval >> VTD_PAGE_SHIFT; |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 1970 | } |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 1971 | |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 1972 | if (!pte) { |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 1973 | largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res); |
| 1974 | |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 1975 | first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, &largepage_lvl); |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 1976 | if (!pte) |
| 1977 | return -ENOMEM; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 1978 | /* It is large page*/ |
Woodhouse, David | 6491d4d | 2012-12-19 13:25:35 +0000 | [diff] [blame] | 1979 | if (largepage_lvl > 1) { |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 1980 | pteval |= DMA_PTE_LARGE_PAGE; |
Woodhouse, David | 6491d4d | 2012-12-19 13:25:35 +0000 | [diff] [blame] | 1981 | /* Ensure that old small page tables are removed to make room |
| 1982 | for superpage, if they exist. */ |
| 1983 | dma_pte_clear_range(domain, iov_pfn, |
| 1984 | iov_pfn + lvl_to_nr_pages(largepage_lvl) - 1); |
| 1985 | dma_pte_free_pagetable(domain, iov_pfn, |
| 1986 | iov_pfn + lvl_to_nr_pages(largepage_lvl) - 1); |
| 1987 | } else { |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 1988 | pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE; |
Woodhouse, David | 6491d4d | 2012-12-19 13:25:35 +0000 | [diff] [blame] | 1989 | } |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 1990 | |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 1991 | } |
| 1992 | /* We don't need lock here, nobody else |
| 1993 | * touches the iova range |
| 1994 | */ |
David Woodhouse | 7766a3f | 2009-07-01 20:27:03 +0100 | [diff] [blame] | 1995 | tmp = cmpxchg64_local(&pte->val, 0ULL, pteval); |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 1996 | if (tmp) { |
David Woodhouse | 1bf20f0 | 2009-06-29 22:06:43 +0100 | [diff] [blame] | 1997 | static int dumps = 5; |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 1998 | printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n", |
| 1999 | iov_pfn, tmp, (unsigned long long)pteval); |
David Woodhouse | 1bf20f0 | 2009-06-29 22:06:43 +0100 | [diff] [blame] | 2000 | if (dumps) { |
| 2001 | dumps--; |
| 2002 | debug_dma_dump_mappings(NULL); |
| 2003 | } |
| 2004 | WARN_ON(1); |
| 2005 | } |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2006 | |
| 2007 | lvl_pages = lvl_to_nr_pages(largepage_lvl); |
| 2008 | |
| 2009 | BUG_ON(nr_pages < lvl_pages); |
| 2010 | BUG_ON(sg_res < lvl_pages); |
| 2011 | |
| 2012 | nr_pages -= lvl_pages; |
| 2013 | iov_pfn += lvl_pages; |
| 2014 | phys_pfn += lvl_pages; |
| 2015 | pteval += lvl_pages * VTD_PAGE_SIZE; |
| 2016 | sg_res -= lvl_pages; |
| 2017 | |
| 2018 | /* If the next PTE would be the first in a new page, then we |
| 2019 | need to flush the cache on the entries we've just written. |
| 2020 | And then we'll need to recalculate 'pte', so clear it and |
| 2021 | let it get set again in the if (!pte) block above. |
| 2022 | |
| 2023 | If we're done (!nr_pages) we need to flush the cache too. |
| 2024 | |
| 2025 | Also if we've been setting superpages, we may need to |
| 2026 | recalculate 'pte' and switch back to smaller pages for the |
| 2027 | end of the mapping, if the trailing size is not enough to |
| 2028 | use another superpage (i.e. sg_res < lvl_pages). */ |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 2029 | pte++; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2030 | if (!nr_pages || first_pte_in_page(pte) || |
| 2031 | (largepage_lvl > 1 && sg_res < lvl_pages)) { |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 2032 | domain_flush_cache(domain, first_pte, |
| 2033 | (void *)pte - (void *)first_pte); |
| 2034 | pte = NULL; |
| 2035 | } |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2036 | |
| 2037 | if (!sg_res && nr_pages) |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 2038 | sg = sg_next(sg); |
| 2039 | } |
| 2040 | return 0; |
| 2041 | } |
| 2042 | |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 2043 | static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
| 2044 | struct scatterlist *sg, unsigned long nr_pages, |
| 2045 | int prot) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2046 | { |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 2047 | return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot); |
| 2048 | } |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 2049 | |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 2050 | static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
| 2051 | unsigned long phys_pfn, unsigned long nr_pages, |
| 2052 | int prot) |
| 2053 | { |
| 2054 | return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2055 | } |
| 2056 | |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 2057 | static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2058 | { |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 2059 | if (!iommu) |
| 2060 | return; |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 2061 | |
| 2062 | clear_context_table(iommu, bus, devfn); |
| 2063 | iommu->flush.flush_context(iommu, 0, 0, 0, |
David Woodhouse | 4c25a2c | 2009-05-10 17:16:06 +0100 | [diff] [blame] | 2064 | DMA_CCMD_GLOBAL_INVL); |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 2065 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2066 | } |
| 2067 | |
David Woodhouse | 109b9b0 | 2012-05-25 17:43:02 +0100 | [diff] [blame] | 2068 | static inline void unlink_domain_info(struct device_domain_info *info) |
| 2069 | { |
| 2070 | assert_spin_locked(&device_domain_lock); |
| 2071 | list_del(&info->link); |
| 2072 | list_del(&info->global); |
| 2073 | if (info->dev) |
| 2074 | info->dev->dev.archdata.iommu = NULL; |
| 2075 | } |
| 2076 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2077 | static void domain_remove_dev_info(struct dmar_domain *domain) |
| 2078 | { |
| 2079 | struct device_domain_info *info; |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 2080 | unsigned long flags, flags2; |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 2081 | struct intel_iommu *iommu; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2082 | |
| 2083 | spin_lock_irqsave(&device_domain_lock, flags); |
| 2084 | while (!list_empty(&domain->devices)) { |
| 2085 | info = list_entry(domain->devices.next, |
| 2086 | struct device_domain_info, link); |
David Woodhouse | 109b9b0 | 2012-05-25 17:43:02 +0100 | [diff] [blame] | 2087 | unlink_domain_info(info); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2088 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 2089 | |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 2090 | iommu_disable_dev_iotlb(info); |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 2091 | iommu = device_to_iommu(info->segment, info->bus, info->devfn); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 2092 | iommu_detach_dev(iommu, info->bus, info->devfn); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2093 | |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 2094 | if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) { |
| 2095 | iommu_detach_dependent_devices(iommu, info->dev); |
| 2096 | /* clear this iommu in iommu_bmp, update iommu count |
| 2097 | * and capabilities |
| 2098 | */ |
| 2099 | spin_lock_irqsave(&domain->iommu_lock, flags2); |
| 2100 | if (test_and_clear_bit(iommu->seq_id, |
| 2101 | domain->iommu_bmp)) { |
| 2102 | domain->iommu_count--; |
| 2103 | domain_update_iommu_cap(domain); |
| 2104 | } |
| 2105 | spin_unlock_irqrestore(&domain->iommu_lock, flags2); |
| 2106 | } |
| 2107 | |
| 2108 | free_devinfo_mem(info); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2109 | spin_lock_irqsave(&device_domain_lock, flags); |
| 2110 | } |
| 2111 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 2112 | } |
| 2113 | |
| 2114 | /* |
| 2115 | * find_domain |
David Woodhouse | 1525a29 | 2014-03-06 16:19:30 +0000 | [diff] [blame^] | 2116 | * Note: we use struct device->archdata.iommu stores the info |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2117 | */ |
David Woodhouse | 1525a29 | 2014-03-06 16:19:30 +0000 | [diff] [blame^] | 2118 | static struct dmar_domain *find_domain(struct device *dev) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2119 | { |
| 2120 | struct device_domain_info *info; |
| 2121 | |
| 2122 | /* No lock here, assumes no domain exit in normal case */ |
David Woodhouse | 1525a29 | 2014-03-06 16:19:30 +0000 | [diff] [blame^] | 2123 | info = dev->archdata.iommu; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2124 | if (info) |
| 2125 | return info->domain; |
| 2126 | return NULL; |
| 2127 | } |
| 2128 | |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2129 | static inline struct dmar_domain * |
| 2130 | dmar_search_domain_by_dev_info(int segment, int bus, int devfn) |
| 2131 | { |
| 2132 | struct device_domain_info *info; |
| 2133 | |
| 2134 | list_for_each_entry(info, &device_domain_list, global) |
| 2135 | if (info->segment == segment && info->bus == bus && |
| 2136 | info->devfn == devfn) |
| 2137 | return info->domain; |
| 2138 | |
| 2139 | return NULL; |
| 2140 | } |
| 2141 | |
| 2142 | static int dmar_insert_dev_info(int segment, int bus, int devfn, |
| 2143 | struct pci_dev *dev, struct dmar_domain **domp) |
| 2144 | { |
| 2145 | struct dmar_domain *found, *domain = *domp; |
| 2146 | struct device_domain_info *info; |
| 2147 | unsigned long flags; |
| 2148 | |
| 2149 | info = alloc_devinfo_mem(); |
| 2150 | if (!info) |
| 2151 | return -ENOMEM; |
| 2152 | |
| 2153 | info->segment = segment; |
| 2154 | info->bus = bus; |
| 2155 | info->devfn = devfn; |
| 2156 | info->dev = dev; |
| 2157 | info->domain = domain; |
| 2158 | if (!dev) |
| 2159 | domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES; |
| 2160 | |
| 2161 | spin_lock_irqsave(&device_domain_lock, flags); |
| 2162 | if (dev) |
David Woodhouse | 1525a29 | 2014-03-06 16:19:30 +0000 | [diff] [blame^] | 2163 | found = find_domain(&dev->dev); |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2164 | else |
| 2165 | found = dmar_search_domain_by_dev_info(segment, bus, devfn); |
| 2166 | if (found) { |
| 2167 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 2168 | free_devinfo_mem(info); |
| 2169 | if (found != domain) { |
| 2170 | domain_exit(domain); |
| 2171 | *domp = found; |
| 2172 | } |
| 2173 | } else { |
| 2174 | list_add(&info->link, &domain->devices); |
| 2175 | list_add(&info->global, &device_domain_list); |
| 2176 | if (dev) |
| 2177 | dev->dev.archdata.iommu = info; |
| 2178 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 2179 | } |
| 2180 | |
| 2181 | return 0; |
| 2182 | } |
| 2183 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2184 | /* domain is initialized */ |
| 2185 | static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw) |
| 2186 | { |
Jiang Liu | e85bb5d | 2014-02-19 14:07:27 +0800 | [diff] [blame] | 2187 | struct dmar_domain *domain, *free = NULL; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2188 | struct intel_iommu *iommu; |
| 2189 | struct dmar_drhd_unit *drhd; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2190 | struct pci_dev *dev_tmp; |
| 2191 | unsigned long flags; |
| 2192 | int bus = 0, devfn = 0; |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 2193 | int segment; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2194 | |
David Woodhouse | 1525a29 | 2014-03-06 16:19:30 +0000 | [diff] [blame^] | 2195 | domain = find_domain(&pdev->dev); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2196 | if (domain) |
| 2197 | return domain; |
| 2198 | |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 2199 | segment = pci_domain_nr(pdev->bus); |
| 2200 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2201 | dev_tmp = pci_find_upstream_pcie_bridge(pdev); |
| 2202 | if (dev_tmp) { |
Kenji Kaneshige | 5f4d91a | 2009-11-11 14:36:17 +0900 | [diff] [blame] | 2203 | if (pci_is_pcie(dev_tmp)) { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2204 | bus = dev_tmp->subordinate->number; |
| 2205 | devfn = 0; |
| 2206 | } else { |
| 2207 | bus = dev_tmp->bus->number; |
| 2208 | devfn = dev_tmp->devfn; |
| 2209 | } |
| 2210 | spin_lock_irqsave(&device_domain_lock, flags); |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2211 | domain = dmar_search_domain_by_dev_info(segment, bus, devfn); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2212 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 2213 | /* pcie-pci bridge already has a domain, uses it */ |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2214 | if (domain) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2215 | goto found_domain; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2216 | } |
| 2217 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2218 | drhd = dmar_find_matched_drhd_unit(pdev); |
| 2219 | if (!drhd) { |
| 2220 | printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n", |
| 2221 | pci_name(pdev)); |
| 2222 | return NULL; |
| 2223 | } |
| 2224 | iommu = drhd->iommu; |
| 2225 | |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2226 | /* Allocate and intialize new domain for the device */ |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 2227 | domain = alloc_domain(false); |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2228 | if (!domain) |
| 2229 | goto error; |
| 2230 | if (iommu_attach_domain(domain, iommu)) { |
Alex Williamson | 2fe9723d | 2011-03-04 14:52:30 -0700 | [diff] [blame] | 2231 | free_domain_mem(domain); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2232 | goto error; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2233 | } |
Jiang Liu | e85bb5d | 2014-02-19 14:07:27 +0800 | [diff] [blame] | 2234 | free = domain; |
| 2235 | if (domain_init(domain, gaw)) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2236 | goto error; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2237 | |
| 2238 | /* register pcie-to-pci device */ |
| 2239 | if (dev_tmp) { |
Jiang Liu | e85bb5d | 2014-02-19 14:07:27 +0800 | [diff] [blame] | 2240 | if (dmar_insert_dev_info(segment, bus, devfn, NULL, &domain)) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2241 | goto error; |
Jiang Liu | e85bb5d | 2014-02-19 14:07:27 +0800 | [diff] [blame] | 2242 | else |
| 2243 | free = NULL; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2244 | } |
| 2245 | |
| 2246 | found_domain: |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2247 | if (dmar_insert_dev_info(segment, pdev->bus->number, pdev->devfn, |
| 2248 | pdev, &domain) == 0) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2249 | return domain; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2250 | error: |
Jiang Liu | e85bb5d | 2014-02-19 14:07:27 +0800 | [diff] [blame] | 2251 | if (free) |
| 2252 | domain_exit(free); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2253 | /* recheck it here, maybe others set it */ |
David Woodhouse | 1525a29 | 2014-03-06 16:19:30 +0000 | [diff] [blame^] | 2254 | return find_domain(&pdev->dev); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2255 | } |
| 2256 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2257 | static int iommu_identity_mapping; |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 2258 | #define IDENTMAP_ALL 1 |
| 2259 | #define IDENTMAP_GFX 2 |
| 2260 | #define IDENTMAP_AZALIA 4 |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2261 | |
David Woodhouse | b213203 | 2009-06-26 18:50:28 +0100 | [diff] [blame] | 2262 | static int iommu_domain_identity_map(struct dmar_domain *domain, |
| 2263 | unsigned long long start, |
| 2264 | unsigned long long end) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2265 | { |
David Woodhouse | c5395d5 | 2009-06-28 16:35:56 +0100 | [diff] [blame] | 2266 | unsigned long first_vpfn = start >> VTD_PAGE_SHIFT; |
| 2267 | unsigned long last_vpfn = end >> VTD_PAGE_SHIFT; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2268 | |
David Woodhouse | c5395d5 | 2009-06-28 16:35:56 +0100 | [diff] [blame] | 2269 | if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn), |
| 2270 | dma_to_mm_pfn(last_vpfn))) { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2271 | printk(KERN_ERR "IOMMU: reserve iova failed\n"); |
David Woodhouse | b213203 | 2009-06-26 18:50:28 +0100 | [diff] [blame] | 2272 | return -ENOMEM; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2273 | } |
| 2274 | |
David Woodhouse | c5395d5 | 2009-06-28 16:35:56 +0100 | [diff] [blame] | 2275 | pr_debug("Mapping reserved region %llx-%llx for domain %d\n", |
| 2276 | start, end, domain->id); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2277 | /* |
| 2278 | * RMRR range might have overlap with physical memory range, |
| 2279 | * clear it first |
| 2280 | */ |
David Woodhouse | c5395d5 | 2009-06-28 16:35:56 +0100 | [diff] [blame] | 2281 | dma_pte_clear_range(domain, first_vpfn, last_vpfn); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2282 | |
David Woodhouse | c5395d5 | 2009-06-28 16:35:56 +0100 | [diff] [blame] | 2283 | return domain_pfn_mapping(domain, first_vpfn, first_vpfn, |
| 2284 | last_vpfn - first_vpfn + 1, |
David Woodhouse | 61df744 | 2009-06-28 11:55:58 +0100 | [diff] [blame] | 2285 | DMA_PTE_READ|DMA_PTE_WRITE); |
David Woodhouse | b213203 | 2009-06-26 18:50:28 +0100 | [diff] [blame] | 2286 | } |
| 2287 | |
| 2288 | static int iommu_prepare_identity_map(struct pci_dev *pdev, |
| 2289 | unsigned long long start, |
| 2290 | unsigned long long end) |
| 2291 | { |
| 2292 | struct dmar_domain *domain; |
| 2293 | int ret; |
| 2294 | |
David Woodhouse | c7ab48d | 2009-06-26 19:10:36 +0100 | [diff] [blame] | 2295 | domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH); |
David Woodhouse | b213203 | 2009-06-26 18:50:28 +0100 | [diff] [blame] | 2296 | if (!domain) |
| 2297 | return -ENOMEM; |
| 2298 | |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 2299 | /* For _hardware_ passthrough, don't bother. But for software |
| 2300 | passthrough, we do it anyway -- it may indicate a memory |
| 2301 | range which is reserved in E820, so which didn't get set |
| 2302 | up to start with in si_domain */ |
| 2303 | if (domain == si_domain && hw_pass_through) { |
| 2304 | printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n", |
| 2305 | pci_name(pdev), start, end); |
| 2306 | return 0; |
| 2307 | } |
| 2308 | |
| 2309 | printk(KERN_INFO |
| 2310 | "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n", |
| 2311 | pci_name(pdev), start, end); |
David Woodhouse | 2ff729f | 2009-08-26 14:25:41 +0100 | [diff] [blame] | 2312 | |
David Woodhouse | 5595b52 | 2009-12-02 09:21:55 +0000 | [diff] [blame] | 2313 | if (end < start) { |
| 2314 | WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n" |
| 2315 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", |
| 2316 | dmi_get_system_info(DMI_BIOS_VENDOR), |
| 2317 | dmi_get_system_info(DMI_BIOS_VERSION), |
| 2318 | dmi_get_system_info(DMI_PRODUCT_VERSION)); |
| 2319 | ret = -EIO; |
| 2320 | goto error; |
| 2321 | } |
| 2322 | |
David Woodhouse | 2ff729f | 2009-08-26 14:25:41 +0100 | [diff] [blame] | 2323 | if (end >> agaw_to_width(domain->agaw)) { |
| 2324 | WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n" |
| 2325 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", |
| 2326 | agaw_to_width(domain->agaw), |
| 2327 | dmi_get_system_info(DMI_BIOS_VENDOR), |
| 2328 | dmi_get_system_info(DMI_BIOS_VERSION), |
| 2329 | dmi_get_system_info(DMI_PRODUCT_VERSION)); |
| 2330 | ret = -EIO; |
| 2331 | goto error; |
| 2332 | } |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 2333 | |
David Woodhouse | b213203 | 2009-06-26 18:50:28 +0100 | [diff] [blame] | 2334 | ret = iommu_domain_identity_map(domain, start, end); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2335 | if (ret) |
| 2336 | goto error; |
| 2337 | |
| 2338 | /* context entry init */ |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2339 | ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL); |
David Woodhouse | b213203 | 2009-06-26 18:50:28 +0100 | [diff] [blame] | 2340 | if (ret) |
| 2341 | goto error; |
| 2342 | |
| 2343 | return 0; |
| 2344 | |
| 2345 | error: |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2346 | domain_exit(domain); |
| 2347 | return ret; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2348 | } |
| 2349 | |
| 2350 | static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr, |
| 2351 | struct pci_dev *pdev) |
| 2352 | { |
Keshavamurthy, Anil S | 358dd8a | 2007-10-21 16:41:59 -0700 | [diff] [blame] | 2353 | if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2354 | return 0; |
| 2355 | return iommu_prepare_identity_map(pdev, rmrr->base_address, |
David Woodhouse | 70e535d | 2011-05-31 00:22:52 +0100 | [diff] [blame] | 2356 | rmrr->end_address); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2357 | } |
| 2358 | |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 2359 | #ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA |
Keshavamurthy, Anil S | 49a0429 | 2007-10-21 16:41:57 -0700 | [diff] [blame] | 2360 | static inline void iommu_prepare_isa(void) |
| 2361 | { |
| 2362 | struct pci_dev *pdev; |
| 2363 | int ret; |
| 2364 | |
| 2365 | pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); |
| 2366 | if (!pdev) |
| 2367 | return; |
| 2368 | |
David Woodhouse | c7ab48d | 2009-06-26 19:10:36 +0100 | [diff] [blame] | 2369 | printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n"); |
David Woodhouse | 70e535d | 2011-05-31 00:22:52 +0100 | [diff] [blame] | 2370 | ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024 - 1); |
Keshavamurthy, Anil S | 49a0429 | 2007-10-21 16:41:57 -0700 | [diff] [blame] | 2371 | |
| 2372 | if (ret) |
David Woodhouse | c7ab48d | 2009-06-26 19:10:36 +0100 | [diff] [blame] | 2373 | printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; " |
| 2374 | "floppy might not work\n"); |
Keshavamurthy, Anil S | 49a0429 | 2007-10-21 16:41:57 -0700 | [diff] [blame] | 2375 | |
| 2376 | } |
| 2377 | #else |
| 2378 | static inline void iommu_prepare_isa(void) |
| 2379 | { |
| 2380 | return; |
| 2381 | } |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 2382 | #endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */ |
Keshavamurthy, Anil S | 49a0429 | 2007-10-21 16:41:57 -0700 | [diff] [blame] | 2383 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2384 | static int md_domain_init(struct dmar_domain *domain, int guest_width); |
David Woodhouse | c7ab48d | 2009-06-26 19:10:36 +0100 | [diff] [blame] | 2385 | |
Matt Kraai | 071e137 | 2009-08-23 22:30:22 -0700 | [diff] [blame] | 2386 | static int __init si_domain_init(int hw) |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2387 | { |
| 2388 | struct dmar_drhd_unit *drhd; |
| 2389 | struct intel_iommu *iommu; |
David Woodhouse | c7ab48d | 2009-06-26 19:10:36 +0100 | [diff] [blame] | 2390 | int nid, ret = 0; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2391 | |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 2392 | si_domain = alloc_domain(false); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2393 | if (!si_domain) |
| 2394 | return -EFAULT; |
| 2395 | |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 2396 | si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY; |
| 2397 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2398 | for_each_active_iommu(iommu, drhd) { |
| 2399 | ret = iommu_attach_domain(si_domain, iommu); |
| 2400 | if (ret) { |
| 2401 | domain_exit(si_domain); |
| 2402 | return -EFAULT; |
| 2403 | } |
| 2404 | } |
| 2405 | |
| 2406 | if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { |
| 2407 | domain_exit(si_domain); |
| 2408 | return -EFAULT; |
| 2409 | } |
| 2410 | |
Jiang Liu | 9544c00 | 2014-01-06 14:18:13 +0800 | [diff] [blame] | 2411 | pr_debug("IOMMU: identity mapping domain is domain %d\n", |
| 2412 | si_domain->id); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2413 | |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 2414 | if (hw) |
| 2415 | return 0; |
| 2416 | |
David Woodhouse | c7ab48d | 2009-06-26 19:10:36 +0100 | [diff] [blame] | 2417 | for_each_online_node(nid) { |
Tejun Heo | d4bbf7e | 2011-11-28 09:46:22 -0800 | [diff] [blame] | 2418 | unsigned long start_pfn, end_pfn; |
| 2419 | int i; |
| 2420 | |
| 2421 | for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) { |
| 2422 | ret = iommu_domain_identity_map(si_domain, |
| 2423 | PFN_PHYS(start_pfn), PFN_PHYS(end_pfn)); |
| 2424 | if (ret) |
| 2425 | return ret; |
| 2426 | } |
David Woodhouse | c7ab48d | 2009-06-26 19:10:36 +0100 | [diff] [blame] | 2427 | } |
| 2428 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2429 | return 0; |
| 2430 | } |
| 2431 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2432 | static int identity_mapping(struct pci_dev *pdev) |
| 2433 | { |
| 2434 | struct device_domain_info *info; |
| 2435 | |
| 2436 | if (likely(!iommu_identity_mapping)) |
| 2437 | return 0; |
| 2438 | |
Mike Travis | cb452a4 | 2011-05-28 13:15:03 -0500 | [diff] [blame] | 2439 | info = pdev->dev.archdata.iommu; |
| 2440 | if (info && info != DUMMY_DEVICE_DOMAIN_INFO) |
| 2441 | return (info->domain == si_domain); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2442 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2443 | return 0; |
| 2444 | } |
| 2445 | |
| 2446 | static int domain_add_dev_info(struct dmar_domain *domain, |
David Woodhouse | 5fe60f4 | 2009-08-09 10:53:41 +0100 | [diff] [blame] | 2447 | struct pci_dev *pdev, |
| 2448 | int translation) |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2449 | { |
| 2450 | struct device_domain_info *info; |
| 2451 | unsigned long flags; |
David Woodhouse | 5fe60f4 | 2009-08-09 10:53:41 +0100 | [diff] [blame] | 2452 | int ret; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2453 | |
| 2454 | info = alloc_devinfo_mem(); |
| 2455 | if (!info) |
| 2456 | return -ENOMEM; |
| 2457 | |
| 2458 | info->segment = pci_domain_nr(pdev->bus); |
| 2459 | info->bus = pdev->bus->number; |
| 2460 | info->devfn = pdev->devfn; |
| 2461 | info->dev = pdev; |
| 2462 | info->domain = domain; |
| 2463 | |
| 2464 | spin_lock_irqsave(&device_domain_lock, flags); |
| 2465 | list_add(&info->link, &domain->devices); |
| 2466 | list_add(&info->global, &device_domain_list); |
| 2467 | pdev->dev.archdata.iommu = info; |
| 2468 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 2469 | |
David Woodhouse | e2ad23d | 2012-05-25 17:42:54 +0100 | [diff] [blame] | 2470 | ret = domain_context_mapping(domain, pdev, translation); |
| 2471 | if (ret) { |
| 2472 | spin_lock_irqsave(&device_domain_lock, flags); |
David Woodhouse | 109b9b0 | 2012-05-25 17:43:02 +0100 | [diff] [blame] | 2473 | unlink_domain_info(info); |
David Woodhouse | e2ad23d | 2012-05-25 17:42:54 +0100 | [diff] [blame] | 2474 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 2475 | free_devinfo_mem(info); |
| 2476 | return ret; |
| 2477 | } |
| 2478 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2479 | return 0; |
| 2480 | } |
| 2481 | |
Tom Mingarelli | ea2447f | 2012-11-20 19:43:17 +0000 | [diff] [blame] | 2482 | static bool device_has_rmrr(struct pci_dev *dev) |
| 2483 | { |
| 2484 | struct dmar_rmrr_unit *rmrr; |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 2485 | struct device *tmp; |
Tom Mingarelli | ea2447f | 2012-11-20 19:43:17 +0000 | [diff] [blame] | 2486 | int i; |
| 2487 | |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 2488 | rcu_read_lock(); |
Tom Mingarelli | ea2447f | 2012-11-20 19:43:17 +0000 | [diff] [blame] | 2489 | for_each_rmrr_units(rmrr) { |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 2490 | /* |
| 2491 | * Return TRUE if this RMRR contains the device that |
| 2492 | * is passed in. |
| 2493 | */ |
| 2494 | for_each_active_dev_scope(rmrr->devices, |
| 2495 | rmrr->devices_cnt, i, tmp) |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 2496 | if (tmp == &dev->dev) { |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 2497 | rcu_read_unlock(); |
Tom Mingarelli | ea2447f | 2012-11-20 19:43:17 +0000 | [diff] [blame] | 2498 | return true; |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 2499 | } |
Tom Mingarelli | ea2447f | 2012-11-20 19:43:17 +0000 | [diff] [blame] | 2500 | } |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 2501 | rcu_read_unlock(); |
Tom Mingarelli | ea2447f | 2012-11-20 19:43:17 +0000 | [diff] [blame] | 2502 | return false; |
| 2503 | } |
| 2504 | |
David Woodhouse | 6941af2 | 2009-07-04 18:24:27 +0100 | [diff] [blame] | 2505 | static int iommu_should_identity_map(struct pci_dev *pdev, int startup) |
| 2506 | { |
Tom Mingarelli | ea2447f | 2012-11-20 19:43:17 +0000 | [diff] [blame] | 2507 | |
| 2508 | /* |
| 2509 | * We want to prevent any device associated with an RMRR from |
| 2510 | * getting placed into the SI Domain. This is done because |
| 2511 | * problems exist when devices are moved in and out of domains |
| 2512 | * and their respective RMRR info is lost. We exempt USB devices |
| 2513 | * from this process due to their usage of RMRRs that are known |
| 2514 | * to not be needed after BIOS hand-off to OS. |
| 2515 | */ |
| 2516 | if (device_has_rmrr(pdev) && |
| 2517 | (pdev->class >> 8) != PCI_CLASS_SERIAL_USB) |
| 2518 | return 0; |
| 2519 | |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 2520 | if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev)) |
| 2521 | return 1; |
| 2522 | |
| 2523 | if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev)) |
| 2524 | return 1; |
| 2525 | |
| 2526 | if (!(iommu_identity_mapping & IDENTMAP_ALL)) |
| 2527 | return 0; |
David Woodhouse | 6941af2 | 2009-07-04 18:24:27 +0100 | [diff] [blame] | 2528 | |
David Woodhouse | 3dfc813 | 2009-07-04 19:11:08 +0100 | [diff] [blame] | 2529 | /* |
| 2530 | * We want to start off with all devices in the 1:1 domain, and |
| 2531 | * take them out later if we find they can't access all of memory. |
| 2532 | * |
| 2533 | * However, we can't do this for PCI devices behind bridges, |
| 2534 | * because all PCI devices behind the same bridge will end up |
| 2535 | * with the same source-id on their transactions. |
| 2536 | * |
| 2537 | * Practically speaking, we can't change things around for these |
| 2538 | * devices at run-time, because we can't be sure there'll be no |
| 2539 | * DMA transactions in flight for any of their siblings. |
| 2540 | * |
| 2541 | * So PCI devices (unless they're on the root bus) as well as |
| 2542 | * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of |
| 2543 | * the 1:1 domain, just in _case_ one of their siblings turns out |
| 2544 | * not to be able to map all of memory. |
| 2545 | */ |
Kenji Kaneshige | 5f4d91a | 2009-11-11 14:36:17 +0900 | [diff] [blame] | 2546 | if (!pci_is_pcie(pdev)) { |
David Woodhouse | 3dfc813 | 2009-07-04 19:11:08 +0100 | [diff] [blame] | 2547 | if (!pci_is_root_bus(pdev->bus)) |
| 2548 | return 0; |
| 2549 | if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI) |
| 2550 | return 0; |
Yijing Wang | 62f87c0 | 2012-07-24 17:20:03 +0800 | [diff] [blame] | 2551 | } else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_PCI_BRIDGE) |
David Woodhouse | 3dfc813 | 2009-07-04 19:11:08 +0100 | [diff] [blame] | 2552 | return 0; |
| 2553 | |
| 2554 | /* |
| 2555 | * At boot time, we don't yet know if devices will be 64-bit capable. |
| 2556 | * Assume that they will -- if they turn out not to be, then we can |
| 2557 | * take them out of the 1:1 domain later. |
| 2558 | */ |
Chris Wright | 8fcc537 | 2011-05-28 13:15:02 -0500 | [diff] [blame] | 2559 | if (!startup) { |
| 2560 | /* |
| 2561 | * If the device's dma_mask is less than the system's memory |
| 2562 | * size then this is not a candidate for identity mapping. |
| 2563 | */ |
| 2564 | u64 dma_mask = pdev->dma_mask; |
| 2565 | |
| 2566 | if (pdev->dev.coherent_dma_mask && |
| 2567 | pdev->dev.coherent_dma_mask < dma_mask) |
| 2568 | dma_mask = pdev->dev.coherent_dma_mask; |
| 2569 | |
| 2570 | return dma_mask >= dma_get_required_mask(&pdev->dev); |
| 2571 | } |
David Woodhouse | 6941af2 | 2009-07-04 18:24:27 +0100 | [diff] [blame] | 2572 | |
| 2573 | return 1; |
| 2574 | } |
| 2575 | |
Matt Kraai | 071e137 | 2009-08-23 22:30:22 -0700 | [diff] [blame] | 2576 | static int __init iommu_prepare_static_identity_mapping(int hw) |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2577 | { |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2578 | struct pci_dev *pdev = NULL; |
| 2579 | int ret; |
| 2580 | |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 2581 | ret = si_domain_init(hw); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2582 | if (ret) |
| 2583 | return -EFAULT; |
| 2584 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2585 | for_each_pci_dev(pdev) { |
David Woodhouse | 6941af2 | 2009-07-04 18:24:27 +0100 | [diff] [blame] | 2586 | if (iommu_should_identity_map(pdev, 1)) { |
David Woodhouse | 5fe60f4 | 2009-08-09 10:53:41 +0100 | [diff] [blame] | 2587 | ret = domain_add_dev_info(si_domain, pdev, |
Mike Travis | eae460b | 2012-03-05 15:05:16 -0800 | [diff] [blame] | 2588 | hw ? CONTEXT_TT_PASS_THROUGH : |
| 2589 | CONTEXT_TT_MULTI_LEVEL); |
| 2590 | if (ret) { |
| 2591 | /* device not associated with an iommu */ |
| 2592 | if (ret == -ENODEV) |
| 2593 | continue; |
David Woodhouse | 62edf5d | 2009-07-04 10:59:46 +0100 | [diff] [blame] | 2594 | return ret; |
Mike Travis | eae460b | 2012-03-05 15:05:16 -0800 | [diff] [blame] | 2595 | } |
| 2596 | pr_info("IOMMU: %s identity mapping for device %s\n", |
| 2597 | hw ? "hardware" : "software", pci_name(pdev)); |
David Woodhouse | 62edf5d | 2009-07-04 10:59:46 +0100 | [diff] [blame] | 2598 | } |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2599 | } |
| 2600 | |
| 2601 | return 0; |
| 2602 | } |
| 2603 | |
Joseph Cihula | b779260 | 2011-05-03 00:08:37 -0700 | [diff] [blame] | 2604 | static int __init init_dmars(void) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2605 | { |
| 2606 | struct dmar_drhd_unit *drhd; |
| 2607 | struct dmar_rmrr_unit *rmrr; |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 2608 | struct device *dev; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2609 | struct intel_iommu *iommu; |
Suresh Siddha | 9d783ba | 2009-03-16 17:04:55 -0700 | [diff] [blame] | 2610 | int i, ret; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2611 | |
| 2612 | /* |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2613 | * for each drhd |
| 2614 | * allocate root |
| 2615 | * initialize and program root entry to not present |
| 2616 | * endfor |
| 2617 | */ |
| 2618 | for_each_drhd_unit(drhd) { |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 2619 | /* |
| 2620 | * lock not needed as this is only incremented in the single |
| 2621 | * threaded kernel __init code path all other access are read |
| 2622 | * only |
| 2623 | */ |
Mike Travis | 1b198bb | 2012-03-05 15:05:16 -0800 | [diff] [blame] | 2624 | if (g_num_of_iommus < IOMMU_UNITS_SUPPORTED) { |
| 2625 | g_num_of_iommus++; |
| 2626 | continue; |
| 2627 | } |
| 2628 | printk_once(KERN_ERR "intel-iommu: exceeded %d IOMMUs\n", |
| 2629 | IOMMU_UNITS_SUPPORTED); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 2630 | } |
| 2631 | |
Weidong Han | d9630fe | 2008-12-08 11:06:32 +0800 | [diff] [blame] | 2632 | g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *), |
| 2633 | GFP_KERNEL); |
| 2634 | if (!g_iommus) { |
| 2635 | printk(KERN_ERR "Allocating global iommu array failed\n"); |
| 2636 | ret = -ENOMEM; |
| 2637 | goto error; |
| 2638 | } |
| 2639 | |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 2640 | deferred_flush = kzalloc(g_num_of_iommus * |
| 2641 | sizeof(struct deferred_flush_tables), GFP_KERNEL); |
| 2642 | if (!deferred_flush) { |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 2643 | ret = -ENOMEM; |
Jiang Liu | 989d51f | 2014-02-19 14:07:21 +0800 | [diff] [blame] | 2644 | goto free_g_iommus; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 2645 | } |
| 2646 | |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 2647 | for_each_active_iommu(iommu, drhd) { |
Weidong Han | d9630fe | 2008-12-08 11:06:32 +0800 | [diff] [blame] | 2648 | g_iommus[iommu->seq_id] = iommu; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2649 | |
Suresh Siddha | e61d98d | 2008-07-10 11:16:35 -0700 | [diff] [blame] | 2650 | ret = iommu_init_domains(iommu); |
| 2651 | if (ret) |
Jiang Liu | 989d51f | 2014-02-19 14:07:21 +0800 | [diff] [blame] | 2652 | goto free_iommu; |
Suresh Siddha | e61d98d | 2008-07-10 11:16:35 -0700 | [diff] [blame] | 2653 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2654 | /* |
| 2655 | * TBD: |
| 2656 | * we could share the same root & context tables |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 2657 | * among all IOMMU's. Need to Split it later. |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2658 | */ |
| 2659 | ret = iommu_alloc_root_entry(iommu); |
| 2660 | if (ret) { |
| 2661 | printk(KERN_ERR "IOMMU: allocate root entry failed\n"); |
Jiang Liu | 989d51f | 2014-02-19 14:07:21 +0800 | [diff] [blame] | 2662 | goto free_iommu; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2663 | } |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2664 | if (!ecap_pass_through(iommu->ecap)) |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 2665 | hw_pass_through = 0; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2666 | } |
| 2667 | |
Suresh Siddha | 1531a6a | 2009-03-16 17:04:57 -0700 | [diff] [blame] | 2668 | /* |
| 2669 | * Start from the sane iommu hardware state. |
| 2670 | */ |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 2671 | for_each_active_iommu(iommu, drhd) { |
Suresh Siddha | 1531a6a | 2009-03-16 17:04:57 -0700 | [diff] [blame] | 2672 | /* |
| 2673 | * If the queued invalidation is already initialized by us |
| 2674 | * (for example, while enabling interrupt-remapping) then |
| 2675 | * we got the things already rolling from a sane state. |
| 2676 | */ |
| 2677 | if (iommu->qi) |
| 2678 | continue; |
| 2679 | |
| 2680 | /* |
| 2681 | * Clear any previous faults. |
| 2682 | */ |
| 2683 | dmar_fault(-1, iommu); |
| 2684 | /* |
| 2685 | * Disable queued invalidation if supported and already enabled |
| 2686 | * before OS handover. |
| 2687 | */ |
| 2688 | dmar_disable_qi(iommu); |
| 2689 | } |
| 2690 | |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 2691 | for_each_active_iommu(iommu, drhd) { |
Youquan Song | a77b67d | 2008-10-16 16:31:56 -0700 | [diff] [blame] | 2692 | if (dmar_enable_qi(iommu)) { |
| 2693 | /* |
| 2694 | * Queued Invalidate not enabled, use Register Based |
| 2695 | * Invalidate |
| 2696 | */ |
| 2697 | iommu->flush.flush_context = __iommu_flush_context; |
| 2698 | iommu->flush.flush_iotlb = __iommu_flush_iotlb; |
Yinghai Lu | 680a752 | 2010-04-08 19:58:23 +0100 | [diff] [blame] | 2699 | printk(KERN_INFO "IOMMU %d 0x%Lx: using Register based " |
FUJITA Tomonori | b4e0f9e | 2008-11-19 13:53:42 +0900 | [diff] [blame] | 2700 | "invalidation\n", |
Yinghai Lu | 680a752 | 2010-04-08 19:58:23 +0100 | [diff] [blame] | 2701 | iommu->seq_id, |
FUJITA Tomonori | b4e0f9e | 2008-11-19 13:53:42 +0900 | [diff] [blame] | 2702 | (unsigned long long)drhd->reg_base_addr); |
Youquan Song | a77b67d | 2008-10-16 16:31:56 -0700 | [diff] [blame] | 2703 | } else { |
| 2704 | iommu->flush.flush_context = qi_flush_context; |
| 2705 | iommu->flush.flush_iotlb = qi_flush_iotlb; |
Yinghai Lu | 680a752 | 2010-04-08 19:58:23 +0100 | [diff] [blame] | 2706 | printk(KERN_INFO "IOMMU %d 0x%Lx: using Queued " |
FUJITA Tomonori | b4e0f9e | 2008-11-19 13:53:42 +0900 | [diff] [blame] | 2707 | "invalidation\n", |
Yinghai Lu | 680a752 | 2010-04-08 19:58:23 +0100 | [diff] [blame] | 2708 | iommu->seq_id, |
FUJITA Tomonori | b4e0f9e | 2008-11-19 13:53:42 +0900 | [diff] [blame] | 2709 | (unsigned long long)drhd->reg_base_addr); |
Youquan Song | a77b67d | 2008-10-16 16:31:56 -0700 | [diff] [blame] | 2710 | } |
| 2711 | } |
| 2712 | |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 2713 | if (iommu_pass_through) |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 2714 | iommu_identity_mapping |= IDENTMAP_ALL; |
| 2715 | |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 2716 | #ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 2717 | iommu_identity_mapping |= IDENTMAP_GFX; |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 2718 | #endif |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 2719 | |
| 2720 | check_tylersburg_isoch(); |
| 2721 | |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2722 | /* |
| 2723 | * If pass through is not set or not enabled, setup context entries for |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2724 | * identity mappings for rmrr, gfx, and isa and may fall back to static |
| 2725 | * identity mapping if iommu_identity_mapping is set. |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2726 | */ |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 2727 | if (iommu_identity_mapping) { |
| 2728 | ret = iommu_prepare_static_identity_mapping(hw_pass_through); |
| 2729 | if (ret) { |
| 2730 | printk(KERN_CRIT "Failed to setup IOMMU pass-through\n"); |
Jiang Liu | 989d51f | 2014-02-19 14:07:21 +0800 | [diff] [blame] | 2731 | goto free_iommu; |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2732 | } |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2733 | } |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 2734 | /* |
| 2735 | * For each rmrr |
| 2736 | * for each dev attached to rmrr |
| 2737 | * do |
| 2738 | * locate drhd for dev, alloc domain for dev |
| 2739 | * allocate free domain |
| 2740 | * allocate page table entries for rmrr |
| 2741 | * if context not allocated for bus |
| 2742 | * allocate and init context |
| 2743 | * set present in root table for this bus |
| 2744 | * init context with domain, translation etc |
| 2745 | * endfor |
| 2746 | * endfor |
| 2747 | */ |
| 2748 | printk(KERN_INFO "IOMMU: Setting RMRR:\n"); |
| 2749 | for_each_rmrr_units(rmrr) { |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 2750 | /* some BIOS lists non-exist devices in DMAR table. */ |
| 2751 | for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt, |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 2752 | i, dev) { |
| 2753 | if (!dev_is_pci(dev)) |
| 2754 | continue; |
| 2755 | ret = iommu_prepare_rmrr_dev(rmrr, to_pci_dev(dev)); |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 2756 | if (ret) |
| 2757 | printk(KERN_ERR |
| 2758 | "IOMMU: mapping reserved region failed\n"); |
| 2759 | } |
| 2760 | } |
| 2761 | |
| 2762 | iommu_prepare_isa(); |
Keshavamurthy, Anil S | 49a0429 | 2007-10-21 16:41:57 -0700 | [diff] [blame] | 2763 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2764 | /* |
| 2765 | * for each drhd |
| 2766 | * enable fault log |
| 2767 | * global invalidate context cache |
| 2768 | * global invalidate iotlb |
| 2769 | * enable translation |
| 2770 | */ |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 2771 | for_each_iommu(iommu, drhd) { |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 2772 | if (drhd->ignored) { |
| 2773 | /* |
| 2774 | * we always have to disable PMRs or DMA may fail on |
| 2775 | * this device |
| 2776 | */ |
| 2777 | if (force_on) |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 2778 | iommu_disable_protect_mem_regions(iommu); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2779 | continue; |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 2780 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2781 | |
| 2782 | iommu_flush_write_buffer(iommu); |
| 2783 | |
Keshavamurthy, Anil S | 3460a6d | 2007-10-21 16:41:54 -0700 | [diff] [blame] | 2784 | ret = dmar_set_interrupt(iommu); |
| 2785 | if (ret) |
Jiang Liu | 989d51f | 2014-02-19 14:07:21 +0800 | [diff] [blame] | 2786 | goto free_iommu; |
Keshavamurthy, Anil S | 3460a6d | 2007-10-21 16:41:54 -0700 | [diff] [blame] | 2787 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2788 | iommu_set_root_entry(iommu); |
| 2789 | |
David Woodhouse | 4c25a2c | 2009-05-10 17:16:06 +0100 | [diff] [blame] | 2790 | iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL); |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 2791 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
mark gross | f8bab73 | 2008-02-08 04:18:38 -0800 | [diff] [blame] | 2792 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2793 | ret = iommu_enable_translation(iommu); |
| 2794 | if (ret) |
Jiang Liu | 989d51f | 2014-02-19 14:07:21 +0800 | [diff] [blame] | 2795 | goto free_iommu; |
David Woodhouse | b94996c | 2009-09-19 15:28:12 -0700 | [diff] [blame] | 2796 | |
| 2797 | iommu_disable_protect_mem_regions(iommu); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2798 | } |
| 2799 | |
| 2800 | return 0; |
Jiang Liu | 989d51f | 2014-02-19 14:07:21 +0800 | [diff] [blame] | 2801 | |
| 2802 | free_iommu: |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 2803 | for_each_active_iommu(iommu, drhd) |
Jiang Liu | a868e6b | 2014-01-06 14:18:20 +0800 | [diff] [blame] | 2804 | free_dmar_iommu(iommu); |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 2805 | kfree(deferred_flush); |
Jiang Liu | 989d51f | 2014-02-19 14:07:21 +0800 | [diff] [blame] | 2806 | free_g_iommus: |
Weidong Han | d9630fe | 2008-12-08 11:06:32 +0800 | [diff] [blame] | 2807 | kfree(g_iommus); |
Jiang Liu | 989d51f | 2014-02-19 14:07:21 +0800 | [diff] [blame] | 2808 | error: |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2809 | return ret; |
| 2810 | } |
| 2811 | |
David Woodhouse | 5a5e02a | 2009-07-04 09:35:44 +0100 | [diff] [blame] | 2812 | /* This takes a number of _MM_ pages, not VTD pages */ |
David Woodhouse | 875764d | 2009-06-28 21:20:51 +0100 | [diff] [blame] | 2813 | static struct iova *intel_alloc_iova(struct device *dev, |
| 2814 | struct dmar_domain *domain, |
| 2815 | unsigned long nrpages, uint64_t dma_mask) |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2816 | { |
| 2817 | struct pci_dev *pdev = to_pci_dev(dev); |
| 2818 | struct iova *iova = NULL; |
| 2819 | |
David Woodhouse | 875764d | 2009-06-28 21:20:51 +0100 | [diff] [blame] | 2820 | /* Restrict dma_mask to the width that the iommu can handle */ |
| 2821 | dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask); |
| 2822 | |
| 2823 | if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) { |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2824 | /* |
| 2825 | * First try to allocate an io virtual address in |
Yang Hongyang | 284901a | 2009-04-06 19:01:15 -0700 | [diff] [blame] | 2826 | * DMA_BIT_MASK(32) and if that fails then try allocating |
Joe Perches | 3609801 | 2007-12-17 11:40:11 -0800 | [diff] [blame] | 2827 | * from higher range |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2828 | */ |
David Woodhouse | 875764d | 2009-06-28 21:20:51 +0100 | [diff] [blame] | 2829 | iova = alloc_iova(&domain->iovad, nrpages, |
| 2830 | IOVA_PFN(DMA_BIT_MASK(32)), 1); |
| 2831 | if (iova) |
| 2832 | return iova; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2833 | } |
David Woodhouse | 875764d | 2009-06-28 21:20:51 +0100 | [diff] [blame] | 2834 | iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1); |
| 2835 | if (unlikely(!iova)) { |
| 2836 | printk(KERN_ERR "Allocating %ld-page iova for %s failed", |
| 2837 | nrpages, pci_name(pdev)); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2838 | return NULL; |
| 2839 | } |
| 2840 | |
| 2841 | return iova; |
| 2842 | } |
| 2843 | |
David Woodhouse | 147202a | 2009-07-07 19:43:20 +0100 | [diff] [blame] | 2844 | static struct dmar_domain *__get_valid_domain_for_dev(struct pci_dev *pdev) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2845 | { |
| 2846 | struct dmar_domain *domain; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2847 | int ret; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2848 | |
| 2849 | domain = get_domain_for_dev(pdev, |
| 2850 | DEFAULT_DOMAIN_ADDRESS_WIDTH); |
| 2851 | if (!domain) { |
| 2852 | printk(KERN_ERR |
| 2853 | "Allocating domain for %s failed", pci_name(pdev)); |
Al Viro | 4fe05bb | 2007-10-29 04:51:16 +0000 | [diff] [blame] | 2854 | return NULL; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2855 | } |
| 2856 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2857 | /* make sure context mapping is ok */ |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 2858 | if (unlikely(!domain_context_mapped(pdev))) { |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2859 | ret = domain_context_mapping(domain, pdev, |
| 2860 | CONTEXT_TT_MULTI_LEVEL); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2861 | if (ret) { |
| 2862 | printk(KERN_ERR |
| 2863 | "Domain context map for %s failed", |
| 2864 | pci_name(pdev)); |
Al Viro | 4fe05bb | 2007-10-29 04:51:16 +0000 | [diff] [blame] | 2865 | return NULL; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2866 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2867 | } |
| 2868 | |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2869 | return domain; |
| 2870 | } |
| 2871 | |
David Woodhouse | 147202a | 2009-07-07 19:43:20 +0100 | [diff] [blame] | 2872 | static inline struct dmar_domain *get_valid_domain_for_dev(struct pci_dev *dev) |
| 2873 | { |
| 2874 | struct device_domain_info *info; |
| 2875 | |
| 2876 | /* No lock here, assumes no domain exit in normal case */ |
| 2877 | info = dev->dev.archdata.iommu; |
| 2878 | if (likely(info)) |
| 2879 | return info->domain; |
| 2880 | |
| 2881 | return __get_valid_domain_for_dev(dev); |
| 2882 | } |
| 2883 | |
David Woodhouse | 3d89194 | 2014-03-06 15:59:26 +0000 | [diff] [blame] | 2884 | static int iommu_dummy(struct device *dev) |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2885 | { |
David Woodhouse | 3d89194 | 2014-03-06 15:59:26 +0000 | [diff] [blame] | 2886 | return dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2887 | } |
| 2888 | |
| 2889 | /* Check if the pdev needs to go through non-identity map and unmap process.*/ |
David Woodhouse | 7367683 | 2009-07-04 14:08:36 +0100 | [diff] [blame] | 2890 | static int iommu_no_mapping(struct device *dev) |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2891 | { |
David Woodhouse | 7367683 | 2009-07-04 14:08:36 +0100 | [diff] [blame] | 2892 | struct pci_dev *pdev; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2893 | int found; |
| 2894 | |
Yijing Wang | dbad086 | 2013-12-05 19:43:42 +0800 | [diff] [blame] | 2895 | if (unlikely(!dev_is_pci(dev))) |
David Woodhouse | 7367683 | 2009-07-04 14:08:36 +0100 | [diff] [blame] | 2896 | return 1; |
| 2897 | |
David Woodhouse | 3d89194 | 2014-03-06 15:59:26 +0000 | [diff] [blame] | 2898 | if (iommu_dummy(dev)) |
David Woodhouse | 1e4c64c | 2009-07-04 10:40:38 +0100 | [diff] [blame] | 2899 | return 1; |
| 2900 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2901 | if (!iommu_identity_mapping) |
David Woodhouse | 1e4c64c | 2009-07-04 10:40:38 +0100 | [diff] [blame] | 2902 | return 0; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2903 | |
David Woodhouse | 3d89194 | 2014-03-06 15:59:26 +0000 | [diff] [blame] | 2904 | pdev = to_pci_dev(dev); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2905 | found = identity_mapping(pdev); |
| 2906 | if (found) { |
David Woodhouse | 6941af2 | 2009-07-04 18:24:27 +0100 | [diff] [blame] | 2907 | if (iommu_should_identity_map(pdev, 0)) |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2908 | return 1; |
| 2909 | else { |
| 2910 | /* |
| 2911 | * 32 bit DMA is removed from si_domain and fall back |
| 2912 | * to non-identity mapping. |
| 2913 | */ |
| 2914 | domain_remove_one_dev_info(si_domain, pdev); |
| 2915 | printk(KERN_INFO "32bit %s uses non-identity mapping\n", |
| 2916 | pci_name(pdev)); |
| 2917 | return 0; |
| 2918 | } |
| 2919 | } else { |
| 2920 | /* |
| 2921 | * In case of a detached 64 bit DMA device from vm, the device |
| 2922 | * is put into si_domain for identity mapping. |
| 2923 | */ |
David Woodhouse | 6941af2 | 2009-07-04 18:24:27 +0100 | [diff] [blame] | 2924 | if (iommu_should_identity_map(pdev, 0)) { |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2925 | int ret; |
David Woodhouse | 5fe60f4 | 2009-08-09 10:53:41 +0100 | [diff] [blame] | 2926 | ret = domain_add_dev_info(si_domain, pdev, |
| 2927 | hw_pass_through ? |
| 2928 | CONTEXT_TT_PASS_THROUGH : |
| 2929 | CONTEXT_TT_MULTI_LEVEL); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2930 | if (!ret) { |
| 2931 | printk(KERN_INFO "64bit %s uses identity mapping\n", |
| 2932 | pci_name(pdev)); |
| 2933 | return 1; |
| 2934 | } |
| 2935 | } |
| 2936 | } |
| 2937 | |
David Woodhouse | 1e4c64c | 2009-07-04 10:40:38 +0100 | [diff] [blame] | 2938 | return 0; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2939 | } |
| 2940 | |
FUJITA Tomonori | bb9e6d6 | 2008-10-15 16:08:28 +0900 | [diff] [blame] | 2941 | static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr, |
| 2942 | size_t size, int dir, u64 dma_mask) |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2943 | { |
| 2944 | struct pci_dev *pdev = to_pci_dev(hwdev); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2945 | struct dmar_domain *domain; |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 2946 | phys_addr_t start_paddr; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2947 | struct iova *iova; |
| 2948 | int prot = 0; |
Ingo Molnar | 6865f0d | 2008-04-22 11:09:04 +0200 | [diff] [blame] | 2949 | int ret; |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 2950 | struct intel_iommu *iommu; |
Fenghua Yu | 33041ec | 2009-08-04 15:10:59 -0700 | [diff] [blame] | 2951 | unsigned long paddr_pfn = paddr >> PAGE_SHIFT; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2952 | |
| 2953 | BUG_ON(dir == DMA_NONE); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2954 | |
David Woodhouse | 7367683 | 2009-07-04 14:08:36 +0100 | [diff] [blame] | 2955 | if (iommu_no_mapping(hwdev)) |
Ingo Molnar | 6865f0d | 2008-04-22 11:09:04 +0200 | [diff] [blame] | 2956 | return paddr; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2957 | |
| 2958 | domain = get_valid_domain_for_dev(pdev); |
| 2959 | if (!domain) |
| 2960 | return 0; |
| 2961 | |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 2962 | iommu = domain_get_iommu(domain); |
David Woodhouse | 88cb6a7 | 2009-06-28 15:03:06 +0100 | [diff] [blame] | 2963 | size = aligned_nrpages(paddr, size); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2964 | |
Mike Travis | c681d0b | 2011-05-28 13:15:05 -0500 | [diff] [blame] | 2965 | iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size), dma_mask); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2966 | if (!iova) |
| 2967 | goto error; |
| 2968 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2969 | /* |
| 2970 | * Check if DMAR supports zero-length reads on write only |
| 2971 | * mappings.. |
| 2972 | */ |
| 2973 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \ |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 2974 | !cap_zlr(iommu->cap)) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2975 | prot |= DMA_PTE_READ; |
| 2976 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) |
| 2977 | prot |= DMA_PTE_WRITE; |
| 2978 | /* |
Ingo Molnar | 6865f0d | 2008-04-22 11:09:04 +0200 | [diff] [blame] | 2979 | * paddr - (paddr + size) might be partial page, we should map the whole |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2980 | * page. Note: if two part of one page are separately mapped, we |
Ingo Molnar | 6865f0d | 2008-04-22 11:09:04 +0200 | [diff] [blame] | 2981 | * might have two guest_addr mapping to the same host paddr, but this |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2982 | * is not a big problem |
| 2983 | */ |
David Woodhouse | 0ab36de | 2009-06-28 14:01:43 +0100 | [diff] [blame] | 2984 | ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo), |
Fenghua Yu | 33041ec | 2009-08-04 15:10:59 -0700 | [diff] [blame] | 2985 | mm_to_dma_pfn(paddr_pfn), size, prot); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2986 | if (ret) |
| 2987 | goto error; |
| 2988 | |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 2989 | /* it's a non-present to present mapping. Only flush if caching mode */ |
| 2990 | if (cap_caching_mode(iommu->cap)) |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 2991 | iommu_flush_iotlb_psi(iommu, domain->id, mm_to_dma_pfn(iova->pfn_lo), size, 0, 1); |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 2992 | else |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 2993 | iommu_flush_write_buffer(iommu); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2994 | |
David Woodhouse | 03d6a24 | 2009-06-28 15:33:46 +0100 | [diff] [blame] | 2995 | start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT; |
| 2996 | start_paddr += paddr & ~PAGE_MASK; |
| 2997 | return start_paddr; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2998 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2999 | error: |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3000 | if (iova) |
| 3001 | __free_iova(&domain->iovad, iova); |
David Woodhouse | 4cf2e75 | 2009-02-11 17:23:43 +0000 | [diff] [blame] | 3002 | printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n", |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 3003 | pci_name(pdev), size, (unsigned long long)paddr, dir); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3004 | return 0; |
| 3005 | } |
| 3006 | |
FUJITA Tomonori | ffbbef5 | 2009-01-05 23:47:26 +0900 | [diff] [blame] | 3007 | static dma_addr_t intel_map_page(struct device *dev, struct page *page, |
| 3008 | unsigned long offset, size_t size, |
| 3009 | enum dma_data_direction dir, |
| 3010 | struct dma_attrs *attrs) |
FUJITA Tomonori | bb9e6d6 | 2008-10-15 16:08:28 +0900 | [diff] [blame] | 3011 | { |
FUJITA Tomonori | ffbbef5 | 2009-01-05 23:47:26 +0900 | [diff] [blame] | 3012 | return __intel_map_single(dev, page_to_phys(page) + offset, size, |
| 3013 | dir, to_pci_dev(dev)->dma_mask); |
FUJITA Tomonori | bb9e6d6 | 2008-10-15 16:08:28 +0900 | [diff] [blame] | 3014 | } |
| 3015 | |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3016 | static void flush_unmaps(void) |
| 3017 | { |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 3018 | int i, j; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3019 | |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3020 | timer_on = 0; |
| 3021 | |
| 3022 | /* just flush them all */ |
| 3023 | for (i = 0; i < g_num_of_iommus; i++) { |
Weidong Han | a2bb845 | 2008-12-08 11:24:12 +0800 | [diff] [blame] | 3024 | struct intel_iommu *iommu = g_iommus[i]; |
| 3025 | if (!iommu) |
| 3026 | continue; |
Suresh Siddha | c42d9f3 | 2008-07-10 11:16:36 -0700 | [diff] [blame] | 3027 | |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 3028 | if (!deferred_flush[i].next) |
| 3029 | continue; |
| 3030 | |
Nadav Amit | 78d5f0f | 2010-04-08 23:00:41 +0300 | [diff] [blame] | 3031 | /* In caching mode, global flushes turn emulation expensive */ |
| 3032 | if (!cap_caching_mode(iommu->cap)) |
| 3033 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 3034 | DMA_TLB_GLOBAL_FLUSH); |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 3035 | for (j = 0; j < deferred_flush[i].next; j++) { |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 3036 | unsigned long mask; |
| 3037 | struct iova *iova = deferred_flush[i].iova[j]; |
Nadav Amit | 78d5f0f | 2010-04-08 23:00:41 +0300 | [diff] [blame] | 3038 | struct dmar_domain *domain = deferred_flush[i].domain[j]; |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 3039 | |
Nadav Amit | 78d5f0f | 2010-04-08 23:00:41 +0300 | [diff] [blame] | 3040 | /* On real hardware multiple invalidations are expensive */ |
| 3041 | if (cap_caching_mode(iommu->cap)) |
| 3042 | iommu_flush_iotlb_psi(iommu, domain->id, |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3043 | iova->pfn_lo, iova->pfn_hi - iova->pfn_lo + 1, |
| 3044 | !deferred_flush[i].freelist[j], 0); |
Nadav Amit | 78d5f0f | 2010-04-08 23:00:41 +0300 | [diff] [blame] | 3045 | else { |
| 3046 | mask = ilog2(mm_to_dma_pfn(iova->pfn_hi - iova->pfn_lo + 1)); |
| 3047 | iommu_flush_dev_iotlb(deferred_flush[i].domain[j], |
| 3048 | (uint64_t)iova->pfn_lo << PAGE_SHIFT, mask); |
| 3049 | } |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 3050 | __free_iova(&deferred_flush[i].domain[j]->iovad, iova); |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3051 | if (deferred_flush[i].freelist[j]) |
| 3052 | dma_free_pagelist(deferred_flush[i].freelist[j]); |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 3053 | } |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 3054 | deferred_flush[i].next = 0; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3055 | } |
| 3056 | |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3057 | list_size = 0; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3058 | } |
| 3059 | |
| 3060 | static void flush_unmaps_timeout(unsigned long data) |
| 3061 | { |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 3062 | unsigned long flags; |
| 3063 | |
| 3064 | spin_lock_irqsave(&async_umap_flush_lock, flags); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3065 | flush_unmaps(); |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 3066 | spin_unlock_irqrestore(&async_umap_flush_lock, flags); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3067 | } |
| 3068 | |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3069 | static void add_unmap(struct dmar_domain *dom, struct iova *iova, struct page *freelist) |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3070 | { |
| 3071 | unsigned long flags; |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 3072 | int next, iommu_id; |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3073 | struct intel_iommu *iommu; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3074 | |
| 3075 | spin_lock_irqsave(&async_umap_flush_lock, flags); |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 3076 | if (list_size == HIGH_WATER_MARK) |
| 3077 | flush_unmaps(); |
| 3078 | |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3079 | iommu = domain_get_iommu(dom); |
| 3080 | iommu_id = iommu->seq_id; |
Suresh Siddha | c42d9f3 | 2008-07-10 11:16:36 -0700 | [diff] [blame] | 3081 | |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 3082 | next = deferred_flush[iommu_id].next; |
| 3083 | deferred_flush[iommu_id].domain[next] = dom; |
| 3084 | deferred_flush[iommu_id].iova[next] = iova; |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3085 | deferred_flush[iommu_id].freelist[next] = freelist; |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 3086 | deferred_flush[iommu_id].next++; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3087 | |
| 3088 | if (!timer_on) { |
| 3089 | mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10)); |
| 3090 | timer_on = 1; |
| 3091 | } |
| 3092 | list_size++; |
| 3093 | spin_unlock_irqrestore(&async_umap_flush_lock, flags); |
| 3094 | } |
| 3095 | |
FUJITA Tomonori | ffbbef5 | 2009-01-05 23:47:26 +0900 | [diff] [blame] | 3096 | static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr, |
| 3097 | size_t size, enum dma_data_direction dir, |
| 3098 | struct dma_attrs *attrs) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3099 | { |
| 3100 | struct pci_dev *pdev = to_pci_dev(dev); |
| 3101 | struct dmar_domain *domain; |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 3102 | unsigned long start_pfn, last_pfn; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3103 | struct iova *iova; |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3104 | struct intel_iommu *iommu; |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3105 | struct page *freelist; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3106 | |
David Woodhouse | 7367683 | 2009-07-04 14:08:36 +0100 | [diff] [blame] | 3107 | if (iommu_no_mapping(dev)) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3108 | return; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3109 | |
David Woodhouse | 1525a29 | 2014-03-06 16:19:30 +0000 | [diff] [blame^] | 3110 | domain = find_domain(dev); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3111 | BUG_ON(!domain); |
| 3112 | |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3113 | iommu = domain_get_iommu(domain); |
| 3114 | |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3115 | iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr)); |
David Woodhouse | 85b9827 | 2009-07-01 19:27:53 +0100 | [diff] [blame] | 3116 | if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n", |
| 3117 | (unsigned long long)dev_addr)) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3118 | return; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3119 | |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 3120 | start_pfn = mm_to_dma_pfn(iova->pfn_lo); |
| 3121 | last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3122 | |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 3123 | pr_debug("Device %s unmapping: pfn %lx-%lx\n", |
| 3124 | pci_name(pdev), start_pfn, last_pfn); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3125 | |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3126 | freelist = domain_unmap(domain, start_pfn, last_pfn); |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 3127 | |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3128 | if (intel_iommu_strict) { |
David Woodhouse | 03d6a24 | 2009-06-28 15:33:46 +0100 | [diff] [blame] | 3129 | iommu_flush_iotlb_psi(iommu, domain->id, start_pfn, |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3130 | last_pfn - start_pfn + 1, !freelist, 0); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3131 | /* free iova */ |
| 3132 | __free_iova(&domain->iovad, iova); |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3133 | dma_free_pagelist(freelist); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3134 | } else { |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3135 | add_unmap(domain, iova, freelist); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3136 | /* |
| 3137 | * queue up the release of the unmap to save the 1/6th of the |
| 3138 | * cpu used up by the iotlb flush operation... |
| 3139 | */ |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3140 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3141 | } |
| 3142 | |
FUJITA Tomonori | d7ab5c4 | 2009-01-28 21:53:18 +0900 | [diff] [blame] | 3143 | static void *intel_alloc_coherent(struct device *hwdev, size_t size, |
Andrzej Pietrasiewicz | baa676f | 2012-03-27 14:28:18 +0200 | [diff] [blame] | 3144 | dma_addr_t *dma_handle, gfp_t flags, |
| 3145 | struct dma_attrs *attrs) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3146 | { |
| 3147 | void *vaddr; |
| 3148 | int order; |
| 3149 | |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 3150 | size = PAGE_ALIGN(size); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3151 | order = get_order(size); |
Alex Williamson | e8bb910 | 2009-11-04 15:59:34 -0700 | [diff] [blame] | 3152 | |
| 3153 | if (!iommu_no_mapping(hwdev)) |
| 3154 | flags &= ~(GFP_DMA | GFP_DMA32); |
| 3155 | else if (hwdev->coherent_dma_mask < dma_get_required_mask(hwdev)) { |
| 3156 | if (hwdev->coherent_dma_mask < DMA_BIT_MASK(32)) |
| 3157 | flags |= GFP_DMA; |
| 3158 | else |
| 3159 | flags |= GFP_DMA32; |
| 3160 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3161 | |
| 3162 | vaddr = (void *)__get_free_pages(flags, order); |
| 3163 | if (!vaddr) |
| 3164 | return NULL; |
| 3165 | memset(vaddr, 0, size); |
| 3166 | |
FUJITA Tomonori | bb9e6d6 | 2008-10-15 16:08:28 +0900 | [diff] [blame] | 3167 | *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size, |
| 3168 | DMA_BIDIRECTIONAL, |
| 3169 | hwdev->coherent_dma_mask); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3170 | if (*dma_handle) |
| 3171 | return vaddr; |
| 3172 | free_pages((unsigned long)vaddr, order); |
| 3173 | return NULL; |
| 3174 | } |
| 3175 | |
FUJITA Tomonori | d7ab5c4 | 2009-01-28 21:53:18 +0900 | [diff] [blame] | 3176 | static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr, |
Andrzej Pietrasiewicz | baa676f | 2012-03-27 14:28:18 +0200 | [diff] [blame] | 3177 | dma_addr_t dma_handle, struct dma_attrs *attrs) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3178 | { |
| 3179 | int order; |
| 3180 | |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 3181 | size = PAGE_ALIGN(size); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3182 | order = get_order(size); |
| 3183 | |
David Woodhouse | 0db9b7a | 2009-07-14 02:01:57 +0100 | [diff] [blame] | 3184 | intel_unmap_page(hwdev, dma_handle, size, DMA_BIDIRECTIONAL, NULL); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3185 | free_pages((unsigned long)vaddr, order); |
| 3186 | } |
| 3187 | |
FUJITA Tomonori | d7ab5c4 | 2009-01-28 21:53:18 +0900 | [diff] [blame] | 3188 | static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist, |
| 3189 | int nelems, enum dma_data_direction dir, |
| 3190 | struct dma_attrs *attrs) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3191 | { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3192 | struct pci_dev *pdev = to_pci_dev(hwdev); |
| 3193 | struct dmar_domain *domain; |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 3194 | unsigned long start_pfn, last_pfn; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3195 | struct iova *iova; |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3196 | struct intel_iommu *iommu; |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3197 | struct page *freelist; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3198 | |
David Woodhouse | 7367683 | 2009-07-04 14:08:36 +0100 | [diff] [blame] | 3199 | if (iommu_no_mapping(hwdev)) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3200 | return; |
| 3201 | |
David Woodhouse | 1525a29 | 2014-03-06 16:19:30 +0000 | [diff] [blame^] | 3202 | domain = find_domain(hwdev); |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3203 | BUG_ON(!domain); |
| 3204 | |
| 3205 | iommu = domain_get_iommu(domain); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3206 | |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 3207 | iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address)); |
David Woodhouse | 85b9827 | 2009-07-01 19:27:53 +0100 | [diff] [blame] | 3208 | if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n", |
| 3209 | (unsigned long long)sglist[0].dma_address)) |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3210 | return; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3211 | |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 3212 | start_pfn = mm_to_dma_pfn(iova->pfn_lo); |
| 3213 | last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3214 | |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3215 | freelist = domain_unmap(domain, start_pfn, last_pfn); |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 3216 | |
David Woodhouse | acea001 | 2009-07-14 01:55:11 +0100 | [diff] [blame] | 3217 | if (intel_iommu_strict) { |
| 3218 | iommu_flush_iotlb_psi(iommu, domain->id, start_pfn, |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3219 | last_pfn - start_pfn + 1, !freelist, 0); |
David Woodhouse | acea001 | 2009-07-14 01:55:11 +0100 | [diff] [blame] | 3220 | /* free iova */ |
| 3221 | __free_iova(&domain->iovad, iova); |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3222 | dma_free_pagelist(freelist); |
David Woodhouse | acea001 | 2009-07-14 01:55:11 +0100 | [diff] [blame] | 3223 | } else { |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3224 | add_unmap(domain, iova, freelist); |
David Woodhouse | acea001 | 2009-07-14 01:55:11 +0100 | [diff] [blame] | 3225 | /* |
| 3226 | * queue up the release of the unmap to save the 1/6th of the |
| 3227 | * cpu used up by the iotlb flush operation... |
| 3228 | */ |
| 3229 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3230 | } |
| 3231 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3232 | static int intel_nontranslate_map_sg(struct device *hddev, |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 3233 | struct scatterlist *sglist, int nelems, int dir) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3234 | { |
| 3235 | int i; |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 3236 | struct scatterlist *sg; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3237 | |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 3238 | for_each_sg(sglist, sg, nelems, i) { |
FUJITA Tomonori | 12d4d40 | 2007-10-23 09:32:25 +0200 | [diff] [blame] | 3239 | BUG_ON(!sg_page(sg)); |
David Woodhouse | 4cf2e75 | 2009-02-11 17:23:43 +0000 | [diff] [blame] | 3240 | sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset; |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 3241 | sg->dma_length = sg->length; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3242 | } |
| 3243 | return nelems; |
| 3244 | } |
| 3245 | |
FUJITA Tomonori | d7ab5c4 | 2009-01-28 21:53:18 +0900 | [diff] [blame] | 3246 | static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems, |
| 3247 | enum dma_data_direction dir, struct dma_attrs *attrs) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3248 | { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3249 | int i; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3250 | struct pci_dev *pdev = to_pci_dev(hwdev); |
| 3251 | struct dmar_domain *domain; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3252 | size_t size = 0; |
| 3253 | int prot = 0; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3254 | struct iova *iova = NULL; |
| 3255 | int ret; |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 3256 | struct scatterlist *sg; |
David Woodhouse | b536d24 | 2009-06-28 14:49:31 +0100 | [diff] [blame] | 3257 | unsigned long start_vpfn; |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3258 | struct intel_iommu *iommu; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3259 | |
| 3260 | BUG_ON(dir == DMA_NONE); |
David Woodhouse | 7367683 | 2009-07-04 14:08:36 +0100 | [diff] [blame] | 3261 | if (iommu_no_mapping(hwdev)) |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 3262 | return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3263 | |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3264 | domain = get_valid_domain_for_dev(pdev); |
| 3265 | if (!domain) |
| 3266 | return 0; |
| 3267 | |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3268 | iommu = domain_get_iommu(domain); |
| 3269 | |
David Woodhouse | b536d24 | 2009-06-28 14:49:31 +0100 | [diff] [blame] | 3270 | for_each_sg(sglist, sg, nelems, i) |
David Woodhouse | 88cb6a7 | 2009-06-28 15:03:06 +0100 | [diff] [blame] | 3271 | size += aligned_nrpages(sg->offset, sg->length); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3272 | |
David Woodhouse | 5a5e02a | 2009-07-04 09:35:44 +0100 | [diff] [blame] | 3273 | iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size), |
| 3274 | pdev->dma_mask); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3275 | if (!iova) { |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 3276 | sglist->dma_length = 0; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3277 | return 0; |
| 3278 | } |
| 3279 | |
| 3280 | /* |
| 3281 | * Check if DMAR supports zero-length reads on write only |
| 3282 | * mappings.. |
| 3283 | */ |
| 3284 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \ |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3285 | !cap_zlr(iommu->cap)) |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3286 | prot |= DMA_PTE_READ; |
| 3287 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) |
| 3288 | prot |= DMA_PTE_WRITE; |
| 3289 | |
David Woodhouse | b536d24 | 2009-06-28 14:49:31 +0100 | [diff] [blame] | 3290 | start_vpfn = mm_to_dma_pfn(iova->pfn_lo); |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 3291 | |
Fenghua Yu | f532959 | 2009-08-04 15:09:37 -0700 | [diff] [blame] | 3292 | ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot); |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 3293 | if (unlikely(ret)) { |
| 3294 | /* clear the page */ |
| 3295 | dma_pte_clear_range(domain, start_vpfn, |
| 3296 | start_vpfn + size - 1); |
| 3297 | /* free page tables */ |
| 3298 | dma_pte_free_pagetable(domain, start_vpfn, |
| 3299 | start_vpfn + size - 1); |
| 3300 | /* free iova */ |
| 3301 | __free_iova(&domain->iovad, iova); |
| 3302 | return 0; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3303 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3304 | |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 3305 | /* it's a non-present to present mapping. Only flush if caching mode */ |
| 3306 | if (cap_caching_mode(iommu->cap)) |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3307 | iommu_flush_iotlb_psi(iommu, domain->id, start_vpfn, size, 0, 1); |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 3308 | else |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3309 | iommu_flush_write_buffer(iommu); |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 3310 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3311 | return nelems; |
| 3312 | } |
| 3313 | |
FUJITA Tomonori | dfb805e | 2009-01-28 21:53:17 +0900 | [diff] [blame] | 3314 | static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr) |
| 3315 | { |
| 3316 | return !dma_addr; |
| 3317 | } |
| 3318 | |
FUJITA Tomonori | 160c1d8 | 2009-01-05 23:59:02 +0900 | [diff] [blame] | 3319 | struct dma_map_ops intel_dma_ops = { |
Andrzej Pietrasiewicz | baa676f | 2012-03-27 14:28:18 +0200 | [diff] [blame] | 3320 | .alloc = intel_alloc_coherent, |
| 3321 | .free = intel_free_coherent, |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3322 | .map_sg = intel_map_sg, |
| 3323 | .unmap_sg = intel_unmap_sg, |
FUJITA Tomonori | ffbbef5 | 2009-01-05 23:47:26 +0900 | [diff] [blame] | 3324 | .map_page = intel_map_page, |
| 3325 | .unmap_page = intel_unmap_page, |
FUJITA Tomonori | dfb805e | 2009-01-28 21:53:17 +0900 | [diff] [blame] | 3326 | .mapping_error = intel_mapping_error, |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3327 | }; |
| 3328 | |
| 3329 | static inline int iommu_domain_cache_init(void) |
| 3330 | { |
| 3331 | int ret = 0; |
| 3332 | |
| 3333 | iommu_domain_cache = kmem_cache_create("iommu_domain", |
| 3334 | sizeof(struct dmar_domain), |
| 3335 | 0, |
| 3336 | SLAB_HWCACHE_ALIGN, |
| 3337 | |
| 3338 | NULL); |
| 3339 | if (!iommu_domain_cache) { |
| 3340 | printk(KERN_ERR "Couldn't create iommu_domain cache\n"); |
| 3341 | ret = -ENOMEM; |
| 3342 | } |
| 3343 | |
| 3344 | return ret; |
| 3345 | } |
| 3346 | |
| 3347 | static inline int iommu_devinfo_cache_init(void) |
| 3348 | { |
| 3349 | int ret = 0; |
| 3350 | |
| 3351 | iommu_devinfo_cache = kmem_cache_create("iommu_devinfo", |
| 3352 | sizeof(struct device_domain_info), |
| 3353 | 0, |
| 3354 | SLAB_HWCACHE_ALIGN, |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3355 | NULL); |
| 3356 | if (!iommu_devinfo_cache) { |
| 3357 | printk(KERN_ERR "Couldn't create devinfo cache\n"); |
| 3358 | ret = -ENOMEM; |
| 3359 | } |
| 3360 | |
| 3361 | return ret; |
| 3362 | } |
| 3363 | |
| 3364 | static inline int iommu_iova_cache_init(void) |
| 3365 | { |
| 3366 | int ret = 0; |
| 3367 | |
| 3368 | iommu_iova_cache = kmem_cache_create("iommu_iova", |
| 3369 | sizeof(struct iova), |
| 3370 | 0, |
| 3371 | SLAB_HWCACHE_ALIGN, |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3372 | NULL); |
| 3373 | if (!iommu_iova_cache) { |
| 3374 | printk(KERN_ERR "Couldn't create iova cache\n"); |
| 3375 | ret = -ENOMEM; |
| 3376 | } |
| 3377 | |
| 3378 | return ret; |
| 3379 | } |
| 3380 | |
| 3381 | static int __init iommu_init_mempool(void) |
| 3382 | { |
| 3383 | int ret; |
| 3384 | ret = iommu_iova_cache_init(); |
| 3385 | if (ret) |
| 3386 | return ret; |
| 3387 | |
| 3388 | ret = iommu_domain_cache_init(); |
| 3389 | if (ret) |
| 3390 | goto domain_error; |
| 3391 | |
| 3392 | ret = iommu_devinfo_cache_init(); |
| 3393 | if (!ret) |
| 3394 | return ret; |
| 3395 | |
| 3396 | kmem_cache_destroy(iommu_domain_cache); |
| 3397 | domain_error: |
| 3398 | kmem_cache_destroy(iommu_iova_cache); |
| 3399 | |
| 3400 | return -ENOMEM; |
| 3401 | } |
| 3402 | |
| 3403 | static void __init iommu_exit_mempool(void) |
| 3404 | { |
| 3405 | kmem_cache_destroy(iommu_devinfo_cache); |
| 3406 | kmem_cache_destroy(iommu_domain_cache); |
| 3407 | kmem_cache_destroy(iommu_iova_cache); |
| 3408 | |
| 3409 | } |
| 3410 | |
Dan Williams | 556ab45 | 2010-07-23 15:47:56 -0700 | [diff] [blame] | 3411 | static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev) |
| 3412 | { |
| 3413 | struct dmar_drhd_unit *drhd; |
| 3414 | u32 vtbar; |
| 3415 | int rc; |
| 3416 | |
| 3417 | /* We know that this device on this chipset has its own IOMMU. |
| 3418 | * If we find it under a different IOMMU, then the BIOS is lying |
| 3419 | * to us. Hope that the IOMMU for this device is actually |
| 3420 | * disabled, and it needs no translation... |
| 3421 | */ |
| 3422 | rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar); |
| 3423 | if (rc) { |
| 3424 | /* "can't" happen */ |
| 3425 | dev_info(&pdev->dev, "failed to run vt-d quirk\n"); |
| 3426 | return; |
| 3427 | } |
| 3428 | vtbar &= 0xffff0000; |
| 3429 | |
| 3430 | /* we know that the this iommu should be at offset 0xa000 from vtbar */ |
| 3431 | drhd = dmar_find_matched_drhd_unit(pdev); |
| 3432 | if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000, |
| 3433 | TAINT_FIRMWARE_WORKAROUND, |
| 3434 | "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n")) |
| 3435 | pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO; |
| 3436 | } |
| 3437 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu); |
| 3438 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3439 | static void __init init_no_remapping_devices(void) |
| 3440 | { |
| 3441 | struct dmar_drhd_unit *drhd; |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 3442 | struct device *dev; |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 3443 | int i; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3444 | |
| 3445 | for_each_drhd_unit(drhd) { |
| 3446 | if (!drhd->include_all) { |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 3447 | for_each_active_dev_scope(drhd->devices, |
| 3448 | drhd->devices_cnt, i, dev) |
| 3449 | break; |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 3450 | /* ignore DMAR unit if no devices exist */ |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3451 | if (i == drhd->devices_cnt) |
| 3452 | drhd->ignored = 1; |
| 3453 | } |
| 3454 | } |
| 3455 | |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 3456 | for_each_active_drhd_unit(drhd) { |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 3457 | if (drhd->include_all) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3458 | continue; |
| 3459 | |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 3460 | for_each_active_dev_scope(drhd->devices, |
| 3461 | drhd->devices_cnt, i, dev) |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 3462 | if (!dev_is_pci(dev) || !IS_GFX_DEVICE(to_pci_dev(dev))) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3463 | break; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3464 | if (i < drhd->devices_cnt) |
| 3465 | continue; |
| 3466 | |
David Woodhouse | c0771df | 2011-10-14 20:59:46 +0100 | [diff] [blame] | 3467 | /* This IOMMU has *only* gfx devices. Either bypass it or |
| 3468 | set the gfx_mapped flag, as appropriate */ |
| 3469 | if (dmar_map_gfx) { |
| 3470 | intel_iommu_gfx_mapped = 1; |
| 3471 | } else { |
| 3472 | drhd->ignored = 1; |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 3473 | for_each_active_dev_scope(drhd->devices, |
| 3474 | drhd->devices_cnt, i, dev) |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 3475 | dev->archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3476 | } |
| 3477 | } |
| 3478 | } |
| 3479 | |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3480 | #ifdef CONFIG_SUSPEND |
| 3481 | static int init_iommu_hw(void) |
| 3482 | { |
| 3483 | struct dmar_drhd_unit *drhd; |
| 3484 | struct intel_iommu *iommu = NULL; |
| 3485 | |
| 3486 | for_each_active_iommu(iommu, drhd) |
| 3487 | if (iommu->qi) |
| 3488 | dmar_reenable_qi(iommu); |
| 3489 | |
Joseph Cihula | b779260 | 2011-05-03 00:08:37 -0700 | [diff] [blame] | 3490 | for_each_iommu(iommu, drhd) { |
| 3491 | if (drhd->ignored) { |
| 3492 | /* |
| 3493 | * we always have to disable PMRs or DMA may fail on |
| 3494 | * this device |
| 3495 | */ |
| 3496 | if (force_on) |
| 3497 | iommu_disable_protect_mem_regions(iommu); |
| 3498 | continue; |
| 3499 | } |
| 3500 | |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3501 | iommu_flush_write_buffer(iommu); |
| 3502 | |
| 3503 | iommu_set_root_entry(iommu); |
| 3504 | |
| 3505 | iommu->flush.flush_context(iommu, 0, 0, 0, |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 3506 | DMA_CCMD_GLOBAL_INVL); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3507 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 3508 | DMA_TLB_GLOBAL_FLUSH); |
Joseph Cihula | b779260 | 2011-05-03 00:08:37 -0700 | [diff] [blame] | 3509 | if (iommu_enable_translation(iommu)) |
| 3510 | return 1; |
David Woodhouse | b94996c | 2009-09-19 15:28:12 -0700 | [diff] [blame] | 3511 | iommu_disable_protect_mem_regions(iommu); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3512 | } |
| 3513 | |
| 3514 | return 0; |
| 3515 | } |
| 3516 | |
| 3517 | static void iommu_flush_all(void) |
| 3518 | { |
| 3519 | struct dmar_drhd_unit *drhd; |
| 3520 | struct intel_iommu *iommu; |
| 3521 | |
| 3522 | for_each_active_iommu(iommu, drhd) { |
| 3523 | iommu->flush.flush_context(iommu, 0, 0, 0, |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 3524 | DMA_CCMD_GLOBAL_INVL); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3525 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 3526 | DMA_TLB_GLOBAL_FLUSH); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3527 | } |
| 3528 | } |
| 3529 | |
Rafael J. Wysocki | 134fac3 | 2011-03-23 22:16:14 +0100 | [diff] [blame] | 3530 | static int iommu_suspend(void) |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3531 | { |
| 3532 | struct dmar_drhd_unit *drhd; |
| 3533 | struct intel_iommu *iommu = NULL; |
| 3534 | unsigned long flag; |
| 3535 | |
| 3536 | for_each_active_iommu(iommu, drhd) { |
| 3537 | iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS, |
| 3538 | GFP_ATOMIC); |
| 3539 | if (!iommu->iommu_state) |
| 3540 | goto nomem; |
| 3541 | } |
| 3542 | |
| 3543 | iommu_flush_all(); |
| 3544 | |
| 3545 | for_each_active_iommu(iommu, drhd) { |
| 3546 | iommu_disable_translation(iommu); |
| 3547 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 3548 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3549 | |
| 3550 | iommu->iommu_state[SR_DMAR_FECTL_REG] = |
| 3551 | readl(iommu->reg + DMAR_FECTL_REG); |
| 3552 | iommu->iommu_state[SR_DMAR_FEDATA_REG] = |
| 3553 | readl(iommu->reg + DMAR_FEDATA_REG); |
| 3554 | iommu->iommu_state[SR_DMAR_FEADDR_REG] = |
| 3555 | readl(iommu->reg + DMAR_FEADDR_REG); |
| 3556 | iommu->iommu_state[SR_DMAR_FEUADDR_REG] = |
| 3557 | readl(iommu->reg + DMAR_FEUADDR_REG); |
| 3558 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 3559 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3560 | } |
| 3561 | return 0; |
| 3562 | |
| 3563 | nomem: |
| 3564 | for_each_active_iommu(iommu, drhd) |
| 3565 | kfree(iommu->iommu_state); |
| 3566 | |
| 3567 | return -ENOMEM; |
| 3568 | } |
| 3569 | |
Rafael J. Wysocki | 134fac3 | 2011-03-23 22:16:14 +0100 | [diff] [blame] | 3570 | static void iommu_resume(void) |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3571 | { |
| 3572 | struct dmar_drhd_unit *drhd; |
| 3573 | struct intel_iommu *iommu = NULL; |
| 3574 | unsigned long flag; |
| 3575 | |
| 3576 | if (init_iommu_hw()) { |
Joseph Cihula | b779260 | 2011-05-03 00:08:37 -0700 | [diff] [blame] | 3577 | if (force_on) |
| 3578 | panic("tboot: IOMMU setup failed, DMAR can not resume!\n"); |
| 3579 | else |
| 3580 | WARN(1, "IOMMU setup failed, DMAR can not resume!\n"); |
Rafael J. Wysocki | 134fac3 | 2011-03-23 22:16:14 +0100 | [diff] [blame] | 3581 | return; |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3582 | } |
| 3583 | |
| 3584 | for_each_active_iommu(iommu, drhd) { |
| 3585 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 3586 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3587 | |
| 3588 | writel(iommu->iommu_state[SR_DMAR_FECTL_REG], |
| 3589 | iommu->reg + DMAR_FECTL_REG); |
| 3590 | writel(iommu->iommu_state[SR_DMAR_FEDATA_REG], |
| 3591 | iommu->reg + DMAR_FEDATA_REG); |
| 3592 | writel(iommu->iommu_state[SR_DMAR_FEADDR_REG], |
| 3593 | iommu->reg + DMAR_FEADDR_REG); |
| 3594 | writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG], |
| 3595 | iommu->reg + DMAR_FEUADDR_REG); |
| 3596 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 3597 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3598 | } |
| 3599 | |
| 3600 | for_each_active_iommu(iommu, drhd) |
| 3601 | kfree(iommu->iommu_state); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3602 | } |
| 3603 | |
Rafael J. Wysocki | 134fac3 | 2011-03-23 22:16:14 +0100 | [diff] [blame] | 3604 | static struct syscore_ops iommu_syscore_ops = { |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3605 | .resume = iommu_resume, |
| 3606 | .suspend = iommu_suspend, |
| 3607 | }; |
| 3608 | |
Rafael J. Wysocki | 134fac3 | 2011-03-23 22:16:14 +0100 | [diff] [blame] | 3609 | static void __init init_iommu_pm_ops(void) |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3610 | { |
Rafael J. Wysocki | 134fac3 | 2011-03-23 22:16:14 +0100 | [diff] [blame] | 3611 | register_syscore_ops(&iommu_syscore_ops); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3612 | } |
| 3613 | |
| 3614 | #else |
Rafael J. Wysocki | 99592ba | 2011-06-07 21:32:31 +0200 | [diff] [blame] | 3615 | static inline void init_iommu_pm_ops(void) {} |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3616 | #endif /* CONFIG_PM */ |
| 3617 | |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3618 | |
| 3619 | int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header) |
| 3620 | { |
| 3621 | struct acpi_dmar_reserved_memory *rmrr; |
| 3622 | struct dmar_rmrr_unit *rmrru; |
| 3623 | |
| 3624 | rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL); |
| 3625 | if (!rmrru) |
| 3626 | return -ENOMEM; |
| 3627 | |
| 3628 | rmrru->hdr = header; |
| 3629 | rmrr = (struct acpi_dmar_reserved_memory *)header; |
| 3630 | rmrru->base_address = rmrr->base_address; |
| 3631 | rmrru->end_address = rmrr->end_address; |
Jiang Liu | 2e45528 | 2014-02-19 14:07:36 +0800 | [diff] [blame] | 3632 | rmrru->devices = dmar_alloc_dev_scope((void *)(rmrr + 1), |
| 3633 | ((void *)rmrr) + rmrr->header.length, |
| 3634 | &rmrru->devices_cnt); |
| 3635 | if (rmrru->devices_cnt && rmrru->devices == NULL) { |
| 3636 | kfree(rmrru); |
| 3637 | return -ENOMEM; |
| 3638 | } |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3639 | |
Jiang Liu | 2e45528 | 2014-02-19 14:07:36 +0800 | [diff] [blame] | 3640 | list_add(&rmrru->list, &dmar_rmrr_units); |
| 3641 | |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3642 | return 0; |
| 3643 | } |
| 3644 | |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3645 | int __init dmar_parse_one_atsr(struct acpi_dmar_header *hdr) |
| 3646 | { |
| 3647 | struct acpi_dmar_atsr *atsr; |
| 3648 | struct dmar_atsr_unit *atsru; |
| 3649 | |
| 3650 | atsr = container_of(hdr, struct acpi_dmar_atsr, header); |
| 3651 | atsru = kzalloc(sizeof(*atsru), GFP_KERNEL); |
| 3652 | if (!atsru) |
| 3653 | return -ENOMEM; |
| 3654 | |
| 3655 | atsru->hdr = hdr; |
| 3656 | atsru->include_all = atsr->flags & 0x1; |
Jiang Liu | 2e45528 | 2014-02-19 14:07:36 +0800 | [diff] [blame] | 3657 | if (!atsru->include_all) { |
| 3658 | atsru->devices = dmar_alloc_dev_scope((void *)(atsr + 1), |
| 3659 | (void *)atsr + atsr->header.length, |
| 3660 | &atsru->devices_cnt); |
| 3661 | if (atsru->devices_cnt && atsru->devices == NULL) { |
| 3662 | kfree(atsru); |
| 3663 | return -ENOMEM; |
| 3664 | } |
| 3665 | } |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3666 | |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 3667 | list_add_rcu(&atsru->list, &dmar_atsr_units); |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3668 | |
| 3669 | return 0; |
| 3670 | } |
| 3671 | |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 3672 | static void intel_iommu_free_atsr(struct dmar_atsr_unit *atsru) |
| 3673 | { |
| 3674 | dmar_free_dev_scope(&atsru->devices, &atsru->devices_cnt); |
| 3675 | kfree(atsru); |
| 3676 | } |
| 3677 | |
| 3678 | static void intel_iommu_free_dmars(void) |
| 3679 | { |
| 3680 | struct dmar_rmrr_unit *rmrru, *rmrr_n; |
| 3681 | struct dmar_atsr_unit *atsru, *atsr_n; |
| 3682 | |
| 3683 | list_for_each_entry_safe(rmrru, rmrr_n, &dmar_rmrr_units, list) { |
| 3684 | list_del(&rmrru->list); |
| 3685 | dmar_free_dev_scope(&rmrru->devices, &rmrru->devices_cnt); |
| 3686 | kfree(rmrru); |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3687 | } |
| 3688 | |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 3689 | list_for_each_entry_safe(atsru, atsr_n, &dmar_atsr_units, list) { |
| 3690 | list_del(&atsru->list); |
| 3691 | intel_iommu_free_atsr(atsru); |
| 3692 | } |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3693 | } |
| 3694 | |
| 3695 | int dmar_find_matched_atsr_unit(struct pci_dev *dev) |
| 3696 | { |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 3697 | int i, ret = 1; |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3698 | struct pci_bus *bus; |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 3699 | struct pci_dev *bridge = NULL; |
| 3700 | struct device *tmp; |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3701 | struct acpi_dmar_atsr *atsr; |
| 3702 | struct dmar_atsr_unit *atsru; |
| 3703 | |
| 3704 | dev = pci_physfn(dev); |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3705 | for (bus = dev->bus; bus; bus = bus->parent) { |
Jiang Liu | b5f82dd | 2014-02-19 14:07:31 +0800 | [diff] [blame] | 3706 | bridge = bus->self; |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3707 | if (!bridge || !pci_is_pcie(bridge) || |
Yijing Wang | 62f87c0 | 2012-07-24 17:20:03 +0800 | [diff] [blame] | 3708 | pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3709 | return 0; |
Jiang Liu | b5f82dd | 2014-02-19 14:07:31 +0800 | [diff] [blame] | 3710 | if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3711 | break; |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3712 | } |
Jiang Liu | b5f82dd | 2014-02-19 14:07:31 +0800 | [diff] [blame] | 3713 | if (!bridge) |
| 3714 | return 0; |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3715 | |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 3716 | rcu_read_lock(); |
Jiang Liu | b5f82dd | 2014-02-19 14:07:31 +0800 | [diff] [blame] | 3717 | list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) { |
| 3718 | atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header); |
| 3719 | if (atsr->segment != pci_domain_nr(dev->bus)) |
| 3720 | continue; |
| 3721 | |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 3722 | for_each_dev_scope(atsru->devices, atsru->devices_cnt, i, tmp) |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 3723 | if (tmp == &bridge->dev) |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 3724 | goto out; |
Jiang Liu | b5f82dd | 2014-02-19 14:07:31 +0800 | [diff] [blame] | 3725 | |
| 3726 | if (atsru->include_all) |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 3727 | goto out; |
Jiang Liu | b5f82dd | 2014-02-19 14:07:31 +0800 | [diff] [blame] | 3728 | } |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 3729 | ret = 0; |
| 3730 | out: |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 3731 | rcu_read_unlock(); |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3732 | |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 3733 | return ret; |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3734 | } |
| 3735 | |
Jiang Liu | 59ce051 | 2014-02-19 14:07:35 +0800 | [diff] [blame] | 3736 | int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info) |
| 3737 | { |
| 3738 | int ret = 0; |
| 3739 | struct dmar_rmrr_unit *rmrru; |
| 3740 | struct dmar_atsr_unit *atsru; |
| 3741 | struct acpi_dmar_atsr *atsr; |
| 3742 | struct acpi_dmar_reserved_memory *rmrr; |
| 3743 | |
| 3744 | if (!intel_iommu_enabled && system_state != SYSTEM_BOOTING) |
| 3745 | return 0; |
| 3746 | |
| 3747 | list_for_each_entry(rmrru, &dmar_rmrr_units, list) { |
| 3748 | rmrr = container_of(rmrru->hdr, |
| 3749 | struct acpi_dmar_reserved_memory, header); |
| 3750 | if (info->event == BUS_NOTIFY_ADD_DEVICE) { |
| 3751 | ret = dmar_insert_dev_scope(info, (void *)(rmrr + 1), |
| 3752 | ((void *)rmrr) + rmrr->header.length, |
| 3753 | rmrr->segment, rmrru->devices, |
| 3754 | rmrru->devices_cnt); |
| 3755 | if (ret > 0) |
| 3756 | break; |
| 3757 | else if(ret < 0) |
| 3758 | return ret; |
| 3759 | } else if (info->event == BUS_NOTIFY_DEL_DEVICE) { |
| 3760 | if (dmar_remove_dev_scope(info, rmrr->segment, |
| 3761 | rmrru->devices, rmrru->devices_cnt)) |
| 3762 | break; |
| 3763 | } |
| 3764 | } |
| 3765 | |
| 3766 | list_for_each_entry(atsru, &dmar_atsr_units, list) { |
| 3767 | if (atsru->include_all) |
| 3768 | continue; |
| 3769 | |
| 3770 | atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header); |
| 3771 | if (info->event == BUS_NOTIFY_ADD_DEVICE) { |
| 3772 | ret = dmar_insert_dev_scope(info, (void *)(atsr + 1), |
| 3773 | (void *)atsr + atsr->header.length, |
| 3774 | atsr->segment, atsru->devices, |
| 3775 | atsru->devices_cnt); |
| 3776 | if (ret > 0) |
| 3777 | break; |
| 3778 | else if(ret < 0) |
| 3779 | return ret; |
| 3780 | } else if (info->event == BUS_NOTIFY_DEL_DEVICE) { |
| 3781 | if (dmar_remove_dev_scope(info, atsr->segment, |
| 3782 | atsru->devices, atsru->devices_cnt)) |
| 3783 | break; |
| 3784 | } |
| 3785 | } |
| 3786 | |
| 3787 | return 0; |
| 3788 | } |
| 3789 | |
Fenghua Yu | 99dcade | 2009-11-11 07:23:06 -0800 | [diff] [blame] | 3790 | /* |
| 3791 | * Here we only respond to action of unbound device from driver. |
| 3792 | * |
| 3793 | * Added device is not attached to its DMAR domain here yet. That will happen |
| 3794 | * when mapping the device to iova. |
| 3795 | */ |
| 3796 | static int device_notifier(struct notifier_block *nb, |
| 3797 | unsigned long action, void *data) |
| 3798 | { |
| 3799 | struct device *dev = data; |
| 3800 | struct pci_dev *pdev = to_pci_dev(dev); |
| 3801 | struct dmar_domain *domain; |
| 3802 | |
David Woodhouse | 3d89194 | 2014-03-06 15:59:26 +0000 | [diff] [blame] | 3803 | if (iommu_dummy(dev)) |
David Woodhouse | 44cd613 | 2009-12-02 10:18:30 +0000 | [diff] [blame] | 3804 | return 0; |
| 3805 | |
Jiang Liu | 7e7dfab | 2014-02-19 14:07:23 +0800 | [diff] [blame] | 3806 | if (action != BUS_NOTIFY_UNBOUND_DRIVER && |
| 3807 | action != BUS_NOTIFY_DEL_DEVICE) |
| 3808 | return 0; |
| 3809 | |
David Woodhouse | 1525a29 | 2014-03-06 16:19:30 +0000 | [diff] [blame^] | 3810 | domain = find_domain(dev); |
Fenghua Yu | 99dcade | 2009-11-11 07:23:06 -0800 | [diff] [blame] | 3811 | if (!domain) |
| 3812 | return 0; |
| 3813 | |
Jiang Liu | 3a5670e | 2014-02-19 14:07:33 +0800 | [diff] [blame] | 3814 | down_read(&dmar_global_lock); |
Jiang Liu | 7e7dfab | 2014-02-19 14:07:23 +0800 | [diff] [blame] | 3815 | domain_remove_one_dev_info(domain, pdev); |
| 3816 | if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) && |
| 3817 | !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) && |
| 3818 | list_empty(&domain->devices)) |
| 3819 | domain_exit(domain); |
Jiang Liu | 3a5670e | 2014-02-19 14:07:33 +0800 | [diff] [blame] | 3820 | up_read(&dmar_global_lock); |
Alex Williamson | a97590e | 2011-03-04 14:52:16 -0700 | [diff] [blame] | 3821 | |
Fenghua Yu | 99dcade | 2009-11-11 07:23:06 -0800 | [diff] [blame] | 3822 | return 0; |
| 3823 | } |
| 3824 | |
| 3825 | static struct notifier_block device_nb = { |
| 3826 | .notifier_call = device_notifier, |
| 3827 | }; |
| 3828 | |
Jiang Liu | 75f0556 | 2014-02-19 14:07:37 +0800 | [diff] [blame] | 3829 | static int intel_iommu_memory_notifier(struct notifier_block *nb, |
| 3830 | unsigned long val, void *v) |
| 3831 | { |
| 3832 | struct memory_notify *mhp = v; |
| 3833 | unsigned long long start, end; |
| 3834 | unsigned long start_vpfn, last_vpfn; |
| 3835 | |
| 3836 | switch (val) { |
| 3837 | case MEM_GOING_ONLINE: |
| 3838 | start = mhp->start_pfn << PAGE_SHIFT; |
| 3839 | end = ((mhp->start_pfn + mhp->nr_pages) << PAGE_SHIFT) - 1; |
| 3840 | if (iommu_domain_identity_map(si_domain, start, end)) { |
| 3841 | pr_warn("dmar: failed to build identity map for [%llx-%llx]\n", |
| 3842 | start, end); |
| 3843 | return NOTIFY_BAD; |
| 3844 | } |
| 3845 | break; |
| 3846 | |
| 3847 | case MEM_OFFLINE: |
| 3848 | case MEM_CANCEL_ONLINE: |
| 3849 | start_vpfn = mm_to_dma_pfn(mhp->start_pfn); |
| 3850 | last_vpfn = mm_to_dma_pfn(mhp->start_pfn + mhp->nr_pages - 1); |
| 3851 | while (start_vpfn <= last_vpfn) { |
| 3852 | struct iova *iova; |
| 3853 | struct dmar_drhd_unit *drhd; |
| 3854 | struct intel_iommu *iommu; |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3855 | struct page *freelist; |
Jiang Liu | 75f0556 | 2014-02-19 14:07:37 +0800 | [diff] [blame] | 3856 | |
| 3857 | iova = find_iova(&si_domain->iovad, start_vpfn); |
| 3858 | if (iova == NULL) { |
| 3859 | pr_debug("dmar: failed get IOVA for PFN %lx\n", |
| 3860 | start_vpfn); |
| 3861 | break; |
| 3862 | } |
| 3863 | |
| 3864 | iova = split_and_remove_iova(&si_domain->iovad, iova, |
| 3865 | start_vpfn, last_vpfn); |
| 3866 | if (iova == NULL) { |
| 3867 | pr_warn("dmar: failed to split IOVA PFN [%lx-%lx]\n", |
| 3868 | start_vpfn, last_vpfn); |
| 3869 | return NOTIFY_BAD; |
| 3870 | } |
| 3871 | |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3872 | freelist = domain_unmap(si_domain, iova->pfn_lo, |
| 3873 | iova->pfn_hi); |
| 3874 | |
Jiang Liu | 75f0556 | 2014-02-19 14:07:37 +0800 | [diff] [blame] | 3875 | rcu_read_lock(); |
| 3876 | for_each_active_iommu(iommu, drhd) |
| 3877 | iommu_flush_iotlb_psi(iommu, si_domain->id, |
| 3878 | iova->pfn_lo, |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3879 | iova->pfn_hi - iova->pfn_lo + 1, |
| 3880 | !freelist, 0); |
Jiang Liu | 75f0556 | 2014-02-19 14:07:37 +0800 | [diff] [blame] | 3881 | rcu_read_unlock(); |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3882 | dma_free_pagelist(freelist); |
Jiang Liu | 75f0556 | 2014-02-19 14:07:37 +0800 | [diff] [blame] | 3883 | |
| 3884 | start_vpfn = iova->pfn_hi + 1; |
| 3885 | free_iova_mem(iova); |
| 3886 | } |
| 3887 | break; |
| 3888 | } |
| 3889 | |
| 3890 | return NOTIFY_OK; |
| 3891 | } |
| 3892 | |
| 3893 | static struct notifier_block intel_iommu_memory_nb = { |
| 3894 | .notifier_call = intel_iommu_memory_notifier, |
| 3895 | .priority = 0 |
| 3896 | }; |
| 3897 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3898 | int __init intel_iommu_init(void) |
| 3899 | { |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 3900 | int ret = -ENODEV; |
Takao Indoh | 3a93c84 | 2013-04-23 17:35:03 +0900 | [diff] [blame] | 3901 | struct dmar_drhd_unit *drhd; |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 3902 | struct intel_iommu *iommu; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3903 | |
Joseph Cihula | a59b50e | 2009-06-30 19:31:10 -0700 | [diff] [blame] | 3904 | /* VT-d is required for a TXT/tboot launch, so enforce that */ |
| 3905 | force_on = tboot_force_iommu(); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3906 | |
Jiang Liu | 3a5670e | 2014-02-19 14:07:33 +0800 | [diff] [blame] | 3907 | if (iommu_init_mempool()) { |
| 3908 | if (force_on) |
| 3909 | panic("tboot: Failed to initialize iommu memory\n"); |
| 3910 | return -ENOMEM; |
| 3911 | } |
| 3912 | |
| 3913 | down_write(&dmar_global_lock); |
Joseph Cihula | a59b50e | 2009-06-30 19:31:10 -0700 | [diff] [blame] | 3914 | if (dmar_table_init()) { |
| 3915 | if (force_on) |
| 3916 | panic("tboot: Failed to initialize DMAR table\n"); |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 3917 | goto out_free_dmar; |
Joseph Cihula | a59b50e | 2009-06-30 19:31:10 -0700 | [diff] [blame] | 3918 | } |
| 3919 | |
Takao Indoh | 3a93c84 | 2013-04-23 17:35:03 +0900 | [diff] [blame] | 3920 | /* |
| 3921 | * Disable translation if already enabled prior to OS handover. |
| 3922 | */ |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 3923 | for_each_active_iommu(iommu, drhd) |
Takao Indoh | 3a93c84 | 2013-04-23 17:35:03 +0900 | [diff] [blame] | 3924 | if (iommu->gcmd & DMA_GCMD_TE) |
| 3925 | iommu_disable_translation(iommu); |
Takao Indoh | 3a93c84 | 2013-04-23 17:35:03 +0900 | [diff] [blame] | 3926 | |
Suresh Siddha | c2c7286 | 2011-08-23 17:05:19 -0700 | [diff] [blame] | 3927 | if (dmar_dev_scope_init() < 0) { |
Joseph Cihula | a59b50e | 2009-06-30 19:31:10 -0700 | [diff] [blame] | 3928 | if (force_on) |
| 3929 | panic("tboot: Failed to initialize DMAR device scope\n"); |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 3930 | goto out_free_dmar; |
Joseph Cihula | a59b50e | 2009-06-30 19:31:10 -0700 | [diff] [blame] | 3931 | } |
Suresh Siddha | 1886e8a | 2008-07-10 11:16:37 -0700 | [diff] [blame] | 3932 | |
FUJITA Tomonori | 75f1cdf | 2009-11-10 19:46:20 +0900 | [diff] [blame] | 3933 | if (no_iommu || dmar_disabled) |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 3934 | goto out_free_dmar; |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 3935 | |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3936 | if (list_empty(&dmar_rmrr_units)) |
| 3937 | printk(KERN_INFO "DMAR: No RMRR found\n"); |
| 3938 | |
| 3939 | if (list_empty(&dmar_atsr_units)) |
| 3940 | printk(KERN_INFO "DMAR: No ATSR found\n"); |
| 3941 | |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 3942 | if (dmar_init_reserved_ranges()) { |
| 3943 | if (force_on) |
| 3944 | panic("tboot: Failed to reserve iommu ranges\n"); |
Jiang Liu | 3a5670e | 2014-02-19 14:07:33 +0800 | [diff] [blame] | 3945 | goto out_free_reserved_range; |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 3946 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3947 | |
| 3948 | init_no_remapping_devices(); |
| 3949 | |
Joseph Cihula | b779260 | 2011-05-03 00:08:37 -0700 | [diff] [blame] | 3950 | ret = init_dmars(); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3951 | if (ret) { |
Joseph Cihula | a59b50e | 2009-06-30 19:31:10 -0700 | [diff] [blame] | 3952 | if (force_on) |
| 3953 | panic("tboot: Failed to initialize DMARs\n"); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3954 | printk(KERN_ERR "IOMMU: dmar init failed\n"); |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 3955 | goto out_free_reserved_range; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3956 | } |
Jiang Liu | 3a5670e | 2014-02-19 14:07:33 +0800 | [diff] [blame] | 3957 | up_write(&dmar_global_lock); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3958 | printk(KERN_INFO |
| 3959 | "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n"); |
| 3960 | |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3961 | init_timer(&unmap_timer); |
FUJITA Tomonori | 75f1cdf | 2009-11-10 19:46:20 +0900 | [diff] [blame] | 3962 | #ifdef CONFIG_SWIOTLB |
| 3963 | swiotlb = 0; |
| 3964 | #endif |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 3965 | dma_ops = &intel_dma_ops; |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 3966 | |
Rafael J. Wysocki | 134fac3 | 2011-03-23 22:16:14 +0100 | [diff] [blame] | 3967 | init_iommu_pm_ops(); |
Joerg Roedel | a8bcbb0d | 2008-12-03 15:14:02 +0100 | [diff] [blame] | 3968 | |
Joerg Roedel | 4236d97d | 2011-09-06 17:56:07 +0200 | [diff] [blame] | 3969 | bus_set_iommu(&pci_bus_type, &intel_iommu_ops); |
Fenghua Yu | 99dcade | 2009-11-11 07:23:06 -0800 | [diff] [blame] | 3970 | bus_register_notifier(&pci_bus_type, &device_nb); |
Jiang Liu | 75f0556 | 2014-02-19 14:07:37 +0800 | [diff] [blame] | 3971 | if (si_domain && !hw_pass_through) |
| 3972 | register_memory_notifier(&intel_iommu_memory_nb); |
Fenghua Yu | 99dcade | 2009-11-11 07:23:06 -0800 | [diff] [blame] | 3973 | |
Eugeni Dodonov | 8bc1f85 | 2011-11-23 16:42:14 -0200 | [diff] [blame] | 3974 | intel_iommu_enabled = 1; |
| 3975 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3976 | return 0; |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 3977 | |
| 3978 | out_free_reserved_range: |
| 3979 | put_iova_domain(&reserved_iova_list); |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 3980 | out_free_dmar: |
| 3981 | intel_iommu_free_dmars(); |
Jiang Liu | 3a5670e | 2014-02-19 14:07:33 +0800 | [diff] [blame] | 3982 | up_write(&dmar_global_lock); |
| 3983 | iommu_exit_mempool(); |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 3984 | return ret; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3985 | } |
Keshavamurthy, Anil S | e820482 | 2007-10-21 16:41:55 -0700 | [diff] [blame] | 3986 | |
Han, Weidong | 3199aa6 | 2009-02-26 17:31:12 +0800 | [diff] [blame] | 3987 | static void iommu_detach_dependent_devices(struct intel_iommu *iommu, |
| 3988 | struct pci_dev *pdev) |
| 3989 | { |
| 3990 | struct pci_dev *tmp, *parent; |
| 3991 | |
| 3992 | if (!iommu || !pdev) |
| 3993 | return; |
| 3994 | |
| 3995 | /* dependent device detach */ |
| 3996 | tmp = pci_find_upstream_pcie_bridge(pdev); |
| 3997 | /* Secondary interface's bus number and devfn 0 */ |
| 3998 | if (tmp) { |
| 3999 | parent = pdev->bus->self; |
| 4000 | while (parent != tmp) { |
| 4001 | iommu_detach_dev(iommu, parent->bus->number, |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 4002 | parent->devfn); |
Han, Weidong | 3199aa6 | 2009-02-26 17:31:12 +0800 | [diff] [blame] | 4003 | parent = parent->bus->self; |
| 4004 | } |
Stefan Assmann | 45e829e | 2009-12-03 06:49:24 -0500 | [diff] [blame] | 4005 | if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */ |
Han, Weidong | 3199aa6 | 2009-02-26 17:31:12 +0800 | [diff] [blame] | 4006 | iommu_detach_dev(iommu, |
| 4007 | tmp->subordinate->number, 0); |
| 4008 | else /* this is a legacy PCI bridge */ |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 4009 | iommu_detach_dev(iommu, tmp->bus->number, |
| 4010 | tmp->devfn); |
Han, Weidong | 3199aa6 | 2009-02-26 17:31:12 +0800 | [diff] [blame] | 4011 | } |
| 4012 | } |
| 4013 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 4014 | static void domain_remove_one_dev_info(struct dmar_domain *domain, |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4015 | struct pci_dev *pdev) |
| 4016 | { |
Yijing Wang | bca2b91 | 2013-10-31 17:26:04 +0800 | [diff] [blame] | 4017 | struct device_domain_info *info, *tmp; |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4018 | struct intel_iommu *iommu; |
| 4019 | unsigned long flags; |
| 4020 | int found = 0; |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4021 | |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 4022 | iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number, |
| 4023 | pdev->devfn); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4024 | if (!iommu) |
| 4025 | return; |
| 4026 | |
| 4027 | spin_lock_irqsave(&device_domain_lock, flags); |
Yijing Wang | bca2b91 | 2013-10-31 17:26:04 +0800 | [diff] [blame] | 4028 | list_for_each_entry_safe(info, tmp, &domain->devices, link) { |
Mike Habeck | 8519dc4 | 2011-05-28 13:15:07 -0500 | [diff] [blame] | 4029 | if (info->segment == pci_domain_nr(pdev->bus) && |
| 4030 | info->bus == pdev->bus->number && |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4031 | info->devfn == pdev->devfn) { |
David Woodhouse | 109b9b0 | 2012-05-25 17:43:02 +0100 | [diff] [blame] | 4032 | unlink_domain_info(info); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4033 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 4034 | |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 4035 | iommu_disable_dev_iotlb(info); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4036 | iommu_detach_dev(iommu, info->bus, info->devfn); |
Han, Weidong | 3199aa6 | 2009-02-26 17:31:12 +0800 | [diff] [blame] | 4037 | iommu_detach_dependent_devices(iommu, pdev); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4038 | free_devinfo_mem(info); |
| 4039 | |
| 4040 | spin_lock_irqsave(&device_domain_lock, flags); |
| 4041 | |
| 4042 | if (found) |
| 4043 | break; |
| 4044 | else |
| 4045 | continue; |
| 4046 | } |
| 4047 | |
| 4048 | /* if there is no other devices under the same iommu |
| 4049 | * owned by this domain, clear this iommu in iommu_bmp |
| 4050 | * update iommu count and coherency |
| 4051 | */ |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 4052 | if (iommu == device_to_iommu(info->segment, info->bus, |
| 4053 | info->devfn)) |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4054 | found = 1; |
| 4055 | } |
| 4056 | |
Roland Dreier | 3e7abe2 | 2011-07-20 06:22:21 -0700 | [diff] [blame] | 4057 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 4058 | |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4059 | if (found == 0) { |
| 4060 | unsigned long tmp_flags; |
| 4061 | spin_lock_irqsave(&domain->iommu_lock, tmp_flags); |
Mike Travis | 1b198bb | 2012-03-05 15:05:16 -0800 | [diff] [blame] | 4062 | clear_bit(iommu->seq_id, domain->iommu_bmp); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4063 | domain->iommu_count--; |
Sheng Yang | 58c610b | 2009-03-18 15:33:05 +0800 | [diff] [blame] | 4064 | domain_update_iommu_cap(domain); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4065 | spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags); |
Alex Williamson | a97590e | 2011-03-04 14:52:16 -0700 | [diff] [blame] | 4066 | |
Alex Williamson | 9b4554b | 2011-05-24 12:19:04 -0400 | [diff] [blame] | 4067 | if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) && |
| 4068 | !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)) { |
| 4069 | spin_lock_irqsave(&iommu->lock, tmp_flags); |
| 4070 | clear_bit(domain->id, iommu->domain_ids); |
| 4071 | iommu->domains[domain->id] = NULL; |
| 4072 | spin_unlock_irqrestore(&iommu->lock, tmp_flags); |
| 4073 | } |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4074 | } |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4075 | } |
| 4076 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 4077 | static int md_domain_init(struct dmar_domain *domain, int guest_width) |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 4078 | { |
| 4079 | int adjust_width; |
| 4080 | |
| 4081 | init_iova_domain(&domain->iovad, DMA_32BIT_PFN); |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 4082 | domain_reserve_special_ranges(domain); |
| 4083 | |
| 4084 | /* calculate AGAW */ |
| 4085 | domain->gaw = guest_width; |
| 4086 | adjust_width = guestwidth_to_adjustwidth(guest_width); |
| 4087 | domain->agaw = width_to_agaw(adjust_width); |
| 4088 | |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 4089 | domain->iommu_coherency = 0; |
Sheng Yang | c5b1525 | 2009-08-06 13:31:56 +0800 | [diff] [blame] | 4090 | domain->iommu_snooping = 0; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 4091 | domain->iommu_superpage = 0; |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4092 | domain->max_addr = 0; |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 4093 | domain->nid = -1; |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 4094 | |
| 4095 | /* always allocate the top pgd */ |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 4096 | domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid); |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 4097 | if (!domain->pgd) |
| 4098 | return -ENOMEM; |
| 4099 | domain_flush_cache(domain, domain->pgd, PAGE_SIZE); |
| 4100 | return 0; |
| 4101 | } |
| 4102 | |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 4103 | static int intel_iommu_domain_init(struct iommu_domain *domain) |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4104 | { |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 4105 | struct dmar_domain *dmar_domain; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4106 | |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 4107 | dmar_domain = alloc_domain(true); |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 4108 | if (!dmar_domain) { |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4109 | printk(KERN_ERR |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 4110 | "intel_iommu_domain_init: dmar_domain == NULL\n"); |
| 4111 | return -ENOMEM; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4112 | } |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 4113 | if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4114 | printk(KERN_ERR |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 4115 | "intel_iommu_domain_init() failed\n"); |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 4116 | domain_exit(dmar_domain); |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 4117 | return -ENOMEM; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4118 | } |
Allen Kay | 8140a95 | 2011-10-14 12:32:17 -0700 | [diff] [blame] | 4119 | domain_update_iommu_cap(dmar_domain); |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 4120 | domain->priv = dmar_domain; |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4121 | |
Joerg Roedel | 8a0e715 | 2012-01-26 19:40:54 +0100 | [diff] [blame] | 4122 | domain->geometry.aperture_start = 0; |
| 4123 | domain->geometry.aperture_end = __DOMAIN_MAX_ADDR(dmar_domain->gaw); |
| 4124 | domain->geometry.force_aperture = true; |
| 4125 | |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 4126 | return 0; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4127 | } |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4128 | |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 4129 | static void intel_iommu_domain_destroy(struct iommu_domain *domain) |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4130 | { |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 4131 | struct dmar_domain *dmar_domain = domain->priv; |
| 4132 | |
| 4133 | domain->priv = NULL; |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 4134 | domain_exit(dmar_domain); |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4135 | } |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4136 | |
Joerg Roedel | 4c5478c | 2008-12-03 14:58:24 +0100 | [diff] [blame] | 4137 | static int intel_iommu_attach_device(struct iommu_domain *domain, |
| 4138 | struct device *dev) |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4139 | { |
Joerg Roedel | 4c5478c | 2008-12-03 14:58:24 +0100 | [diff] [blame] | 4140 | struct dmar_domain *dmar_domain = domain->priv; |
| 4141 | struct pci_dev *pdev = to_pci_dev(dev); |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4142 | struct intel_iommu *iommu; |
| 4143 | int addr_width; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4144 | |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4145 | /* normally pdev is not mapped */ |
| 4146 | if (unlikely(domain_context_mapped(pdev))) { |
| 4147 | struct dmar_domain *old_domain; |
| 4148 | |
David Woodhouse | 1525a29 | 2014-03-06 16:19:30 +0000 | [diff] [blame^] | 4149 | old_domain = find_domain(dev); |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4150 | if (old_domain) { |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 4151 | if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE || |
| 4152 | dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) |
| 4153 | domain_remove_one_dev_info(old_domain, pdev); |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4154 | else |
| 4155 | domain_remove_dev_info(old_domain); |
| 4156 | } |
| 4157 | } |
| 4158 | |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 4159 | iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number, |
| 4160 | pdev->devfn); |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4161 | if (!iommu) |
| 4162 | return -ENODEV; |
| 4163 | |
| 4164 | /* check if this iommu agaw is sufficient for max mapped address */ |
| 4165 | addr_width = agaw_to_width(iommu->agaw); |
Tom Lyon | a99c47a | 2010-05-17 08:20:45 +0100 | [diff] [blame] | 4166 | if (addr_width > cap_mgaw(iommu->cap)) |
| 4167 | addr_width = cap_mgaw(iommu->cap); |
| 4168 | |
| 4169 | if (dmar_domain->max_addr > (1LL << addr_width)) { |
| 4170 | printk(KERN_ERR "%s: iommu width (%d) is not " |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4171 | "sufficient for the mapped address (%llx)\n", |
Tom Lyon | a99c47a | 2010-05-17 08:20:45 +0100 | [diff] [blame] | 4172 | __func__, addr_width, dmar_domain->max_addr); |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4173 | return -EFAULT; |
| 4174 | } |
Tom Lyon | a99c47a | 2010-05-17 08:20:45 +0100 | [diff] [blame] | 4175 | dmar_domain->gaw = addr_width; |
| 4176 | |
| 4177 | /* |
| 4178 | * Knock out extra levels of page tables if necessary |
| 4179 | */ |
| 4180 | while (iommu->agaw < dmar_domain->agaw) { |
| 4181 | struct dma_pte *pte; |
| 4182 | |
| 4183 | pte = dmar_domain->pgd; |
| 4184 | if (dma_pte_present(pte)) { |
Sheng Yang | 25cbff1 | 2010-06-12 19:21:42 +0800 | [diff] [blame] | 4185 | dmar_domain->pgd = (struct dma_pte *) |
| 4186 | phys_to_virt(dma_pte_addr(pte)); |
Jan Kiszka | 7a66101 | 2010-11-02 08:05:51 +0100 | [diff] [blame] | 4187 | free_pgtable_page(pte); |
Tom Lyon | a99c47a | 2010-05-17 08:20:45 +0100 | [diff] [blame] | 4188 | } |
| 4189 | dmar_domain->agaw--; |
| 4190 | } |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4191 | |
David Woodhouse | 5fe60f4 | 2009-08-09 10:53:41 +0100 | [diff] [blame] | 4192 | return domain_add_dev_info(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL); |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4193 | } |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4194 | |
Joerg Roedel | 4c5478c | 2008-12-03 14:58:24 +0100 | [diff] [blame] | 4195 | static void intel_iommu_detach_device(struct iommu_domain *domain, |
| 4196 | struct device *dev) |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4197 | { |
Joerg Roedel | 4c5478c | 2008-12-03 14:58:24 +0100 | [diff] [blame] | 4198 | struct dmar_domain *dmar_domain = domain->priv; |
| 4199 | struct pci_dev *pdev = to_pci_dev(dev); |
| 4200 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 4201 | domain_remove_one_dev_info(dmar_domain, pdev); |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4202 | } |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4203 | |
Joerg Roedel | b146a1c9f | 2010-01-20 17:17:37 +0100 | [diff] [blame] | 4204 | static int intel_iommu_map(struct iommu_domain *domain, |
| 4205 | unsigned long iova, phys_addr_t hpa, |
Ohad Ben-Cohen | 5009065 | 2011-11-10 11:32:25 +0200 | [diff] [blame] | 4206 | size_t size, int iommu_prot) |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4207 | { |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 4208 | struct dmar_domain *dmar_domain = domain->priv; |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4209 | u64 max_addr; |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 4210 | int prot = 0; |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4211 | int ret; |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4212 | |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 4213 | if (iommu_prot & IOMMU_READ) |
| 4214 | prot |= DMA_PTE_READ; |
| 4215 | if (iommu_prot & IOMMU_WRITE) |
| 4216 | prot |= DMA_PTE_WRITE; |
Sheng Yang | 9cf06697 | 2009-03-18 15:33:07 +0800 | [diff] [blame] | 4217 | if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping) |
| 4218 | prot |= DMA_PTE_SNP; |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 4219 | |
David Woodhouse | 163cc52 | 2009-06-28 00:51:17 +0100 | [diff] [blame] | 4220 | max_addr = iova + size; |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 4221 | if (dmar_domain->max_addr < max_addr) { |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4222 | u64 end; |
| 4223 | |
| 4224 | /* check if minimum agaw is sufficient for mapped address */ |
Tom Lyon | 8954da1 | 2010-05-17 08:19:52 +0100 | [diff] [blame] | 4225 | end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1; |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4226 | if (end < max_addr) { |
Tom Lyon | 8954da1 | 2010-05-17 08:19:52 +0100 | [diff] [blame] | 4227 | printk(KERN_ERR "%s: iommu width (%d) is not " |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4228 | "sufficient for the mapped address (%llx)\n", |
Tom Lyon | 8954da1 | 2010-05-17 08:19:52 +0100 | [diff] [blame] | 4229 | __func__, dmar_domain->gaw, max_addr); |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4230 | return -EFAULT; |
| 4231 | } |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 4232 | dmar_domain->max_addr = max_addr; |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4233 | } |
David Woodhouse | ad05122 | 2009-06-28 14:22:28 +0100 | [diff] [blame] | 4234 | /* Round up size to next multiple of PAGE_SIZE, if it and |
| 4235 | the low bits of hpa would take us onto the next page */ |
David Woodhouse | 88cb6a7 | 2009-06-28 15:03:06 +0100 | [diff] [blame] | 4236 | size = aligned_nrpages(hpa, size); |
David Woodhouse | ad05122 | 2009-06-28 14:22:28 +0100 | [diff] [blame] | 4237 | ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT, |
| 4238 | hpa >> VTD_PAGE_SHIFT, size, prot); |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4239 | return ret; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4240 | } |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4241 | |
Ohad Ben-Cohen | 5009065 | 2011-11-10 11:32:25 +0200 | [diff] [blame] | 4242 | static size_t intel_iommu_unmap(struct iommu_domain *domain, |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 4243 | unsigned long iova, size_t size) |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4244 | { |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 4245 | struct dmar_domain *dmar_domain = domain->priv; |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 4246 | struct page *freelist = NULL; |
| 4247 | struct intel_iommu *iommu; |
| 4248 | unsigned long start_pfn, last_pfn; |
| 4249 | unsigned int npages; |
| 4250 | int iommu_id, num, ndomains, level = 0; |
Sheng Yang | 4b99d35 | 2009-07-08 11:52:52 +0100 | [diff] [blame] | 4251 | |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 4252 | /* Cope with horrid API which requires us to unmap more than the |
| 4253 | size argument if it happens to be a large-page mapping. */ |
| 4254 | if (!pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level)) |
| 4255 | BUG(); |
| 4256 | |
| 4257 | if (size < VTD_PAGE_SIZE << level_to_offset_bits(level)) |
| 4258 | size = VTD_PAGE_SIZE << level_to_offset_bits(level); |
| 4259 | |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 4260 | start_pfn = iova >> VTD_PAGE_SHIFT; |
| 4261 | last_pfn = (iova + size - 1) >> VTD_PAGE_SHIFT; |
| 4262 | |
| 4263 | freelist = domain_unmap(dmar_domain, start_pfn, last_pfn); |
| 4264 | |
| 4265 | npages = last_pfn - start_pfn + 1; |
| 4266 | |
| 4267 | for_each_set_bit(iommu_id, dmar_domain->iommu_bmp, g_num_of_iommus) { |
| 4268 | iommu = g_iommus[iommu_id]; |
| 4269 | |
| 4270 | /* |
| 4271 | * find bit position of dmar_domain |
| 4272 | */ |
| 4273 | ndomains = cap_ndoms(iommu->cap); |
| 4274 | for_each_set_bit(num, iommu->domain_ids, ndomains) { |
| 4275 | if (iommu->domains[num] == dmar_domain) |
| 4276 | iommu_flush_iotlb_psi(iommu, num, start_pfn, |
| 4277 | npages, !freelist, 0); |
| 4278 | } |
| 4279 | |
| 4280 | } |
| 4281 | |
| 4282 | dma_free_pagelist(freelist); |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4283 | |
David Woodhouse | 163cc52 | 2009-06-28 00:51:17 +0100 | [diff] [blame] | 4284 | if (dmar_domain->max_addr == iova + size) |
| 4285 | dmar_domain->max_addr = iova; |
Joerg Roedel | b146a1c9f | 2010-01-20 17:17:37 +0100 | [diff] [blame] | 4286 | |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 4287 | return size; |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4288 | } |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4289 | |
Joerg Roedel | d14d657 | 2008-12-03 15:06:57 +0100 | [diff] [blame] | 4290 | static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain, |
Varun Sethi | bb5547ac | 2013-03-29 01:23:58 +0530 | [diff] [blame] | 4291 | dma_addr_t iova) |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4292 | { |
Joerg Roedel | d14d657 | 2008-12-03 15:06:57 +0100 | [diff] [blame] | 4293 | struct dmar_domain *dmar_domain = domain->priv; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4294 | struct dma_pte *pte; |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 4295 | int level = 0; |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4296 | u64 phys = 0; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4297 | |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 4298 | pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level); |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4299 | if (pte) |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4300 | phys = dma_pte_addr(pte); |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4301 | |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4302 | return phys; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4303 | } |
Joerg Roedel | a8bcbb0d | 2008-12-03 15:14:02 +0100 | [diff] [blame] | 4304 | |
Sheng Yang | dbb9fd8 | 2009-03-18 15:33:06 +0800 | [diff] [blame] | 4305 | static int intel_iommu_domain_has_cap(struct iommu_domain *domain, |
| 4306 | unsigned long cap) |
| 4307 | { |
| 4308 | struct dmar_domain *dmar_domain = domain->priv; |
| 4309 | |
| 4310 | if (cap == IOMMU_CAP_CACHE_COHERENCY) |
| 4311 | return dmar_domain->iommu_snooping; |
Tom Lyon | 323f99c | 2010-07-02 16:56:14 -0400 | [diff] [blame] | 4312 | if (cap == IOMMU_CAP_INTR_REMAP) |
Suresh Siddha | 95a02e9 | 2012-03-30 11:47:07 -0700 | [diff] [blame] | 4313 | return irq_remapping_enabled; |
Sheng Yang | dbb9fd8 | 2009-03-18 15:33:06 +0800 | [diff] [blame] | 4314 | |
| 4315 | return 0; |
| 4316 | } |
| 4317 | |
Alex Williamson | 783f157 | 2012-05-30 14:19:43 -0600 | [diff] [blame] | 4318 | #define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF) |
| 4319 | |
Alex Williamson | abdfdde | 2012-05-30 14:19:19 -0600 | [diff] [blame] | 4320 | static int intel_iommu_add_device(struct device *dev) |
Alex Williamson | 70ae6f0 | 2011-10-21 15:56:11 -0400 | [diff] [blame] | 4321 | { |
| 4322 | struct pci_dev *pdev = to_pci_dev(dev); |
Alex Williamson | 3da4af0a | 2012-11-13 10:22:03 -0700 | [diff] [blame] | 4323 | struct pci_dev *bridge, *dma_pdev = NULL; |
Alex Williamson | abdfdde | 2012-05-30 14:19:19 -0600 | [diff] [blame] | 4324 | struct iommu_group *group; |
| 4325 | int ret; |
Alex Williamson | 70ae6f0 | 2011-10-21 15:56:11 -0400 | [diff] [blame] | 4326 | |
Alex Williamson | abdfdde | 2012-05-30 14:19:19 -0600 | [diff] [blame] | 4327 | if (!device_to_iommu(pci_domain_nr(pdev->bus), |
| 4328 | pdev->bus->number, pdev->devfn)) |
Alex Williamson | 70ae6f0 | 2011-10-21 15:56:11 -0400 | [diff] [blame] | 4329 | return -ENODEV; |
| 4330 | |
| 4331 | bridge = pci_find_upstream_pcie_bridge(pdev); |
| 4332 | if (bridge) { |
Alex Williamson | abdfdde | 2012-05-30 14:19:19 -0600 | [diff] [blame] | 4333 | if (pci_is_pcie(bridge)) |
| 4334 | dma_pdev = pci_get_domain_bus_and_slot( |
| 4335 | pci_domain_nr(pdev->bus), |
| 4336 | bridge->subordinate->number, 0); |
Alex Williamson | 3da4af0a | 2012-11-13 10:22:03 -0700 | [diff] [blame] | 4337 | if (!dma_pdev) |
Alex Williamson | abdfdde | 2012-05-30 14:19:19 -0600 | [diff] [blame] | 4338 | dma_pdev = pci_dev_get(bridge); |
| 4339 | } else |
| 4340 | dma_pdev = pci_dev_get(pdev); |
| 4341 | |
Alex Williamson | a4ff1fc | 2012-08-04 12:08:55 -0600 | [diff] [blame] | 4342 | /* Account for quirked devices */ |
Alex Williamson | 783f157 | 2012-05-30 14:19:43 -0600 | [diff] [blame] | 4343 | swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev)); |
| 4344 | |
Alex Williamson | a4ff1fc | 2012-08-04 12:08:55 -0600 | [diff] [blame] | 4345 | /* |
| 4346 | * If it's a multifunction device that does not support our |
Alex Williamson | c14d269 | 2013-05-30 12:39:18 -0600 | [diff] [blame] | 4347 | * required ACS flags, add to the same group as lowest numbered |
| 4348 | * function that also does not suport the required ACS flags. |
Alex Williamson | a4ff1fc | 2012-08-04 12:08:55 -0600 | [diff] [blame] | 4349 | */ |
Alex Williamson | 783f157 | 2012-05-30 14:19:43 -0600 | [diff] [blame] | 4350 | if (dma_pdev->multifunction && |
Alex Williamson | c14d269 | 2013-05-30 12:39:18 -0600 | [diff] [blame] | 4351 | !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS)) { |
| 4352 | u8 i, slot = PCI_SLOT(dma_pdev->devfn); |
| 4353 | |
| 4354 | for (i = 0; i < 8; i++) { |
| 4355 | struct pci_dev *tmp; |
| 4356 | |
| 4357 | tmp = pci_get_slot(dma_pdev->bus, PCI_DEVFN(slot, i)); |
| 4358 | if (!tmp) |
| 4359 | continue; |
| 4360 | |
| 4361 | if (!pci_acs_enabled(tmp, REQ_ACS_FLAGS)) { |
| 4362 | swap_pci_ref(&dma_pdev, tmp); |
| 4363 | break; |
| 4364 | } |
| 4365 | pci_dev_put(tmp); |
| 4366 | } |
| 4367 | } |
Alex Williamson | 783f157 | 2012-05-30 14:19:43 -0600 | [diff] [blame] | 4368 | |
Alex Williamson | a4ff1fc | 2012-08-04 12:08:55 -0600 | [diff] [blame] | 4369 | /* |
| 4370 | * Devices on the root bus go through the iommu. If that's not us, |
| 4371 | * find the next upstream device and test ACS up to the root bus. |
| 4372 | * Finding the next device may require skipping virtual buses. |
| 4373 | */ |
Alex Williamson | 783f157 | 2012-05-30 14:19:43 -0600 | [diff] [blame] | 4374 | while (!pci_is_root_bus(dma_pdev->bus)) { |
Alex Williamson | a4ff1fc | 2012-08-04 12:08:55 -0600 | [diff] [blame] | 4375 | struct pci_bus *bus = dma_pdev->bus; |
| 4376 | |
| 4377 | while (!bus->self) { |
| 4378 | if (!pci_is_root_bus(bus)) |
| 4379 | bus = bus->parent; |
| 4380 | else |
| 4381 | goto root_bus; |
| 4382 | } |
| 4383 | |
| 4384 | if (pci_acs_path_enabled(bus->self, NULL, REQ_ACS_FLAGS)) |
Alex Williamson | 783f157 | 2012-05-30 14:19:43 -0600 | [diff] [blame] | 4385 | break; |
| 4386 | |
Alex Williamson | a4ff1fc | 2012-08-04 12:08:55 -0600 | [diff] [blame] | 4387 | swap_pci_ref(&dma_pdev, pci_dev_get(bus->self)); |
Alex Williamson | 70ae6f0 | 2011-10-21 15:56:11 -0400 | [diff] [blame] | 4388 | } |
| 4389 | |
Alex Williamson | a4ff1fc | 2012-08-04 12:08:55 -0600 | [diff] [blame] | 4390 | root_bus: |
Alex Williamson | abdfdde | 2012-05-30 14:19:19 -0600 | [diff] [blame] | 4391 | group = iommu_group_get(&dma_pdev->dev); |
| 4392 | pci_dev_put(dma_pdev); |
| 4393 | if (!group) { |
| 4394 | group = iommu_group_alloc(); |
| 4395 | if (IS_ERR(group)) |
| 4396 | return PTR_ERR(group); |
| 4397 | } |
Alex Williamson | bcb71ab | 2011-10-21 15:56:24 -0400 | [diff] [blame] | 4398 | |
Alex Williamson | abdfdde | 2012-05-30 14:19:19 -0600 | [diff] [blame] | 4399 | ret = iommu_group_add_device(group, dev); |
Alex Williamson | 70ae6f0 | 2011-10-21 15:56:11 -0400 | [diff] [blame] | 4400 | |
Alex Williamson | abdfdde | 2012-05-30 14:19:19 -0600 | [diff] [blame] | 4401 | iommu_group_put(group); |
| 4402 | return ret; |
| 4403 | } |
| 4404 | |
| 4405 | static void intel_iommu_remove_device(struct device *dev) |
| 4406 | { |
| 4407 | iommu_group_remove_device(dev); |
Alex Williamson | 70ae6f0 | 2011-10-21 15:56:11 -0400 | [diff] [blame] | 4408 | } |
| 4409 | |
Joerg Roedel | a8bcbb0d | 2008-12-03 15:14:02 +0100 | [diff] [blame] | 4410 | static struct iommu_ops intel_iommu_ops = { |
| 4411 | .domain_init = intel_iommu_domain_init, |
| 4412 | .domain_destroy = intel_iommu_domain_destroy, |
| 4413 | .attach_dev = intel_iommu_attach_device, |
| 4414 | .detach_dev = intel_iommu_detach_device, |
Joerg Roedel | b146a1c9f | 2010-01-20 17:17:37 +0100 | [diff] [blame] | 4415 | .map = intel_iommu_map, |
| 4416 | .unmap = intel_iommu_unmap, |
Joerg Roedel | a8bcbb0d | 2008-12-03 15:14:02 +0100 | [diff] [blame] | 4417 | .iova_to_phys = intel_iommu_iova_to_phys, |
Sheng Yang | dbb9fd8 | 2009-03-18 15:33:06 +0800 | [diff] [blame] | 4418 | .domain_has_cap = intel_iommu_domain_has_cap, |
Alex Williamson | abdfdde | 2012-05-30 14:19:19 -0600 | [diff] [blame] | 4419 | .add_device = intel_iommu_add_device, |
| 4420 | .remove_device = intel_iommu_remove_device, |
Ohad Ben-Cohen | 6d1c56a | 2011-11-10 11:32:30 +0200 | [diff] [blame] | 4421 | .pgsize_bitmap = INTEL_IOMMU_PGSIZES, |
Joerg Roedel | a8bcbb0d | 2008-12-03 15:14:02 +0100 | [diff] [blame] | 4422 | }; |
David Woodhouse | 9af8814 | 2009-02-13 23:18:03 +0000 | [diff] [blame] | 4423 | |
Daniel Vetter | 9452618 | 2013-01-20 23:50:13 +0100 | [diff] [blame] | 4424 | static void quirk_iommu_g4x_gfx(struct pci_dev *dev) |
| 4425 | { |
| 4426 | /* G4x/GM45 integrated gfx dmar support is totally busted. */ |
| 4427 | printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n"); |
| 4428 | dmar_map_gfx = 0; |
| 4429 | } |
| 4430 | |
| 4431 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx); |
| 4432 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx); |
| 4433 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx); |
| 4434 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx); |
| 4435 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx); |
| 4436 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx); |
| 4437 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx); |
| 4438 | |
Greg Kroah-Hartman | d34d651 | 2012-12-21 15:05:21 -0800 | [diff] [blame] | 4439 | static void quirk_iommu_rwbf(struct pci_dev *dev) |
David Woodhouse | 9af8814 | 2009-02-13 23:18:03 +0000 | [diff] [blame] | 4440 | { |
| 4441 | /* |
| 4442 | * Mobile 4 Series Chipset neglects to set RWBF capability, |
Daniel Vetter | 210561f | 2013-01-21 19:48:59 +0100 | [diff] [blame] | 4443 | * but needs it. Same seems to hold for the desktop versions. |
David Woodhouse | 9af8814 | 2009-02-13 23:18:03 +0000 | [diff] [blame] | 4444 | */ |
| 4445 | printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n"); |
| 4446 | rwbf_quirk = 1; |
| 4447 | } |
| 4448 | |
| 4449 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf); |
Daniel Vetter | 210561f | 2013-01-21 19:48:59 +0100 | [diff] [blame] | 4450 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf); |
| 4451 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf); |
| 4452 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf); |
| 4453 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf); |
| 4454 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf); |
| 4455 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf); |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 4456 | |
Adam Jackson | eecfd57 | 2010-08-25 21:17:34 +0100 | [diff] [blame] | 4457 | #define GGC 0x52 |
| 4458 | #define GGC_MEMORY_SIZE_MASK (0xf << 8) |
| 4459 | #define GGC_MEMORY_SIZE_NONE (0x0 << 8) |
| 4460 | #define GGC_MEMORY_SIZE_1M (0x1 << 8) |
| 4461 | #define GGC_MEMORY_SIZE_2M (0x3 << 8) |
| 4462 | #define GGC_MEMORY_VT_ENABLED (0x8 << 8) |
| 4463 | #define GGC_MEMORY_SIZE_2M_VT (0x9 << 8) |
| 4464 | #define GGC_MEMORY_SIZE_3M_VT (0xa << 8) |
| 4465 | #define GGC_MEMORY_SIZE_4M_VT (0xb << 8) |
| 4466 | |
Greg Kroah-Hartman | d34d651 | 2012-12-21 15:05:21 -0800 | [diff] [blame] | 4467 | static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev) |
David Woodhouse | 9eecabc | 2010-09-21 22:28:23 +0100 | [diff] [blame] | 4468 | { |
| 4469 | unsigned short ggc; |
| 4470 | |
Adam Jackson | eecfd57 | 2010-08-25 21:17:34 +0100 | [diff] [blame] | 4471 | if (pci_read_config_word(dev, GGC, &ggc)) |
David Woodhouse | 9eecabc | 2010-09-21 22:28:23 +0100 | [diff] [blame] | 4472 | return; |
| 4473 | |
Adam Jackson | eecfd57 | 2010-08-25 21:17:34 +0100 | [diff] [blame] | 4474 | if (!(ggc & GGC_MEMORY_VT_ENABLED)) { |
David Woodhouse | 9eecabc | 2010-09-21 22:28:23 +0100 | [diff] [blame] | 4475 | printk(KERN_INFO "DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n"); |
| 4476 | dmar_map_gfx = 0; |
David Woodhouse | 6fbcfb3 | 2011-09-25 19:11:14 -0700 | [diff] [blame] | 4477 | } else if (dmar_map_gfx) { |
| 4478 | /* we have to ensure the gfx device is idle before we flush */ |
| 4479 | printk(KERN_INFO "DMAR: Disabling batched IOTLB flush on Ironlake\n"); |
| 4480 | intel_iommu_strict = 1; |
| 4481 | } |
David Woodhouse | 9eecabc | 2010-09-21 22:28:23 +0100 | [diff] [blame] | 4482 | } |
| 4483 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt); |
| 4484 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt); |
| 4485 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt); |
| 4486 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt); |
| 4487 | |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 4488 | /* On Tylersburg chipsets, some BIOSes have been known to enable the |
| 4489 | ISOCH DMAR unit for the Azalia sound device, but not give it any |
| 4490 | TLB entries, which causes it to deadlock. Check for that. We do |
| 4491 | this in a function called from init_dmars(), instead of in a PCI |
| 4492 | quirk, because we don't want to print the obnoxious "BIOS broken" |
| 4493 | message if VT-d is actually disabled. |
| 4494 | */ |
| 4495 | static void __init check_tylersburg_isoch(void) |
| 4496 | { |
| 4497 | struct pci_dev *pdev; |
| 4498 | uint32_t vtisochctrl; |
| 4499 | |
| 4500 | /* If there's no Azalia in the system anyway, forget it. */ |
| 4501 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL); |
| 4502 | if (!pdev) |
| 4503 | return; |
| 4504 | pci_dev_put(pdev); |
| 4505 | |
| 4506 | /* System Management Registers. Might be hidden, in which case |
| 4507 | we can't do the sanity check. But that's OK, because the |
| 4508 | known-broken BIOSes _don't_ actually hide it, so far. */ |
| 4509 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL); |
| 4510 | if (!pdev) |
| 4511 | return; |
| 4512 | |
| 4513 | if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) { |
| 4514 | pci_dev_put(pdev); |
| 4515 | return; |
| 4516 | } |
| 4517 | |
| 4518 | pci_dev_put(pdev); |
| 4519 | |
| 4520 | /* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */ |
| 4521 | if (vtisochctrl & 1) |
| 4522 | return; |
| 4523 | |
| 4524 | /* Drop all bits other than the number of TLB entries */ |
| 4525 | vtisochctrl &= 0x1c; |
| 4526 | |
| 4527 | /* If we have the recommended number of TLB entries (16), fine. */ |
| 4528 | if (vtisochctrl == 0x10) |
| 4529 | return; |
| 4530 | |
| 4531 | /* Zero TLB entries? You get to ride the short bus to school. */ |
| 4532 | if (!vtisochctrl) { |
| 4533 | WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n" |
| 4534 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", |
| 4535 | dmi_get_system_info(DMI_BIOS_VENDOR), |
| 4536 | dmi_get_system_info(DMI_BIOS_VERSION), |
| 4537 | dmi_get_system_info(DMI_PRODUCT_VERSION)); |
| 4538 | iommu_identity_mapping |= IDENTMAP_AZALIA; |
| 4539 | return; |
| 4540 | } |
| 4541 | |
| 4542 | printk(KERN_WARNING "DMAR: Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n", |
| 4543 | vtisochctrl); |
| 4544 | } |