Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 1 | #include <dt-bindings/clock/tegra114-car.h> |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 2 | #include <dt-bindings/gpio/tegra-gpio.h> |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 3 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 4 | |
Stephen Warren | 1bd0bd4 | 2012-10-17 16:38:21 -0600 | [diff] [blame] | 5 | #include "skeleton.dtsi" |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 6 | |
| 7 | / { |
| 8 | compatible = "nvidia,tegra114"; |
| 9 | interrupt-parent = <&gic>; |
| 10 | |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 11 | aliases { |
| 12 | serial0 = &uarta; |
| 13 | serial1 = &uartb; |
| 14 | serial2 = &uartc; |
| 15 | serial3 = &uartd; |
| 16 | }; |
| 17 | |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 18 | gic: interrupt-controller { |
| 19 | compatible = "arm,cortex-a15-gic"; |
| 20 | #interrupt-cells = <3>; |
| 21 | interrupt-controller; |
| 22 | reg = <0x50041000 0x1000>, |
| 23 | <0x50042000 0x1000>, |
| 24 | <0x50044000 0x2000>, |
| 25 | <0x50046000 0x2000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 26 | interrupts = <GIC_PPI 9 |
| 27 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 28 | }; |
| 29 | |
| 30 | timer@60005000 { |
| 31 | compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer"; |
| 32 | reg = <0x60005000 0x400>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 33 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 34 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
| 35 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
| 36 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
| 37 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, |
| 38 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 39 | clocks = <&tegra_car TEGRA114_CLK_TIMER>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 40 | }; |
| 41 | |
| 42 | tegra_car: clock { |
Peter De Schrijver | 672d889 | 2013-04-03 17:40:48 +0300 | [diff] [blame] | 43 | compatible = "nvidia,tegra114-car"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 44 | reg = <0x60006000 0x1000>; |
| 45 | #clock-cells = <1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 46 | #reset-cells = <1>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 47 | }; |
| 48 | |
Laxman Dewangan | c5d9da4 | 2013-03-14 01:19:50 +0530 | [diff] [blame] | 49 | apbdma: dma { |
| 50 | compatible = "nvidia,tegra114-apbdma"; |
| 51 | reg = <0x6000a000 0x1400>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 52 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| 53 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
| 54 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
| 55 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
| 56 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
| 57 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
| 58 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| 59 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
| 60 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, |
| 61 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
| 62 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
| 63 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
| 64 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| 65 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| 66 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| 67 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, |
| 68 | <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, |
| 69 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, |
| 70 | <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, |
| 71 | <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
| 72 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, |
| 73 | <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, |
| 74 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, |
| 75 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
| 76 | <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, |
| 77 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, |
| 78 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, |
| 79 | <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, |
| 80 | <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, |
| 81 | <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, |
| 82 | <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 83 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 84 | clocks = <&tegra_car TEGRA114_CLK_APBDMA>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 85 | resets = <&tegra_car 34>; |
| 86 | reset-names = "dma"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 87 | #dma-cells = <1>; |
Laxman Dewangan | c5d9da4 | 2013-03-14 01:19:50 +0530 | [diff] [blame] | 88 | }; |
| 89 | |
Hiroshi Doyu | 0dfe42e | 2013-01-15 10:17:27 +0200 | [diff] [blame] | 90 | ahb: ahb { |
| 91 | compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; |
| 92 | reg = <0x6000c004 0x14c>; |
| 93 | }; |
| 94 | |
Laxman Dewangan | b16f918 | 2013-01-29 18:26:18 +0530 | [diff] [blame] | 95 | gpio: gpio { |
| 96 | compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; |
| 97 | reg = <0x6000d000 0x1000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 98 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
| 99 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, |
| 100 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, |
| 101 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, |
| 102 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
| 103 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, |
| 104 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, |
| 105 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | b16f918 | 2013-01-29 18:26:18 +0530 | [diff] [blame] | 106 | #gpio-cells = <2>; |
| 107 | gpio-controller; |
| 108 | #interrupt-cells = <2>; |
| 109 | interrupt-controller; |
| 110 | }; |
| 111 | |
Laxman Dewangan | 031b77a | 2013-01-29 18:26:20 +0530 | [diff] [blame] | 112 | pinmux: pinmux { |
| 113 | compatible = "nvidia,tegra114-pinmux"; |
| 114 | reg = <0x70000868 0x148 /* Pad control registers */ |
| 115 | 0x70003000 0x40c>; /* Mux registers */ |
| 116 | }; |
| 117 | |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 118 | /* |
| 119 | * There are two serial driver i.e. 8250 based simple serial |
| 120 | * driver and APB DMA based serial driver for higher baudrate |
| 121 | * and performace. To enable the 8250 based driver, the compatible |
| 122 | * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable |
| 123 | * the APB DMA based serial driver, the comptible is |
| 124 | * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". |
| 125 | */ |
| 126 | uarta: serial@70006000 { |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 127 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| 128 | reg = <0x70006000 0x40>; |
| 129 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 130 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 131 | clocks = <&tegra_car TEGRA114_CLK_UARTA>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 132 | resets = <&tegra_car 6>; |
| 133 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 134 | dmas = <&apbdma 8>, <&apbdma 8>; |
| 135 | dma-names = "rx", "tx"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 136 | status = "disabled"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 137 | }; |
| 138 | |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 139 | uartb: serial@70006040 { |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 140 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| 141 | reg = <0x70006040 0x40>; |
| 142 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 143 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 144 | clocks = <&tegra_car TEGRA114_CLK_UARTB>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 145 | resets = <&tegra_car 7>; |
| 146 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 147 | dmas = <&apbdma 9>, <&apbdma 9>; |
| 148 | dma-names = "rx", "tx"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 149 | status = "disabled"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 150 | }; |
| 151 | |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 152 | uartc: serial@70006200 { |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 153 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| 154 | reg = <0x70006200 0x100>; |
| 155 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 156 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 157 | clocks = <&tegra_car TEGRA114_CLK_UARTC>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 158 | resets = <&tegra_car 55>; |
| 159 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 160 | dmas = <&apbdma 10>, <&apbdma 10>; |
| 161 | dma-names = "rx", "tx"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 162 | status = "disabled"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 163 | }; |
| 164 | |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 165 | uartd: serial@70006300 { |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 166 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| 167 | reg = <0x70006300 0x100>; |
| 168 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 169 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 170 | clocks = <&tegra_car TEGRA114_CLK_UARTD>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 171 | resets = <&tegra_car 65>; |
| 172 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 173 | dmas = <&apbdma 19>, <&apbdma 19>; |
| 174 | dma-names = "rx", "tx"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 175 | status = "disabled"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 176 | }; |
| 177 | |
Andrew Chew | 6c716db | 2013-03-12 16:40:50 -0700 | [diff] [blame] | 178 | pwm: pwm { |
| 179 | compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; |
| 180 | reg = <0x7000a000 0x100>; |
| 181 | #pwm-cells = <2>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 182 | clocks = <&tegra_car TEGRA114_CLK_PWM>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 183 | resets = <&tegra_car 17>; |
| 184 | reset-names = "pwm"; |
Andrew Chew | 6c716db | 2013-03-12 16:40:50 -0700 | [diff] [blame] | 185 | status = "disabled"; |
| 186 | }; |
| 187 | |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 188 | i2c@7000c000 { |
| 189 | compatible = "nvidia,tegra114-i2c"; |
| 190 | reg = <0x7000c000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 191 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 192 | #address-cells = <1>; |
| 193 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 194 | clocks = <&tegra_car TEGRA114_CLK_I2C1>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 195 | clock-names = "div-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 196 | resets = <&tegra_car 12>; |
| 197 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 198 | dmas = <&apbdma 21>, <&apbdma 21>; |
| 199 | dma-names = "rx", "tx"; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 200 | status = "disabled"; |
| 201 | }; |
| 202 | |
| 203 | i2c@7000c400 { |
| 204 | compatible = "nvidia,tegra114-i2c"; |
| 205 | reg = <0x7000c400 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 206 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 207 | #address-cells = <1>; |
| 208 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 209 | clocks = <&tegra_car TEGRA114_CLK_I2C2>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 210 | clock-names = "div-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 211 | resets = <&tegra_car 54>; |
| 212 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 213 | dmas = <&apbdma 22>, <&apbdma 22>; |
| 214 | dma-names = "rx", "tx"; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 215 | status = "disabled"; |
| 216 | }; |
| 217 | |
| 218 | i2c@7000c500 { |
| 219 | compatible = "nvidia,tegra114-i2c"; |
| 220 | reg = <0x7000c500 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 221 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 222 | #address-cells = <1>; |
| 223 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 224 | clocks = <&tegra_car TEGRA114_CLK_I2C3>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 225 | clock-names = "div-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 226 | resets = <&tegra_car 67>; |
| 227 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 228 | dmas = <&apbdma 23>, <&apbdma 23>; |
| 229 | dma-names = "rx", "tx"; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 230 | status = "disabled"; |
| 231 | }; |
| 232 | |
| 233 | i2c@7000c700 { |
| 234 | compatible = "nvidia,tegra114-i2c"; |
| 235 | reg = <0x7000c700 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 236 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 237 | #address-cells = <1>; |
| 238 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 239 | clocks = <&tegra_car TEGRA114_CLK_I2C4>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 240 | clock-names = "div-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 241 | resets = <&tegra_car 103>; |
| 242 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 243 | dmas = <&apbdma 26>, <&apbdma 26>; |
| 244 | dma-names = "rx", "tx"; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 245 | status = "disabled"; |
| 246 | }; |
| 247 | |
| 248 | i2c@7000d000 { |
| 249 | compatible = "nvidia,tegra114-i2c"; |
| 250 | reg = <0x7000d000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 251 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 252 | #address-cells = <1>; |
| 253 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 254 | clocks = <&tegra_car TEGRA114_CLK_I2C5>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 255 | clock-names = "div-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 256 | resets = <&tegra_car 47>; |
| 257 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 258 | dmas = <&apbdma 24>, <&apbdma 24>; |
| 259 | dma-names = "rx", "tx"; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 260 | status = "disabled"; |
| 261 | }; |
| 262 | |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 263 | spi@7000d400 { |
| 264 | compatible = "nvidia,tegra114-spi"; |
| 265 | reg = <0x7000d400 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 266 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 267 | #address-cells = <1>; |
| 268 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 269 | clocks = <&tegra_car TEGRA114_CLK_SBC1>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 270 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 271 | resets = <&tegra_car 41>; |
| 272 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 273 | dmas = <&apbdma 15>, <&apbdma 15>; |
| 274 | dma-names = "rx", "tx"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 275 | status = "disabled"; |
| 276 | }; |
| 277 | |
| 278 | spi@7000d600 { |
| 279 | compatible = "nvidia,tegra114-spi"; |
| 280 | reg = <0x7000d600 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 281 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 282 | #address-cells = <1>; |
| 283 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 284 | clocks = <&tegra_car TEGRA114_CLK_SBC2>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 285 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 286 | resets = <&tegra_car 44>; |
| 287 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 288 | dmas = <&apbdma 16>, <&apbdma 16>; |
| 289 | dma-names = "rx", "tx"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 290 | status = "disabled"; |
| 291 | }; |
| 292 | |
| 293 | spi@7000d800 { |
| 294 | compatible = "nvidia,tegra114-spi"; |
| 295 | reg = <0x7000d800 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 296 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 297 | #address-cells = <1>; |
| 298 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 299 | clocks = <&tegra_car TEGRA114_CLK_SBC3>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 300 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 301 | resets = <&tegra_car 46>; |
| 302 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 303 | dmas = <&apbdma 17>, <&apbdma 17>; |
| 304 | dma-names = "rx", "tx"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 305 | status = "disabled"; |
| 306 | }; |
| 307 | |
| 308 | spi@7000da00 { |
| 309 | compatible = "nvidia,tegra114-spi"; |
| 310 | reg = <0x7000da00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 311 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 312 | #address-cells = <1>; |
| 313 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 314 | clocks = <&tegra_car TEGRA114_CLK_SBC4>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 315 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 316 | resets = <&tegra_car 68>; |
| 317 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 318 | dmas = <&apbdma 18>, <&apbdma 18>; |
| 319 | dma-names = "rx", "tx"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 320 | status = "disabled"; |
| 321 | }; |
| 322 | |
| 323 | spi@7000dc00 { |
| 324 | compatible = "nvidia,tegra114-spi"; |
| 325 | reg = <0x7000dc00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 326 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 327 | #address-cells = <1>; |
| 328 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 329 | clocks = <&tegra_car TEGRA114_CLK_SBC5>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 330 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 331 | resets = <&tegra_car 104>; |
| 332 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 333 | dmas = <&apbdma 27>, <&apbdma 27>; |
| 334 | dma-names = "rx", "tx"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 335 | status = "disabled"; |
| 336 | }; |
| 337 | |
| 338 | spi@7000de00 { |
| 339 | compatible = "nvidia,tegra114-spi"; |
| 340 | reg = <0x7000de00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 341 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 342 | #address-cells = <1>; |
| 343 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 344 | clocks = <&tegra_car TEGRA114_CLK_SBC6>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 345 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 346 | resets = <&tegra_car 105>; |
| 347 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 348 | dmas = <&apbdma 28>, <&apbdma 28>; |
| 349 | dma-names = "rx", "tx"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 350 | status = "disabled"; |
| 351 | }; |
| 352 | |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 353 | rtc { |
| 354 | compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; |
| 355 | reg = <0x7000e000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 356 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 357 | clocks = <&tegra_car TEGRA114_CLK_RTC>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 358 | }; |
| 359 | |
Laxman Dewangan | cd467b7 | 2013-03-14 01:19:53 +0530 | [diff] [blame] | 360 | kbc { |
| 361 | compatible = "nvidia,tegra114-kbc"; |
| 362 | reg = <0x7000e200 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 363 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 364 | clocks = <&tegra_car TEGRA114_CLK_KBC>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 365 | resets = <&tegra_car 36>; |
| 366 | reset-names = "kbc"; |
Laxman Dewangan | cd467b7 | 2013-03-14 01:19:53 +0530 | [diff] [blame] | 367 | status = "disabled"; |
| 368 | }; |
| 369 | |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 370 | pmc { |
Joseph Lo | 2b84e53 | 2013-02-26 16:27:43 +0000 | [diff] [blame] | 371 | compatible = "nvidia,tegra114-pmc"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 372 | reg = <0x7000e400 0x400>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 373 | clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; |
Joseph Lo | 7021d12 | 2013-04-03 19:31:27 +0800 | [diff] [blame] | 374 | clock-names = "pclk", "clk32k_in"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 375 | }; |
| 376 | |
Hiroshi Doyu | 2da1396 | 2013-01-15 10:17:28 +0200 | [diff] [blame] | 377 | iommu { |
| 378 | compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; |
Hiroshi Doyu | 4cca9593 | 2013-10-30 17:17:48 -0600 | [diff] [blame] | 379 | reg = <0x70019010 0x02c |
| 380 | 0x700191f0 0x010 |
| 381 | 0x70019228 0x074>; |
Hiroshi Doyu | 2da1396 | 2013-01-15 10:17:28 +0200 | [diff] [blame] | 382 | nvidia,#asids = <4>; |
| 383 | dma-window = <0 0x40000000>; |
| 384 | nvidia,swgroups = <0x18659fe>; |
| 385 | nvidia,ahb = <&ahb>; |
| 386 | }; |
| 387 | |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 388 | ahub { |
| 389 | compatible = "nvidia,tegra114-ahub"; |
| 390 | reg = <0x70080000 0x200>, |
| 391 | <0x70080200 0x100>, |
| 392 | <0x70081000 0x200>; |
| 393 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 394 | clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, |
Stephen Warren | 2bd541f | 2013-11-07 10:59:42 -0700 | [diff] [blame] | 395 | <&tegra_car TEGRA114_CLK_APBIF>; |
| 396 | clock-names = "d_audio", "apbif"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 397 | resets = <&tegra_car 106>, /* d_audio */ |
| 398 | <&tegra_car 107>, /* apbif */ |
| 399 | <&tegra_car 30>, /* i2s0 */ |
| 400 | <&tegra_car 11>, /* i2s1 */ |
| 401 | <&tegra_car 18>, /* i2s2 */ |
| 402 | <&tegra_car 101>, /* i2s3 */ |
| 403 | <&tegra_car 102>, /* i2s4 */ |
| 404 | <&tegra_car 108>, /* dam0 */ |
| 405 | <&tegra_car 109>, /* dam1 */ |
| 406 | <&tegra_car 110>, /* dam2 */ |
| 407 | <&tegra_car 10>, /* spdif */ |
| 408 | <&tegra_car 153>, /* amx */ |
| 409 | <&tegra_car 154>; /* adx */ |
| 410 | reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", |
| 411 | "i2s3", "i2s4", "dam0", "dam1", "dam2", |
| 412 | "spdif", "amx", "adx"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 413 | dmas = <&apbdma 1>, <&apbdma 1>, |
| 414 | <&apbdma 2>, <&apbdma 2>, |
| 415 | <&apbdma 3>, <&apbdma 3>, |
| 416 | <&apbdma 4>, <&apbdma 4>, |
| 417 | <&apbdma 6>, <&apbdma 6>, |
| 418 | <&apbdma 7>, <&apbdma 7>, |
| 419 | <&apbdma 12>, <&apbdma 12>, |
| 420 | <&apbdma 13>, <&apbdma 13>, |
| 421 | <&apbdma 14>, <&apbdma 14>, |
| 422 | <&apbdma 29>, <&apbdma 29>; |
| 423 | dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", |
| 424 | "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", |
| 425 | "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", |
| 426 | "rx9", "tx9"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 427 | ranges; |
| 428 | #address-cells = <1>; |
| 429 | #size-cells = <1>; |
| 430 | |
| 431 | tegra_i2s0: i2s@70080300 { |
| 432 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; |
| 433 | reg = <0x70080300 0x100>; |
| 434 | nvidia,ahub-cif-ids = <4 4>; |
| 435 | clocks = <&tegra_car TEGRA114_CLK_I2S0>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 436 | resets = <&tegra_car 30>; |
| 437 | reset-names = "i2s"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 438 | status = "disabled"; |
| 439 | }; |
| 440 | |
| 441 | tegra_i2s1: i2s@70080400 { |
| 442 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; |
| 443 | reg = <0x70080400 0x100>; |
| 444 | nvidia,ahub-cif-ids = <5 5>; |
| 445 | clocks = <&tegra_car TEGRA114_CLK_I2S1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 446 | resets = <&tegra_car 11>; |
| 447 | reset-names = "i2s"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 448 | status = "disabled"; |
| 449 | }; |
| 450 | |
| 451 | tegra_i2s2: i2s@70080500 { |
| 452 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; |
| 453 | reg = <0x70080500 0x100>; |
| 454 | nvidia,ahub-cif-ids = <6 6>; |
| 455 | clocks = <&tegra_car TEGRA114_CLK_I2S2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 456 | resets = <&tegra_car 18>; |
| 457 | reset-names = "i2s"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 458 | status = "disabled"; |
| 459 | }; |
| 460 | |
| 461 | tegra_i2s3: i2s@70080600 { |
| 462 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; |
| 463 | reg = <0x70080600 0x100>; |
| 464 | nvidia,ahub-cif-ids = <7 7>; |
| 465 | clocks = <&tegra_car TEGRA114_CLK_I2S3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 466 | resets = <&tegra_car 101>; |
| 467 | reset-names = "i2s"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 468 | status = "disabled"; |
| 469 | }; |
| 470 | |
| 471 | tegra_i2s4: i2s@70080700 { |
| 472 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; |
| 473 | reg = <0x70080700 0x100>; |
| 474 | nvidia,ahub-cif-ids = <8 8>; |
| 475 | clocks = <&tegra_car TEGRA114_CLK_I2S4>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 476 | resets = <&tegra_car 102>; |
| 477 | reset-names = "i2s"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 478 | status = "disabled"; |
| 479 | }; |
| 480 | }; |
| 481 | |
Pritesh Raithatha | 933d87a | 2013-02-20 13:35:14 -0500 | [diff] [blame] | 482 | sdhci@78000000 { |
| 483 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| 484 | reg = <0x78000000 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 485 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 486 | clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 487 | resets = <&tegra_car 14>; |
| 488 | reset-names = "sdhci"; |
Pritesh Raithatha | 933d87a | 2013-02-20 13:35:14 -0500 | [diff] [blame] | 489 | status = "disable"; |
| 490 | }; |
| 491 | |
| 492 | sdhci@78000200 { |
| 493 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| 494 | reg = <0x78000200 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 495 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 496 | clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 497 | resets = <&tegra_car 9>; |
| 498 | reset-names = "sdhci"; |
Pritesh Raithatha | 933d87a | 2013-02-20 13:35:14 -0500 | [diff] [blame] | 499 | status = "disable"; |
| 500 | }; |
| 501 | |
| 502 | sdhci@78000400 { |
| 503 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| 504 | reg = <0x78000400 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 505 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 506 | clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 507 | resets = <&tegra_car 69>; |
| 508 | reset-names = "sdhci"; |
Pritesh Raithatha | 933d87a | 2013-02-20 13:35:14 -0500 | [diff] [blame] | 509 | status = "disable"; |
| 510 | }; |
| 511 | |
| 512 | sdhci@78000600 { |
| 513 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| 514 | reg = <0x78000600 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 515 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 516 | clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 517 | resets = <&tegra_car 15>; |
| 518 | reset-names = "sdhci"; |
Pritesh Raithatha | 933d87a | 2013-02-20 13:35:14 -0500 | [diff] [blame] | 519 | status = "disable"; |
| 520 | }; |
| 521 | |
Mikko Perttunen | 328dc0e | 2013-08-01 18:00:18 +0300 | [diff] [blame] | 522 | usb@7d000000 { |
| 523 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; |
| 524 | reg = <0x7d000000 0x4000>; |
| 525 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 526 | phy_type = "utmi"; |
| 527 | clocks = <&tegra_car TEGRA114_CLK_USBD>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 528 | resets = <&tegra_car 22>; |
| 529 | reset-names = "usb"; |
Mikko Perttunen | 328dc0e | 2013-08-01 18:00:18 +0300 | [diff] [blame] | 530 | nvidia,phy = <&phy1>; |
| 531 | status = "disabled"; |
| 532 | }; |
| 533 | |
| 534 | phy1: usb-phy@7d000000 { |
| 535 | compatible = "nvidia,tegra30-usb-phy"; |
| 536 | reg = <0x7d000000 0x4000 0x7d000000 0x4000>; |
| 537 | phy_type = "utmi"; |
| 538 | clocks = <&tegra_car TEGRA114_CLK_USBD>, |
| 539 | <&tegra_car TEGRA114_CLK_PLL_U>, |
| 540 | <&tegra_car TEGRA114_CLK_USBD>; |
| 541 | clock-names = "reg", "pll_u", "utmi-pads"; |
| 542 | nvidia,hssync-start-delay = <0>; |
| 543 | nvidia,idle-wait-delay = <17>; |
| 544 | nvidia,elastic-limit = <16>; |
| 545 | nvidia,term-range-adj = <6>; |
| 546 | nvidia,xcvr-setup = <9>; |
| 547 | nvidia,xcvr-lsfslew = <0>; |
| 548 | nvidia,xcvr-lsrslew = <3>; |
| 549 | nvidia,hssquelch-level = <2>; |
| 550 | nvidia,hsdiscon-level = <5>; |
| 551 | nvidia,xcvr-hsslew = <12>; |
| 552 | status = "disabled"; |
| 553 | }; |
| 554 | |
| 555 | usb@7d008000 { |
| 556 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; |
| 557 | reg = <0x7d008000 0x4000>; |
| 558 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
| 559 | phy_type = "utmi"; |
| 560 | clocks = <&tegra_car TEGRA114_CLK_USB3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 561 | resets = <&tegra_car 59>; |
| 562 | reset-names = "usb"; |
Mikko Perttunen | 328dc0e | 2013-08-01 18:00:18 +0300 | [diff] [blame] | 563 | nvidia,phy = <&phy3>; |
| 564 | status = "disabled"; |
| 565 | }; |
| 566 | |
| 567 | phy3: usb-phy@7d008000 { |
| 568 | compatible = "nvidia,tegra30-usb-phy"; |
| 569 | reg = <0x7d008000 0x4000 0x7d000000 0x4000>; |
| 570 | phy_type = "utmi"; |
| 571 | clocks = <&tegra_car TEGRA114_CLK_USB3>, |
| 572 | <&tegra_car TEGRA114_CLK_PLL_U>, |
| 573 | <&tegra_car TEGRA114_CLK_USBD>; |
| 574 | clock-names = "reg", "pll_u", "utmi-pads"; |
| 575 | nvidia,hssync-start-delay = <0>; |
| 576 | nvidia,idle-wait-delay = <17>; |
| 577 | nvidia,elastic-limit = <16>; |
| 578 | nvidia,term-range-adj = <6>; |
| 579 | nvidia,xcvr-setup = <9>; |
| 580 | nvidia,xcvr-lsfslew = <0>; |
| 581 | nvidia,xcvr-lsrslew = <3>; |
| 582 | nvidia,hssquelch-level = <2>; |
| 583 | nvidia,hsdiscon-level = <5>; |
| 584 | nvidia,xcvr-hsslew = <12>; |
| 585 | status = "disabled"; |
| 586 | }; |
| 587 | |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 588 | cpus { |
| 589 | #address-cells = <1>; |
| 590 | #size-cells = <0>; |
| 591 | |
| 592 | cpu@0 { |
| 593 | device_type = "cpu"; |
| 594 | compatible = "arm,cortex-a15"; |
| 595 | reg = <0>; |
| 596 | }; |
| 597 | |
| 598 | cpu@1 { |
| 599 | device_type = "cpu"; |
| 600 | compatible = "arm,cortex-a15"; |
| 601 | reg = <1>; |
| 602 | }; |
| 603 | |
| 604 | cpu@2 { |
| 605 | device_type = "cpu"; |
| 606 | compatible = "arm,cortex-a15"; |
| 607 | reg = <2>; |
| 608 | }; |
| 609 | |
| 610 | cpu@3 { |
| 611 | device_type = "cpu"; |
| 612 | compatible = "arm,cortex-a15"; |
| 613 | reg = <3>; |
| 614 | }; |
| 615 | }; |
| 616 | |
| 617 | timer { |
| 618 | compatible = "arm,armv7-timer"; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 619 | interrupts = |
| 620 | <GIC_PPI 13 |
| 621 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 622 | <GIC_PPI 14 |
| 623 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 624 | <GIC_PPI 11 |
| 625 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 626 | <GIC_PPI 10 |
| 627 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 628 | }; |
| 629 | }; |